WO2016024483A1

WO2016024483A1 - Analog/digital conversion circuit

Info

Publication number: WO2016024483A1
Application number: PCT/JP2015/071756
Authority: WO
Inventors: 平山　博文
Original assignee: アズビル株式会社
Priority date: 2014-08-12
Filing date: 2015-07-31
Publication date: 2016-02-18
Also published as: JP2016040647A

Abstract

This analog/digital conversion circuit (10) is provided with: an analog/digital conversion unit (101) that cyclically executes an analog/digital conversion process that converts an analog signal (VA) to a digital signal (DOUT); a storage unit (103); a control unit (102) that, every time the analog/digital conversion process is executed, writes to the storage unit the analog/digital conversion results (DOUT) resulting from the analog/digital conversion process and identification data (DID) associated with the analog/digital conversion results; and an output unit (106) that reads and outputs the analog/digital conversion results and corresponding identification data written to the storage unit.

Description

Analog / digital conversion circuit

The present invention relates to an analog / digital conversion circuit.

Instrumentation equipment such as a temperature controller provided in a plant or building air conditioner, etc. monitors the state of the controlled device, and includes a heater or a heater provided in the controlled device so that the controlled device is in a target state. Controls valves and the like.
For example, Patent Document 1 below discloses a temperature regulator that controls a control target device so as to reach a target temperature. This temperature controller is an analog / digital conversion circuit (hereinafter referred to as “A / D”) that periodically converts the detection result (analog signal) of the temperature of the control target device detected by the temperature sensor into a digital signal. And a data processing unit (processor such as a CPU) that performs PID (Proportional Integral Derivative) computation using the continuous measurement data.

JP 2009-53044 A

Instrumentation equipment such as a temperature controller needs to accurately grasp the change in the state of the controlled device and perform appropriate control according to the change in the state. Therefore, an instrumentation device such as a temperature controller must periodically A / D convert the detection result of the sensor and transmit the continuous A / D conversion result to a data processing unit such as a CPU without omission. If there is missing measurement data on the data processing unit side, the continuity of the measurement data is lost. When the data processing unit performs a PID operation such as a differential operation in a state where the continuity of the measurement data is lost, the operation amount calculated by the operation suddenly changes to an unintended value, and the control result is not good. There is a risk of becoming stable.

However, it is not easy for the data processing unit to reliably acquire the A / D conversion result periodically updated by the A / D conversion circuit without omission. Therefore, the data processing unit determines whether or not the continuity of the acquired data is maintained, and uses the acquired data for the PID calculation only when the continuity of the data is maintained. It is possible to avoid abnormalities such as a sudden change in the operation amount due to the control and to maintain control stability. However, in a conventional instrument such as a temperature controller, the data processing unit cannot determine whether the continuity of the acquired A / D conversion result is maintained.

For example, in general, an A / D conversion circuit and a data processing unit such as a CPU are configured by separate semiconductor chips. If these chips cannot be arranged close to each other, the same clock signal may not be supplied from two oscillator chips from a single oscillator. In such a case, it is necessary to provide an oscillator for each semiconductor chip. However, when the oscillators are individually provided, by using the clocks of the respective oscillators, the A / D conversion process is executed and the A / D conversion result read period coincides with the A / D conversion result readout period. Even if the conversion circuit and the data processing unit are operated, an error based on an individual difference of oscillators or a difference in performance actually occurs in both operation cycles. If the errors accumulate, the data processing unit may acquire the same A / D conversion result twice from the A / D conversion circuit. If the data processing unit acquires the same A / D conversion result twice, the data processing unit only needs to look at the acquired data twice to obtain the A / D conversion result in one A / D conversion cycle. It was not possible to determine whether each A / D conversion result in the two consecutive A / D conversion periods had the same value because the input value was stable or it happened to be acquired.

Further, as a countermeasure against the above problem, for example, the on / off state of the port of the semiconductor chip on which the A / D conversion circuit is formed is switched according to whether the A / D conversion process is completed, and the data processing unit A method is also conceivable in which the on / off state switching is detected by polling or interrupt processing, and the A / D conversion result read processing is executed based on the detection result.
However, in this method, when the A / D conversion result read process executed after the polling determination process or the interrupt process is delayed, the A / D conversion result of the target A / D conversion cycle cannot be acquired. There is a possibility of acquiring an A / D conversion result of the next A / D conversion cycle. When the data processing unit misses the A / D conversion result of the target A / D conversion cycle, does the data processing unit miss the A / D conversion result for one cycle only by looking at the acquired data? It was not possible to judge whether or not. In order to keep the reading process of the A / D conversion result from being delayed, the timing for executing the A / D conversion process and the timing for reading the A / D conversion result can be strictly defined. There is a problem that the time restriction of the processing on the side increases and the design of the data processing unit becomes complicated.

An object of the present invention is to provide a continuity of a plurality of acquired A / D conversion results in a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion. It is to be able to determine whether or not the above is maintained.

An analog / digital conversion circuit according to the present invention includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit. A controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed; And an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.

As described above, according to the present invention, a circuit that continuously acquires a plurality of A / D conversion results from an A / D conversion circuit that periodically performs A / D conversion can be obtained by using the acquired A / D conversion results. It can be determined whether or not the continuity of the D conversion result is maintained.

FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a temperature controller including the A / D converter according to the first embodiment. FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data. FIG. 3B is a diagram illustrating an example when data based on the execution time of the A / D conversion process is used as identification data. FIG. 3C is a diagram illustrating an example in which identification data is 1-bit data whose logic level is inverted each time an A / D conversion process is performed. FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the first embodiment. 4B is a diagram showing an example of a response message format related to a data read request in the temperature controller including the A / D converter according to Embodiment 1. FIG. FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment. FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register. FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment. FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment. FIG. 8 is a diagram illustrating an example of assignment of addresses of A / D conversion processing registers and identification data registers in an A / D conversion circuit including a plurality of A / D conversion units.

First, an outline of an analog / digital conversion circuit according to the present invention will be described.
An analog / digital conversion circuit according to the present invention includes an analog / digital conversion unit that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal, a storage unit, and the analog / digital conversion unit. A controller that writes an analog / digital conversion result by the analog / digital conversion process and identification data associated with the analog / digital conversion result to the storage unit each time the analog / digital conversion process is executed; And an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.

In the analog / digital conversion circuit, the control unit performs the storage unit by the output unit until writing of both the analog / digital conversion result and the identification data by the analog / digital conversion unit to the storage unit is completed. May not be allowed to be read.

In the analog / digital conversion circuit, the identification data may be data indicating the number of executions of the analog / digital conversion processing by the analog / digital conversion unit.

In the analog / digital conversion circuit, the identification data may be data indicating a time when the analog / digital conversion processing is executed by the analog / digital conversion unit.

In the analog / digital conversion circuit, the identification data may be 1-bit data whose logic level is inverted every time the analog / digital conversion process is executed by the analog / digital conversion unit.

In the analog / digital conversion circuit, the identification data may be data based on a count value of a free-run counter.

In the analog / digital conversion circuit, the storage unit is a register including a first register that stores the analog / digital conversion result obtained by the analog / digital conversion process and a second register that stores the identification data. Each time the analog / digital conversion process is executed, the control unit sequentially stores the analog / digital conversion result of the executed analog / digital conversion process and the identification data in the register pair. In response to a read request input from the outside, the writing and the output unit read the analog / digital conversion result and the identification data related to the analog / digital conversion processing for a plurality of times from the plurality of register pairs. May be.

Hereinafter, embodiments of an analog / digital conversion circuit according to the present invention will be described in detail with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 is a diagram showing a configuration of a temperature control system including a temperature controller including an A / D conversion circuit according to the first embodiment.
A temperature control system 300 shown in the figure includes a temperature controller 1, a control target device 2, a temperature sensor 3, an operation unit 4, and a heater 5.

The temperature sensor 3 detects the temperature of the control target device 2 and outputs an analog detection signal (hereinafter also referred to as “analog signal”) VA. The heater 5 is, for example, a device that is provided inside the control target device 2 and heats the control target device 2. The operation unit 4 is a device that adjusts the heating temperature of the heater 5. For example, the operation unit 4 adjusts the heating temperature of the heater 5 by changing the current or voltage supplied to the heater 5 based on the control signal CNT supplied from the temperature controller 2.

The temperature controller 1 periodically converts the analog signal VA output from the temperature sensor 3 into a digital signal, and performs a PID operation using the converted digital signal (measurement data), so that the control target device 2 can perform the target operation. The control signal CNT is generated so that the temperature becomes.
FIG. 2 is a diagram illustrating a configuration of the temperature regulator 1 including the A / D conversion circuit according to the first embodiment.
As shown in FIG. 2, the temperature controller 1 includes an A / D conversion circuit 10, a data processing control unit 11, and other power supply circuits and external input / output interface circuits not shown.

The A / D conversion circuit 10 is a circuit that converts the analog signal VIN output from the temperature sensor 3 into a digital signal. The A / D conversion circuit 10 not only outputs the A / D conversion result but also has a function of outputting the identification data associated with the A / D conversion result to the data processing control unit 11 at the subsequent stage. Yes.

Specifically, the A / D conversion circuit 10 includes an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106. The A / D conversion circuit 10 is, for example, a one-chip semiconductor device in which an A / D conversion unit 101, a control unit 102, a storage unit 103, and a communication circuit 106 are formed on one semiconductor substrate by a known CMOS manufacturing process. It is realized as.

The A / D converter 101 periodically executes A / D conversion processing for converting the analog signal VIN output from the temperature sensor 3 into a digital signal. For example, the A / D conversion unit 101 converts the analog signal VIN into the digital signal DOUT and outputs it at a constant cycle (for example, every 10 ms). The A / D converter 101 is, for example, a ΔΣ type A / D converter. In the following description, the digital signal DOUT converted by the A / D conversion unit 10 is also referred to as an A / D conversion result DOUT.

Each time the A / D conversion process by the A / D conversion unit 10 is completed, the control unit 102 writes the A / D conversion result DOUT of the completed A / D conversion process in the storage unit 103 and also performs the A / D conversion. The identification data DID associated with the result DOUT is written in the storage unit 103.
Here, the identification data DID is data for identifying a conversion result by an A / D conversion process executed at a certain timing and a conversion result by an A / D conversion process executed at a timing before and after that. Details of the identification data DID will be described later.

Further, the control unit 102 outputs an enable signal EN instructing permission / non-permission of data reading from the storage unit 103 by the communication circuit 106 described later. For example, the control unit 102 stores the A / D conversion result DOUT and the enable signal EN in an invalid state until the writing of the identification data DIN corresponding to the A / D conversion result DOUT to the storage unit 103 is completed. When reading of data from the unit 103 is prohibited and writing of both the A / D conversion result DOUT and the identification data DIN is completed, the enable signal EN is set to a valid state, whereby the data from the storage unit 103 is read. Allow reading. As a result, reading of data from the storage unit 103 in a situation where only one of the A / D conversion result DOUT and the identification data DID has been rewritten (updated) is prohibited, and the read A / D conversion result is identified. It is possible to prevent the correspondence relationship with data from deviating.

The storage unit 103 includes a circuit having a storage area for storing data, and stores the A / D conversion result DOUT and the identification data DID. Specifically, the storage unit 103 includes an A / D conversion result register 104 as a storage circuit for storing the A / D conversion result DOUT, and an identification data register 105 as a storage circuit for storing the identification data DID. Have.

The A / D conversion result register 104 and the identification data register 105 can be rewritten by the control unit 102 and read by the communication circuit 106. For example, every time the A / D conversion process by the A / D conversion unit 10 is completed, the control unit 102 displays the A / D conversion result OUT of the completed A / D conversion process and the identification data DID corresponding thereto as A / D By writing to the D conversion result register 104 and the identification data register 105, the values of the A / D conversion result register 104 and the identification data register 105 are updated. The A / D conversion result DOUT and the identification data DID stored in the A / D conversion result register 104 and the identification data register 105 are periodically read by the communication circuit 106.

The communication circuit 106 functions as an output unit that reads and outputs data from the storage unit 103. Specifically, in response to a data read request from the data processing control unit 11, the communication circuit 106 reads the A / D conversion result DOUT and the identification data DID written in the storage unit 103, and reads the two read Data is transmitted to the data processing control unit 11. More specifically, when the communication circuit 106 receives a data read request from the data processing control unit 11 and the enable signal EN is in a valid state, the communication circuit 106 receives the A / D conversion result DOUT from the storage unit 103. The identification data DID is read and transmitted to the data processing control unit 11, and when the enable signal EN is in an invalid state, the process waits until the enable signal EN is in an effective state. When the enable signal EN becomes valid, the A / D conversion result DOUT and the identification data DID are read from the storage unit 103 and transmitted to the data processing control unit 11.

The data processing control unit 11 is a microcontroller, for example, and includes a CPU 111, a storage device 112, a communication circuit 113, an external interface circuit (not shown), and the like. For example, the data processing control unit 11 may be configured as a one-chip microcontroller in which the CPU 111, the storage device 112, the communication circuit 113, and the like are formed on one semiconductor substrate, or the CPU 111, the storage device 112, and The communication circuit 113 or the like may be configured as a multi-chip microcontroller formed on separate semiconductor chips.

The communication circuit 113 is a circuit for performing communication with an external circuit. For example, the communication circuit 113 issues a data read request to the A / D conversion circuit 10 in accordance with an instruction from the CPU 111, and the A output from the A / D conversion circuit 10 in response to the issued read request. / D conversion result DOUT and identification data DID are received. The A / D conversion result DOUT and the identification data DID received by the communication circuit 113 are stored in the storage device 112, for example.

The storage device 112 includes a ROM (Read Only Memory), a RAM (Random Access Memory), a plurality of registers, and the like. For example, the ROM stores a program for causing the CPU 111 to execute various calculations, and the plurality of registers store the A / D conversion result DOUT received by the communication circuit 113, the identification data DID, and the like. Stores the program read from the ROM and expanded, the calculation result by the CPU 111, and the like.

The CPU 111 performs overall control of the temperature controller 1 by performing various calculations in accordance with programs stored in the storage device 112. Further, the CPU 111 generates a control signal CNT so that the control target device 2 reaches a target temperature by performing a PID calculation based on the A / D conversion result DOUT stored in the storage device 112. The control signal CNT generated by the CPU 111 is supplied to the operation unit 4 via an external interface circuit (not shown) and is used for controlling the heating temperature of the heater 5 as described above.

Next, the identification data DID will be described in detail.
As described above, the A / D conversion circuit 10 outputs the identification data DID associated with the A / D conversion result DOUT to the subsequent data processing control unit 11 in addition to the A / D conversion result DOUT. As a method for generating the identification data DID, for example, the following four can be exemplified.

The first example is a technique for generating identification data DID from data based on the number of execution times of A / D conversion processing.
FIG. 3A is a diagram illustrating an example when data based on the number of executions of the A / D conversion process is used as identification data DID.
As shown in the figure, the A / D conversion circuit 10 counts the number of executions of the A / D conversion process, and uses the count value as identification data DID. Specifically, a counter is provided in the control unit 102, and the count value of the counter is incremented each time the A / D conversion result DOUT is output from the A / D conversion unit 10. Whenever the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105, and the count value of the counter at that time Is written into the identification data register 105.

As the counter, for example, a counter that counts the number of execution times of A / D conversion processing can be exemplified. For example, in FIG. 3A, an 8-bit counter counts the number of executions of the A / D conversion process, resets the count value when the number of executions of the A / D conversion process is counted up to the 256th time, and starts from the 257th time. The case where the count operation starts again from “0” is shown.

By recording the number of executions of the A / D conversion process as the identification data DID as described above, the A / D conversion result by the A / D conversion process executed at a certain timing and the A / D executed at the timing before and after the A / D conversion process are recorded. It becomes possible to identify the A / D conversion result by the D conversion process.

In FIG. 3A, an 8-bit counter is exemplified as the counter. However, in order to store the number of A / D conversions executed in the past for debugging the temperature controller 1, a counter having a larger number of bits is used. Use it.
For example, when the A / D conversion process is executed at an interval of 1 ms, it is possible to record the number of executions of the A / D conversion process for about 49 days by using a 32-bit counter. For example, by using a 40-bit counter, it is possible to record the number of executions of A / D conversion in about 34 years, and continuously record the number of executions exceeding the life of a general product. Is also possible. Further, in a general design, a counter of about 32 bits can be prepared, so that the number of bits can be increased as necessary.

The second example is a method for generating identification data DID from data based on the execution time of the A / D conversion process.
FIG. 3B is a diagram illustrating an example in which the data based on the execution time of the A / D conversion process is the identification data DID. In this case, as shown in the figure, the execution time (time stamp) of the A / D conversion process becomes the identification data DID. The execution time is, for example, the time when the A / D conversion process is completed.

Here, for example, the following two methods can be exemplified as specific methods using the execution time of the A / D conversion process.
The first technique is a technique in which a real-time clock is provided inside or outside the A / D conversion circuit 10. In this method, every time the A / D conversion result DOUT is output from the A / D conversion unit 101, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and The value of the real time clock is written in the identification data register 105 as identification data DID. Here, the number of bits required for the real-time clock is, for example, 48 to 64 bits.

The second method is a method of providing a counter that is incremented at a constant cycle, for example, at time 0 when power is turned on, inside or outside the control unit 102 instead of the real-time clock. In this method, every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT into the A / D conversion result register 105 and The counter value is written in the identification data register 105 as identification data DID.

With any of the above methods, the A / D conversion result obtained by the A / D conversion process executed at a certain timing and the A / D conversion result obtained by the A / D conversion process executed at the timing before and after that are identified. It becomes possible. Furthermore, according to the first method using the real-time clock described above, the accurate time when the A / D conversion process is executed can be recorded, so that the identification data DID can be used for debugging of the temperature controller 1 and the like. Become. On the other hand, according to the second method not using the real-time clock described above, an increase in circuit scale can be suppressed.

The third example is a method of generating identification data DID from 1-bit data whose logic level is inverted every time A / D conversion processing is executed.
FIG. 3C is a diagram illustrating an example in which identification data DID is 1-bit data whose logic level is inverted each time an A / D conversion process is performed.

As shown in the figure, the identification data register 105 is composed of a 1-bit storage element (flag). Further, every time the A / D conversion result DOUT is output from the A / D conversion unit 10, the control unit 102 writes the A / D conversion result DOUT in the A / D conversion result register 105 and also in the identification data register 105. The recorded 1-bit value is inverted. Here, the identification data register 105 may be realized by a 1-bit counter.

According to this, it is possible to identify the A / D conversion result by the A / D conversion process executed at a certain timing and the A / D conversion result by the A / D conversion process executed at the timing before and after the A / D conversion process. It becomes. Also, by realizing the identification data register 105 with a 1-bit storage element, it is possible to reduce the necessary hardware resources and suppress an increase in circuit scale.

The fourth example is a technique for generating identification data DID from data based on the count value of the free-run counter. For example, an 8-bit free-run counter is provided in the A / D conversion circuit 10, and the free-run counter counts continuously input pulses regardless of the execution process of the A / D conversion process. The value is the identification data DID. According to this, since a counter having a large bit width is not required, an increase in circuit scale can be suppressed. Note that the data stored as the identification data DID may not be the count value (numerical value) of the free-run counter itself, but may be a character code with a known order such as “A to Z” of the alphabet, for example.

Next, a specific communication method between the A / D conversion circuit 10 and the data processing control unit 11 will be described.
Communication between the A / D conversion circuit 10 and the data processing control unit 11 is performed by, for example, an SPI (Serial Peripheral Interface). The communication circuit 106 on the A / D conversion circuit 10 side and the communication circuit 113 on the data processing control unit 11 side each have hardware resources necessary for communication by SPI.

As described above, the A / D conversion result is transmitted from the A / D conversion circuit 10 to the data processing control unit 11 by the data processing control unit 11 issuing a data read request (read command). The circuit 10 is realized by outputting the A / D conversion result DOUT and the identification data DID as a set as a response to the read request.

FIG. 4A is a diagram illustrating an example of a format of a transmission message of a data read request according to the first embodiment. FIG. 4B is a diagram illustrating an example of a response message format related to a data read request according to the first embodiment.
As shown in FIG. 4A, the transmission message related to the data read request issued by the data processing control unit 11 is serial data in which a header is attached to the head of the data and a footer is attached to the end of the data, for example, according to the SPI protocol. It is configured as. FIG. 4A shows an instruction for instructing “reading a set of A / D conversion results DOUT and identification data DID from address 100H”.

Further, as shown in FIG. 4B, the response message transmitted from the A / D conversion circuit 10 in response to the transmission message of the data processing control unit 11 is placed at the head of the data according to the SPI protocol, similarly to the transmission message. It is configured as one frame of serial data with a header and a footer at the end of the data. FIG. 4B shows a case where an A / D conversion result DOUT “3356H” and identification data DID “01H” are output as a response to the read command.

The cycle in which the data processing control unit 11 issues a read request to the A / D conversion circuit 10 is a cycle in which A / D conversion processing is executed in the A / D conversion circuit 10 (A / D conversion result register 104 and identification The cycle is the same as or shorter than the cycle in which the data register 105 is updated. Thereby, the data processing control unit 11 can continuously acquire the A / D conversion result DOUT periodically updated by the A / D conversion circuit 10.

As described above, according to the A / D conversion circuit according to the present invention, identification data is assigned for each A / D conversion result, and the A / D conversion result and the identification data are output as a set. The received circuit can determine whether the continuity of the acquired A / D conversion result is maintained.

For example, in the temperature controller 1 including the A / D conversion circuit according to the first embodiment, the data processing control unit 11 performs identification data corresponding to the acquired A / D conversion result and the A / D conversion acquired immediately before it. By comparing the identification data corresponding to the result, it is possible to determine whether or not the A / D conversion result of the same A / D conversion period is acquired and whether or not the A / D conversion result is missed. That is, it is possible for the data processing control unit 11 to determine whether the continuity of the acquired A / D conversion results is maintained. Thus, when the data processing control unit 11 determines that the continuity of the acquired A / D conversion result is maintained, the data processing control unit 11 performs the PID calculation using the acquired A / D conversion result, and acquires the acquired A / D When it is determined that the continuity of the D conversion result is not maintained, it is possible to perform processing such as not using the acquired A / D conversion result for the PID calculation. As a result, it is possible to avoid an abnormality such as a sudden change in the PID calculation result by the data processing control unit, so that the control of the temperature control system 300 can be kept stable.

In addition, even when there are duplicate acquisitions of A / D conversion results or missing A / D conversion results, the data processing control unit 11 can deal with them as described above. It is possible to make the execution cycle of the A / D conversion process by A and the read cycle of the A / D conversion result by the data processing control unit 11 asynchronous. As a result, the data processing control unit 11 does not need to strictly define the timing for executing the constant monitoring and interrupt processing by polling, so the time restriction of the processing by the data processing control unit 11 is reduced, and the data The processing unit 11 can be easily designed.

In addition, according to the A / D conversion circuit according to the first embodiment, since the data reading is not permitted until the writing of both the A / D conversion result and the identification data is completed, the read A / D is not permitted. It is possible to prevent the correspondence between the conversion result and the identification data from deviating.

<< Embodiment 2 >>
The A / D conversion circuit according to the second embodiment is different from the A / D conversion circuit 10 according to the first embodiment in that a plurality of registers for storing A / D conversion results and identification data are provided. Other points are the same as those of the A / D conversion circuit 10 according to the first embodiment.
FIG. 5 is a diagram illustrating a configuration of a temperature regulator including an A / D conversion circuit according to the second embodiment. In the temperature controller 6 according to the second embodiment, the same components as those of the temperature controller 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

The A / D conversion circuit 60 in the temperature controller 6 includes a storage unit 603 that stores an A / D conversion result and identification data. The storage unit 603 includes a plurality of A / D conversion result registers 604_1 to 604_n (n is an integer of 2 or more) and a plurality of identification data registers 605_1 to 605_n. The A / D conversion result register 604_1 and the identification data register 605_1 constitute a pair of registers 606_1. Similarly, the A / D conversion result register 604_n and the identification data register 605_n constitute a pair of register pairs 606_n.

Each time the A / D conversion process is executed by the A / D conversion unit 10, the control unit 602 sends the A / D conversion result DOUT and the corresponding identification data DID to the plurality of register pairs 606_1 to 606_n. Write sequentially.
For example, the control unit 602 obtains the A / D conversion result DOUT_1 by the A / D conversion process executed in a certain A / D conversion cycle and the corresponding identification data DID_1 from the A / D conversion result register 604_1 and the identification data register 605_1. And A / D conversion result DOUT_2 by the A / D conversion process executed in the next A / D conversion cycle and identification data DID_2 corresponding to the A / D conversion result register 604_2 and identification data register 605_2 Write to. In this way, the control unit 602 writes data to the register pairs 606_1 to 606_n in order every time the A / D conversion process is completed. When the A / D conversion process is executed in a state where data is written in all the register pairs 606_1 to 606_n, the control unit 602 sets the oldest A / D conversion result and the identification data to the register pair in which the identification data is written. The latest A / D conversion result and identification data are overwritten.

The transmission of the A / D conversion result from the A / D conversion circuit 60 to the data processing control unit 11 is performed by the data processing control unit 11 issuing a data read request (read command) as in the first embodiment. The / D conversion circuit 60 is realized by outputting the A / D conversion result DOUT and the identification data DID as a response to the read request.

Here, the data processing control unit 11 issues a command for requesting reading of a plurality of sets of A / D conversion results DOUT and identification data DID as the read command. Hereinafter, this content will be described in detail with reference to FIGS. 6, 7A, and 7B.

FIG. 6 is a diagram illustrating an example of assignment of addresses of the A / D conversion processing register and the identification data register.
FIG. 7A is a diagram illustrating an example of a format of a transmission message of a data read request in the temperature controller including the A / D converter according to the second embodiment.
FIG. 7B is a diagram illustrating an example of a response message format related to a data read request in the temperature controller including the A / D converter according to the second embodiment.
As shown in FIG. 6, the register pairs 606_1 to 606_n are assigned addresses in order. In this way, by sequentially assigning addresses to each of the register pairs 606_1 to 606_n, a plurality of continuous A / D conversion results and identification data can be easily read.
For example, as shown in FIG. 7A, a read command is issued in which the read start address is “100h” and the read number is “03h”. As a result, as shown in FIG. 7B, data from the register addresses “100h” to “105h” is read, and A / D conversion results and identification data for three times can be acquired by one read command. . That is, as shown in FIG. 6, register addresses are sequentially assigned to each of the register pairs 606_1 to 606_n, and by issuing a command designating the read start address and the read number as shown in FIG. A plurality of A / D conversion results and identification data can be acquired.

As described above, according to the A / D conversion circuit 60 according to the second embodiment, a plurality of registers are provided as a storage unit for storing the A / D conversion result and the identification data, and the A / D conversion result and the identification data are stored. By making it possible to read a plurality of sets, it is possible to prevent missing A / D conversion results. For example, even if a single A / D conversion result is missed in the data reading process by the data processing control unit 11, it is possible to acquire the A / D conversion result for the missing data in the next reading process. It becomes.

Further, according to the A / D conversion circuit 60 according to the second embodiment, the A / D conversion result and the identification data for a plurality of times can be read by one read command, so that the data processing control unit 11 performs data transfer. It is possible to reduce the number of readings.
This eliminates the need for high-speed and high-precision processing time management by the data processing control unit 11, facilitates the design of the data processing control unit 11, and provides a low-speed and inexpensive microcontroller (CPU) as the data processing control unit 11. Therefore, the cost can be reduced.

For example, when the A / D conversion cycle by the A / D conversion circuit 10 is 1 MHz, the A / D conversion result and the identification data are updated every 1 μs. In this case, if the data processing control unit must read data every 1 μs as in the prior art, the data processing control unit must be operated with an operation clock corresponding to the A / D conversion processing time every 1 μs. .
On the other hand, by providing n register pairs as in the A / D conversion circuit 60 according to the second embodiment, the data processing control unit executes the data reading process every (n × 1) μs. In this case, data can be acquired without missing. For example, when 1000 register pairs are provided, the data processing control unit may execute data read processing every 1 ms. That is, according to the A / D conversion circuit 60 according to the second embodiment, the operation clock frequency of the microcontroller as the data processing control unit 11 can be lowered as compared with the conventional case, and the cost can be reduced.

Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

For example, in the first and second embodiments, the register is exemplified as the storage circuit that stores the A / D conversion result and the identification data, but any circuit that can store the A / D conversion result and the identification data may be used. It is not limited to registers.

In the second embodiment, the case where the A / D conversion circuit 60 includes one A / D conversion unit 101 is illustrated. However, the present invention is not limited to this, and the A / D conversion circuit 60 includes the A / D conversion unit 101. A plurality may be provided. In this case, the address assignment of each register in the storage unit 603 is set as shown in FIG. 8, and the A / D of a plurality of channels is issued by issuing an instruction designating the read start address and the read number as described above. The conversion result and the identification data can be read by one read command.

In the first and second embodiments, the case where the A /

D conversion circuits

10 and 60 are applied to the temperature controller 1 is exemplified. However, the analog signal from the sensor or the like is periodically A / D converted, and the A The A /

D conversion circuits

10 and 60 can also be applied to a recorder or the like that sequentially records the / D conversion results.

In the first and second embodiments, the A / D conversion unit 101 is a ΔΣ A / D conversion circuit. However, the A / D conversion unit 101 is an A / D conversion circuit of another conversion method. It may be. For example, the A / D converter 101 may be a successive approximation A / D converter circuit.

In the first embodiment, the case where a plurality of A / D conversion result registers 104 are prepared so as not to cause data loss has been described as an example. However, the present invention is not limited to this. For example, when a plurality of prepared A / D conversion result registers 104 are full and a new A / D conversion result cannot be stored, the A / D conversion result register 104 is used as a ring buffer, and A The oldest data stored in the / D conversion result register 104 may be overwritten by the latest data.

The analog / digital conversion circuit according to the present invention can be applied to various uses such as industrial instrumentation equipment.

10, 60 ... A / D conversion circuit, 101 ... A / D conversion unit, 102,602 ... control unit, 103,603 ... storage unit, VA ... analog signal, DOUT ... A / D conversion result, DID ... identification data.

Claims

An analog / digital converter that periodically executes an analog / digital conversion process for converting an input analog signal into a digital signal;
A storage unit;
Each time the analog / digital conversion process is executed by the analog / digital conversion unit, the analog / digital conversion result by the analog / digital conversion process and the identification data associated with the analog / digital conversion result are A control unit for writing to the storage unit;
An analog / digital conversion circuit comprising: an output unit that reads out and outputs the analog / digital conversion result written in the storage unit and the corresponding identification data.
The analog / digital conversion circuit according to claim 1,
The control unit does not allow the output unit to read the storage unit until writing of both the analog / digital conversion result and the identification data by the analog / digital conversion unit to the storage unit is completed. An analog / digital conversion circuit.
The analog / digital conversion circuit according to claim 1,
The identification data is data indicating the number of execution times of the analog / digital conversion processing by the analog / digital conversion unit.
The analog / digital conversion circuit according to claim 1,
The identification data is data indicating a time when the analog / digital conversion processing is executed by the analog / digital conversion unit.
The analog / digital conversion circuit according to claim 1,
The identification data is 1-bit data whose logic level is inverted each time the analog / digital conversion unit executes the analog / digital conversion process.
The analog / digital conversion circuit according to claim 1,
The analog / digital conversion circuit, wherein the identification data is data based on a count value of a free-run counter.
The analog / digital conversion circuit according to claim 1,
The storage unit includes a plurality of register pairs each including a first register that stores the analog / digital conversion result obtained by the analog / digital conversion process and a second register that stores the identification data.
The controller sequentially writes the analog / digital conversion result of the executed analog / digital conversion process and the identification data to the register pair each time the analog / digital conversion process is executed,
The output unit reads the analog / digital conversion result and the identification data of the analog / digital conversion processing for a plurality of times from the plurality of register pairs in response to a read request input from the outside. Analog / digital conversion circuit.