WO2015196653A1

WO2015196653A1 - Data processing method and device

Info

Publication number: WO2015196653A1
Application number: PCT/CN2014/088866
Authority: WO
Inventors: 吴红海; 吴晓东; 罗小妮
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-06-25
Filing date: 2014-10-17
Publication date: 2015-12-30
Also published as: CN105306389B; CN105306389A

Abstract

Disclosed are a data processing method and device. The method comprises: configuring parameters of an interface between a switching chip and a processing chip according to predetermined parameters, so that all ES packets from the switching chip can reach the processing chip within a predetermined period of time, the predetermined parameters comprising at least the total number of DSLs; and delivering the received ES packets by using an ES packet branch added in a receiving and processing interface in the processing chip. Therefore, the problem in the prior art that a burst of precoded packets exist within a short period of time in the vector technology is solved, the delivering and processing priority of the ES packets in the processing chip is raised, and the possibility that the ES packets can be processed within a period of time specified in the protocol is increased to some extent.

Description

Data processing method and device

Technical field

The present invention relates to the field of communications, and in particular to a data processing method and apparatus.

Background technique

With the gradual development of broadband, due to its short-distance bandwidth advantage (up to 100 Mbps in an ideal application environment), the second generation of Very High-rate Digital Subscriber Loop (VDSL2) Become the mainstream access method for the current "last segment" of copper wire. However, due to the higher frequency band used by VDSL2, the problem of crosstalk between lines is more prominent. Compared with the bandwidth of single-line VDSL2 access, the bandwidth drop of each pair when VDSL2 is connected is very obvious. The crosstalk problem becomes the main factor limiting the performance of VDSL2, and far end crosstalk (Far End Cross-Talk) , referred to as FEXT) is another top priority.

In order to more completely eliminate the impact of FEXT on VDSL2, ITU-T has introduced a vector technology standard, namely Demand Side Management Level 3 (DSM Level 3). . The vector solves the FEXT in the VDSL2 line by vectorization, and improves the performance of the multi-line VDSL2 line.

However, due to the high sensitivity of the vector technology to the processing time of the pre-encoding message, the internal bandwidth of the system is highly demanded. In the end, many multi-user VDSL2 access devices with multiple Dwelling Units (MDUs) are discouraged. How to achieve high-reliability and easy operation and maintenance of these massive data transmission and processing is the main challenge of vector productization.

In order to solve the problem that a large number of bursts of precoding packets in the vector technology exist in a short period of time and must be processed within a specified time, so that the MDU type VDSL2 access device can implement the board level vector function, we need an MDU type VDSL2 connection. The device supports a board level vector (BLV) implementation.

In view of the related art, the problem that a pre-coded message in the vector technology has a large number of bursts in a short time has not yet proposed an effective solution.

Summary of the invention

The embodiments of the present invention provide a data processing method and apparatus to solve at least the problem caused by a large number of bursts in a short period of time in a vector technology.

According to an aspect of an embodiment of the present invention, a data processing method includes: configuring parameters of an interface between a switch chip and a processing chip according to a predetermined parameter, so that all error samples from the switch chip (Error Sample , the abbreviated as ES) message can reach the processing chip within a predetermined time; wherein the predetermined parameter includes at least: a total number of lines of a digital subscriber loop (DSL); The ES packet branch added to the receiving processing interface in the chip distributes the received ES packet.

Configuring the parameters of the interface between the switch chip and the processing chip according to the predetermined parameter includes: when the rate of the interface is a first threshold range, the predetermined parameter includes only: DSL And the total number of lines; and/or, in a case where the rate of the interface is a second threshold range, the predetermined parameter further includes: a capability of the processing chip.

Configuring parameters of the interface between the switch chip and the processing chip according to the predetermined parameter includes: first-in-first-out of an interface between the switch chip and the processing chip according to the predetermined parameter The queue (First input First Output, FIFO for short) is configured in depth.

After configuring parameters of the interface between the switch chip and the processing chip according to the predetermined parameter, the method further includes: estimating, according to the predetermined parameter, the ES message within a predetermined duration a maximum burst amount; adjusting, according to the burst amount, a rate limit value for transmitting the ES packet to the processing chip by using the interface.

The priority of the branch for processing the ES message is the highest priority.

The distribution of the received ES message by the branch of the ES packet includes: checking the received packet; and determining whether the packet is a valid packet, and determining whether the packet is the ES packet. If the result of the determination is yes, the ES message is distributed through the ES packet branch.

The method further includes: limiting a network packet to the uplink interface connected to the switch chip and the uplink daughter card.

Performing the network packet rate limit on the uplink interface of the switch chip and the uplink subcard includes: classifying the network packet from the uplink interface; and classifying according to the network packet The network packet is limited in speed.

According to another aspect of the present invention, there is further provided a data processing apparatus, comprising: a configuration module 22 configured to configure parameters of an interface between a switch chip and a processing chip according to predetermined parameters, such that all from the The ES packets of the switch chip can reach the processing chip within a predetermined time; wherein The predetermined parameter includes at least: a total number of lines of the DSL; and the distribution module 24 is configured to distribute the received ES message by using an ES message branch added in the receiving processing interface in the processing chip.

In a case where the rate of the interface is a first threshold range, the predetermined parameter includes only: a total number of lines of the DSL; and/or, in a case where the rate of the interface is a second threshold range, the predetermined The parameters also include: the capacity of the CPU.

The configuration module is further configured to configure a FIFO depth of an interface between the switch chip and the processing chip according to the predetermined parameter.

The apparatus further includes: an adjustment module 26 configured to estimate a maximum burst amount of the ES message within a predetermined duration according to the predetermined parameter, and to pass the interface to the processing chip according to the burst amount Send the rate limit value of the ES packet to adjust.

The distribution module 24 includes: a verification unit 32 configured to check the received message; and a determination unit 34 configured to determine whether the message is the ES message for the message whose verification result is legal; 36. Set, in the case that the determination result is yes, distribute the ES message by using the branch for processing the ES message.

The device further includes a rate limiting module 28 configured to limit the network packet to the uplink interface connected to the switch chip and the uplink daughter card.

The rate limiting module 28 includes: a classifying unit 42 configured to classify the network packet from the uplink interface; and the rate limiting unit 44 is configured to limit the network packet according to the classification of the network packet speed.

The embodiment of the present invention configures parameters of an interface between a switch chip and a processing chip (CPU) according to a predetermined parameter, so that all ES messages from the switch chip can reach the processing chip within a predetermined time; The predetermined parameter includes at least: the total number of lines of the DSL; and the received ES message is distributed by the ES packet branch added in the receiving processing interface in the processing chip, and the precoding report in the vector technology in the prior art is solved. The problem caused by a large number of bursts in a short period of time, which improves the distribution and processing priority of ES packets in the processing chip, and improves the processing of ES messages in the specified time of the protocol to some extent. possibility.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a flow chart of a data processing method according to an embodiment of the present invention;

2 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention;

3 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention;

4 is a block diagram 2 of a data processing apparatus according to an embodiment of the present invention;

FIG. 5 is a block diagram 3 of a data processing apparatus according to an embodiment of the present invention; FIG.

6 is a structural block diagram 4 of a data processing apparatus according to an embodiment of the present invention;

7 is a schematic diagram of a general system architecture and a BLV implementation of an MDU-type VDSL2 access device according to an embodiment of the present invention;

8 is a flowchart of a general system architecture and a BLV implementation of an MDU-type VDSL2 access device according to an embodiment of the present invention;

FIG. 9 is a flowchart of a CPU port parameter optimization method according to an embodiment of the present invention; FIG.

FIG. 10 is a flowchart of a method for adding an ES packet processing branch according to an embodiment of the present invention; FIG.

FIG. 11 is a flowchart of a method for implementing network packet rate limiting on an interface connected to a switch and an uplink daughter card according to an embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

A data processing method is provided in this embodiment. FIG. 1 is a flowchart of a data processing method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:

Step S102, configuring parameters of the interface between the switch chip and the processing chip according to the predetermined parameter, so that all ES messages from the switch chip can reach the processing chip within a predetermined time; wherein the predetermined parameters include at least: DSL Total number of lines;

Step S104: The received ES message is distributed by the ES packet branch added in the receiving processing interface in the processing chip.

Through the above steps, the parameters of the interface between the switch chip and the processing chip are configured according to predetermined parameters. Compared with the prior art, the parameters of the interface between the switch chip and the processing chip are fixed values, resulting in the vector technology. The problem that the pre-coded message has a large number of bursts in a short time and must be processed within a specified time can enable all ES messages from the switch chip to reach the processing chip within a predetermined time and receive the chips through the processing chip. The ES packets added to the interface are used to distribute the received ES packets. This improves the distribution and processing priorities of the ES packets on the processing chip. This improves the processing of ES packets in the time specified by the protocol. possibility.

In the above step S102, the basis for configuring the parameters of the interface between the switch chip and the processing chip is described. The basis for configuring the parameters of the interface between the switch chip and the processing chip may be various. This is illustrated below. In an optional embodiment, in the case that the rate of the interface is in the first threshold range, the predetermined parameter includes only: the total number of lines of the DSL; in another optional embodiment, the rate at the interface is the second threshold. In the case of the range, the predetermined parameters include not only the total number of DSL lines, but also the capability of the processing chip. These two alternative embodiments can be used alone or in combination.

In an alternative embodiment, configuring the parameters of the interface between the switch chip and the processing chip includes configuring the FIFO depth of the interface between the switch chip and the processing chip. For example, it may be an almost_full parameter, but there may be differences in parameters of different types of switch chips.

In order to enable all ES messages from the switch chip to reach the processing chip within a predetermined time, in an alternative embodiment, after the parameters of the interface between the switch chip and the processing chip are configured according to predetermined parameters, according to the reservation The parameter estimates the maximum burst amount of the ES packet in the predetermined duration, and adjusts the rate limit value of the ES packet sent to the processing chip through the interface according to the burst amount.

The embodiment of the present invention relates to a technical solution for effectively processing an ES packet. Therefore, in an optional embodiment, the priority of the branch for processing the ES packet is the highest priority, so that the ES packet can be ensured. Get priority treatment.

In order to quickly distribute the ES packets to the DSL driver and ensure the smooth running of the service, in an optional embodiment, distributing the received ES packets through the ES packet branch includes: checking the received packets. If the packet is a valid packet, the packet is judged to be an ES packet. If the result is YES, the ES packet is distributed through the ES packet branch.

The network packet rate limit is caused by the uplink interface of the switch chip and the uplink daughter card in an optional embodiment, because the network packet is over-processed and the processing load of the system is affected, thereby affecting the sending rate and processing capability of the ES packet. . Specifically, in another optional embodiment, the network packets from the uplink interface are classified, and the network packets are rate-limited according to the classification of the network packets. Of course, other methods for limiting the speed of the network packet can be used for the uplink interface that can be connected to the switch chip and the uplink daughter card, and details are not described herein. Finally, the network packet is restricted by the existing rules of the switch chip, so that the ES packet is discarded or the processing timeout is caused by the network packet impact, and finally the validity of the vector function is ensured.

In this embodiment, a data processing device is further provided, and the device is configured to implement the foregoing method. The descriptions of the modules in the following devices are not described herein. The functionality of the modules described below can be implemented by a processor.

2 is a structural block diagram of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 2, the apparatus includes: a configuration module 22 configured to configure parameters of an interface between a switch chip and a processing chip according to predetermined parameters, So that all the ES messages from the switch chip can reach the processing chip within a predetermined time; wherein the predetermined parameters include at least: the total number of lines of the DSL; the distribution module 24 is connected to the configuration module 22, and is configured to pass through the processing chip. The ES packet branch added to the receiving processing interface distributes the received ES packet.

Optionally, if the rate of the interface is the first threshold, the predetermined parameter includes only: the total number of lines of the DSL; and/or, if the rate of the interface is the second threshold, the predetermined parameter further includes: CPU's ability to withstand.

Optionally, the configuration module 22 is further configured to configure the FIFO depth of the interface between the switch chip and the processing chip.

3 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 3, the apparatus further includes: an adjustment module 26 configured to estimate a maximum burst of the ES message within a predetermined duration according to a predetermined parameter. The amount is adjusted according to the burst amount to the rate limit value of sending the ES packet to the processing chip through the interface.

Optionally, the priority of the branch for processing the ES packet is the highest priority.

4 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 4, the distribution module 24 includes: a checking unit 32 configured to check a received message; and a determining unit 34 configured to be Check The result of the test is a legal message to determine whether the message is an ES message; the distribution unit 36 is configured to distribute the ES message through the branch for processing the ES message if the judgment result is yes. .

FIG. 5 is a block diagram 3 of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 5, the apparatus further includes: a rate limiting module 28 configured to network the uplink interface of the switch chip and the uplink daughter card. Package speed limit.

6 is a structural block diagram of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 6, the speed limit module 28 includes: a classification unit 42 configured to classify the network packet from the uplink interface; 44, set to limit the network packet according to the classification of the network packet.

In order to implement BLV in a small multi-user access device of the MDU type, the following method is proposed to satisfy the goal of implementing the BLV by the MDU type access device. FIG. 7 is a schematic diagram of a general system architecture and a BLV implementation of an MDU-type VDSL2 access device according to an embodiment of the present invention. As shown in FIG. 7, to implement BLV on an MDU-type VDSL2 access device, the following requirements should be met:

1) The processing chip (CPU) is used for both system control and ES operation to ensure that the ES packet is processed within the expected time;

2) Minimize the impact of large-flow ES packet impact processing chips on normal business functions;

According to the above requirements, an implementation scheme and system for supporting a board-level vector of an MDU-type VDSL2 access device are proposed in the preferred embodiment, and the interface parameters connected to the CPU are optimized by the switch chip to avoid ES packets. Packet loss, and the priority of the distribution and processing of ES packets in the CPU, ensuring that ES packets can be processed within the time specified by the protocol, and finally restricting network packets through the existing rules of the switch to avoid network packet impact. The ES packet is discarded or the processing timeout expires, and finally the validity of the vector function is ensured.

The main advantages of this alternative embodiment:

1) Using the existing device implementation, there is no need to add a VECTORING Control Engine (VCE) sub-card, and no hardware modification is required;

2) Basically no impact on other services of the system;

The preferred embodiment will be described below with reference to the accompanying drawings:

In this alternative embodiment, an implementation scheme of an MDU-type VDSL2 access device supporting BLV is first provided, which specifically refers to a software optimization to solve the BLV ES packet large-flow fast processing requirement and the maximum speed limit reduction ES report. The impact of the impact of the text on other businesses of the system.

FIG. 8 is a flowchart of a general system architecture and a BLV implementation of an MDU-type VDSL2 access device according to an embodiment of the present invention. As shown in FIG. 8, the specific steps are as follows:

Step S802: By optimizing the parameters of the connection port between the switch and the CPU (hereinafter referred to as the CPU port), it is ensured that the transmission requirement of the ES message can be satisfied when the link rate is 100M/1000M. For example, all ES packets need to be sent and sent within 64 ms, and the ES packets are proportional to the total number of lines. The more lines, the more ES packets in 64 ms, so you need to optimize the parameters of the CPU port to ensure all the parameters. The ES message can be sent to the CPU within the specified time.

Step S804: After receiving the ES message sent by the switch, the CPU also needs to complete the processing within a certain period of time, for example, quickly distributes to the DSL driver for vector calculation for crosstalk cancellation within 64 ms. In order to meet the requirements of the distribution of fast ES packets and the requirements of other services, we add the ES packet distribution branch to the receiving and processing interface of the CPU, and place this branch at the highest priority.

Step S806: For a system in which only one Media Independent Interface (MII) port is connected between the switch and the CPU, the ES message is interspersed throughout the life cycle of the link establishment and chain establishment, so the network is reduced. If the packet is too large and the system is burdened, which affects the sending rate and processing capacity of the ES packet, we need to apply the corresponding network packet rate limit on the interface connected to the uplink card to swicth, and reduce the impact of the network packet on the system. The smallest.

In order to optimize the configuration of the switch and CPU port parameters, the present alternative embodiment provides a preferred manner. FIG. 9 is a flowchart of a CPU port parameter optimization method according to an embodiment of the present invention. As shown in FIG. 9, the specific steps are as follows:

Step S902: Perform different branch processing according to the CPU port establishment rate;

Step S904: When the CPU port construction rate in the above step S902 is 100 M, the FIFO parameters of the CPU port are optimized according to the total number of DSL lines, so that the CPU port can cope with the multi-line ES packet burst scenario, and the ES message can be ensured. All delivered to the CPU;

Step S906: When the CPU port establishment rate in the above step S902 is 1000M, the FIFO parameters of the CPU port are optimized according to the total number of lines of the DSL and the bearing capacity of the CPU, so that the CPU port can cope with the burst scenario of the multi-line ES packet. , to ensure that the ES message can be delivered to the CPU, and does not exceed the processing limit of the CPU;

Step S908: Estimate the maximum burst amount in the ES packet 1s according to the total number of lines of the DSL, thereby guiding the adjustment of the CPU port outbound speed limit value.

In order to quickly distribute ES messages and make various services go smoothly, this alternative embodiment provides a preferred manner. FIG. 10 is a flowchart of a method for adding an ES packet processing branch according to an embodiment of the present invention. As shown in FIG. 10, the specific steps are as follows:

Step S1002: The system CPU receives the packet forwarded by the CPU port of the switch;

Step S1004: Perform a legality check on the packet received in the above step S1002; mainly verify the hardware address (Media Access Control, MAC address) of the packet, the IP legality, the correctness of the corresponding checksum, and the like;

Step S1006: Perform a discarding action on the packet that is illegal in the above step S1004, and perform corresponding error reporting statistics;

Step S1008: For the packet with the normal inspection fee in the above step S1004, the packet is distributed according to the virtual eth port;

Step S1010: Perform corresponding processing on the packet belonging to the eth0 port in the above step S1008;

Step S1012: Perform corresponding processing on the packet belonging to the eth1 port in the above step S1008;

Step S1014: Perform corresponding processing on the packet belonging to the eth2 port in the above step S1008;

Step S1016: For the packet of the eth2 port in the foregoing step S1014, specifically, the ES packet is preferentially processed, and first, according to the destination MAC, whether it is an ES packet;

Step S1018: The original normal process is performed for the packet that is determined to be non-ES in the foregoing step S1016;

Step S1020: Perform a separate ES distribution process for the message determined to be ES in the above step S1016.

In order to reduce the system burden caused by excessive network packets, thereby affecting the transmission rate and processing capability of the ES packets, the optional embodiment provides a preferred manner. FIG. 11 is a flowchart of a method for implementing network packet rate limiting on an interface connected to a switch and an uplink daughter card according to an embodiment of the present invention. As shown in FIG. 11, the specific steps are as follows:

Step S1102: The switch on the switch receives the data packet sent by the network side.

Step S1104: classify network packets received by the uplink port in step S1102.

Step S1106: The rate limit of the ARP packet is determined according to the rate limit of the ARP packet, and the rate limit unit is pps, and the speed limit value can be matched.

Step S1108: The rate limit of the DHCP/IGMP packet is determined according to the rate limit of the DHCP/IGMP packet, and the rate limit unit is pps, and the rate limit value can be configured;

In the step S1110, the rate limit is kbps and the rate limit value can be configured according to the special ACL rule applied by the uplink port for the other network packets that are determined to be non-ARP/DHCP/IGMP in the step S1104.

Industrial applicability:

The present invention relates to the field of communications, and provides a data processing method and apparatus, wherein the method includes: configuring parameters of an interface between a switch chip and a processing chip according to a predetermined parameter, so that all ES messages from the switch chip can be configured. The processing chip is reached within a predetermined time; wherein the predetermined parameter includes at least: a total number of lines of the DSL; and the received ES message is distributed by the ES packet branch added in the receiving processing interface in the processing chip. The problem that the pre-coded message in the vector technology in the prior art has a large number of bursts in a short time is solved, thereby improving the distribution and processing priority of the ES packet in the processing chip, and improving the ES to some extent. The message can handle the possibility of completion within the time specified in the agreement.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

A data processing method comprising:

Arranging parameters of the interface between the switch chip and the processing chip according to predetermined parameters, so that all error sampling ES messages from the switch chip can reach the processing chip within a predetermined time; wherein the predetermined parameter is at least Including: the total number of lines of the digital subscriber loop DSL;

The received ES message is distributed by the ES packet branch added to the receiving processing interface in the processing chip.
The method of claim 1, wherein configuring parameters of the interface between the switch chip and the processing chip according to the predetermined parameter comprises:

Where the rate of the interface is a first threshold range, the predetermined parameter includes only: the total number of lines of the DSL; and/or,

In a case where the rate of the interface is a second threshold range, the predetermined parameter further includes: a capability of the processing chip.
The method of claim 1, wherein configuring parameters of the interface between the switch chip and the processing chip comprises:

The first in first out queue FIFO depth of the interface between the switch chip and the processing chip is configured.
The method according to claim 1 or 2, wherein after the parameter of the interface between the switch chip and the processing chip is configured according to the predetermined parameter, the method further comprises:

Estimating, according to the predetermined parameter, a maximum burst amount of the ES message within a predetermined duration;

And adjusting, according to the burst quantity, a rate limit value for sending the ES message to the processing chip by using the interface.
The method of claim 1, wherein the priority of the branch for processing the ES message is the highest priority.
The method of claim 1, wherein distributing the received ES message by using the ES packet branch comprises:

Check the received message;

Determining whether the message is the ES message of the packet whose test result is legal;

If the result of the determination is yes, the ES message is distributed by the ES packet branch.
The method of any of claims 1 to 6, wherein the method further comprises:

The network packet is limited to the uplink interface connected to the switch chip and the uplink daughter card.
The method of claim 7, wherein the performing network packet rate limiting on the uplink interface of the switch chip and the uplink subcard comprises:

Classifying the network packets from the uplink interface;

The network packet is limited in speed according to the classification of the network packet.
A data processing device comprising:

a configuration module configured to configure parameters of an interface between the switch chip and the processing chip according to a predetermined parameter, so that all ES messages from the switch chip can reach the processing chip within a predetermined time; The predetermined parameters include at least: the total number of lines of the DSL;

The distribution module is configured to distribute the received ES message by using an ES packet branch added in the receiving processing interface in the processing chip.
The apparatus according to claim 9, wherein the configuration module is further configured to: if the rate of the interface is a first threshold range, the predetermined parameter only includes: a total number of lines of the DSL; and / Or, in a case that the rate of the interface is a second threshold range, the predetermined parameter further includes: a capability of the CPU.
The apparatus of claim 9, wherein the configuration module is further configured to configure a FIFO depth of an interface between the switch chip and the processing chip.
The device according to claim 9 or 10, wherein the device further comprises:

And an adjusting module, configured to estimate, according to the predetermined parameter, a maximum burst amount of the ES packet within a predetermined duration, and send the ES packet to the processing chip by using the interface according to the burst amount The speed limit value is adjusted.
The apparatus of claim 9, wherein the priority of the branch for processing the ES message is the highest priority.
The apparatus of claim 9 wherein said distribution module comprises:

The verification unit is configured to check the received message;

a judging unit, configured to determine whether the packet is a valid packet, and whether the packet is the ES packet;

The distribution unit is configured to distribute the ES message by using the branch for processing the ES message if the determination result is yes.
The device according to any one of claims 9 to 14, wherein the device further comprises:

The speed limit module is configured to limit the network packet to the uplink interface connected to the switch chip and the uplink daughter card.
The apparatus of claim 15 wherein said rate limiting module comprises:

a classifying unit configured to classify the network packet from the uplink interface;

The speed limit unit is configured to limit the network packet according to the classification of the network packet.