WO2015173958A1

WO2015173958A1 - Communication system, information processing device, and communication control method

Info

Publication number: WO2015173958A1
Application number: PCT/JP2014/063097
Authority: WO
Inventors: 徹吉永
Original assignee: 富士通株式会社
Priority date: 2014-05-16
Filing date: 2014-05-16
Publication date: 2015-11-19
Also published as: JP5962861B2; JPWO2015173958A1

Abstract

In order to reliably complete a connection process, a second information processing device (20) is provided with a second detection unit (122) that detects a connection to a first reception unit (131) in a first information processing device (10) and said first information processing device (10) is provided with a first detection unit (122) that detects a connection to a second reception unit (131) in the second information processing device (20), a first prevention unit (14, 123) that prevents the first detection unit (122) from detecting a connection to the second reception unit (131) when an initialization process for the first or second information processing device (10 or 20) is started, and a second prevention unit (14, 133) that prevents the second detection unit (122) from detecting a connection to the first reception unit (131) when an initialization process for the first or second information processing device (10 or 20) is started.

Description

Communication system, information processing apparatus, and communication control method

The present invention relates to a communication system, an information processing apparatus, and a communication control method.

In recent years, Peripheral Component Interconnect Express (PCI Express) has been used as an input / output (I / O) serial interface for server devices and the like.
FIG. 5 is a diagram schematically showing a functional configuration of a communication system as a conventional example.
A communication system 100a illustrated in FIG. 5 is provided in, for example, a server device, and includes a CPU 1a, a PCI Express card 2a, and a system control unit 3a. The CPU 1a and the system control unit 3a are communicably connected via an inter-integrated circuit (I2C) bus 32a, and the PCI Express card 2a and the system control unit 3a are also communicably connected via the I2C bus 32a.

The system control unit 3a resets and initializes each device (the CPU 1a and the PCI Express card 2a) via the I2C bus 32a (preprocessing for performing link-up such as initialization setting of internal registers provided in each device) Link up start instruction).
The CPU 1a includes a root complex 10a, and the root complex 10a is communicably connected to the PCI Express card 2a via a PCI Express Link 31a.

The PCI Express card 2a includes an end point 20a, and the end point 20a is communicably connected to the CPU 1a via the PCI Express link 31a.
The root complex 10a and the end point 20a are devices conforming to the PCI Express standard.
The physical layer of the root complex 10a and the endpoint 20a includes a Link Training and Status State Machine (LTSSM) that is a state machine that initializes the PCI Express link 31a. The LTSSM operates based on the PCI Express standard.

FIG. 6 is a diagram showing state transition of link-up processing in a communication system as a conventional example.
When initialization (reset) of the PCI Express link 31 a is performed, the LTSSM changes the link-up process to the Detect state 40. The Detect state 40 includes a Detect.quite state 41 and a Detect.active state 42 as substates.

When the LTSSM detects a link destination device via the PCI Express link 31a, the LTSSM transitions the link-up process to the polling state 50. The Polling state 50 includes a Polling.active state 51, a Polling.compliance state 52, and a Polling.configuration state 53 as substates. In the Polling state 50, the LTSSM transmits / receives an ordered set of training sequences to / from a link destination device. The training sequence is an initialization procedure for making the PCI Express link 31a usable. The LTSSM advances the link-up process in synchronization with the link-destination device by transmitting / receiving an order set corresponding to each state to / from the link-destination device.

When the LTSSM transitions the link-up process to the Configuration state 60, the LTSSM establishes the lane configuration of the PCI Express link 31a by transmitting and receiving a training sequence to and from the link destination device.
Then, the LTSSM shifts the link-up process to the L0 state 70 which is a normal state in which control packets and data packets can be transmitted and received.
JP 2011-248814 A Special table 2008-547362

The system control unit 3a initializes each device in turn, and each device starts link-up processing independently. For example, the PCI Express card 2a (end point 20a) starts the link-up process before the CPU 1a (root complex 10a). Since the initialization procedure of the root complex 10a and the endpoint 20a is not defined by the PCI Express specification, the timing for starting the link-up process varies depending on the device manufacturer. Further, the CPU 1a (root complex 10a) and the PCI Express card 2a (end point 20a) having different manufacturers may be mounted on one server device. In this case, the initialization procedure of each device cannot be changed, and the link-up process between the root complex 10a and the end point 20a is not executed synchronously.

Thus, for example, the end point 20a may transition to the link-up process in the polling state 50 before the root complex 10a. In this case, the LTSSM of the endpoint 20a cannot start the link-up process synchronized with the root complex 10a until the link-up process of the root complex 10a can transition to the polling state 50. For this reason, the LTSSM of the endpoint 20a repeatedly executes the link-up process in the Detect state 40 and the Polling state 50. Specifically, the LTSSM of the endpoint 20a can detect the existence of the root complex 10a, but detects the timeout because it cannot receive the ordered set of training sequences from the root complex 10a in the Polling state 50. When the LTSSM of the endpoint 20a detects a timeout, the LTSSM determines that the training sequence has failed, returns the link-up process to the Detect state 40, and tries to re-link up.

On the other hand, when both the LTSSM of the root complex 10a and the end point 20a have been able to transition the link-up process to the polling state 50, the LTSSM of each device can transmit and receive an order set of training sequences to each other. The LTSSM of each device executes link-up processing in synchronization with the order of the Polling.active state 51, the Polling.configuration state 53, the Configuration state 60, and the L0 state 70, and proceeds with initialization of the PCI Express link 31a. Can do.

Here, the Polling.compliance state 52 is a test state that does not need to transition in the normal normal operation of PCI Express. As described above, in the conventional communication system 100a, since each device does not execute the link-up process in synchronization with each other, the LTSSM of each device starts the link-up process independently. In this case, the LTSSM of the device that has previously transitioned to the Polling state 50 may transition to the Polling.compliance state 52 because the link-up process of the link destination device is the Detect state 40. When a failure or the like occurs in the test function in the Polling.compliance state 52 and the transition from the Polling.compliance state 52 to the next state cannot be made, the LTSSM of each device cannot perform link-up processing.

As described above, the conventional communication system 100a has a problem that normal operation cannot be performed when a failure or the like occurs in a test function in the initialization process of PCI Express.
In one aspect, the object is to reliably complete the connection process.

For this reason, this communication system is a communication system having first and second information processing apparatuses that are communicably connected to each other, and the second information processing apparatus is a first reception included in the first information processing apparatus. A second detection unit that detects connection with a first detection unit, wherein the first information processing device includes a first detection unit that detects connection with a second reception unit included in the second information processing device, and the first or A first deterrence unit for deterring detection of a connection with the second reception unit by the first detection unit, and an initialization process of the second information processing device; A second deterring unit that deters detection of connection with the first receiving unit by the second detecting unit when starting the initialization process;

According to the disclosed communication system, the connection process can be completed reliably.

It is a figure which shows typically the function structure of the communication system as an example of embodiment. It is a figure which shows typically the function structure of the PCI Express device with which the communication system as an example of embodiment is provided. It is a flowchart which shows the communication control process in the communication system as an example of embodiment. (A) is a figure which illustrates the state transition when the link up process in the communication system as a conventional example is normally completed, and (b) is a failure during the link up process in the communication system as a conventional example. FIG. 6C is a diagram illustrating state transitions in the communication system as an example of the present embodiment. It is a figure which shows typically the function structure of the communication system as a prior art example. It is a figure which shows the state transition of the link up process in the communication system as a prior art example.

Hereinafter, an embodiment according to a communication system, an information processing apparatus, and a communication control method will be described with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment.
Each figure is not intended to include only the components shown in the figure, and may include other functions.

Hereinafter, in the drawings, the same reference numerals indicate the same parts, and the description thereof is omitted.
[A] Example of Embodiment [A-1] System Configuration FIG. 1 is a diagram schematically showing a functional configuration of a communication system as an example of the embodiment, and FIG. 2 is provided in the communication system as an example of the embodiment. It is a figure which shows typically the function structure of a PCI Express device.

1 is provided in, for example, a server device, and includes a route complex (first information processing device) 10, an endpoint (second information processing device) 20, and a system control unit 3. The route complex 10 and the system control unit 3 are communicably connected via the I2C bus 32, and the endpoint 20 and the system control unit 3 are also communicably connected via the I2C bus 32.

In an example of the present embodiment, the root complex 10 and the end point 20 are provided on a CPU and a PCI Express card (not shown), respectively. As shown in FIG. 1, the root complex 10 and the end point 20 are connected by a PCI Express link 31, so that the CPU and the PCI Express card can communicate with each other.
Further, on the PCI Express link 31, for example, a coupling capacitor 33 is provided.

The system control unit 3 uses the I2C bus 32 to reset and initialize each device (the root complex 10 and the endpoint 20) (before performing link-up processing such as initialization setting of internal registers included in each device). Process and link-up process start instruction).
Hereinafter, the processing in the Detect state 40, Polling state 50, Configuration state 60, and L0 state 70 shown in FIG. 6 may be collectively referred to as “link-up processing”. In addition, the process in the Detect state 40 during the “link up process” may be particularly referred to as “initialization process”.

Specifically, when resetting the root complex 10 or the endpoint 20, the system control unit 3 sends a signal “1” (hereinafter referred to as “receiver detection suppression” to a Flip-Flop (FF) 14 described later included in the root complex 10. In some cases, such as “mode setting”. That is, the system control unit 3 sets the receiver detection inhibition mode by inputting the signal “1” to the FF 14.

Further, the system control unit 3 sends a signal “0” (hereinafter referred to as “receiver detection inhibition mode”) to the FF 14 when the link-up process in the route complex 10 becomes a state in which transition to the polling state 50 (see FIG. 6) is possible. In some cases, such as “Release”, etc.). That is, the system control unit 3 cancels the receiver detection inhibition mode by inputting the signal “0” to the FF 14.

As shown in FIG. 2, the root complex 10 and the endpoint 20 have a Physical Layer 101, a Data Link Layer 102, and a Transaction Layer as layers for performing communication conforming to the PCI Express standard. (Transaction layer) 103 is provided. In the example shown in FIG. 2, the system control unit 3 is not shown for simplicity.

The transaction layer 103 generates and decrypts Transaction Layer Packet (TLP), for example.
The data link layer 102 performs management, error detection, and correction of the PCI Express link 31, for example.
The physical layer 101 of the root complex 10 includes a logical sub-block (logical sub-block) 110 and a serializer / deserializer (SERDES; electrical sub-block) 120.

The logical sub block 110 includes the LTSSM 11. In addition to the LTSSM 11, the logical sub-block 110 includes the FF 14 shown in FIG. That is, the logical sub block 110 illustrated in FIG. 2 corresponds to the LTSSM 11 and the FF 14 of the root complex 10 illustrated in FIG. The functions of the LTSSM 11 and the FF 14 will be described later with reference to FIG.

The SERDES 120 includes a transmission device (TX) 12 and a reception device (RX) 13, and corresponds to the TX 12 and the RX 13 shown in FIG. A functional configuration included in the TX 12 and the RX 13 will be described later with reference to FIG.
The physical layer 101 of the endpoint 20 includes a logical sub block 210 and a SERDES 220.

The logical sub-block 210 includes the LTSSM 11 and corresponds to the LTSSM 11 of the endpoint 20 shown in FIG.
The SERDES 220 includes TX22 and RX23, and corresponds to TX22 and RX23 shown in FIG. A functional configuration of the TX 22 and the RX 23 will be described later with reference to FIG.

As shown in FIG. 2, the TX 12 of the root complex 10 is connected to the RX 23 of the endpoint 20 via a PCI Express link 31 so that data can be transmitted. The TX 22 of the end point 20 is connected to the RX 13 of the root complex 10 via the PCI Express link 31 so that data can be transmitted.
As shown in FIG. 1, the root complex 10 includes an LTSSM (management unit) 11, TX 12, RX 13, and FF 14 in the physical layer 101 shown in FIG.

The FF 14 is a logic circuit that temporarily holds 1-bit information in a “0” or “1” state.
Specifically, the FF 14 receives the signal “1” when set to the receiver detection inhibition mode from the system control unit 3. The FF 14 receives the signal “0” when the receiver detection inhibition mode is canceled from the system control unit 3.

Then, the FF 14 outputs a signal input from the system control unit 3 as an rcv_det_dis signal, and inputs the signal to an AND circuit 123 described later included in the TX 12 and a switch 133 described later included in the RX 13.
The RX 13 includes a receiver (first receiving unit) 131, two termination resistors (resistors) 132d and 132e, and two

switches

133d and 133e. Hereinafter, the two

termination resistors

132d and 132e may be collectively referred to as “termination resistor 132”, and the two

switches

133d and 133e may be collectively referred to as “switch 133”.

The receiver 131 is connected to a driver 121, which will be described later, included in the endpoint 20 via the PCI Express link 31. In the example shown in FIG. 1, as a specific configuration of the PCI Express link 31 between the receiver 131 of the root complex 10 and the driver 121 of the endpoint 20, a data transmission line 31d for transmitting a pair of differential signals and A data transmission line 31e is shown. The receiver 131 of the route complex 10 receives the data transmitted by the driver 121 of the endpoint 20 via the data transmission line 31d and the data transmission line 31e.

The termination resistor 132 is connected to the PCI Express link 31 and the power supply VDDR. Specifically, the termination resistor 132d has one end connected to the data transmission line 31d and the other end connected to the power supply VDDR. The termination resistor 132e has one end connected to the data transmission line 31e and the other end connected to the power supply VDDR.
The termination resistor 132 generates an impedance having a magnitude that allows a later-described receiver detection circuit 122 included in the endpoint 20 to detect the receiver 131 of the root complex 10.

The switch 133 is provided on a circuit between the termination resistor 132 and the PCI Express link 31. Specifically, the switch 133d is provided on a circuit between the termination resistor 132d and the data transmission line 31d, and the switch 133e is provided on a circuit between the termination resistor 132e and the data transmission line 31e.
The switch 133 is connected to the FF 14 and operates when an rcv_det_dis signal output from the FF 14 is input.

Specifically, the switch 133 is in a state (close) in which the termination resistor 132 is connected to the PCI Express link 31 when rcv_det_dis = 0, and the termination resistor 132 is connected to the PCI Express link 31 when rcv_det_dis = 1. It becomes the state (open) which does not let it. That is, the switch 133 invalidates the termination resistor 132 and invalidates the PCI Express link 31 when resetting the root complex 10 or the endpoint 20. As a result, the switch 133 suppresses detection of connection with the receiver 131 of the root complex 10 by the receiver detection circuit 122 of the endpoint 20. Further, the switch 133 validates the termination resistance when the link-up process in the root complex 10 can transition to the Polling state 50 (see FIG. 6).

That is, the FF 14 and the switch 133 function as a second suppression unit that suppresses detection of connection with the receiver 131 of the root complex 10 by the receiver detection circuit 122 of the endpoint 20 when the receiver detection suppression mode is set. The FF 14 and the switch 133 also function as a suppression release unit that cancels the suppression by the second suppression unit when the receiver detection suppression mode is canceled.

The TX 12 includes a driver (first transmission unit) 121, a receiver detection circuit (first detection unit) 122, and an AND circuit 123.
The driver 121 is connected to a later-described receiver 131 included in the endpoint 20 via the PCI Express link 31 and transmits data to the receiver 131. In the example shown in FIG. 1, as a specific configuration of the PCI Express link 31 between the driver 121 of the root complex 10 and the receiver 131 of the endpoint 20, a data transmission line 31d for transmitting a pair of differential signals and A data transmission line 31e is shown. The driver 121 of the route complex 10 transmits data to the receiver 131 of the endpoint 20 via the data transmission line 31d and the data transmission line 31e.

The receiver detection circuit 122 is connected to the PCI Express link 31 (the data transmission line 31d and the data transmission line 31e), and detects the connection with the receiver 131 included in the endpoint 20.
The receiver detection circuit 122 is connected to the AND circuit 123, and inputs a detection signal “1” to the AND circuit 123 when detecting the connection with the receiver 131 of the endpoint 20.

The AND circuit 123 is a 2-input / 1-output logic circuit.
Two input terminals of the AND circuit 123 are connected to the FF 14 and the receiver detection circuit 122, respectively. The FF 14 side input terminal of the AND circuit 123 inverts the rcv_det_dis signal output from the FF 14 and inputs the inverted signal to the AND circuit 123. That is, the AND circuit 123 takes a logical product of the inverted signal of the rcv_det_dis signal output from the FF 14 and the detection signal output from the receiver detection circuit 122.

An output terminal of the AND circuit 123 is connected to the LTSSM11, and a logical product obtained by two input signals is input to the LTSSM11 as an rcv_det signal.
Specifically, the AND circuit 123 sets an inverted signal “0” of the output signal rcv_det_dis = 1 of the FF 14 when the receiver detection inhibition mode is set and the receiver detection circuit 122 does not detect the receiver 131 of the endpoint 20. And the detection signal “0” output from the receiver detection circuit 122 is input. The AND circuit 123 calculates the logical product of the two input signals and inputs rcv_det = 0 to the LTSSM 11.

Further, the AND circuit 123 sets the inverted signal “0” of the output signal rcv_det_dis = 1 of the FF 14 and the receiver detection circuit 122 when the receiver detection suppression mode is set and the receiver detection circuit 122 detects the receiver 131 of the endpoint 20. The detection signal “1” output from is input. The AND circuit 123 calculates the logical product of the two input signals and inputs rcv_det = 0 to the LTSSM 11.

Furthermore, when the receiver detection inhibition mode is canceled and the receiver detection circuit 122 has not detected the receiver 131 of the endpoint 20, the AND circuit 123 detects the receiver signal that is the inverted signal “1” of the output signal rcv_det_dis = 0 of the FF14. The detection signal “0” output from the circuit 122 is input. The AND circuit 123 calculates the logical product of the two input signals and inputs rcv_det = 0 to the LTSSM 11.

The AND circuit 123 cancels the receiver detection suppression release mode, and when the receiver detection circuit 122 detects the receiver 131 of the endpoint 20, the inverted signal “1” of the output signal rcv_det_dis = 0 of the FF 14 and the receiver detection circuit The detection signal “1” output from 122 is input. The AND circuit 123 calculates the logical product of the two input signals and inputs rcv_det = 1 to the LTSSM 11.

That is, the FF 14 and the AND circuit 123 serve as a first deterrence unit that deters (masks) the detection of the connection with the receiver 131 of the endpoint 20 by the receiver detection circuit 122 of the root complex 10 when the receiver detection deterrence mode is set. Function. Further, the FF 14 and the AND circuit 123 also function as a suppression release unit that cancels the suppression (mask) by the first suppression unit when the receiver detection suppression mode is canceled.

The LTSSM 11 is a state machine that initializes the PCI Express link 31 and operates based on the PCI Express standard. In other words, the LTSSM 11 manages the initialization process of the route complex 10 and the link-up process (connection process) with the end point 20.
The LTSSM 11 is connected to the AND circuit 123 and receives the rcv_det signal from the AND circuit 123.

Then, when the input signal from the AND circuit 123 is rcv_det = 0, the LTSSM 11 prevents the link-up process in the route complex 10 from transitioning to the Polling state 50 (see FIG. 6). When the input signal from the AND circuit 123 is rcv_det = 1, the LTSSM 11 synchronizes the link-up process in the route complex 10 with the link-up process in the endpoint 20 and transitions to the Polling state 50 (see FIG. 6). Let

The LTSSM 11 receives the output signal rcv_det = 0 of the AND circuit 123 when the receiver detection inhibition mode is set. The LTSSM 11 receives the output signal rcv_det = 0 of the AND circuit 123 even when the receiver detection inhibition mode is canceled and the receiver detection circuit 122 has not detected the receiver 131 of the endpoint 20. Further, the LTSSM 11 receives the output signal rcv_det = 1 of the AND circuit 123 when the receiver detection suppression mode is canceled and the receiver detection circuit 122 detects the receiver 131 of the endpoint 20.

As illustrated in FIG. 1, the endpoint 20 includes the LTSSM 11, TX 22, and RX 23 in the physical layer 101 illustrated in FIG. 2.
The TX 22 includes a driver (second transmission unit) 121 and a receiver detection circuit (second detection unit) 122.
The RX 23 includes a receiver (second receiving unit) 131 and two termination resistors 132.

Thus, unlike the root complex 10, the end point 20 does not include the FF 14, the AND circuit 123, and the switch 133. However, since the end point 20 has the same functional configuration as that of the root complex 10 except that the end point 20 does not include the FF 14, the AND circuit 123, and the switch 133, detailed description thereof will be omitted.
[A-2] Operation A communication control process in the communication system as an example of the embodiment configured as described above will be described according to the flowchart (steps S1 to S4) shown in FIG.

The system control unit 3 issues a reset signal to the root complex 10 and the end point 20, and sets the root complex 10 to the receiver detection inhibition mode (step S1).
Specifically, the system control unit 3 inputs a signal “1” to the FF 14 of the root complex 10 via the I2C bus 32.

As a result, the FF 14 and the AND circuit 123 function as a first suppression unit that inputs the suppression signal “0” to the LTSSM 11. Then, the first deterrence unit deters the LTSSM 11 of the root complex 10 from shifting the link-up process of the root complex 10 to the polling state 50 (see FIG. 6).
The FF 14 and the switch 133 function as a second suppression unit that suppresses detection of connection with the receiver 131 of the root complex 10 by the receiver detection circuit 122 of the endpoint 20 by disabling the PCI Express link 31. Then, the second deterrence unit inhibits the LTSSM 11 of the end point 20 from transitioning the link-up process of the end point 20 to the polling state 50 (see FIG. 6).

The LTSSM 11 of the end point 20 executes the initialization process of the Detect state 40 (see FIG. 6) in the end point 20 (step S2).
Then, the LTSSM 11 of the root complex 10 executes an initialization process of the Detect state 40 (see FIG. 6) in the root complex 10 (step S3).
The root complex 10 and the endpoint 20 start the link-up process in the Detect state 40 (see FIG. 6), but cannot detect the partner receiver 131 because the receiver detection suppression mode is set. Therefore, the link up process of the root complex 10 and the endpoint 20 continues to remain in the Detect state 40 (see FIG. 6).

Note that the order of the processes shown in steps S2 and S3 may be reversed, or the processes shown in steps S2 and S3 may be performed simultaneously.
The system control unit 3 cancels the receiver detection inhibition mode when the link-up process of the root complex 10 becomes transitionable to the polling state 50 (see FIG. 6) (step S4).

Specifically, the system control unit 3 inputs a signal “0” to the FF 14 of the route complex 10 via the I2C bus 32. As a result, the FF 14 and the AND circuit 123 enable the detection signal output from the receiver detection circuit 122 of the root complex 10 so that the LTSSM 11 of the root complex 10 can recognize the detection signal. Further, the FF 14 and the switch 133 enable the PCI Express link 31 between the receiver 131 of the root complex 10 and the receiver detection circuit 122 of the endpoint 20. As described above, the FF 14, the AND circuit 123, and the switch 133 function as a suppression release unit that cancels the suppression by the first and second suppression units. Then, the suppression release unit synchronizes the respective link-up processes with the LTSSM 11 of the root complex 10 and the endpoint 20 and makes a transition to the Polling state 50 (see FIG. 6).

That is, the root complex 10 and the endpoint 20 can detect the receiver 131 of the other party because the receiver detection inhibition mode has been canceled. Then, the root complex 10 and the endpoint 20 transition to the link-up process in the polling state 50 (see FIG. 6) in synchronization with each other, and continue the link-up process.
[A-3] Effects Hereinafter, effects that can be achieved by the communication system 100 according to an example of the present embodiment will be described with reference to FIGS.

FIG. 4A is a diagram illustrating a state transition when the link-up process in the communication system as the conventional example is normally completed.
In the example shown in FIG. 4A, the link-up start timing of the route complex 10a and the endpoint 20a is shifted, and the link-up process of the endpoint 20a is performed before the link-up process of the route complex 10a. Transition to the state (see symbol A1). Here, if no failure or the like occurs in the end point 20a and the link up process of the root complex 10a transits to the Detect.active state (see reference A2), the link up process of the end point 20a is also detected in the Detect.active state (reference sign). (See A3). Then, the root complex 10a and the end point 20a can execute link-up processing in the polling state (see symbols A4 and A5) in synchronization with each other.

FIG. 4B is a diagram illustrating state transition when a failure occurs during link-up processing in a communication system as a conventional example.
In the example shown in FIG. 4B, in the link-up process of the end point 20a, a failure has occurred such as a transition condition from the Polling.compliance state (see reference numeral B1) to the next state cannot be detected. As a result, even if the link-up process of the root complex 10a can transition to the Detect.active state (see reference B2), the link-up process of the root complex 10a is performed in the Polling state (see reference B3), the Detect state (see reference B4). Will be repeated. Then, the route complex 10a and the end point 20a cannot complete the link-up process.

FIG. 4C is a diagram illustrating state transition in the communication system as an example of the present embodiment.
In the example shown in FIG. 4C, the second deterrence unit (FF 14 and switch 133) causes the link-up process of the endpoint 20 to transition from the Detect.active state (see C1) to the Polling.compliance state (not shown). Suppress it. As a result, the route complex 10 and the endpoint 20 link up in the polling state (see symbols C3 and C4) in synchronization with each other after the link-up process of the route complex 10 transitions to the Detect.active state (see symbol C2). Processing can be executed. That is, since the link-up process of the endpoint 20 does not transition to the Polling.compliance state (not shown), no problem occurs even if a failure or the like occurs in the test function executed in the Polling.compliance state. Then, the route complex 10 and the end point 20 can reliably complete the link-up process.

In the example of this embodiment, when the root complex 10 executes the link-up process in the Detect.active state before the end point 20, the function of the first deterrence unit (FF 14 and AND circuit 123) The same effect as described with reference to FIG. 4C can be obtained. That is, the first inhibition unit (FF 14 and AND circuit 123) inhibits the link-up process of the root complex 10 from transitioning from the Detect.active state to the Polling.compliance state. Thereby, similarly to the example shown in FIG. 4C, the root complex 10 and the end point 20 can reliably complete the link-up process.

Thus, according to the communication system 100 in the exemplary embodiment described above, the following effects can be achieved.
The first suppression unit (FF 14 and AND circuit 123) detects the connection with the second reception unit 131 by the first detection unit 122 when starting the initialization process of the first or second

information processing device

10 or 20. Is suppressed. The second deterring unit (FF 14 and switch 133) is connected to the first receiving unit 131 by the second detecting unit 122 when starting the initialization process of the first or second

information processing apparatus

10 or 20. Suppress detection. As a result, the communication system 100 can reliably complete the connection process.

The

first deterrence units

14 and 123 perform deterrence by preventing the first detection unit 122 from inputting a detection signal indicating that the connection with the second reception unit 131 has been input to the management unit 11. As a result, the link-up process of the first information processing apparatus 10 continues to remain in the Detect state until the transition condition to the Polling state is satisfied in the link-up process of the second information processing apparatus 20, and transits to the Polling.compliance state. There is no. The first information processing apparatus 10 and the second information processing apparatus 20 reliably complete the link-up process even if a failure or the like occurs in the test function executed in the Polling.compliance state of the root complex 10. Can be made.

The second deterrence units 14 and 133 perform deterrence by invalidating the communication path 31 between the first reception unit 131 and the second detection unit 122. As a result, the link-up process of the second information processing apparatus 20 continues to remain in the Detect state until the transition condition to the Polling state is satisfied in the link-up process of the first information processing apparatus 10, and transits to the Polling.compliance state. There is no. Even if a failure or the like occurs in the test function executed in the Polling.compliance state of the second information processing apparatus 20, the first information processing apparatus 10 and the endpoint 20 reliably complete the link-up process. Can be made.

The deterrence cancellation unit (FF14, AND circuit 123 and switch 133) cancels the deterrence by the first and

second deterrence units

14, 123, 133 when the initialization process of the first information processing apparatus 10 is completed. Thereby, the first detection unit 122 can detect the connection with the second reception unit 131, and the second detection unit 122 can detect the connection with the first reception unit 131. Then, the first and second

information processing apparatuses

10 and 20 make the link-up process transition to the Polling.configuration state in synchronization with each other without causing the link-up process to transition to the Polling.compliance state, and continues the link-up process. can do.

Moreover, in the example of the above-described embodiment, the first and second

information processing apparatuses

10 and 20 have the function as the first and second deterring

units

14, 123, 133 mounted on the first

information processing apparatus

10, 20. And the link-up process of the 2nd

information processing apparatus

10 and 20 can be performed synchronously mutually. Therefore, for example, even when the configuration of the second information processing device 20 cannot be changed, the above-described effects can be obtained by causing the first information processing device 10 to implement the functions as the first and second deterring

units

14, 123, and 133. Can play.

[B] Others The disclosed technology is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present embodiment. Each structure and each process of this embodiment can be selected as needed, or may be combined suitably.
In the example of the embodiment described above, the root complex 10 serves as the first inhibition unit (FF14 and AND circuit 123), the second inhibition unit (FF14 and switch 133), and the inhibition release unit (FF14, AND circuit 123 and switch 133). However, the present invention is not limited to this. The end point 20 may have a function as a first inhibition unit (FF14 and AND circuit 123), a second inhibition unit (FF14 and switch 133), and an inhibition release unit (FF14, AND circuit 123 and switch 133).

In the example of the embodiment described above, the communication system 100 includes the root complex 10 and the endpoint 20, and the root complex 10 and the endpoint 20 are provided on a CPU and a PCI Express card (not shown), respectively. It is not limited to this. The communication system 100 may include any two or more devices that conform to the PCI Express standard. One of the devices functions as the above-described first suppression unit (FF14 and AND circuit 123), second suppression unit (FF14 and switch 133), and suppression cancellation unit (FF14, AND circuit 123 and switch 133). May be.

Furthermore, in the example of the above-described embodiment, the communication system 100 includes the route complex 10 and the end point 20 that conform to the PCI Express standard, but is not limited thereto. The communication system 100 may include two or more various devices that conform to a standard other than the PCI Express standard and have states corresponding to the Detect state and the Polling state of the PCI Express standard in the link-up process.

In the example of the embodiment described above, the FF 14, the AND circuit 123, and the switch 133 function as the first deterrence unit, the second deterrence unit, and the deterrence release unit, but the present invention is not limited to this. In the communication system 100 shown in FIG. 1, a switch is provided on the PCI Express link 31 between TX12 and RX23 and between TX22 and RX13 so that the system control unit 3 operates the switch on the PCI Express link 31. Anyway. The system control unit 3 sets and cancels the receiver detection inhibition mode by operating a switch on the PCI Express link 31.

As described above, even if the communication system 100 in the example of the embodiment described above is variously modified, the same effect as that of the communication system 100 in the example of the embodiment described above can be obtained.

100 communication system 10 route complex (first information processing apparatus)
11 LTSSM (Management Department)
12 TX (Transmitter)
121 driver (first transmitter, second transmitter)
122 Receiver detection circuit (first detection unit, second detection unit)
123 AND circuit (first suppression unit, suppression cancellation unit)
13 RX (receiving device)
131 Receiver (first receiver, second receiver)
132 Terminating resistor (resistor)
133 switch (second deterrence unit, deterrence release unit)
14 FF (first deterrence unit, second deterrence unit, deterrence release unit)
20 Endpoint (second information processing device)
22 TX (Transmitter)
23 RX (receiving device)
3 System controller 31 PCI Express link (communication path)
31d Data transmission line 31e Data transmission line 32 I2C bus 33 Coupling capacitor 101 Physical layer 102 Data link layer 103 Transaction layer 110 Logical sub-block 120 SERDES
100a communication system 1a CPU
10a Root Complex 2a PCI Express Card 20a Endpoint 3a System Control Unit 31a PCI Express Link 32a I2C Bus 40 Detect State 41 Detect.quite State 42 Detect.active State 50 Polling State 51 Polling.active State 52 Polling.compliance State 53 Polling. Configuration state 60 Configuration state 70 L0 state

Claims

A communication system having first and second information processing apparatuses that are communicably connected to each other,
The second information processing apparatus
A second detector for detecting a connection with a first receiver included in the first information processing apparatus;
The first information processing apparatus
A first detector that detects a connection with a second receiver included in the second information processing apparatus;
A first deterring unit that deters detection of connection with the second receiving unit by the first detecting unit when starting the initialization process of the first or second information processing apparatus;
A second deterring unit that deters detection of connection with the first receiving unit by the second detecting unit when starting the initialization process of the first or second information processing apparatus;
A communication system comprising:
The first information processing apparatus includes a management unit that manages initialization processing of the first information processing apparatus and connection processing between the second information processing apparatus,
When the first detection unit detects a connection with the second reception unit, the first detection unit inputs a detection signal indicating that the connection with the second reception unit is detected to the management unit,
The first suppression unit performs the suppression by blocking the detection signal from being input to the management unit.
The communication system according to claim 1, wherein:
The second suppression unit performs the suppression by invalidating a communication path between the first reception unit and the second detection unit.
The communication system according to claim 1, wherein the communication system is characterized.
The first information processing apparatus includes a resistor on the communication path for generating an impedance having a magnitude that allows the second detection unit to detect connection with the first reception unit,
The second suppression unit performs the invalidation by disconnecting the connection between the resistor and the communication path.
The communication system according to claim 3, wherein:
5. The deterrence canceling unit for canceling the deterrence by the first and second deterrence units when the initialization process of the first information processing apparatus is completed. The communication system according to 1.
The communication between the first information processing apparatus and the second information processing apparatus is PCI Express.
The communication system according to any one of claims 1 to 5, characterized in that:
An information processing apparatus that is communicably connected to another information processing apparatus,
A detection unit that detects a connection with a second reception unit included in the other information processing apparatus;
A first deterring unit that deters detection of a connection with the second receiving unit by the detecting unit when starting an initialization process of the information processing apparatus or the other information processing apparatus;
A second deterrence unit that deters detection of a connection with the first receiver included in the information processing apparatus by the other information processing apparatus when starting the initialization process of the information processing apparatus or the other information processing apparatus When,
An information processing apparatus comprising:
A management unit that manages initialization processing of the information processing device and connection processing between the other information processing devices;
When the detection unit detects the connection with the second reception unit, the detection unit inputs a detection signal indicating that the connection with the second reception unit is detected, to the management unit,
The first suppression unit performs the suppression by blocking the detection signal from being input to the management unit.
The information processing apparatus according to claim 7, wherein:
The second suppression unit performs the suppression by invalidating a communication path between the first reception unit and the other information processing apparatus.
The information processing apparatus according to claim 7 or 8, characterized by the above.
The information processing apparatus includes a resistor on the communication path for generating an impedance having a magnitude that allows the other information processing apparatus to detect the connection with the first receiving unit.
The second suppression unit performs the invalidation by disconnecting the connection between the resistor and the communication path.
The information processing apparatus according to claim 9.
11. The deterrence canceling unit for canceling the deterrence by the first and second deterrence units when the initialization process of the information processing apparatus is completed. Information processing device.
Communication between the information processing apparatus and the other information processing apparatus is PCI Express.
The information processing apparatus according to any one of claims 7 to 11, characterized in that:
A communication control method in a communication system having first and second information processing apparatuses that are communicably connected to each other,
The second information processing apparatus
Detecting a connection with the first receiving unit of the first information processing apparatus;
The first information processing apparatus
Detecting a connection with a second receiving unit of the second information processing apparatus;
When the initialization process of the first or second information processing apparatus is started, detection of connection with the second receiving unit is suppressed,
When the initialization process of the first or second information processing apparatus is started, detection of connection with the first reception unit is suppressed.
A communication control method.
The first information processing apparatus
A management unit for managing initialization processing of the first information processing apparatus and connection processing between the second information processing apparatus;
When detecting the connection with the second receiving unit, a detection signal indicating that the connection with the second receiving unit is detected is input to the management unit,
The inhibition is performed by preventing the detection signal from being input to the management unit.
The communication control method according to claim 13, wherein:
The first information processing device performs the suppression by invalidating a communication path between the first reception unit and the second information processing device.
The communication control method according to claim 13 or 14, characterized by the above.
The first information processing apparatus
On the communication path, the second information processing apparatus includes a resistor for generating an impedance having a magnitude capable of detecting connection with the first receiving unit,
The invalidation is performed by disconnecting the resistor and the communication path.
The communication control method according to claim 15, wherein:
The first information processing apparatus cancels the suppression when the initialization process of the first information processing apparatus is completed.
The communication control method according to any one of claims 13 to 16, characterized in that:
The communication between the first information processing apparatus and the second information processing apparatus is PCI Express.
The communication control method according to any one of claims 13 to 17, characterized in that: