WO2015173889A1 - Dispositif de stockage - Google Patents

Dispositif de stockage Download PDF

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Publication number
WO2015173889A1
WO2015173889A1 PCT/JP2014/062714 JP2014062714W WO2015173889A1 WO 2015173889 A1 WO2015173889 A1 WO 2015173889A1 JP 2014062714 W JP2014062714 W JP 2014062714W WO 2015173889 A1 WO2015173889 A1 WO 2015173889A1
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Prior art keywords
data
cache
write
write data
internal
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PCT/JP2014/062714
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English (en)
Japanese (ja)
Inventor
悠二 伊藤
彬史 鈴木
山本　彰
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株式会社日立製作所
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Priority to PCT/JP2014/062714 priority Critical patent/WO2015173889A1/fr
Publication of WO2015173889A1 publication Critical patent/WO2015173889A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Definitions

  • the present invention relates to a storage apparatus.
  • SSD Solid State Drive
  • SSDs are superior in random access performance compared to conventional HDDs (Hard Disk Drives), and especially SSDs using NAND flash memories are increasing in capacity and price, and are being replaced by HDDs.
  • SCM Storage Class Memory
  • SCM Storage Class Memory
  • MRAM Magnetic Random Access Memory
  • PRAM Phase Change Random Access Memory
  • ReRAM Resistance Random Access Memory
  • Servers and storage systems improve system performance by using data access bias and providing caches using high-speed storage media for servers and storage controllers. This is because if the access to the HDD that is the final storage destination of data is performed one by one, a large overhead occurs. By storing frequently accessed data in the cache, it is possible to access the data at high speed without accessing the HDD when accessing the data again. Therefore, the larger the cache capacity, the larger the amount of data that can be accessed at high speed. In other words, the data hit rate in the cache is improved, and an improvement in system performance can be expected.
  • DRAM is widely used as a cache in servers and storage systems. DRAM is much faster than HDD, but has a problem of large capacity and price.
  • Patent Document 1 a technique for applying an SSD having a low-cost and large-capacity characteristic as compared with a DRAM as a cache of a storage system has been disclosed (Patent Document 1). By using a NAND flash memory that is lower in price and larger than DRAM as a cache, the cache hit rate is improved and system performance and cost performance can be improved.
  • Flash memory has a limited number of data erasures. Further, in the flash memory, data cannot be overwritten on the same physical address, and it is necessary to write after erasing in a unit (block) larger than a read / write unit (page). Erasing one by one for overwriting has a large overhead and wastes a limited number of erasures. Therefore, a system using flash memory has a capacity larger than the capacity that can be recognized by the user, secures an update area for overwritten data, and logical addresses in the logical area that can be recognized by the user, Update processing is performed by associating with a physical address.
  • staging In a server or storage system cache, reading data to the cache is called staging, and eviction of data from the cache is called destaging.
  • a storage medium used as a cache of a server or a storage system the number of times of data erasure becomes much larger than that of a normal final storage device (storage device in which data is finally managed) due to staging and destaging of cache data. This is because in a cache having a small capacity relative to the capacity of the entire system, I / O processed by a large number of final storage devices is processed by a small number of cache storage media, so the load per storage medium This is because the update frequency increases.
  • write processing for storing read data is performed on the storage medium for cache.
  • an MLC (Multi Level Cell) type NAND flash memory has a limited number of data erasures, and therefore, if used as a cache, it will have a shorter lifetime than that used as a final storage device.
  • SLC (Single Level Cell) type flash memory and SCM which have a longer life than MLC type NAND flash memory, have a higher capacity unit price than MLC type flash memory, as described above, so increase the cache capacity. It is difficult to improve system performance.
  • an SSD with a problem in life When an SSD with a problem in life is used as a cache for a host device such as a server or a storage system, data with a small effect of caching may not be cached only in a high-cost, small-capacity DRAM with a long life, or may not be cached in an SSD. Conceivable. However, if the data is not cached in the SSD, the function of the SSD used as the cache device becomes unusable, and it is necessary to realize an equivalent function by the CPU of the host device or separately installed hardware. When the CPU of the host device is used, the processing overhead is increased and the system performance is degraded. If hardware is installed separately, the cost of the system will increase.
  • the data stored in the SSD is encrypted internally and the encrypted data can be read.
  • the SSD as a cache device, when data is cached, it is encrypted inside the SSD, and the data destaged from the SSD is stored in the final storage medium while being encrypted, thereby consuming resources such as the CPU of the host device It is possible to realize a system that encrypts all data without having to do so.
  • the data is stored once in the SSD so that it can be decoded inside the SSD, and when it hits as a cache, the data can be read faster than the HDD.
  • a storage device includes a cache device that caches data requested by a host device such as a server or a storage controller, and the cache device includes a high-speed, small-capacity, long-life internal cache unit, It has a storage unit that has a shorter lifetime than the cache unit and includes an internal controller that controls them.
  • the internal controller controls the priority of the internal destage from the internal cache unit to the storage unit according to the attribute / characteristic of each data stored in the internal cache unit of the cache device.
  • the internal controller preferentially destages data having a high internal destage priority from the internal cache unit to the storage unit, and suppresses writing of data having a low internal destage priority to the storage unit.
  • the cache device included in the storage device has a function of performing data conversion processing such as encryption and compression on the data stored in the cache device, and the write data received from the host device is data When conversion processing is performed and the data is stored in the cache device and data is transmitted to the host device, data is inversely converted and data is transmitted to the host device.
  • data conversion processing such as encryption and compression
  • the number of data writes to the storage unit can be appropriately suppressed.
  • the life can be extended.
  • the cache device has a function such as data conversion, the function of the cache device can be applied to the write data while suppressing the number of times of data writing to the short-lived storage unit.
  • FIG. 1 is a configuration diagram of an example of a storage system according to the first embodiment.
  • FIG. 2 is a diagram illustrating an example of a cache management table according to the first embodiment.
  • FIG. 3 is a configuration diagram of an example of the cache SSD according to the first embodiment.
  • FIG. 4 is a diagram illustrating an example of an internal cache management table according to the first embodiment.
  • FIG. 5 is a diagram illustrating an example of a logical-physical address conversion table according to the first embodiment.
  • FIG. 6 is a diagram illustrating an example of a write request command and a response command between the storage controller and the cache SSD controller according to the first embodiment.
  • FIG. 7 is a diagram illustrating an example of a read / data invalidation request command and a response command between the storage controller and the cache SSD controller according to the first embodiment.
  • FIG. 8 is a flowchart of write processing by the storage controller according to the first embodiment.
  • FIG. 9 is a flowchart of the cache storage process to the cache SSD by the storage controller according to the first embodiment.
  • FIG. 10 is a diagram illustrating the destage processing from the cache SSD to the final storage medium by the storage controller according to the first embodiment.
  • FIG. 11 is a flowchart of processing when a read request is received in the cache SSD according to the first embodiment.
  • FIG. 12 is a flowchart of processing when a data invalidation request is received in the cache SSD according to the first embodiment.
  • FIG. 13 is a flowchart of processing when a write request is received in the cache SSD according to the first embodiment.
  • FIG. 14 is a flowchart of internal destage processing in the cache SSD according to the first embodiment.
  • FIG. 15 is a flowchart of read processing by the storage controller according to the first embodiment.
  • FIG. 16 is a flowchart of internal destage processing in the cache SSD according to the second embodiment.
  • FIG. 17 is a flowchart of a write process to the cache SSD by the storage controller according to the second embodiment.
  • FIG. 18 is a flowchart of write processing by the storage controller according to the third embodiment.
  • FIG. 19 is a flowchart of read processing by the storage controller according to the third embodiment.
  • FIG. 20 is a flowchart of write processing by the storage controller according to the fourth embodiment.
  • FIG. 21 is a flowchart of a write process executed by the cache SSD according to the fifth embodiment.
  • FIG. 1 is a configuration diagram of an example of a computer system according to Embodiment 1 of the present invention.
  • the computer system includes a storage device 10 as an example of a cache control device and a host computer 40.
  • the storage apparatus 10 and the host computer 40 are connected via a network 20 such as a SAN (Storage Area Network) or a LAN (Local Area Network).
  • the host computer 40 is, for example, a general-purpose computer, and reads data stored in the storage device 10 or stores data in the storage device 10 to execute predetermined business processing.
  • the storage device 10 includes a storage controller 100 and one or more final storage media 190.
  • the final storage medium 190 is a storage medium that finally stores data written from the host computer 40 to the storage apparatus 10, and an HDD is used as an example. However, a configuration using a storage medium other than the HDD, such as an SSD, may be used.
  • the storage controller 100 is connected to the final storage medium 190 via the bus 170.
  • the storage controller 100 includes a host interface controller (I / F CTL) 110, a CPU 120, for example, a memory 130 represented by DRAM, a disk interface controller (I / F CTL) 150, a cache SSD 200 used as a secondary cache, and an ASIC 140.
  • the host I / F CTL 110, CPU 120, memory 130, disk I / F CTL 150, and cache SSD 200 are connected to the ASIC 140 via a dedicated internal bus 160 such as PCI and a memory bus 180.
  • the host I / F CTL 110 is a device for performing communication via the network 20.
  • the CPU 120 controls the operation of the entire storage apparatus 10.
  • the memory 130 includes a cache management table 1301 for managing the entire cache of the storage controller 100, a cache area 1302 for caching data, and a buffer area 1303 used as a temporary storage area for data transfer.
  • the cache area 1302 may be referred to as a cache DRAM 1302.
  • the ASIC 140 includes a DMA (Direct Memory Access) 141 that transfers data on the memory 130 without using the CPU 120.
  • the disk I / F CTL 150 is a device for communicating with the final storage medium 190 via the internal bus 170.
  • the storage controller 100 caches data read or written by the host computer 40 on the cache area 1302 on the memory 130 or the cache SSD 200. Processing for storing and reading data in the cache area 1302 or the cache SSD 200 will be described later.
  • FIG. 2 is an example of a cache management table for managing the cache of the storage controller 100 according to the first embodiment.
  • the cache management table 1301 is information for managing location information on the cache area 1301 or the cache SSD 200 in which data written from the host computer 40 is stored, and is stored on the memory 130 of the storage controller 100.
  • the contents of the cache management table 1301 are updated by the CPU 120 of the storage controller when data is stored in the cache.
  • the storage controller 100 (the CPU 120) manages the storage area on the cache DRAM 1302 and the cache SSD 200 by dividing the storage area into 64 KB fixed areas. In the embodiment of the present invention, this 64 KB fixed area is referred to as a cache segment. Call (or also called “segment”).
  • the CPU 120 manages each segment with a unique identification number (ID) in the storage apparatus 10, and this identification number is called a cache segment ID (or also called a “segment ID”).
  • 0x0 to 0x1FFFFF of the cache segment ID 13011 is attached to each segment (total storage area of 128 GB) of the cache DRAM 1302, and 0x200000 to 0x9FFFFF of the cache segment ID 13011 is allocated to each segment of the cache SSD 200 (total storage area of 512 GB).
  • the allocation method of the cache management unit and the cache segment ID is not limited to this.
  • the storage controller 100 manages the storage areas on the cache DRAM 1302 and the cache SSD 200 in 64 KB segment units, but the storage controller 100 secures the storage areas in the cache DRAM 1302 and / or the cache SSD 200. This is the minimum unit when releasing, and is not the minimum access unit when the storage controller 100 accesses (reads / writes) data to the cache DRAM 1302 and the cache SSD 200.
  • the storage controller 100 can read / write data from / to the cache segment in units of disk blocks (512 bytes, also referred to as sectors), which are the minimum access unit for the storage apparatus 10 of the host computer 40.
  • 4 KB which is a data unit for performing data compression or encryption is the minimum access. Become a unit.
  • the cache management table 1301 includes, for each cache segment specified by the cache segment ID 13011, the final storage medium 190 (or a plurality of final storage media 190) in which the data stored in the cache segment should be originally stored.
  • LBA 13012 which is a storage position (address) on the logical volume
  • bitmap 13013 representing a position where data is actually stored in the cache segment
  • cache state 13014 a cache state 13014
  • reference when destaged to the final storage medium 190 The latest access time 13015 (or also called the last access time 13015) is stored.
  • Bit map 13013 is 128-bit information representing the position where data is actually stored on the cache segment.
  • the cache segment size is 64 KB, but data may be stored (cached) in all 64 KB areas, or may not necessarily be stored.
  • Each bit of the bitmap 13013 indicates whether data is stored in each disk block in the cache segment (one disk block has 512 bytes. Therefore, one cache segment consists of 128 disk blocks).
  • the first bit (MSB) of the bitmap 13013 indicates whether data is stored in the first disk block in the cache segment.
  • the second, third,... Bits in the following order are the second, third, and third bits in the cache segment, respectively. This indicates whether data is stored in the disk blocks. When the content of each bit is 1, it means that data is stored in the disk block on the cache segment corresponding to the bit, and when 0, data is stored in the disk block on the cache segment corresponding to the bit. Means not stored.
  • the cache state 13014 indicates whether or not the cached data has been updated with respect to the data stored in the final storage medium 190.
  • “dirty” is stored in the cache state 13014, and when it is not updated (that is, stored in the cache segment).
  • Cache data 13014 is stored in the cache state 13014 (when the stored data and the data stored in the final storage medium 190 have the same content).
  • dirty data needs to be written (destaged) to the final storage medium 190.
  • the cache state 13014 includes Dirty is stored.
  • the latest access time 13015 information on the time when the cache segment corresponding to the latest access time 13015 was last accessed is stored.
  • the time information for example, the number of seconds elapsed from a certain point in time (such as January 1, 2010) is stored, but the time information may be stored in a format other than this.
  • the latest access time 13015 is information necessary when the storage controller 100 selects data to be destaged to the final storage medium 190 by using the LRU (Least Recently Used) algorithm.
  • the data selection policy at the time of destage is not limited to LRU.
  • the cache management table 1301 stores information necessary for the data selection policy instead of the most recent access time 13015.
  • the cache DRAM 1302 is used as a primary cache and the cache SSD 200 is used as a secondary cache. Therefore, the write data from the host computer 40 may be stored in both the cache DRAM 1302 and the cache SSD 200.
  • an entry having the same LBA 13012 exists among entries having a cache segment ID 13011 of 0x0 to 0x1FFFFF (segment in the cache DRAM 1302) and entries having a cache segment ID 13011 of 0x200000 to 0x9FFFFF (segment in the cache SSD 200).
  • FIG. 3 is an example of a configuration diagram of the cache SSD 200 in the present embodiment.
  • the cache SSD 200 in this embodiment is mainly a flash memory (which may be abbreviated as FM hereinafter) which is a non-volatile storage medium.
  • the cache SSD 200 includes one or more SSD controllers (SSD CTL) 201 and a plurality of FM 2011.
  • the SSD controller 201 includes an interface controller (I / F CTL) 2001, a processor 2003, an internal memory (DRAM) 2005, a data processing assist unit (Assist) 2006, an FM controller (FMC) 2007, and data transfer with each other.
  • An internal switch (S / W) 2004 is provided.
  • the interface controller 2001, the processor 2003, the data processing assist unit 2006, and the FM controller 2007 are connected to the internal switch 2004 via an internal bus.
  • the internal memory 2005 is connected to the internal switch 2004 via the memory bus 2009.
  • the interface controller 2001 is for accepting various commands for the cache SSD 200 or transferring data from the CPU 120 of the storage controller 100.
  • the interface controller 2001 is connected to the ASIC 140 included in the storage controller 100 in the storage apparatus 10.
  • the CPU 2003 is connected to each part of the SSD controller 201 via the internal switch 2004, and controls the entire SSD controller 201 using programs and management information (such as an internal cache management table 20052 described later) recorded in the internal memory 2005. To do.
  • the internal memory 2005 is a volatile memory such as a DRAM, which has a higher bit cost than FM2011 but has a higher speed and a longer life than FM2011.
  • an internal cache area 20051 used for temporarily storing data in the middle of data transfer processing in the SSD controller 201, and an internal cache management for managing data information stored in the internal cache area 20051
  • the internal cache area 20051 may be simply referred to as an internal cache 20051.
  • the size (capacity) of the internal cache 20051 is smaller than the total capacity of the plurality of FM 2011, but the size of the internal cache 20051 is smaller than the total capacity of the FM 2011. Even if it is not, the present invention is effective.
  • the FM controller 2007 is connected to the FM 2011 by a plurality of buses (for example, 16) 2010.
  • a plurality (for example, 2) of FM 2011 is connected to each bus 2010.
  • the cache SSD 200 provides a logical storage space composed of storage areas of a plurality of FM 2011 to the storage controller 100 to which the cache SSD 200 is connected. .
  • the storage controller 100 accesses (reads, writes, etc.) the cache SSD 200, for example, when data is written (written) to the cache SSD 200, a write command specifying a one-dimensional logical address in the logical storage space is cached.
  • the write target data can be written (virtually) on the logical storage space provided by the cache SSD 200.
  • the data that has arrived at the cache SSD 200 together with the write command is temporarily stored in the internal cache area 20051 and then moved (internal destage) to a storage area on the FM 2011 associated with a logical storage space.
  • These controls are realized by the CPU 2003 using the program and management information recorded in the internal memory 2005.
  • the cache SSD 200 has a function of performing data conversion processing and reverse conversion processing such as compression / decompression, parity generation, encryption / decryption of data stored in the cache SSD 200.
  • the data processing assist unit 2006 is hardware having a function of performing these data conversion processing / inverse conversion processing, for example, data compression / decompression processing.
  • the data processing assist unit 2006 performs data conversion processing (compression, encryption, etc.) on data that arrives from the interface controller 2001 and is written to the FM 2011 in accordance with an instruction from the CPU 2003, or data that is sent from the FM 2011 to the interface controller 2001.
  • Data reverse conversion processing decompression of compressed data, decryption of encrypted data, etc.
  • Each part of the SSD controller 201 described above may be configured in one semiconductor element as an ASIC or FPGA (Field Programmable Gate Array), or a plurality of individual dedicated ICs (Integrated Circuits) are connected to each other. It may be a configuration. Further, the cache SSD 200 may be provided with a capacitor or battery for the internal memory 2005, and the data and management information stored in the internal memory 2005 that volatilizes when power is interrupted may be saved in the FM 2011.
  • FM is used as a main storage medium as shown in FIG. 3, but the storage medium installed in the cache SSD 200 is not limited to FM, and Phase Change RAM. Or non-volatile memory such as Resistance RAM. Further, a configuration in which a part or all of the FM 2011 is a volatile RAM (DRAM or the like) may be used.
  • DRAM volatile RAM
  • the storage controller 100 designates an address (logical address) on the logical storage space as the write destination.
  • a write command is issued to the cache SSD 200.
  • Data that arrives at the cache SSD 200 together with the write command is temporarily stored (cached) in the internal cache area 20051.
  • the CPU 2003 of the cache SSD 200 associates the logical address, which is the write destination of the write data, with the location on the internal cache 20051 where the write data is temporarily stored, and records and manages it in the internal cache management table 20052.
  • the CPU 2003 of the cache SSD 200 manages the internal cache area 20051 by dividing it into fixed areas (called internal cache segments) of a predetermined size (for example, 4 KB or 8 KB). This is a unit for allocating and releasing the internal cache area 20051, and a unit for performing data processing (compression and encryption) by the data processing assist unit 2006. Further, the CPU 2003 manages each internal cache segment with an identification number (referred to as an internal cache segment ID, but may be abbreviated as “segment ID”) that is unique within the cache SSD 200.
  • an identification number referred to as an internal cache segment ID, but may be abbreviated as “segment ID”
  • the original write destination of the data stored in the internal cache segment (in the logical storage space described above)
  • a logical address 20052 that is a write destination address designated by the storage controller 100
  • a data size 200533 representing a data size after data processing (compression, etc.) of the internal cache segment
  • an internal cache State 200524 the latest access time 200525 to be referred to at the time of destage to FM
  • internal destage priority 200526 (sometimes abbreviated as destage priority) to FM are stored.
  • the data size 200533 is used when the data size fluctuates as a result of performing data processing by the data processing assist unit 2006 when data is stored in the cache SSD 200. For example, when compression is performed as data processing, the data size is often reduced.
  • the data size 20053 stores data size information after data processing (for example, compression). For example, in the example of FIG. 4, taking the information stored in the row (20052-0) where the internal cache segment ID 200521 is 0x1 as an example, the 4 KB internal cache area 20051 whose internal cache segment ID 200521 is 0x1 is secured. However, data after data processing is stored in the internal cache area, and it can be seen that the size is 1 KB when referring to the contents stored in the data size 200533.
  • the cache SSD 200 provides the storage controller 100 even when the cache SSD 200 performs data compression by the data processing assist unit 2006 and stores the compressed data in the internal cache area 20051 or FM 2011, for example.
  • the logical storage space is not affected, and the storage controller 100 seems to read / write data before compression (uncompressed data).
  • the internal cache state 200524 is the same as the cache state 13014 of the cache management table 1301 described above, and the internal cache state 200524 stores either “clean” or “dirty” information.
  • the latest access time 200525 is the same as the latest access time 13015 of the cache management table 1301 described above, and information on the last access time to the internal cache segment corresponding to the latest access time 200525 is stored. Similar to the cache area 1302, when data is moved (destaged) from the internal cache area 20051 to the FM 2011, an LRU algorithm is used as a selection policy for data to be moved, but the policy is not necessarily limited to the LRU algorithm. When the LRU algorithm is not used, information corresponding to the destage policy is stored in the internal cache management table 20052 instead of the latest access time 200525.
  • the write data is immediately evicted from the cache SSD 200 by using the data information 3005 included in the write request command 3000 described later transmitted from the storage controller 100. Is determined (or the storage controller 100 is unlikely to re-access the write data) or is held (re-accessed from the storage controller 100), and the internal destage priority 200526 is determined. And set when the internal cache management table 20052 is updated. In order to suppress deterioration due to writing of the short-lived FM 2011, for data predicted to be immediately evicted from the cache SSD 200, the internal destage priority 200526 is set low, and the internal cache 20051 is not written to the FM as much as possible. Fasten with.
  • the data is on the internal cache 20051 of the cache SSD 200 when the storage controller 100 destages to the final storage medium 190.
  • a read from the cache SSD 200 becomes a hit in the internal cache 20051, and data is invalidated from the cache SSD 200 by a subsequent invalidation request, so that no write to the FM occurs. Details of this series of processing will be described later.
  • the destage priority to the FM 200526 is used for selecting data to be destaged from the internal cache 20051 to the FM, together with the latest access time 200525, when the data is evicted from the internal cache 20051.
  • the destage priority 2005526 either high (High) information or low (Low) information is stored (in addition, “1” is stored instead of storing high (High) information, or low ( (“Low”) may be stored instead of storing "0").
  • the data destage from the internal cache 20051 to the FM by the SSD controller 201 is referred to as an internal destage.
  • data to be internally destaged by the LRU algorithm is selected from data having a high destage priority level of 200526.
  • Data with a low destage priority 200526 is selected for internal destage only when there is no data with a high destage priority 200526.
  • the internal destage policy is not limited to the above policy.
  • a policy is adopted such that in addition to data with a high destage priority 200526, data with a low destage priority 200526 is also an internal destage candidate. May be.
  • a plurality of levels of information may be stored.
  • the CPU 120 of the storage controller 100 determines whether each write data is sequential access data or random access data.
  • a known method such as determining whether or not an access request has arrived can be used), and during a write request to the cache SSD 200 (specifically, in the data information 3005 described later).
  • Information of either “random access data” or “sequential access data” is stored and transmitted to the SSD controller 201.
  • sequential access there is a low possibility that re-access to write data will be performed (that is, the possibility of a cache hit is low). Therefore, the sequential access data stored in the cache DRAM 1302 and the cache SSD 200 is destaged to the final storage medium 190 without hitting.
  • the SSD controller 201 predicts that the data notified as sequential access data has a low possibility of a cache hit, and sets the internal destage priority 200526 to “low” when the data is stored in the internal cache 20051. And set.
  • the internal destage priority 200526 is set to “high” to make internal destage easier (easier to be written to FM) than sequential access data.
  • the sequential access data is relatively kept in the internal cache 20051 as much as possible to make it difficult to be internally destaged.
  • the logical / physical address translation / update (logical / physical conversion / logical / physical update) of the cache SSD 200 will be described with reference to FIG.
  • the FM 2011 cannot overwrite the same physical address.
  • the cache SSD 200 assigns a new (unwritten) physical address of the FM 2011 to the logical address specified by the write command, and writes to the assigned physical address.
  • the mapping between the logical address 20000531 designated by the storage controller 100 and the physical address on the FM 2011 assigned to the logical address 2005312 is stored in the logical / physical address conversion table 20053 on the internal memory 2005, and Manage the mapping.
  • the CPU 2003 refers to and updates the logical / physical address conversion table 20053.
  • the CPU 2003 When the SSD controller 201 receives a read request, the CPU 2003 refers to the logical / physical address conversion table 20053 and acquires the physical address 20000532 corresponding to the logical address 20000531 for which the read request has been made. This process is called logical-physical conversion. Thereafter, the CPU 2003 makes a read request to the corresponding FM 2011 using the physical address 20052, reads data from the FM 2011, and transfers the read data to the storage controller 100 via the interface controller 2001.
  • the CPU 2003 secures an unwritten area on the FM 2011 for storing write data, and writes the data to the FM 2011 having the secured area. Thereafter, the CPU 2003 refers to the logical / physical address conversion table 20053 and updates the physical address 20000532 corresponding to the logical address 20000531 for which the write request has been made, to the physical address of the area in which data is newly stored. This process is called logical update.
  • the cache SSD 200 performs data processing in units of 4 KB when performing data processing (compression or encryption) by the data processing assist unit 2006.
  • the management of logical addresses in the address conversion table 20053 is also performed in units of 4 KB.
  • the write request command 3000 includes a command number (command No.) 3001 for identifying a command, a request content 3002 indicating that it is a write, a start address 3003 in the write destination logical space, a data size 3004 of the write data, and an SSD controller 201.
  • Data information 3005 serving as a hint for setting the destage priority to the FM is included.
  • the request content 3002 includes information indicating the type of command (information indicating that it is a write), the address of the area where the write target data is currently stored (for example, the address of the cache area 1302), and the data processing assist unit. Information specifying whether or not to perform data compression or encryption is included in 2006. As described above, the data information 3005 stores either “random access data” or “sequential access data”.
  • the SSD controller 201 transmits a response command 4000 to the write request command 3000 to the CPU 120 of the storage controller 100.
  • the response command 4000 includes a command number 4001 for identifying the command and result information 4002 indicating information such as completion or failure.
  • the command number 4001 stores the same information as the command number 3001 included in the write request command 3000.
  • the CPU 120 of the storage controller 100 can determine whether the write request by the write request command 3000 issued by the storage controller 100 has ended normally or has failed.
  • the CPU 120 of the storage controller 100 transmits a read or data invalidation request command 5000 to the SSD controller 201.
  • the read or data invalidation request command 5000 includes a command number 5001 for identifying the command, a request content 5002 indicating read or data invalidation, a read or invalidation start address 5003, and a read or invalidation request size 5004.
  • the request content 5002 includes information indicating the type of command (information indicating that it is a read request or invalidation request), and the data processing assist unit 2006 decompresses or decrypts the read data to store the controller. Information specifying whether or not to return to 100 is included.
  • a response command 6000 is transmitted from the SSD controller 201 to the CPU 120 of the storage controller 100. Similar to the response command 4000 to the write request command 3000, the response command 6000 includes a command number 6001 for identifying the command and result information 6002 indicating information such as completion or failure.
  • the cache DRAM 1302 is a primary cache and the cache SSD 200 is a secondary cache for the cache destination selection by the CPU 120 of the storage controller 100 will be described.
  • the area specified by the read / write request from the host computer 40 is the final storage medium 190 (or a volume composed of one or more final storage media 190) accessed by the host computer 40.
  • the boundary coincides with the 4 KB boundary in the storage space (this is because the minimum unit of data processing by the data processing assist unit 2006 is 4 KB) will be described.
  • FIG. 8 is processing executed by the CPU 120 of the storage controller 100 unless otherwise specified.
  • the write request received from the host computer 40 may be referred to as a host write request below.
  • a read request received from the host computer 40 may be referred to as a host read request.
  • the CPU 120 of the storage controller 100 When the CPU 120 of the storage controller 100 receives a host write request from the host computer 40 (S10), it performs a hit determination of the cache DRAM 1302 using the cache management table 1301 (S20).
  • the cache DRAM 1302 When the cache DRAM 1302 is hit, that is, when a cache segment for storing the data specified by the host write request has been secured on the cache DRAM 1302 (S20: hit), the write data is overwritten on the corresponding segment on the cache DRAM 1302 (S60). If there is a miss in the cache DRAM 1302 (S20: miss), it is checked whether there is an empty (unused) segment in the cache DRAM 1302 (S30).
  • the cache SSD 200 After the data is stored in the cache DRAM 1302, it is checked whether the cache SSD 200 is hit using the cache management table 1301 (whether the cache segment for storing the write target data written by the host write request has been secured) (S70). . If there is a hit (S70: hit), the storage controller 100 requests the cache SSD 200 to invalidate the corresponding data (S80). The case of hit means that the cache SSD 200 stores pre-update data of the write target data written by the host write request, but the pre-update data is unnecessary and invalid. Process. Data invalidation processing in the cache SSD 200 will be described later.
  • the storage controller 100 notifies the host computer 40 of the write completion (S90).
  • the hit determination of the cache SSD 200 may be performed when the hit of the cache DRAM 1302 is determined in S20.
  • destage (S40) process to the cache SSD 200 which is performed in order to secure the free space in the cache DRAM 1302, will be described. This process is also executed by the CPU 120 of the storage controller 100.
  • the CPU 120 of the storage controller 100 selects data to be destaged from the cache DRAM 1302 to the cache SSD 200 (S41). As described above, the selection is performed in order from the data having the oldest access time (last access time) using the cache management table 1301. Further, since this destage process is a process for securing an area necessary for storing the data designated by the host write request, in S41, a plurality of data to be destaged (at least the host write request) May be the same or larger than the data specified in.
  • the cache management table 1301 is used to perform a hit determination of the cache SSD 200, that is, a process of confirming whether or not a segment for storing data to be destaged has been secured in the cache SSD 200. (S42). If it is a miss (S42: miss), it is confirmed whether there is an empty segment in the cache SSD 200 (S43). If there is no space (S43: No), the data in the cache SSD 200 is destaged to the final storage medium 190 (S44). The destage processing from the cache SSD 200 to the final storage medium 190 will be described later.
  • a new cache segment corresponding to the cache SSD 200 is secured (S45), and a write request command 3000 is transmitted to the cache SSD 200.
  • the destaged data is written from the cache DRAM 1302 to the cache SSD 200 (S46).
  • the data information 3005 stores either “random access data” or “sequential access data” for transmission.
  • a response command 4000 which is a write request completion result, is received from the cache SSD 200, and the destage processing from the cache DRAM 1302 is completed.
  • the CPU 120 of the storage controller 100 uses the cache management table 1301 to select data to be destaged from the cache SSD 200 using LRU as described above (S441). Subsequently, the CPU 120 reads the selected data from the cache SSD 200 (S442, S443, S444), and writes the read data to the final storage medium 190 (S445, S446, S447). Thereafter, since the data is stored in the final storage medium 190, the CPU 120 invalidates the data on the cache SSD 200 (S448, S449, S4410), and stores information about the last invalidated segment on the cache SSD 200 from the cache management table 1301. By deleting, a segment release process is performed (S4411). For the read from the cache SSD 200 (S443) and the data invalidation request (S449) on the cache SSD 200, the commands shown in FIG. 7 are used. Details of this processing will be described later.
  • the read process (S443) executed by the cache SSD 200 will be described with reference to FIG.
  • the CPU 2003 of the SSD controller 201 uses the internal cache management table 20052 to make a hit determination of the internal cache 20051 (S4432).
  • the CPU 2003 reads data from the internal cache 20051 (S4435). If there is a miss in the internal cache 20051 (S4432: miss), the CPU 2003 performs the above-described logical-physical conversion (S4433) and reads data from the FM 2011 (S4434). Thereafter, the CPU 2003 applies the data processing function of the cache SSD 200 to the read data as necessary (S4436), transfers the data to the storage controller 100 (S4437), and notifies the CPU 120 of completion (S4438). In the processing of S4436, the CPU 2003 performs data processing using the data processing assist unit 2006.
  • the read data is not cached in the internal cache 20051 of the cache SSD 200.
  • the data at the time of reading may be cached in the internal cache 20051.
  • the free space in the internal cache 20051 is confirmed. If there is no free space, internal destage is performed to secure the free space. Thereafter, a new empty segment is secured, and data read from the FM is transferred to the storage controller 100 and stored in the internal cache 20051.
  • the storage controller 100 since the storage controller 100 destages to the final storage medium 190, data conversion / inverse conversion processing is not performed when data is read from the cache SSD 200. .
  • the compressed data is read and destaged to the final storage medium 190, so that the storage controller 100 destages to the final storage medium 190.
  • the request content 5002 of the read request command specifies that conversion / reverse conversion of the read data is not performed (therefore, the process of S4436 described above is performed).
  • the storage controller 100 reads the read data for returning to the host computer 40 from the cache SSD 200 (and the cache SSD 200 stores data that has been converted by the data processing assist unit 2006). In this case, it is necessary to read data that has been subjected to data inverse transformation (decompression, decoding, etc.). For this reason, the request content 5002 of the read request command 5000 issued to the cache SSD 200 by the CPU 120 of the storage controller 100 specifies that reverse conversion of the read data is performed (therefore, the processing of S4436 described above is performed). Done).
  • the CPU 2003 of the SSD controller 201 When the CPU 2003 of the SSD controller 201 receives the data invalidation request command 5000 (S4491), it performs a hit determination of the internal cache 20051 using the internal cache management table 20052 (S4492). When the internal cache is hit (S4492: hit), the CPU 2003 releases the corresponding segment in the internal cache 20051 (S4493). When the segment is released or when a miss is made in the internal cache 20051 (S4492: miss), the CPU 2003 performs the above-described logical-physical conversion (S4494), and confirms the corresponding table entry in the logical-physical address conversion table 20053 (S4495).
  • data may be stored in both the internal cache 20051 and the FM 2011, and it is necessary to invalidate both of them, so that logical-physical conversion is performed even when the internal cache hits.
  • the corresponding table entry is valid (S4495: Valid)
  • the CPU 2003 records that the data of the relevant physical address is invalid in the block information 20054 (S4496), and further logically Information on the corresponding physical address recorded in the logical physical address conversion table 20053 is deleted from the physical address conversion table 20053 (S4497). Thereafter, the CPU 2003 sends a completion notification to the CPU 120 of the storage controller 100 (S4498) and ends the process.
  • the CPU 2003 of the SSD controller 201 uses the data processing assist unit 2006 as necessary according to the request content 3002 of the command 3000 (for example, a compression instruction, an encryption instruction, etc.). Data conversion processing is performed on the write data (S462).
  • the cache SSD 200 performs data conversion. For this reason, when the write request command 3000 is issued in order to store the write data received from the host computer 40 in the cache SSD 200 by the storage controller 100, the request content 3002 of the write request command is converted to data. Is specified.
  • the cache SSD 200 is not subjected to data conversion / inverse conversion processing. Therefore, in this case, the request content 3002 of the write request command issued to the cache SSD 200 by the CPU 120 of the storage controller 100 specifies that data conversion / inverse conversion is not performed (therefore, in S462 described above) No processing is performed).
  • the CPU 2003 makes a hit determination of the internal cache 20051 using the internal cache management table 20052 (S463).
  • the CPU 2003 overwrites the data in the corresponding segment of the internal cache (S467).
  • the CPU 2003 checks whether there is an empty (unused) segment in the internal cache 20051 (S464). If there is no free space (S464: No), the CPU 2003 internally destages the data on the internal cache 20051 to the FM 2011 in order to secure a free segment (S465). The internal destage process will be described later.
  • the determination in S464 is not limited to the mode in which the internal destage (S465) process is performed when there are no unused segments.
  • the unused area size (number of segments) is insufficient (when the size of the unused area is smaller than the size of the data requested to be written from the storage controller 100, or the size of the unused area is a predetermined value)
  • the internal destage (S465) process may be performed when the value is less than the threshold value.
  • the CPU 2003 secures a new segment of the internal cache 20051 (S466) and writes data to the internal cache 20051 (S467).
  • the CPU 2003 sets the cache segment in which the write data is stored based on the “random access data” or “sequential access data” information included in the data information 3005 of the write request command 300 received in step S461. Corresponding “high” or “low” is stored in the column of the destage priority 200526 of the internal cache management table 20052. Thereafter, the CPU 2003 sends a response command 4000 to the CPU 120 of the storage controller 100 to give a write completion notification (S468).
  • the CPU 2003 of the SSD controller 201 selects data to be internally destaged (S4641).
  • the internal destage target data is selected, for example, by using the latest access time 200525 and the destage priority 200526 of the internal cache management table 20052, and the data whose destage priority 200526 is “high”. Is selected by selecting the oldest one having the latest access time of 200525. If there is no data with the destage priority 200526 “high”, the oldest data having the latest access time 200525 is selected from the data with the destage priority 200526 “low”.
  • other data selection methods may be employed.
  • the CPU 2003 After selecting data to be internally destaged, the CPU 2003 searches for an empty (unused) area (physical address) of the FM 2011 that is the internal destage destination (S4642). When there are a plurality of free areas (physical addresses) that can store the internal destage target data, the CPU 2003 selects an appropriate physical address in consideration of the life of the FM 2011 or the like. The CPU 2003 issues a write request to the FM 2011 corresponding to the selected write destination physical address (S4643), and writes that the data of the write destination physical address is valid in the block information 20054 (S4644). Further, the CPU 2003 updates the logical physical address conversion table 20053 in order to associate the requested logical address with the write destination physical address (S4645). Since the data has been stored in the FM 2011 as described above, the CPU 2003 updates the internal cache management table 20052 to release the corresponding segment in the internal cache 20051 (S4646), and the internal destage processing ends.
  • the CPU 120 of the storage controller 100 receives a host read request from the host computer 40 (S100), it performs cache hit determination using the cache management table 1301 (S110, S120).
  • the cache DRAM 1302 is hit (S110: hit)
  • the CPU 120 reads data from the cache DRAM 1302 (S190).
  • the cache DRAM 1302 is not hit (S110: miss) and the cache SSD 200 is hit (S120: hit)
  • the CPU 120 issues a read request command to the cache SSD 200 (S140).
  • the read process performed in the cache SSD 200 is the same as the process performed in S443.
  • the cache SSD 200 applies the data processing function in the cache SSD 200 to the data, and processes the data (data decompression or data decryption). ). Then, the processed data is transferred to the buffer area 1303 of the storage controller 100.
  • the CPU 120 If there is also a miss in the cache SSD 200 (S120: miss), the CPU 120 reads the data from the final storage medium 190 and stores the data in the temporary storage area in the memory 130, ASIC 140, or IF CTL 150 (S130). Further, the CPU 120 checks whether there is an empty segment in the cache SSD 200 (S150). If there is no empty segment (S150: No), the CPU 120 performs destage processing from the cache SSD 200 to the final storage medium 190 (S160). The empty confirmation of the cache SSD 200 and the destage processing (S150, S160) may be performed before reading from the final storage medium 190 (S130). The destage processing (S160) is the same as S44.
  • the CPU 120 After destage or when the cache SSD 200 is empty (S150: Yes), the CPU 120 secures a new cache segment corresponding to the cache SSD 200 and issues a request to the cache SSD 200 to write the data read from the final storage medium 190. (S170).
  • the write process to the cache SSD 200 is the same as S46.
  • the CPU 120 issues a request to read the data written in the cache SSD 200 to the cache SSD 200 (S180).
  • the cache SSD 200 that has received this read request performs processing (data decompression and data decryption) on the data as in S443, and the processed data is transferred to the buffer area 1303 of the storage controller 100.
  • the storage controller 100 transfers the data read from any medium to the host computer 40 (S200) and ends the process.
  • the CPU 120 when any of the caches misses and is read from the final storage medium 190 (S130), the CPU 120 once writes the data read from the final storage medium 190 to the cache SSD 200 and then writes to the cache SSD 200.
  • Read data Since the data processing function of the cache SSD 200 is applied to the data on the final storage medium 190 at the time of writing and processing such as compression and encryption is performed, the data is stored in the cache SSD 200 once and the data processing function is applied again. This is because the data needs to be handled by the host computer 40 by performing data expansion or decryption. For this reason, data to be transmitted to the host computer 40 needs to be temporarily written from the final storage medium 190 to the cache SSD 200.
  • the FM 2011 Is unlikely to occur and the read latency is low.
  • the storage controller 100 may manage it.
  • the cache SSD 200 is notified of necessary information by a write request command 3000 and a read request command 5000 to the cache SSD 200.
  • another information different from the write request command 3000 and the read request command 5000 may be issued to notify the cache SSD 200 of necessary information.
  • data in which the destage priority level 200526 is set high is preferentially written to the FM 2011. This prevents data with a low destage priority 200526 from being written to the FM 2011 as much as possible, and minimizes the lifetime degradation of the FM 2011. However, if data having a high destage priority 200526 does not exist in the internal cache 20051 of the cache SSD 200, data having a low destage priority 200526 is also written to the FM 2011. On the other hand, in the storage apparatus 10 and the cache SSD 200 according to the second embodiment, control is performed so that only data having a high destage priority 200526 is written to the FM 2011.
  • the cache SSD 200 notifies the CPU 120 of the storage controller 100 that destage is necessary. This notification is performed at the timing when the cache SSD 200 receives a write request, but may be notified at other timings.
  • the SSD controller 200 may periodically monitor the free capacity of the internal cache 20051 and notify the CPU 120 of the storage controller 100 that destage is necessary when the free capacity of the internal cache 20051 becomes small.
  • FIG. 16 is an example of a flow of internal destage processing performed by the cache SSD 200 in the second embodiment.
  • the CPU 2003 of the SSD controller 201 confirms whether or not there is data having a high internal destage priority 200526 for the data in the internal cache 20051 (S46411), and if there is no such data (S46411: No), the SSD controller 201 Of the data in the internal cache 20051 that the destage to the final storage medium 190 is necessary, and the data (the last access time 200525 of the data managed by the internal cache management table 20052) among the data in the internal cache 20051 is the oldest ( (Data stored in the cache segment) is included in the result information 4002 of the response command 4000 to the write request command 3000 and notified to the CPU 120 of the storage controller 100 (S46412). , Internal de-stage processing of cache SSD20 is completed.
  • the CPU 120 of the storage controller 100 includes information indicating that destage to the final storage medium 190 is required in the result information 4002 of the response command 4000 returned from the SSD controller 201. In such a case, a process of destageing the data in the cache SSD 200 to the final storage medium 190 is performed.
  • the write completion notification is received from the cache SSD 200 with a response command 4000 to the write request command 3000. (S47).
  • the CPU 120 confirms from the result information 4002 whether write completion or destage is necessary (S48).
  • the result information 4002 includes information indicating that destage to the final storage medium 190 is necessary (S48: destage required)
  • the CPU 120 destages data from the cache SSD 200 to the final storage medium 190 ( S49).
  • This destage processing is substantially the same as S44 of the first embodiment (that is, the processing described in FIG.
  • the CPU 120 determines the final data among the data in the internal cache 20051 notified from the cache SSD 200 as destaged data. Select data with the oldest access time. This is because new data cannot be written to the cache SSD 200 unless the data in the internal cache 20051 is destaged. After the destage, the CPU 120 makes a write request to the cache SSD 200 again, and repeats the above processing until the write is completed.
  • the memory 130 (specifically, the cache DRAM 1302 in the memory 130) on the storage controller 100 is used as the primary cache and the cache SSD 200 is used as the secondary cache.
  • the primary cache is not used. That is, the point that only the cache SSD 200 is used as the cache of the storage apparatus 10 is different from the storage apparatus 10 according to the first or second embodiment.
  • the configuration of the storage apparatus 10 according to the third embodiment is substantially the same as that described in the first embodiment (described in FIG. 1), the illustration is omitted.
  • the storage apparatus 10 according to the third embodiment is different from the storage apparatus 10 according to the first embodiment in that the memory cache area 1302 does not exist in the memory 130.
  • Other points are the same as those described in the first embodiment.
  • the cache management table 1301 managed by the storage apparatus 10 according to the third embodiment Since the information included in the cache management table 1301 according to the third embodiment is the same as that in the first embodiment, the illustration is omitted. However, in the cache management table 1301 in the first embodiment, information about the cache segment of the cache DRAM 1302 (FIG. 2: 1310) is stored, but in the storage apparatus 10 according to the third embodiment, the storage area used as a cache is Since only the cache SSD 200 is stored, only information on the cache segment of the cache SSD (FIG. 2: 1311) is stored, and information on the cache segment of the cache DRAM 1302 (FIG. 2: 1310) is not stored.
  • the configuration of the cache SSD 200 according to the third embodiment and information managed by the cache SSD 200 in the internal memory 2005 are the same as the cache SSD 200 according to the first embodiment. Since they are the same, they will not be described here.
  • the CPU 120 of the storage controller 100 receives a write request from the host computer 40 (S10). This process is the same as the process S10 described with reference to FIG. Subsequently, the storage controller 100 performs a hit determination on the cache SSD 200 using the cache management table 1301 (S20 ').
  • the cache SSD 200 is hit, that is, when the cache segment for storing the data specified by the write request has been secured on the cache SSD 200 (S20 ′: hit), the write data of the corresponding segment on the cache SSD 200 is stored. Overwriting is performed (S60 '). If there is a miss in the cache SSD 200 (S20 ': miss), it is checked whether there is an empty (unused) segment in the cache SSD 200 (S30').
  • the CPU 120 of the storage controller 100 performs a cache hit determination using the cache management table 1301 (S120).
  • the cache SSD 200 is hit (S120: hit)
  • the CPU 120 issues a read request to the cache SSD 200 (S140).
  • the read process of the cache SSD 200 is the same as the process of S443 described in the first embodiment (that is, the process of FIG. 11).
  • the CPU 120 reads data from the final storage medium 190 and stores it in the temporary storage area in the memory 130, ASIC 140, or IF CTL 150 (S130).
  • the CPU 120 checks whether or not there is an empty segment in the cache SSD 200 (S150). If there is no empty segment (S150: No), the CPU 120 destages data from the cache SSD 200 to the final storage medium 190 (S160). The empty confirmation of the cache SSD 200 and the destage processing (S150, S160) may be performed before the read from the final storage medium 190 (S130). The destage processing (S160) is the same as S44. After destage or when there is a free space in the cache SSD 200 (S150: Yes), the CPU 120 newly secures a cache segment and writes the data read from the final storage medium 190 to the cache SSD 200 (S170). The write process to the cache SSD 200 is the same as S46.
  • the data processing function in the cache SSD 200 is applied to the data.
  • the CPU 120 issues a request for reading the data written in the cache SSD 200 to the cache SSD 200 (S180).
  • the cache SSD 200 that has received this read request performs processing (data decompression and data decryption) on the data as in S443, and the processed data is transferred to the buffer area 1303 of the storage controller 100.
  • the CPU 120 transfers the data read from any medium to the host computer 40 (S200), and ends the process.
  • the internal destage processing described in FIG. 14 is performed.
  • the internal destage processing as in the first embodiment, by selecting the data to be internally destaged by the LRU algorithm from the data having the high destage priority 200526, there is a possibility that the data will be reaccessed like sequential access data. Is less likely to be stored in the FM 2010 (internal destage).
  • the internal destage processing (the processing in FIG. 16) described in the second embodiment may be employed. Then, like the storage apparatus 10 according to the second embodiment, the storage apparatus 10 according to the third embodiment operates so as to write only data with a high destage priority 200526 to the FM 2011.
  • Example 4 Since the hardware configuration of the storage device and the cache SSD according to the fourth embodiment is the same as that described in the first or second embodiment, it will not be described here.
  • the memory 130 (specifically, the cache DRAM 1302 in the memory 130) on the storage controller 100 is used as the primary cache and the cache SSD 200 is used as the secondary cache.
  • the CPU of the storage controller 100 selects either the cache SSD 200 or the cache DRAM 1302 according to the data characteristics (for example, the final storage destination of the write data) and caches the data.
  • the final storage location of the write data can be determined by referring to the address information (LBA or the like) of the write target data included in the host write request.
  • the final storage medium 190 is a high-speed medium such as an SSD, for example, even if it is cached in the cache SSD 200 having the same access speed, the effect of improving the access performance is small.
  • the final storage medium 190 is a medium that is slower than the SSD, such as an HDD, only the cache SSD 200 is cached. In this case, the data stored in the cache DRAM 1302 cannot be used with the data processing function of the cache SSD 200, so the CPU 120 of the storage controller 100 or other hardware performs similar processing.
  • the handling of the data cached in the cache SSD 200 is the same as that in the third embodiment and the details are omitted.
  • write data is cached in either the cache DRAM 1302 or the cache SSD 200 based on the first data characteristic such as the type of the final storage medium.
  • the cache SSD 200 destages from the internal cache to the FM based on the second data characteristic (for example, write access type (sequential / random)) received from the CPU 120 of the storage controller 100. Determine the priority of.
  • the CPU 120 of the storage controller 100 receives a write request from the host computer 40 (S10). This process is the same as the process S10 described with reference to FIG. Subsequently, the CPU 120 confirms the LBA of the write request command and determines whether the final storage destination of the write data is a high speed medium such as SSD or a low speed medium such as HDD (S11). If the final storage destination is SSD (S11: SSD), the write data is stored in the cache DRAM 1302 (S13).
  • the storage processing in the cache DRAM 1302 is processing excluding S70 and S80 in FIG. This is because the cache DRAM 1302 and the cache SSD 200 do not hold the same LBA data, and therefore the data on the cache DRAM 1302 is not on the cache SSD 200.
  • the write data is stored in the cache SSD 200 (S12).
  • the storage process in the cache SSD 200 is the same as that after S42 in FIG.
  • the storage device of the fourth embodiment only the data stored in the final storage medium 190 that uses a storage medium with lower access performance than the SSD, such as an HDD, is cached in the cache SSD 200, such as an SSD.
  • the cache SSD 200 such as an SSD.
  • data stored in the final storage medium 190 using a storage medium having an access performance equivalent to that of the cache SSD 200 is not cached. Therefore, the amount of data written to the cache SSD 200 can be reduced, and the life of the storage medium (FM 2011) of the cache SSD 200 can be extended.
  • Example 5 will be described.
  • the hardware configurations of the storage device and the cache SSD according to the fifth embodiment are the same as those described in the first or second embodiment.
  • the cache SSD 200 according to the fifth embodiment when the deterioration of the FM 2011 of the cache SSD 200 progresses and it becomes difficult to keep the data, the cache SSD 200 does not perform internal destage and is the same as the second embodiment.
  • the storage controller 100 is requested to destage, and the data is destaged to the final storage medium 190. At this time, among the data stored in the FM 2011, a destage request is also made to the storage controller 100 for data whose cache state 13014 is “dirty”.
  • the cacheable capacity of the cache SSD 200 is reduced, but the data of the cache SSD 200 with respect to the write data or the data read from the final storage medium 190 is prevented while preventing the data from being lost due to the deterioration of the FM 2011. You can continue to apply functions such as data conversion.
  • FIG. 21 will be used to explain the operation when the FM 2011 of the cache SSD 200 reaches the end of its life.
  • FIG. 21 is a diagram for explaining the flow of processing executed by the cache SSD 200 when the cache SSD 200 receives a write request command from the storage controller 100. Many of the processes are the same as those in FIG. 13 of the first embodiment. Yes.
  • the cache SSD 200 when the cache SSD 200 receives a write request from the CPU 120 of the storage controller 100 (S461), the cache SSD 200 performs data processing (S462), and uses the internal cache management table 20052 to determine whether the internal cache 20051 is hit. This is performed (S463). When there is a hit in the internal cache (S463: hit), it overwrites the corresponding segment in the internal cache (S467).
  • miss If there is a miss in the internal cache 20051 (S463: miss), it is confirmed whether there is an empty (unused) segment in the internal cache 20051 (S464). If the internal cache 20051 has a free space (S464: Yes), a new internal cache segment is secured as in the first embodiment, and data is written to the internal cache. On the other hand, if there is no empty segment in the internal cache 20051 (S464: No), it is determined whether the FM 2011 has reached the end of its life (S469). As a determination method here, for example, the CPU 2003 of the SSD controller 201 periodically reads the data regardless of the request from the host device, and uses the guarantee code such as CRC attached to the data to determine the error rate. There may be a method of checking and determining that the lifetime has been reached when the error rate exceeds a preset threshold value.
  • the cache SSD 200 requests the CPU 120 of the storage controller 100 that destage is necessary (S46412). However, you may make it notify to CPU120 that a destage is required by the opportunity other than that.
  • the SSD controller 200 periodically monitors the free capacity of the internal cache 20051 and notifies the CPU 120 of the storage controller 100 that destage is necessary when the free capacity of the internal cache 20051 becomes small. May be. Further, the cache SSD 200 may notify the storage controller 100 that the FM 2011 has reached the end of its life.
  • the CPU 120 of the storage controller 100 that has received the notification that the FM 2011 of the cache SSD 200 has reached the end of its life, stores data whose cache state 13014 is “dirty” to the final storage medium 190 for the data already stored in the cache SSD 200. Stage.
  • the cache management table 1301 is updated and stored in the cache SSD 200 for those data. Treat as not. Specifically, the cache management information is updated assuming that the data recorded in the cache SSD 200 has been lost. Thereafter, for data stored in the cache SSD 200 that cannot be stored in the internal cache 20051, as described above, the storage controller 100 is notified that destage is necessary, and the storage controller 100 is destaged. No data is stored in the FM 2011 that has reached the end of its life.
  • the CPU 120 of the storage controller 100 acquires information based on the life of the FM 2011 from the cache SSD 200, and stores the data in the internal memory 2005 including the DRAM of the cache SSD 200. Destaging to the final storage medium 190 makes it possible to improve reliability.
  • Example 6 The hardware configurations of the storage device and the cache SSD according to the sixth embodiment are the same as those described in the first or second embodiment.
  • the storage apparatus manages a plurality of final storage media 190 as a RAID group, generates RAID Parity (hereinafter also abbreviated as “Parity”) from write data from the host computer 40, and writes A configuration in which Parity is stored in the final storage medium 190 together with data is targeted.
  • Parity RAID Parity
  • the cache SSD 200 generates a RAID parity from the data stored in the cache SSD 200 (write data written from the host computer 40) based on an instruction from the storage controller 100. According to this configuration, it is possible to offload a load related to RAID parity generation from the storage controller 100, and it is possible to improve the performance of the entire storage apparatus 10. For this reason, the cache SSD according to the sixth embodiment has a function of generating a parity. As described in the first embodiment, this function may be provided in the data processing assist unit 2006, or may be implemented in the cache SSD 200 as parity generation hardware different from the data processing assist unit 2006. Also good. Alternatively, the CPU 2003 may execute the parity generation.
  • the storage controller 100 stores the write data from the host computer 40 in the cache SSD 200 and then issues a parity generation command to the SSD.
  • This Parity generation command is at least an LBA that specifies the storage location of data to be generated for Parity (this is an address on the logical storage space provided by the cache SSD to the storage controller described in the first embodiment). ), One or two LBAs that specify the storage destination of the generated parity (one for RAID5, two for RAID6), and data length information.
  • the cache SSD 200 that has received this parity generation command from the CPU 120 of the storage controller 100 acquires data associated with the LBA specified by the command from the FM 2011 or the internal cache 20051, and performs a parity operation. Then, a parity is generated using the acquired data, stored in the internal cache 20051, and managed in association with the LBA specified by the parity generation command (specifically, managed using the internal cache management table 20052). Keep it).
  • a storage device performs destage processing to transfer infrequently accessed data from a cache to a final storage medium such as an HDD when the free capacity of the cache is reduced and new data cannot be placed in the cache.
  • An empty area is generated by deleting from the cache the data recorded in the final storage medium according to the stage.
  • the storage apparatus since the storage apparatus generally generates a parity for data determined to be destaged (destage target data), the generated parity is also generated in a short period of time after the generation, similar to the destage target data. It is transferred to the final storage medium and erased from the cache.
  • the parity generated by the parity generation described above is expected to be destaged in a short period of time. Therefore, when storing the generated parity in the internal cache 20051, the cache SSD 200 manages the parity as data having a low internal destage priority (the internal destage priority 200526 of the internal cache management table 20052 is “ Record as “Low”).
  • the Parity is preferentially stored in the DRAM 2005 (internal cache 20051) until the storage controller destages the Parity to the final storage medium 190 and an instruction to erase data (Parity) from the cache SSD 200 is given, and FM2011.
  • the amount of writing to FM2011 can be reduced and FM degradation can be reduced.
  • a storage apparatus includes an internal cache composed of a high-speed storage medium such as a DRAM and a cache apparatus (cache SSD) having a low-priced and large-capacity storage medium such as FM as a main storage area. . Since FM has a defect that the number of times of data erasure (the number of rewrites) is limited, the lifetime is shortened when rewriting is performed frequently.
  • the cache apparatus controls the priority of the internal destage of the cache target data based on the attribute / characteristic of the data.
  • a higher-level device such as a storage controller stores (caches) data in the cache device
  • it notifies the cache device of information related to the attributes and characteristics of the data (for example, sequential access, random access, etc.)
  • the cache device obtains data attributes and characteristics.
  • data that is evicted without being re-accessed from the host device data having a small cache effect
  • sequential write data is moved from the internal cache to the FM (internal destage). Therefore, it is possible to reduce the frequency of writing to the FM and extend the life (service life) of the cache device.
  • data is destaged from the cache device to the final storage medium based on a standard (such as LRU) that is different from the priority of data movement from the internal cache to the FM (internal destage). Without destaging to the final storage medium, and the frequency of writing to the FM is suppressed.
  • a standard such as LRU
  • the present invention is not limited to an example in which the storage controller designates data attributes and the cache device changes the priority of the internal destage based on the attributes. Even in a mode in which the cache device autonomously changes the destage priority depending on the type of data as in the cache SSD according to the sixth embodiment, the write frequency to the FM is reduced, and the life of the cache device (lifetime) ) Can be obtained.
  • Storage device 20 Network 40: Host computer 100: Storage controller 110: I / F CTL 120: CPU 130: Memory 140: ASIC 150: I / F CTL 160: Dedicated internal bus 170: Internal bus 180: Memory bus 190: Final storage medium 200: Cache SSD 2001: I / F CTL 2003: CPU 2004: Internal switch 2005: Internal memory 2006: Data processing assist unit (Assist) 2007: FMC 2011: FM

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Abstract

La présente invention concerne un dispositif de stockage qui comporte un dispositif de cache qui met en cache des données demandées à partir d'un dispositif de niveau supérieur, tel qu'un ordinateur hôte. Le dispositif de cache comporte un dispositif de commande interne qui comprend un cache interne configuré à partir d'une mémoire capable d'un accès à grande vitesse, telle qu'une mémoire vive dynamique (DRAM), et une unité de stockage configurée à partir d'un support de stockage ayant une limite de nombre d'effacements, tel qu'une mémoire flash (FM), et qui a la fonction de commander le cache interne et l'unité de stockage et de réaliser un processus de conversion et de conversion inverse par rapport à des données stockées. Après que le dispositif de stockage stocke des données d'écriture dans le dispositif de cache, le dispositif de cache, sur la base d'un attribut ou de caractéristiques des données d'écriture, détermine la priorité d'une désactivation interne des données d'écriture de l'unité de cache interne à l'unité de stockage. Le dispositif de cache réalise ensuite une désactivation interne de l'unité de cache interne à l'unité de stockage de manière préférentielle à partir de données ayant une priorité de désactivation interne supérieure.
PCT/JP2014/062714 2014-05-13 2014-05-13 Dispositif de stockage WO2015173889A1 (fr)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019133252A (ja) * 2018-01-29 2019-08-08 東芝メモリ株式会社 メモリシステム
CN111865326A (zh) * 2020-07-14 2020-10-30 北京灵汐科技有限公司 数据压缩方法、装置、设备及存储介质
CN114067879A (zh) * 2021-10-14 2022-02-18 西安紫光国芯半导体有限公司 3d非易失性存储装置及其读数据方法、写数据方法

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JP2008015918A (ja) * 2006-07-07 2008-01-24 Toshiba Corp ディスク装置及びディスクコントローラ
JP2008217527A (ja) * 2007-03-06 2008-09-18 Hitachi Ltd ストレージシステム及びデータ管理方法
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JP2011204060A (ja) * 2010-03-26 2011-10-13 Nec Corp ディスク装置

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Publication number Priority date Publication date Assignee Title
JP2008015918A (ja) * 2006-07-07 2008-01-24 Toshiba Corp ディスク装置及びディスクコントローラ
JP2008217527A (ja) * 2007-03-06 2008-09-18 Hitachi Ltd ストレージシステム及びデータ管理方法
JP2009205335A (ja) * 2008-02-27 2009-09-10 Hitachi Ltd ２種のメモリデバイスをキャッシュに用いるストレージシステム及びそのストレージシステムを制御する方法
JP2011204060A (ja) * 2010-03-26 2011-10-13 Nec Corp ディスク装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019133252A (ja) * 2018-01-29 2019-08-08 東芝メモリ株式会社 メモリシステム
CN111865326A (zh) * 2020-07-14 2020-10-30 北京灵汐科技有限公司 数据压缩方法、装置、设备及存储介质
CN114067879A (zh) * 2021-10-14 2022-02-18 西安紫光国芯半导体有限公司 3d非易失性存储装置及其读数据方法、写数据方法

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