WO2015167513A1

WO2015167513A1 - Communication between processor and logic device

Info

Publication number: WO2015167513A1
Application number: PCT/US2014/036098
Authority: WO
Inventors: Mohammadreza Rozehrezvani; Shiraz QURESHI
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2014-04-30
Filing date: 2014-04-30
Publication date: 2015-11-05

Abstract

A processor sends a communication to a logic device. The communication includes a plurality of atomic units, each atomic unit including a transaction ID.

Description

COMMUNICATION BETWEEN PROCESSOR AND LOGIC DEVICE

BACKGROUND

[0001] Computers, networking equipment and other devices may have a central processing unit (CPU) and/or a logic device. A CPU executes machine readable instructions stored in a memory and is very versatile. A logic device such as an application specific integrated chip (ASIC), field programmable gate array (FPGA), complex programmable logic device (CPLD) etc. comprises logic circuits that perform specific applications. ASICs have hardwired logic circuits, while FPGAs, CPLDs are programmable logic devices that have programmable logic circuits.

[0002] In some cases a CPU will work together with a logic device. For example, some functions may be handled by a CPU and other functions handled by a logic device. The CPU and logic device may communicate with each other. For example, a function may be passed from the CPU to the logic device and the logic device may return a result of the function to the CPU.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Examples will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0004] Figure 1 shows an example of communication between a CPU and a logic device;

[0005] Figure 2 shows another example of communication between a CPU and a logic device;

[0006] Figure 3A is an example method diagram from the perspective of the CPU;

[0007] Figure 3B is an example method diagram from the perspective of the CPU;

[0008] Figure 4 shows an example structure of a function request in more detail;

[0009] Figure 5 is a block diagram showing an example structure of a logic device including a communication interface, a transaction ID module, a first function module and a second function module; and

[0010] Figure 6 shows an example of a CPU obtaining a transaction ID from a memory structure.

DETAILED DESCRIPTION

[0011] One approach to handling communication between a CPU and a logic device is for the CPU to employ a mutex or semaphore. A mutex prevents two processes from accessing the communication channel between the CPU and logic device concurrently. For example only one process may be allowed to access the CPU's interface with the logic device at a time and the process may keep the resource until the process has finished. A semaphore is a flag which indicates when a process is using a resource such as a logic device and other processes may wait until the flag is cleared before accessing the resource.

However, when these approaches are employed, only one function can be sent to the logic device at a time. Interrupts, whereby a communication relating to a first function is interrupted by a communication relating to a second function, are not possible. This may waste resources.

[0012] The present disclosure proposes using a transaction ID to identify which transaction each atomic unit in a communication belongs to. An atomic unit is a unit which can be sent or received (e.g. written or read) in a single atomic operation. A single atomic operation is an operation that may be completed in one cycle of a processor. As each atomic unit includes a transaction ID, it may not be necessary to employ a mutex or semaphore to prevent the communication from being interrupted. If the communication is interrupted, then subsequent atomic units relating to the interrupted communication may be identified by their transaction ID.

[0013] Figure 1 shows an example of communications between a central processing unit (CPU) 1 and a logic device 2. The logic device may for example be a FPGA, CPLD or ASIC etc. The CPU can communicate with the logic device via a bus or other connecting architecture.

[0014] At 10 the CPU 1 sends a first communication 100 to the logic device 2. The first communication 100 may for example be function request. The function request may include a single atomic unit or a plurality of atomic units. [0015] An atomic unit is a unit which can be sent or received (e.g. written or read) in a single atomic operation. A single atomic operation is an operation that may be completed in one cycle of the CPU 1 . As such the atomic operation may not be interrupted by other operations or threads. The atomic unit may for example be a "word". A "word" is a fixed length set of digits (binary, digital or hexadecimal etc) that is treated as a single unit by the instruction set of a logic device or CPU. For instance, if the CPU is able to process units of 32 bits in a single operation, then the atomic unit may be a 32 bit word.

[0016] In the example shown in Figure 1 the communication 100 is a function request including a plurality of atomic units 101 , 102 which together form a packet. Each atomic unit of the function request comprises a transaction ID 1 10 and main body 105, 106 which includes data or instructions. The transaction ID 1 10 identifies the atomic unit as relating to a particular transaction. A transaction is a process carried out between the CPU and the logic device, for instance it may be a function which is carried out by the logic device 1 on request from the CPU. As the atomic units 101 and 102 relate to the same function request the transaction ID 1 10 is the same for both. That is each atomic unit in the function request packet includes a transaction ID; and the transaction ID for each atomic unit is the same.

[0017] At 20 the logic device 2 receives the function request 100, processes the function request and at 30 sends a communication called a function response 100R to the CPU 1 . In the context of this disclose the logic device "sending" a function response to the CPU includes sending through a bus or other communication interface, putting the function response in a memory of the logic device which may be read by the CPU or otherwise making the function response available to the CPU.

[0018] The function response 100R may include a single atomic unit or a plurality of atomic units 101 R, 102R which together form a packet. Each atomic unit incudes data or instructions 105R, 106R and may include a transaction ID 1 10. The transaction ID 1 10 identifies the function response as relating to a particular transaction. The transaction ID is the same for each atomic unit in the function response. As the function response 100R relates to the same

transaction as the function request 100, the transaction ID 1 10 for atomic units in both the function request 100 and function response 100R may be the same. The CPU receives the function response 100R at 40, e.g. by reading it from a memory or receiving it at a communication interface, and processes it

accordingly.

[0019] At 50 a second function request 120 is sent from the CPU 1 to the logic device 2. The second function request 120 includes a single atomic unit or a plurality of atomic units 121 , 122 each of which includes a transaction ID 130. The same transaction ID 130 is used for each atomic unit in the second function request 120. As the second function request is a different transaction to the first function request the transaction ID 130 for the atomic units in the second function request is different than the transaction ID 1 10 for the atomic units in the first function request 100. It should be noted that. While in the example of Figure 1 the second function request is sent after the first function response has been received by the CPU, in other examples the second function response may be sent before the first function response has been received by the CPU.

[0020] At 60 the logic device 2 receives the second function request 120, processes the second function request and at 70 sends a second function response 120R to the CPU 1 . The second function response 120R may include a single atomic unit or a plurality of atomic units 121 R, 122R which together form a packet. Each atomic unit incudes data or instructions 125R, 126R and may include a transaction ID 130. The transaction ID identifies the atomic unit as relating to a particular transaction and is the same for each atomic unit in the second function response. As the second function response 120R relates to the same transaction as the second function request 120, the transaction ID 130 for atomic units in both the second function request 120 and second function response 120R may be the same. The second function response is received by the CPU at 80 and the CPU processes the second function response

accordingly. [0021] In the example of Figure 1 , the CPU sends the second function request

120 only after the first function request 100 has been sent by the CPU. In the example of Figure 2 the first function request is interrupted by the second function request. The first and second function requests may be for the same function, or different functions, and may be initiated by separate threads in the same CPU, from two different CPUs (e.g. different cores in a multicore CPU package) which are connected to the logic device.

[0022] At 140 a first atomic unit 101 of the first function request is sent by the CPU 1 to the logic device 20. The first atomic unit includes a main body 105 and a transaction ID 1 10. At 142 the first atomic unit 101 of the first function request is received by the logic device 2. Based on the transaction ID 1 10, the logic device 2 determines that the first atomic unit 101 relates to the first function. Based on this determination the logic device may assemble the first atomic unit 101 with other atomic units relating to the first function request to form a complete package.

[0023] At 144 the first function request is interrupted and a first atomic unit

121 of a second function request is sent by the CPU 1 , or another CPU, to the logic device 2. The first atomic unit 121 of the second function request includes a main body 125 and a transaction ID 130. At 148 the second logic device receives the first atomic unit 121 of the second function request. Based on the transaction ID 130, the logic device 2 determines that the first atomic unit 121 relates to the second function.

[0024] At 150 the second function request is interrupted and a second atomic unit 102 of the first function request is sent from the CPU 1 to the second logic device 20. The second atomic unit includes a main body 106 and a transaction ID 1 10. At 152 the second atomic unit 102 of the first function request is received by the logic device 2. Based on the transaction ID 1 10, the logic device 2 determines that the second atomic unit 102 relates to the first function request and assembles it together with the first atomic unit 101 .

[0025] At 154 a second atomic unit 122 of the second function request is sent by the CPU 1 , or another CPU, to the logic device 2. The second atomic unit 122 of the second function request includes a main body 126 and a transaction ID 130. At 158 the second logic device receives the second atomic unit 122 of the second function request. Based on the transaction ID 130, the logic device 2 determines that the second atomic unit 122 relates to the second function request and assembles it together with the first atomic unit 121 relating to the second function request.

[0026] At 160 a response to the first function request is sent by the logic device 2 to the CPU 1 . In this disclosure we refer to this response as the first function response 100R. The first function response 100R may include plural atomic units. Sending by the logic device to the CPU may be accomplished by sending through a communication interface, or writing the function response to a memory which is accessible by the CPU or otherwise making the function response available to the CPU.

[0027] In one example, the logic device 2 writes the function response to an area of memory. The memory may be in the logic device itself or elsewhere. The CPU reads the function response atomic unit by atomic unit from that area of memory. If the CPU is interrupted after reading an atomic unit, then it handles the interrupt and then goes back to the area of memory to read subsequent atomic units until the entire packet of the function response has been read by the CPU. In other examples the function response packet may be sent by the logic device to a communication interface of the CPU via a bus or other connecting

architecture.

[0028] In the illustrated example the function response 100R includes a first atomic unit 101 R and a second atomic unit 102R. Each atomic unit includes a main body 105R, 106R and may include a transaction ID 1 10 indicating that it relates to the first function. At 162 the first function response 100R is received by the CPU 1 . The CPU 1 determines that the first function response is a response to the first function request based on the transaction ID 1 10 or other identifiers contained in the function response packet and processes it accordingly.

[0029] While in the illustrated example all atomic units in the function response include a transaction ID, in some cases just one atomic unit in the function response may include a transaction ID. If the function response is read by the CPU from a memory area, then in the case of an interrupt the CPU may be programmed to assume that atomic units stored in the same memory area relate to the same transaction ID.

[0030] At 170 a second function response 120R is sent by the logic device 2 to the CPU 1 or other processor. The second function response 120R may include a plurality of atomic units 121 R, 122R and each atomic unit includes a main body 125R, 126R and may include a transaction ID 130 indicating that it relates to the second function response. At 172 the second function response 120R is received by the CPU 1 or other processor. The CPU 1 or other processor determines that the second function response 120R is a response to the second function request based on the transaction ID 130 or other identifiers in the function response and processes it accordingly.

[0031] Figure 3A is a method diagram from the perspective of the CPU. At block 310 the CPU obtains a transaction ID. For example the transaction ID may be obtained from the logic device. In one example the CPU sends a read command to an in-out (IO) address which is mapped to a first-in-first-out (FIFO) memory structure in the logic device. At block 320 the CPU sends a function request to the logic device and uses the transaction ID to identify the function request. At block 330 the CPU receives a function response from the logic device and processes it accordingly, for example by sending it to a thread which is waiting for the function response. The CPU may for example determine which function request the function response relates to based on a transaction ID in the function response, from another identifying field in the function response or otherwise. In some examples, the function request may be interrupted by other communications as explained above with reference to Figure 2.

[0032] Figure 3B is a method diagram showing an example of block 320 of Figure 3A in more detail. At 322 the function request is split into a plurality of atomic units. At 324 a transaction ID is added to each atomic unit, the transaction ID being the same for each atomic unit in the function request. At 326 each atomic unit is sent in turn from the CPU to the logic device. [0033] Figure 4 shows an example structure of a function request 100 in more detail. The function request includes a plurality of atomic units 101 , 102, 103. Each atomic unit may be thought of as a line of the function request. Each atomic unit may be sent by a single operation of the CPU. For instance, in one example, each atomic unit may be a 32 bit word and the CPU may be capable of sending or receiving 32 bits in a single operation. In other examples the atomic unit may be a word of a different length. In the illustrated example the function request includes n units, of which the first two 101 and 102 and the last one 103 are shown in Figure 4. Each atomic unit may include data or instructions in a main body 101 -M, 102-M, 103-M, a transaction ID (TID) and an end section (E) and a start section (S). The end section indicates the end of an atomic unit and the start section indicates the start of a new atomic unit. Another field may indicate an atomic unit which is the first in a function request packet and a field may indicate when an atomic unit is the last one in a function request packet. This is just one example and other formats of atomic unit may be used.

[0034] Figure 5 is a block diagram showing an example structure of a logic device 2 including a communication interface 510, a transaction ID module 520, a first function module 530, a second function module 540 and a transaction determining module 550. The communication interface 510 receives

communications from external and may include one port or a plurality of ports. The communication interface may be connected to the CPU and/or other external devices via a bus or other communication infrastructure.

[0035] The transaction ID module 520 manages transaction IDs. When a request for a transaction ID by an external device is received by the

communication interface 510, the request is directed to the transaction ID module and a transaction ID is returned via the communication interface. The transaction ID module may store a predetermined limited number of unique transaction IDs and may track which transaction IDs are available and which are in use. For the logic device may free the transaction ID after the related function has been completed or after the function response has been sent. The transaction ID module may be implemented by a memory in the logic device and associated logic circuitry.

[0036] In one example the transaction ID may be obtained by the CPU in a single atomic operation of the CPU. This avoids the use of mutex for obtaining a transaction ID. If obtaining a transaction ID required more than one operation of the CPU then a mutex or other mechanism would be necessary to prevent a request for a transaction ID being interrupted, or to prevent two processes requesting the same transaction ID.

[0037] The first function module 530 may comprise logic circuitry for performing a first function and generating a function response to the first function. The second function module 540 may comprise logic circuitry for performing a second function and generating a function response to the second function.

[0038] When an atomic unit relating to a function request is received at the communication interface of the logic device, the transaction determining module 550 may read the transaction ID field of the atomic module to determine how to handle the atomic module. The transaction determining module 550 may send the atomic unit to one of the first function module 530 and the second function module 540 based on the transaction ID. In this way the logic device is able to cope with interrupted function requests whereby atomic modules relating to a second function request are received before all the atomic modules relating to a first function request have been received by the logic device. Likewise when an atomic unit of a function response is generated by one of the first and second function modules the transaction determining module 550 may write a transaction ID into the atomic unit so that it may be identified as belonging to that

transaction. In other examples there may be more than two function modules in the logic device.

[0039] As mentioned above, the transaction ID may be provided by the logic device to the CPU upon request from the CPU. This relieves the operating system or application program from the burden of generating, tracking and assigning transaction IDs as this may all be handled by the logic device rather than the operating system or application running on the CPU. In one example the CPU may obtain the transaction ID by issuing a read command to an area of memory which is mapped to the logic device. In this way the application programmer can simply program the application running on the CPU to read a predetermined memory address whenever a transaction ID is needed and the logic device will return an available transaction ID. When the CPU subsequently needs another transaction ID, it may issue a read command again to the same address and receive a new transaction ID from among the pool of available transaction IDs.

[0040] In one example the transaction IDs are managed by a memory structure, such as a first-in-first-out (FIFO) memory structure or last-in-first-out (LIFO) memory structure. A FIFO memory structure is a memory structure including a plurality of entries, wherein in response to read commands entries are read in the order in which they were written with the most recently written entries being read first. A LIFO memory structure is a memory structure including a plurality of entries, wherein in response to read commands entries are read in the order in which they were written with the oldest or least recently written entries being read first.

[0041] A memory structure, such as FIFO or LIFO, is a convenient way of providing a source of transaction IDs which can read or written in a single atomic operation. The memory structure is able to use read and write pointers to assign the transaction IDs and track which ones are available. Thus, from the

perspective of the requesting CPU, the memory assigns or releases a transaction ID and handles the tracking of which transaction IDs are available in a single atomic operation of the CPU.

[0042] Figure 6 shows an example of a CPU 1 obtaining a transaction ID from a FIFO memory structure 600 in a logic device 2. The FIFO memory structure 600 may be implemented in a memory of the logic device 2. The FIFO memory structure 600 includes a plurality of memory segments 610-0, 610-1 ... to 610-n which form a FIFO queue, a read pointer 610 and a write pointer 620. When the FIFO memory structure is initialized the memory segments 610-0 to 610-n are each populated with a unique transaction ID. Thus at the start each memory segment stores a different transaction ID and the number of available transaction IDs is equal to the number of memory segments in the FIFO queue. The

"memory segments" may also be referred to as "memory entries". Each memory segment in the FIFO may be the same size. At 650 the CPU issues a memory read command to the FIFO memory structure. The CPU may issue this as a read command to a specific memory address which is mapped to the FIFO memory structure. In this way the application programmer need only program a read command to that memory address whenever a transaction ID is needed (the address is same each time) and the FIFO memory structure ensures that a unique, available transaction ID is provided each time.

[0043] At 660 the transaction ID is sent from the logic device to CPU. The processes 650 and 660 may appear to be a single operation from the perspective of other devices.

[0044] The transaction ID is of a size (e.g. number of bits) such that the CPU can read the transaction ID in a single atomic operation. Thus a transaction ID may be obtained from the FIFO memory structure in a single atomic operation. As the read operation is atomic and may not be interrupted there is no need for a mutex or semaphore while the transaction ID is being requested. This is in contrast to some software approaches in which assigning or freeing a transaction ID cannot be achieved in a single atomic operation and which would thus require a semaphore or mutex to prevent different functions from requesting the same transaction ID.

[0045] The FIFO uses the read pointer 620 and write pointer 630 to keep track of which transaction IDs are available and to determine which transaction ID to send in response to a read command from the CPU. In response to a read command the FIFO returns the contents of the memory segment which the read pointer points to. After responding to a read command the read pointer is moved by one segment, so the next segment is read in response to a subsequent read command. When a transaction ID is released and made available again, for example when a function has been completed, the released transaction ID is written to the location indicated by the write pointer. After writing the write pointer is moved by one segment.

[0046] If the FIFO queue is full then an error handling routine be initiated to hold the CPU or send an error interrupt. In some examples the FIFO memory is made sufficiently large that it holds more transaction IDs than are expected to be used in practice. Just by way of example, if no more than 20 transactions are expected to run in parallel, then the FIFO memory may have 200 memory segments. Thus if the FIFO memory runs out of available transaction IDs this may indicate that a serious error has occurred, such as run-away process on the CPU which is continually generating new transactions.

[0047] Unlike some approaches, with a FIFO or LIFO the transaction IDs do not need to be sequential. The transaction IDs should be unique but do not have to follow a particular order or sequence. Further, when a transaction ID for a new process is requested, it is not necessary to check the transaction ID against all currently used transaction IDs or existing processes to make sure the transaction ID is not already in use, as the memory structure takes care of this automatically through the read and write pointers which operate a queue. Thus using a FIFO or LIFO memory may be less processor intensive than checking a new transaction IDs against those already in use.

[0048] In the above examples the FIFO or LIFO memory structure is implemented in the logic device. For instance the FIFO or LIFO memory structure may be implemented in a RAM (random access memory) and may be formed from semiconductor memory chips. Associated logic circuitry may take care of the read and write pointers. Implementing the FIFO or LIFO memory structure in hardware on the logic device is efficient as the related processing may be carried out by the logic device circuitry. However, in other examples it would in principle be possible to implement a virtual FIFO or LIFO structure in memory using a CPU.

[0049] While a FIFO memory is used as an example above, in other examples the transaction IDs may be stored in a last-in-first-out (LIFO) memory. A LIFO memory structure is a memory structure including a plurality of entries, wherein in response to read commands entries are read in the order in which they were written with the oldest or least recently written entries being read first.

[0050] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[0051] Each feature disclosed in this specification (including any

accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Claims

WHAT IS CLAIMED IS:

A method comprising sending by a processor to a logic device a communication relating to a process handled by the logic device, the communication including a plurality of atomic units, each atomic unit including a transaction ID identifying the atomic unit as relating to said process, the communication being interruptible by communications relating to other processes handled by the logic device.

The method of claim 1 wherein the processor obtains a transaction ID by performing a single atomic operation.

The method of claim 1 wherein the processor obtains a transaction ID by performing a read operation to a first-in-first-out (FIFO) or last-in-first-out (LIFO) memory structure.

The method of claim 1 wherein the process is a function and wherein the processor obtains a transaction ID from the logic device and then sends a function request to the logic device, said function request including the transaction ID received from the logic device.

The method of claim 1 wherein the processor receives a function response from the logic device, said function response including said transaction ID.

A logic device comprising:

a transaction ID module to provide a transaction ID in response to a request from a central processing unit (CPU) for a transaction ID;

a transaction determining module to receive an atomic unit of a function request from a CPU and determine which function request the atomic unit relates to based on a transaction ID included in the atomic unit.

7. The logic device of claim 6 wherein the transaction ID module stores a predetermined limited number of transaction IDs and tracks which transaction IDs are in use and which are available.

8. The logic device of claim 6 wherein the transaction ID module is a memory structure including a plurality of segments which are populated with transaction IDs.

9. The logic device of claim 8 wherein the memory structure is a first-in-first- out (FIFO) memory structure or last-in-first-out memory structure.

10. The logic device of claim 9 wherein the logic device is to move a read pointer by one segment each time the CPU reads from the memory structure.

1 1 .The logic device of claim 9 wherein the logic device is to release a

transaction ID after a function response has been completed by writing the transaction ID to the memory structure at the position of a write pointer.

12. A non-transitory computer readable storage medium storing machine

readable instructions executable by a processor to obtain a transaction ID from a logic device and, after obtaining the transaction ID, send a function request to a logic device, the function request including the transaction ID which was obtained from the logic device.

13. The non-transitory computer readable storage medium of claim 12

wherein the function request includes multiple atomic units and the instructions include instructions to attach the transaction ID to each atomic unit.

14. The non-transitory computer readable storage medium of claim 12

wherein the instructions include instructions to request transaction IDs for plural different processes by a read operation to a memory address which is the same for each process, said memory address being mapped to the logic device.

15. The non-transitory computer readable storage medium of claim 14

wherein the memory address is mapped to a first-in-first-out (FIFO) or last- in-first-out (LIFO) memory in the logic device.