WO2015129552A1

WO2015129552A1 - Etching composition, etching method employing same, and production method for semiconductor substrate product

Info

Publication number: WO2015129552A1
Application number: PCT/JP2015/054680
Authority: WO
Inventors: 篤史水谷
Original assignee: 富士フイルム株式会社
Priority date: 2014-02-28
Filing date: 2015-02-19
Publication date: 2015-09-03
Also published as: TW201538688A; JP2015162653A; TWI682990B

Abstract

　Provided is an etching method for a substrate in which a first material containing NiPt, and at least one element from among In, Al, Ga, Sb, and As, is present, the etching method involving application of an acidic etching composition containing halogen ions and nitric acid or nitrate ions to a substrate.

Description

Etching composition, etching method using the same, and method for manufacturing semiconductor substrate product

The present invention relates to an etching composition, an etching method using the same, and a method for manufacturing a semiconductor substrate product.

The manufacture of an integrated circuit is composed of various processing steps in multiple stages. In the manufacturing process, deposition of various materials, lithography, etching, and the like are repeated many times. Among them, etching of a metal or metal compound layer is an important process. Certain metals must be selectively etched and other materials must remain without being corroded. It is required to remove only a specific material layer in a form that leaves a specific layer among a plurality of layers made of similar metal species or a more corrosive layer. The size of wirings and integrated circuits in a semiconductor substrate is becoming increasingly smaller, and the importance of accurately etching a layer (material) to be left without corrosion is increasing.
Taking a field effect transistor as an example, with the rapid miniaturization, there is a strong demand for thinning a silicide layer formed on the upper surface of a source / drain region and for developing a new material.
In a salicide (Salicide: Self-Aligned Silicide) process for forming a silicide layer, a part of a source region and a drain region made of silicon or the like formed on a semiconductor substrate and a metal layer attached to the upper surface thereof are annealed. As the metal layer, tungsten (W), titanium (Ti), cobalt (Co), or the like is applied, and recently nickel (Ni) is adopted. Thereby, a low-resistance silicide layer can be formed on the upper side of the source / drain electrodes and the like. For further miniaturization, it has also been proposed to form a NiPt silicide layer to which platinum (Pt) which is a noble metal is added.
After the salicide process, the metal layer left there is removed by etching. This etching is usually performed by wet etching, and a mixed solution of hydrochloric acid and nitric acid (aqua regia) is applied as the chemical solution. Patent Document 1 discloses an example using a chemical solution in which toluenesulfonic acid is added in addition to nitric acid and hydrochloric acid.
As a material change in the channel layer of the transistor, a material study is being performed in order to improve mobility, which is an electron transport property of the transistor. Application of Ge is considered promising for pMOS, and application of InGa, InGaAs, InAlAs, InP, GaP, InSb, etc., called III-V group has been proposed for nMOS (for example, see Non-Patent Document 1).

International Publication No. 2012/125401

It is an object of the present invention to selectively remove a layer containing a specific metal in a substrate on which a layer containing a so-called III-V group material such as InGaAs or InAlAs exists, and to exhibit excellent etching characteristics. It is in providing the composition, the etching method, and the manufacturing method of a semiconductor substrate product.

According to the present invention, the following means are provided.
That is, according to the present invention, etching of a substrate in which NiPt and a first material containing at least one of In, Al, Ga, Sb, and As (hereinafter sometimes referred to as a III-V group material) is present. This is an etching method in which an acidic etching composition containing halogen ions (halide ions) and nitric acid or nitrate ions is applied to a substrate.
In the above etching method, the content of halogen ions in the acidic etching composition is 10% by mass or less, the acidic etching composition further contains sulfonic acid, or the water content of the acidic etching composition is 50% by mass. Or less (more preferably 35% by mass or less).
In the etching method, Ge may further exist in the substrate, and the first material is InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, GaSb, AlSb, AlAs, InAlAs, and GaP. Of these, at least one of them is preferable, and InGaAs or InAlAs is more preferable.
The present invention is also an etching composition for a substrate in which NiPt and a first material containing at least one of In, Al, Ga, Sb, and As are present. Halogen ions and nitric acid or nitrate ions An acidic etching composition containing:
Further, the present invention relates to a substrate including a layer containing NiPt and a layer containing a first material containing at least one of In, Al, Ga, Sb, and As, halogen ions, , A method of manufacturing a semiconductor substrate product having an etching step of applying an acidic etching composition containing nitric acid or nitrate ions.

According to the etching composition of the present invention, the etching method using the same, and the method for manufacturing a semiconductor substrate product, NiPt can be selectively removed without removing the III-V group material, and excellent etching characteristics can be obtained. Show.
The above and other features and advantages of the present invention will become more apparent from the following description, with reference where appropriate to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of a manufacturing process example of a semiconductor substrate according to an embodiment of the present invention. FIG. 2 is a process diagram showing an example of manufacturing a MOS transistor according to an embodiment of the present invention.

All numerical limits (ie, upper and lower limits) of the ranges and ratios described herein are included. Ranges described herein include all intermediate numerical values within the range. In other words, all intermediate numerical values within the ranges described herein are considered to be all disclosed by the disclosure of the ranges. All possible combinations of the various disclosed elements are considered to be within the scope of the present invention unless specifically excluded.
Unless otherwise specified,% is% by mass. All temperatures are measured at Celsius temperature (° C.) unless otherwise noted.
First, a preferred embodiment of the etching method of the present invention will be described with reference to FIGS.

The present invention includes NiPt and a first material containing at least one of In, Al, Ga, Sb, and As (so-called III-V material, hereinafter simply referred to as III-V material). An etching method for an existing substrate, in which an acidic etching composition containing halogen ions and nitric acid or nitrate ions is applied to the substrate.
In the etching method, Ge (germanium) may further exist on the substrate.
In the present invention, NiPt can be selectively removed without removing the III-V group material (and possibly removing Ge as well), thereby improving the performance and yield of substrates and semiconductor substrate products described later. Can be achieved.
[Etching process]
FIG. 1 shows the semiconductor substrate before and after etching. In the manufacturing example of this embodiment, a metal layer (second layer) is formed on the upper surface of the semiconductor layer (first layer) 2 containing a first material containing at least one of In, Al, Ga, Sb, and As. ) 1 is arranged.
Examples of the semiconductor layer (first layer) include a source electrode, a drain electrode, and a channel dope layer, and these are preferably composed of a III-V group material or Ge (germanium). The III-V group material (first material) is preferably at least one of InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, GaSb, AlSb, AlAs, InAlAs, and GaP. More preferably, InGaAs or InAlAs. In the present invention, since the other metal can be selectively removed without removing the first material or its silicide, it is possible to improve the performance and yield of a substrate or semiconductor substrate product to be described later. it can.

The constituent material of the metal layer (second layer) 1 includes titanium (Ti), cobalt (Co), nickel (Ni), nickel platinum (NiPt), tungsten (W), tantalum (Ta), niobium (Nb), etc. In recent years, NiPt has been adopted from the viewpoint of low contact resistance. The metal layer can be formed by a method usually applied to this type of metal film, and specifically, film formation by CVD (Chemical Vapor Deposition) can be mentioned. The thickness of the metal layer at this time is not particularly limited, but examples include a film having a thickness of 5 nm to 50 nm. In the present invention, the metal layer is a NiPt layer (Pt content of more than 0% by mass and preferably 20% by mass or less) and a Ni layer (Pt content of 0% by mass) for selective removal of the etching composition of the present invention. Since the effect of this is exhibited, it is preferable.
The metal layer may contain other elements in addition to the metal atoms listed above. For example, oxygen and nitrogen inevitably mixed in may exist. The amount of inevitable impurities is preferably suppressed to, for example, about 1 ppt to 10 ppm (mass basis).

In the step (a), after the metal layer 1 is formed on the upper side of the semiconductor layer 2 (III-V group material-containing layer), annealing (sintering) is performed, and a metal-Si reaction film (first film) is formed at the interface. Three layers (silicide layers) 3 are formed (step (b)). Annealing may be performed under conditions normally applied to the manufacture of this type of device, and for example, treatment at 200 to 1000 ° C. may be mentioned. The thickness of the silicide layer 3 at this time is not particularly limited, but examples include a layer of 50 nm or less, and an example of a layer of 10 nm or less. Although there is no lower limit in particular, it is practical that it is 1 nm or more. This silicide layer is applied as a low-resistance film, and functions as a conductive portion that electrically connects a source electrode and a drain electrode located below the silicide layer and a wiring disposed thereon. Accordingly, when defects or corrosion occur in the silicide layer, this conduction is hindered, which may lead to quality degradation such as device malfunction. In particular, recently, the integrated circuit structure inside the substrate has been miniaturized, and even a minute damage can have a great influence on the performance of the element. Therefore, it is desirable to prevent such defects and corrosion as much as possible.
In this specification, in a broad sense, the silicide layer is a concept included in the first semiconductor layer 2 (III-V group material-containing layer). Therefore, when the second layer is selectively removed with respect to the first layer, the second layer (metal layer) is given priority over the non-silicided semiconductor layer 2 (III-V group material-containing layer). In addition to the mode of removing the first layer, the second layer (metal layer) is preferentially removed with respect to the silicide layer.

Next, the remaining metal layer 1 is etched (step (b)-> step (c)). In the present embodiment, the etching composition is applied at this time, and the metal layer 1 is removed by applying and contacting the etching composition from the upper side of the metal layer 1.
The semiconductor layer 2 (group III-V material-containing layer) is an epitaxial layer and can be formed by crystal growth on a silicon substrate having specific crystallinity by a chemical vapor deposition (CVD) method. Alternatively, an epitaxial layer formed with desired crystallinity may be formed by an electron beam epitaxy (MBE) method or the like.
In order to make the semiconductor layer 2 (group III-V material-containing layer) a P-type layer, boron (B) having a concentration of about 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ is doped. For the N-type layer, phosphorus (P) is doped at a concentration of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .
Through the salicide process, a layer containing both elements is formed as a silicide layer between the semiconductor layer (first layer) and the metal layer (second layer). This silicide layer is included in the first layer in a broad sense, but is referred to as a “third layer” when distinguished from this in a narrow sense. Its composition is not particularly _{_{_{_{limited, In x Ga y As z M}}}} p: the formula of (M metal element). At this time, x + y + z + p = 1, x is preferably 0.05 or more and 0.80 or less, y is preferably 0.05 or more and 0.40 or less, z is preferably 0.01 or more and 0.60 or less, and p is 0. .05 or more and 0.70 or less is preferable. However, the third layer may contain other elements. This is the same as described for the metal layer (second layer).
In addition, let the density | concentration of each element be the value measured with the following measuring methods. Specifically, the depth direction from 0 to 30 nm is analyzed by etching ESCA (Quanta Quantera manufactured by ULVAC-PHI), and the average value of Ge concentration in the analysis result of 3 to 15 nm is set as the element concentration (mass%).

(Processing of MOS transistors)
Since III-V compound semiconductors have extremely high electron mobility, they are expected as next-generation MOS transistor materials. Development of logic MOS transistors using group III-V compound semiconductors and quantum tunnel transistors capable of ultra-low voltage operation is in progress.
FIG. 2 is a process diagram showing an example of manufacturing a MOS transistor. (A) is a MOS transistor structure formation process, (B) is a metal film sputtering process, (C) is a first annealing process, (D) is a metal film selective removal process, and (E) is a second annealing process. It is a process.
As shown in the figure, a gate electrode 23 is formed through a gate insulating film 22 formed on the surface of the silicon substrate 21. Extension regions may be separately formed on both sides of the gate electrode 23. A protective layer (not shown) that prevents contact with the NiPt layer may be formed on the gate electrode 23. Further, a sidewall 25 made of a silicon oxide film or a silicon nitride film is formed, and a source region 26 and a drain region 27 are formed by ion implantation.
Next, as shown in the figure, a NiPt film 28 is formed and subjected to a rapid annealing process. The silicon substrate has an insulating film made of silicon oxide or aluminum oxide and a III-V group material layer or Ge. By annealing, the elements in the NiPt film 28 are diffused into the silicon substrate to be silicided. As a result, the upper portions of the source electrode 26 and the drain electrode 27 are silicided to form the NiPt-III-V group material-Si source electrode portion 26A and the NiPt-III-V group material-Si drain electrode portion 27A. Depending on the portion of the silicon substrate, the NiPt—Ge—Si source electrode portion 26A and the NiPt—Ge—Si drain electrode portion 27A are formed. At this time, if necessary, the electrode member is changed to a desired state (annealed silicide source electrode 26B, annealed silicide drain electrode 27B) by performing the second annealing as shown in FIG. be able to. The first and second annealing temperatures are not particularly limited, but can be performed at 400 to 1100 ° C., for example.

The NiPt film 28 remaining without contributing to silicidation can be removed by using the etching composition of the present invention (FIGS. 2C and 2D). At this time, what is shown in the figure is schematically shown, and there may or may not be a NiPt film deposited and left on top of the silicided layers (26A, 27A). The structure of the semiconductor substrate or its product is also shown in a simplified manner, and may be interpreted as having necessary members as necessary.

The following forms can be illustrated if the preferable example of a constituent material is given.
21 Silicon substrate Si, SiGe, Ge
Not shown Channel doped layer: III-V material or Ge
22 Gate insulating film: HfO ₂ (High-k)
23 Gate electrode: Al, W, TiN or Ta
25 Side wall: SiOCN, SiN or SiO ₂ (low-k)
26 Source electrode: III-V group material or Ge (n-type, p-type) *
27 Drain electrode: III-V group material or Ge (n-type, p-type) *
28 Metal layer: NiPt
Not shown Cap: TiN
Note that Ge is applied as a channel on the PMOS side, and InGaAs is promising on the NMOS side.

Etched metal films include noble metals (eg, Pt, Au, Pd, Ir, Ni, Mo, Rh, and Re), lanthanide metals (eg, erbium, gadolinium, ytterbium, yttrium, holmium, and dysprosium), and these (For example, NiPt (3 to 20%)). In particular, NiPt can be selectively removed.
High-k materials (eg, HfO ₂ , HfON, and HfSiON) that are highly integrated into a highly integrated circuit and are likely to be exposed to the etching composition and do not want to be etched Metal gate materials (eg, TiN, TaN, TiAlN, and W), interstitial layers (eg, Al ₂ O ₃ and La ₂ O ₅ ), fill metals (eg, aluminum), dielectrics (eg, , Si ₃ N ₄ and SiO ₂ ), semiconductors (eg, p-type and n-type doped Si, Ge, and SiGe), metal silicides to be etched (eg, nickel platinum silicide), contact materials (eg, NiGe) , NiPtGe, and NiInSb), and III-V materials (eg, InGaAs, InSb, aP, mention may be made of GaAs, InAs, AlGaSb, InAs, InAsSb, GaSb, AlSb, AlAs, the InAlAs and InP). The etching compositions and processes according to the present disclosure are optimized to minimize or do no damage to these films while still removing unwanted metals.
In certain embodiments, the metal etching process described herein provides (a) a semiconductor substrate having a metal film that is partially or wholly exposed to the etching composition of the present disclosure and thereby etchable. And (b) contacting the metal film to be etched with the etching composition of the present disclosure, and (c) cleaning the etched semiconductor substrate with a solvent (for example, a solvent containing water).
The etching composition can be contacted to the semiconductor substrate by any suitable means known to those skilled in the art. Such means include, but are not limited to, immersing the semiconductor substrate in a bath of the etching composition, or spraying or flowing the etching composition over the semiconductor substrate. Spraying or flowing the etching composition can be terminated when the substrate is covered with the etching composition, or can continue for some or all of the time that the etching composition is in contact with the semiconductor substrate. it can. Typically, the semiconductor substrate and the etching composition can be brought into full contact within seconds. Depending on the individual process, additional etching compositions can be used during the etching period or consistently during the period.
During the etching period, the process can include stirring means or the stirring means can be eliminated. For example, in a process that is an immersed embodiment, the etching composition can be circulated or agitated. Alternatively, the substrate can be rotated or moved up and down during etching. In the process, which is an embodiment of spraying or flowing, the semiconductor substrate is placed horizontally, but the substrate can be rotated horizontally. In any of the embodiments, the semiconductor substrate can be vibrated to induce agitation. One skilled in the art can determine the optimal combination of contact and agitation means depending on the particular application.
The etching period can typically be run from about 30 seconds to about 30 minutes. The time depends on the thickness of the film being etched, the need to avoid adverse effects on other exposed films, the particular etching composition used, the particular contact means used, and the temperature employed.
The temperature at which the metal film is etched is generally between 20 ° C. and 60 ° C. A preferred temperature range is from about 20 ° C to about 50 ° C. The most preferred temperature range is from about 30 ° C to about 50 ° C.
Following the etching step, the semiconductor substrate is cleaned with a solvent consisting of water, preferably deionized water. Any suitable cleaning method can be employed. Examples include immersing the semiconductor substrate in stagnant water or flowing water, or spraying or flowing water on the semiconductor substrate. The agitation described above may be employed during the etching period.
The aqueous solvent can include an additional water-soluble organic solvent. Use of water-soluble organic solvents helps remove organic residues and quick-dry.
Subsequent to the cleaning step, the drying of the semiconductor substrate is enhanced by using a drying means as an optional step. Examples of drying means include spraying a non-oxidizing gas such as nitrogen gas, rotating the substrate, or baking on a hot plate or in an oven.
Although the specific example to which the etching method of the present invention is applied has been described above, the present invention is not limited to this specific example, and can be applied to other semiconductor manufacturing methods. For example, the transistors disclosed in FIGS. 1 to 8 of WO 2011/087610 (special table 2013-511164) and the devices disclosed in FIGS. 1 to 22 of WO 2011/090583 (special table 2013-513975) can be given.

[Etching composition]
Next, a preferred embodiment of the etching composition of the present invention will be described.
The present invention is an etching composition for a substrate in which NiPt and a first material (III-V group material) containing at least one of In, Al, Ga, Sb, and As are present. An acidic etching composition containing nitric acid or nitrate ions. Halogen ion content of the acidic etching composition is 10% by mass or less, the acidic etching composition further contains sulfonic acid, and the water content of the acidic etching composition (aqueous composition) is 50% by mass or less (more Preferably, it is preferably 35% by mass or less. The acidic etching composition is preferably an aqueous composition and is preferably liquid. Hereinafter, each component including an arbitrary one will be described.

(Halogen ion)
The etching composition according to the present invention contains halogen ions. Among the halogen ions, chlorine ions, bromine ions, iodine ions, and fluorine ions are preferable, and chlorine ions and bromine ions are more preferable. The source of halogen ions is not particularly limited, but may be supplied as a salt with an organic cation described later, or may be supplied by adding a hydride (hydrochloric acid, hydrobromic acid, etc.).
The halogen ion concentration is preferably 0.01% by mass or more, more preferably 0.05% by mass or more, and particularly preferably 0.1% by mass or more in the etching composition. As an upper limit, 30 mass% or less is preferable, 27 mass% or less is more preferable, 25 mass% or less is further more preferable, and 10 mass% or less is especially preferable. By keeping the halogen ion in the above range, the III-V material-containing layer (first layer) or its silicide layer (third layer) is maintained while maintaining good etching properties of the metal layer (second layer). It is preferable because damage can be effectively suppressed. Regarding the identification of the components of the etching composition, it need not be confirmed as a compound. For example, in the case of hydrochloric acid, the presence and amount of chlorine ions (Cl ⁻ ) are identified in an aqueous solution. Is.
In the present invention, the halogen ions may be used alone or in combination of two or more. When using 2 or more types together, the combined use ratio is not particularly limited, but the total use amount is preferably within the above concentration range as the sum of two or more types of ions.

(Nitric acid or nitrate ion)
The etching composition according to this embodiment includes nitric acid or nitrate ions.
The concentration is preferably 0.1% by mass or more, more preferably 0.5% by mass or more, and particularly preferably 1% by mass or more in the etching composition. As an upper limit, 23 mass% or less is preferable, 20 mass% or less is more preferable, 16 mass% or less is further more preferable, and 3 mass% or less is especially preferable. 10 mass parts or more are preferable with respect to 100 mass parts of halogen ions, 30 mass parts or more are more preferable, and 50 mass parts or more are especially preferable. As an upper limit, 3000 mass parts or less are preferable, 1000 mass parts or less are more preferable, and 600 mass parts or less are especially preferable.
By keeping the concentration of nitric acid or nitrate ions in the above range, the III-V material-containing layer (first layer) or its silicide layer (first layer) is maintained while maintaining good etching properties of the metal layer (second layer). This is preferable because damage to the (three layers) can be effectively suppressed. The components of the etching composition need not be confirmed, for example, as nitric acid, but the presence and amount of nitrate ions (NO ₃ ⁻ ) are identified in the aqueous solution. is there. In addition, nitric acid or nitrate ion may use only 1 type, and may use 2 or more types together.

(Sulfonic acid compound)
The etching composition of the present invention may contain a sulfonic acid compound. Even if the sulfonic acid compound is an alkylsulfonic acid compound (preferably having 1 to 12 carbon atoms, more preferably 1 to 6 carbon atoms, and particularly preferably 1 to 3 carbon atoms), an aryl sulfonic acid compound (preferably having 6 to 14 carbon atoms) 6 to 10 is more preferable). The alkyl sulfonic acid compound may be a sulfonic acid compound having an aralkyl group (preferably having 7 to 15 carbon atoms, more preferably 7 to 11 carbon atoms).
As the alkylsulfonic acid compound, methanesulfonic acid, ethanesulfonic acid, octylsulfonic acid, methanedisulfonic acid, ethanedisulfonic acid, benzylsulfonic acid and the like are preferable.
The arylsulfonic acid compound is preferably any of the following formulas (S-1) to (S-3). In formula, Z < ¹ >, Z < ² > is a sulfonic acid group which may pass through the coupling group L. In FIG. R ⁵⁶ is a substituent, and an alkyl group (preferably having 1 to 12 carbon atoms, more preferably 1 to 6 carbon atoms, and particularly preferably 1 to 3 carbon atoms) is particularly preferable. n ⁵¹ and n ⁵⁶ are integers of 0 to 5. n ⁵³ is an integer of 0 to 4. The maximum value of n ⁵¹ , n ⁵³ , and n ⁵⁶ decreases with the number of Z ¹ or Z ^{2 in} the same ring. n ⁵² is an integer of 1 to 6, preferably 1 or 2. n ⁵⁴ and n ⁵⁵ are each independently an integer of 0 to 4, and n ⁵⁴ + n ⁵⁵ is 1 or more. n ⁵⁴ + n ⁵⁵ is preferably 1 or 2. n ⁵⁷ and n ⁵⁸ are each independently an integer of 0 to 5, and n ⁵⁷ + n ⁵⁸ is 1 or more. n ⁵⁷ + n ⁵⁸ is preferably 1 or 2. A plurality of R ⁵⁶ may be the same as or different from each other. The linking group L is preferably O, S, NR ^N , an alkylene group (preferably having 1 to 12 carbon atoms, more preferably 1 to 6 and particularly preferably 1 to 3), or a combination thereof. ^RN represents an alkyl group (preferably having 1 to 12 carbon atoms, more preferably 1 to 6 carbon atoms, particularly preferably 1 to 3 carbon atoms), an aryl group (preferably having 6 to 22 carbon atoms, more preferably 6 to 14 carbon atoms), or hydrogen. An atom is preferred.

Specific examples of the aryl sulfonic acid compound include p-toluene sulfonic acid, benzene sulfonic acid, 2-naphthalene sulfonic acid, naphthalene-1-sulfonic acid, 1,5-naphthalenedisulfonic acid, 2,6-naphthalenedisulfonic acid, and the like. It is done.
The concentration of the sulfonic acid compound is preferably 1% by mass or more, more preferably 5% by mass or more, and particularly preferably 30% by mass or more in the etching composition. As an upper limit, 80 mass% or less is preferable, 75 mass% or less is more preferable, and 70 mass% or less is especially preferable. The application of the sulfonic acid compound at the above concentration is preferable in that effective protection of the III-V group material and the germanium layer can be realized while realizing good etching of the metal layer.

(Organic cation)
The etching composition of the present invention may contain an organic cation, and is preferably a cation having a carbon atom and exhibiting alkalinity. Among these, organic onium is preferable, and organic ammonium is more preferable. Specifically, organic ammonium having 5 or more carbon atoms is preferable, and organic ammonium having 8 or more carbon atoms is more preferable. The upper limit is practically 35 or less carbon atoms.
About the effect | action which an organic cation shows in a system including estimation, it thinks as follows. In the etching composition of the present invention, it is understood that halogen ions and nitrate ions mainly exert an etching action on the metal layer (second layer). It is understood that the sulfonic acid compound has a function of reducing the solubility of the III-V material and germanium and suppressing the elution. Therefore, it is preferable to apply a considerable amount. This enhances the selective removal of the III-V material-containing layer (first layer) and the metal layer (second layer), but it is not sufficient. In the present invention, an organic cation is allowed to coexist therewith to adsorb it to the III-V group material-containing layer or the germanium surface, thereby forming an effective anticorrosion surface. Accordingly, a remarkable etching selectivity is exhibited in combination with the effect of suppressing the elution of the III-V material and germanium by the sulfonic acid compound. Further, when the number of carbon atoms of the organic cation is increased (5 or more), the dissolution of the III-V group material or germanium can be suppressed remarkably. From such an action, the organic cation only needs to be present in a very small amount in the system, and it is particularly preferable to select an amount and type that enhance the cooperative action with the sulfonic acid compound.

Examples of the organic onium include nitrogen-containing onium (such as quaternary ammonium), phosphorus-containing onium (such as quaternary phosphonium), and sulfur-containing onium (for example, SRy ₃ ⁺ : Ry is an alkyl group having 1 to 6 carbon atoms). Of these, nitrogen-containing onium (quaternary ammonium, pyridinium, pyrazolium, imidazolium, etc.) is preferable. In particular, the organic cation is preferably quaternary ammonium.
Examples of the organic onium include ions represented by the following formula (Q-1).

In the formula, R ^Q1 to R ^Q4 are each independently an alkyl group having 1 to 35 carbon atoms, an alkenyl group having 2 to 35 carbon atoms, an alkynyl group having 2 to 35 carbon atoms, an aryl group having 6 to 14 carbon atoms, 7 to 15 aralkyl groups, groups represented by the following formula (y). However, the total number of carbon atoms of R ^Q1 to R ^Q4 is preferably 5 or more, and more preferably 8 or more.

Y1- (Ry1-Y2) my-Ry2- * (y)

Y1 is an alkyl group having 1 to 12 carbon atoms, an alkenyl group having 2 to 12 carbon atoms, an alkynyl group having 2 to 12 carbon atoms, an aralkyl group having 7 to 14 carbon atoms, an aryl group having 6 to 14 carbon atoms, a hydroxyl group, A sulfanyl group, an alkoxy group having 1 to 4 carbon atoms, or a thioalkoxy group having 1 to 4 carbon atoms is represented. Y2 represents O, S, CO, NR ^N ( ^RN is a hydrogen atom or an alkyl group having 1 to 6 carbon atoms). Ry1 and Ry2 each independently represents an alkylene group having 1 to 6 carbon atoms, an alkenylene group having 2 to 6 carbon atoms, an alkynylene group having 2 to 6 carbon atoms, an arylene group having 6 to 10 carbon atoms, or a combination thereof. my represents an integer of 0 to 6. When my is 2 or more, the plurality of Ry1 and Y2 may be different from each other. Ry1 and Ry2 may further have a substituent T. * Is a bond.

The organic cation is preferably at least one selected from the group consisting of an alkyl ammonium cation, an aryl ammonium cation, and an alkyl / aryl ammonium cation.
Specifically, tetraalkylammonium (preferably having a carbon number of 5 to 35, more preferably 8 to 25, particularly preferably 10 to 25) is preferable. At this time, the alkyl group may be substituted with an arbitrary substituent (for example, a hydroxyl group, an allyl group, or an aryl group) as long as the effects of the present invention are not impaired. The alkyl group may be linear, branched or cyclic. Specifically, tetramethylammonium (TMA), tetraethylammonium (TEA), benzyltrimethylammonium, ethyltrimethylammonium, 2-hydroxyethyltrimethylammonium, benzyltriethylammonium, hexadecyltrimethylammonium, tetrabutylammonium (TBA), tetra Hexyl ammonium (THA), tetrapropyl ammonium (TPA), trimethylbenzyl ammonium, lauryl pyridinium, cetyl pyridinium, lauryl trimethyl ammonium, hexadecyl trimethyl ammonium, octadecyl trimethyl ammonium, didecyl dimethyl ammonium, dilauryl dimethyl ammonium, distearyl dimethyl ammonium , Georail dimethylan Chloride, lauryl dimethyl benzyl ammonium, cetyl trimethyl ammonium, cetyl trimethyl ammonium.

The source of the organic cation is not particularly limited, and examples thereof include the salt with the halogen ion and the salt with hydroxide ion.
The concentration of the organic cation is preferably 1 × 10 ⁻⁶ mol / L or more in the etching composition, more preferably 1 × 10 ⁻⁵ mol / L or more, and 5 × 10 ⁻⁵ mol / L or more. It is particularly preferred. The upper limit is preferably 1 mol / L or less, more preferably 0.5 mol / L or less, and particularly preferably 0.1 mol / L or less. By keeping the organic cation in the above range, the III-V material-containing layer (first layer) or its silicide layer (third layer) is maintained while maintaining good etching properties of the metal layer (second layer). It is preferable because damage can be effectively suppressed.

The organic cation preferably has a ClogP of −4 or more, more preferably 0 or more. By setting the ClogP of the organic cation within this range, it is preferable in that high etching selectivity can be realized while effectively protecting the III-V group material-containing layer.
The measurement of the octanol-water partition coefficient (log P value) can be generally carried out by a flask soaking method described in JIS Japanese Industrial Standard Z7260-107 (2000). Further, the octanol-water partition coefficient (log P value) can be estimated by a computational chemical method or an empirical method instead of the actual measurement. As the calculation method, Crippen's fragmentation method (J. Chem. Inf. Comput. Sci., 27, 21 (1987)), Viswanadhan's fragmentation method (J. Chem. Inf. Comput. Sci., 29, 163 (1989)), Broto's It is known to use a fragmentation method (Eur. J. Med. Chem.-Chim. Theor., 19, 71 (1984)). In the present invention, the Crippen's fragmentation method (J. Chem. Inf. Comput. Sci., 27, 21 (1987)) is used. The ClogP value is a value obtained by calculating the common logarithm logP of the distribution coefficient P between 1-octanol and water. Any method and software used for calculating the ClogP value can be used, but unless otherwise specified, ChemDraw Ultra 12.0 (trade name) is used in the present invention.

When a compound or a substituent / linking group includes an alkyl group / alkylene group, an alkenyl group / alkenylene group, an alkynyl group / alkynylene group, etc., these may be cyclic or linear, and may be linear or branched These may be substituted with any group or unsubstituted. In this case, an alkyl group, an alkylene group, an alkenyl group, an alkenylene group, an alkynyl group, an alkynylene group is a group containing a hetero atom (e.g., O, S, CO, NR ^N and the like) may be separated by a, with this To form a ring structure. Moreover, when an aryl group, a heterocyclic group, etc. are included, they may be monocyclic or condensed and may be similarly substituted or unsubstituted.
In the present specification, the technical matters such as temperature and thickness, as well as the choices of substituents and linking groups of the compounds, can be combined with each other even if the list is described independently.

(Aqueous medium)
In the etching composition of the present invention, in one embodiment, water (aqueous medium) is preferably applied as the medium. The water (aqueous medium) may be an aqueous medium containing a dissolved component as long as the effects of the present invention are not impaired, or may contain an unavoidable trace mixed component. Among these, water that has been subjected to purification treatment such as distilled water, ion-exchanged water, or ultrapure water is preferable, and ultrapure water that is used for semiconductor manufacturing is particularly preferable. The concentration of water is not particularly limited, but is preferably 10% by mass or more, and more preferably 15% by mass or more. As an upper limit, 95 mass% or less is preferable, 90 mass% or less is more preferable, 85 mass% or less is more preferable, 50 mass% or less is further more preferable, 35 mass% or less is especially preferable.
(PH)
In the present invention, the pH (25 ° C.) of the etching composition is preferably 3 or less, and more preferably 1 or less. The above range is preferable from the viewpoint of effectively preventing damage to the first layer or the third layer while securing a sufficient etching rate of the second layer.
In the present invention, pH is measured at room temperature (25 ° C.) with F-51 (trade name) manufactured by HORIBA.

Optional additives include solvents, carboxylic acids or other complexing agents, anti-corrosion agents, viscosity reducing agents, and surfactants, and are included in all embodiments to optimize performance and reduce costs. It may be used. The carboxylic acid can be used to improve the solubility of the metal ions by complementing chloride complex formation. The surfactant is not only a conventional purpose as a surface tension modifier, but also a wetting agent to inhibit corrosion on various exposed surfaces such as aluminum, silicon dioxide, silicon nitride, silicide, tungsten, and TiN. Can also be used. The solvent allows the Hansen solubility parameter to be changed as a solution to remove certain targeted organic residues and change the oxidation potential of the solution. The additive used may be a mixture of different types, a mixture of the same class of additives, or a mixture of both the same class and different types of additives. Note that the additive is stable under low pH and oxidizing conditions. In certain embodiments, the etching composition described herein comprises one or more organic solvents. In certain embodiments, the organic solvent suitable for use in the etching composition described herein excludes stabilizers such as glycols, ethers, and polyols. Examples of specific organic solvents (or stabilizers) that can be removed from the etching composition can include glyme, diglyme, triglyme, crown ethers, ethylene glycol, tripropylene glycol, and propylene glycol methyl ether. . In certain embodiments, the etching composition comprises one or more of the removed solvents described above. The concentration of the additive may depend on the effectiveness or purpose of each additive. The concentration of the additional solvent used is about 3% to about 35%. The concentration of the carboxylic acid, other complexing agent, viscosity reducing agent, and surfactant is about. 001% to about 10%.

(kit)
The etching composition in this invention is good also as a kit which divided | segmented the raw material into plurality. For example, the liquid composition containing the said halogen ion and organic cation in water as a 1st liquid is prepared, and the aspect which prepares the liquid composition containing nitric acid or nitrate ion as a 2nd liquid is mentioned. At this time, other components such as other sulfonic acid compounds can be contained separately or together in the first liquid, the second liquid, or the other third liquid.
As an example of its use, a mode in which both solutions are mixed to prepare an etching composition, and then applied to the etching treatment at an appropriate time is preferable. By doing in this way, it does not cause deterioration of the liquid performance by decomposition | disassembly of each component, and a desired etching effect | action can be exhibited effectively. Here, “timely” after mixing refers to the time period after mixing until the desired action is lost, specifically within 60 minutes, more preferably within 30 minutes, and more preferably within 10 minutes. Is more preferably within 1 minute, and particularly preferably within 1 minute. Although there is no lower limit in particular, it is practical that it is 1 second or more.
In addition, it is preferable that the etching composition of this invention has few impurities, for example, a metal content, etc. in a liquid in view of the use use. In particular, the Na, K, and Ca ion concentration in the liquid is preferably in the range of 1 ppt to 1 ppm (mass basis). In the etching composition, the number of coarse particles having an average particle size of 0.5 μm or more is preferably in the range of 100 particles / cm ³ or less, and is preferably in the range of 50 particles / cm ³ or less.

(container)
The etching composition of the present invention can be stored, transported and used in any container as long as corrosivity or the like does not matter (whether or not it is a kit). For semiconductor applications, a container having a high cleanliness and a low impurity elution is preferable. Examples of the containers that can be used include, but are not limited to, “Clean Bottle” series manufactured by Aicero Chemical Co., Ltd., “Pure Bottle” manufactured by Kodama Resin Co., Ltd., and the like.
[Etching conditions]
In the etching method of the present invention, it is preferable to use a single wafer type apparatus. Specifically, the single wafer type apparatus has a processing tank, and the semiconductor substrate is conveyed or rotated in the processing tank, and the etching composition is applied (discharge, jetting, flowing down, dropping, etc.) into the processing tank. The etching composition is preferably brought into contact with the semiconductor substrate.
Advantages of the single wafer type apparatus include (i) since a fresh etching composition is always supplied, so that reproducibility is good, and (ii) in-plane uniformity is high. Furthermore, a kit in which the etching composition is divided into a plurality of parts can be easily used. For example, a method of mixing and discharging the first liquid and the second liquid in-line is suitably employed. At this time, it is preferable to adjust the temperature of both the first liquid and the second liquid, or to adjust the temperature of only one of them and mix and discharge them in-line. Among these, an embodiment in which the temperature is controlled together is more preferable. The management temperature when adjusting the line temperature is preferably in the same range as the processing temperature described later.
The single wafer type apparatus is preferably provided with a nozzle in its treatment tank, and a method of discharging the etching composition onto the semiconductor substrate by swinging the nozzle in the surface direction of the semiconductor substrate is preferable. By doing so, the deterioration of the liquid can be prevented, which is preferable. In addition, it is preferable that a kit is divided into two or more liquids so that it is difficult to generate gas or the like.

The processing temperature at which etching is performed is preferably 10 ° C. or higher, and more preferably 20 ° C. or higher. The upper limit is preferably 80 ° C. or lower, more preferably 70 ° C. or lower, further preferably 60 ° C. or lower, further preferably 50 ° C. or lower, and preferably 40 ° C. or lower. Particularly preferred. By setting it to the above lower limit value or more, a sufficient etching rate for the second layer can be secured, which is preferable. By setting it to the upper limit value or less, it is preferable because the temporal stability of the etching processing rate can be maintained. In addition, the ability to process near room temperature leads to a reduction in energy consumption.
The etching processing temperature is based on the temperature applied to the substrate in the temperature measurement method shown in the examples described later. However, when the temperature is controlled by the storage temperature or batch processing, the temperature in the tank is controlled by the circulation system. In some cases, the temperature may be set in the circulation flow path.

The supply rate of the etching composition is not particularly limited, but is preferably 0.05 to 5 L / min, and more preferably 0.1 to 3 L / min. By setting it to the above lower limit value or more, it is preferable because uniformity in the etching plane can be ensured. By setting it to the upper limit value or less, it is preferable because stable performance can be secured during continuous processing. When the semiconductor substrate is rotated, although it depends on its size and the like, it is preferably rotated at 50 to 1000 rpm from the same viewpoint as described above.

In single-wafer etching according to a preferred embodiment of the present invention, a semiconductor substrate is transported or rotated in a predetermined direction, and an etching composition is sprayed into the space to bring the etching composition into contact with the semiconductor substrate. Is preferred. The supply rate of the etching composition and the rotation speed of the substrate are the same as those already described.
The metal layer is preferably etched at a high etching rate. The etching rate [R2] of the second layer (metal layer) is not particularly limited, but is preferably 20 Å / min or more, more preferably 100 Å / min or more, and 200 Å / min or more in consideration of production efficiency. It is particularly preferred. Although there is no upper limit in particular, it is practical that it is 1200 kg / min or less.

Although the exposed width of the metal layer is not particularly limited, it is preferably 2 nm or more, more preferably 4 nm or more from the viewpoint that the advantages of the present invention become more prominent. Similarly, from the viewpoint of conspicuous effect, the upper limit is practically 1000 nm or less, preferably 100 nm or less, and more preferably 20 nm or less.

The etching rate [R1] of the first layer or its silicide layer (third layer) is not particularly limited, but is preferably not excessively removed, preferably 200 Å / min or less, and 100 Å / min or less. Is more preferably 50 Å / min or less, further preferably 20 Å / min or less, and particularly preferably 10 Å / min or less. There is no particular lower limit, but considering the measurement limit, it is practical that it is 0.1 Å / min or more.
In the selective etching of the first layer, the etching rate ratio ([R2] / [R1]) is not particularly limited, but it is preferably 2 or more on the premise of an element that requires high selectivity. It is more preferably 10 or more, further preferably 20 or more, and particularly preferably 50 or more. The upper limit is not particularly defined and is preferably as high as possible, but is practically 5000 or less. The etching condition of the silicide layer (third layer) is broadly synonymous with the III-V group material-containing layer (first layer), and the layer before the annealing (for example, the III-V group material-containing layer) It can be substituted depending on the etching rate.

Furthermore, in the etching composition according to a preferred embodiment of the present invention, a metal electrode layer such as Al, Cu, Ti, or W, an insulating film such as HfO, HfSiO, AlO _x , SiO, SiOC, SiON, TiN, SiN, or TiAlC Since damage to the layers (which may be collectively referred to as the fourth layer) can be suitably suppressed, it is also preferable to be applied to a semiconductor substrate including these layers. In addition, in this specification, when the composition of a metal compound is expressed by a combination of elements, it means that a composition having an arbitrary composition is widely included. For example, SiOC (SiON) means that Si, O, and C (N) coexist, and does not mean that the ratio of the amounts is 1: 1: 1. This is common in this specification, and the same applies to other metal compounds.

The time required for etching one substrate is preferably 10 seconds or more, and more preferably 50 seconds or more. As an upper limit, it is preferable that it is 300 seconds or less, and it is more preferable that it is 200 seconds or less.

[Manufacture of semiconductor substrate products]
In the present embodiment, a step of forming a semiconductor substrate on which a group III-V material or Ge-containing layer and a metal layer are formed on a silicon wafer; a step of annealing the semiconductor substrate; and an etching composition on the semiconductor substrate. It is preferable to manufacture a semiconductor substrate product having a desired structure through a step of applying and selectively removing the metal layer by bringing the etching composition into contact with the metal layer. At this time, the specific etching composition is used for etching. The order of the above steps is not construed as being limited, and further steps may be included between the steps.
The wafer size is not particularly limited, but a wafer having a diameter of 8 inches, a diameter of 12 inches, or a diameter of 14 inches can be suitably used (1 inch = 25.4 mm).
In this specification, the term “preparation” means that a specific material is synthesized or blended, and a predetermined item is procured by purchase or the like. In this specification, using an etching composition so as to etch each material of a semiconductor substrate is referred to as “application”, but the embodiment is not particularly limited. For example, the method widely includes contacting the etching composition with the substrate. Specifically, the etching composition may be etched by being immersed in a batch type, or may be etched by discharging a single wafer type.
In this specification, the term “semiconductor substrate” is used to mean not only a wafer but also the entire substrate structure having a circuit structure formed thereon. A semiconductor substrate member refers to the member which comprises the semiconductor substrate defined above, and may consist of one material or may consist of several materials. A processed semiconductor substrate is sometimes referred to as a semiconductor substrate product, and is further distinguished as necessary, and a chip that has been processed and diced out and processed product thereof is referred to as a semiconductor element. That is, in a broad sense, a semiconductor element or a semiconductor product incorporating the semiconductor element belongs to a semiconductor substrate product.

Hereinafter, the present invention will be described in more detail with reference to examples. However, the present invention is not limited to the following examples. In addition, unless otherwise indicated,% and part shown as prescription and compounding quantity in an Example are mass references | standards.

[Example 1]
(Production of test substrate)
On a commercially available silicon substrate (diameter: 12 inches), a NiPt layer, an InGaAs layer, an InAlAs layer, and a Ge layer were formed to a thickness of 500 mm, and four types of blank wafers were prepared.
(Etching test)
The blank wafer was etched using a single wafer type apparatus (SPOS-Europe BV, POLOS (trade name)) under the following conditions, and an evaluation test was performed.
-Processing temperature: described in the table-Discharge rate: 1 L / min.
-Wafer rotation speed: 500 rpm
・ Nozzle moving speed: 7cm / S
・ Etching composition: listed in the table (method for measuring processing temperature)
A radiation thermometer IT-550F (trade name) manufactured by HORIBA, Ltd. was fixed at a height of 30 cm above the wafer in the single wafer type apparatus. A thermometer was directed onto the wafer surface 2 cm outside from the wafer center, and the temperature was measured while flowing a chemical solution. The temperature was digitally output from the radiation thermometer and recorded continuously with a personal computer. Among these, the value obtained by averaging the temperature for 10 seconds at which the temperature was stabilized was defined as the temperature on the wafer.
(Etching rate)
About the etching rate (ER), it computed by measuring the film thickness before and behind an etching process using ellipsometry (a spectroscopic ellipsometer, JA Woolum Japan Co., Ltd. Vase was used). An average value of 5 points was adopted (measurement condition measurement range: 1.2-2.5 eV, measurement angle: 70, 75 degrees).

Although the present disclosure has been described herein with reference to specific embodiments, it will be understood that variations, modifications, and variations may be made without departing from the spirit and scope of the inventive concepts described herein. be able to. Accordingly, it is intended to embrace all such alterations, modifications and variations that do not depart from the spirit and scope of the appended claims.

While this invention has been described in conjunction with its embodiments, we do not intend to limit our invention in any detail of the description unless otherwise specified and are contrary to the spirit and scope of the invention as set forth in the appended claims. I think it should be interpreted widely.

This application claims priority based on Japanese Patent Application No. 2014-038710 filed in Japan on February 26, 2014, which is hereby incorporated herein by reference. Capture as part.

1 Metal layer (second layer)
2 Semiconductor layer (first layer)
3 Silicide layer (third layer)
21 Silicon substrate 22 Gate insulating film 23 Gate electrode 25 Side wall 26 Source electrode 27 Drain electrode 28 NiPt film

Claims

NiPt,
A substrate etching method in which a first material containing at least one of In, Al, Ga, Sb, and As is present,
An etching method in which an acidic etching composition containing halogen ions and nitric acid or nitrate ions is applied to a substrate.
The etching method according to claim 1, wherein the content of halogen ions in the acidic etching composition is 10% by mass or less.
The etching method according to claim 1, wherein the acidic etching composition further contains a sulfonic acid.
2. The etching method according to claim 1, wherein the water content of the acidic etching composition is 50% by mass or less.
The etching method according to claim 1, wherein the water content of the acidic etching composition is 35% by mass or less.
The etching method according to claim 1, wherein Ge is further present on the substrate.
The etching method according to claim 1,
An etching method in which the first material is at least one of InGaAs, InP, InAs, AlGaSb, InSb, InAs, GaAs, InAsSb, GaSb, AlSb, AlAs, InAlAs, and GaP.
The etching method according to claim 1,
An etching method in which the first material is InGaAs or InAlAs.
NiPt,
An etching composition for a substrate in which a first material containing at least one of In, Al, Ga, Sb, and As is present,
An acidic etching composition comprising halogen ions and nitric acid or nitrate ions.
For a substrate having a layer containing NiPt and a layer containing a first material containing at least one of In, Al, Ga, Sb and As, halogen ions, nitric acid or nitrate ions The manufacturing method of the semiconductor substrate product which has an etching process which applies the acidic etching composition containing this.