WO2015039337A1 - Semiconductor structure - Google Patents
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- WO2015039337A1 WO2015039337A1 PCT/CN2013/083967 CN2013083967W WO2015039337A1 WO 2015039337 A1 WO2015039337 A1 WO 2015039337A1 CN 2013083967 W CN2013083967 W CN 2013083967W WO 2015039337 A1 WO2015039337 A1 WO 2015039337A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 149
- 239000000463 material Substances 0.000 claims abstract description 103
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 150000001875 compounds Chemical class 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 150000003377 silicon compounds Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
- H01L29/221—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds including two or more compounds, e.g. alloys
- H01L29/225—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
A semiconductor structure, comprising a first semiconductor material layer (106) and a second semiconductor material layer (108) which have different stresses. By using the stack collocation of the first semiconductor material layer (106) and the second semiconductor material layer (108), in the case where the first semiconductor material layer (106) and the second semiconductor material layer (108) are respectively compressed and stretched, or stretched and compressed, the channel stress in a semiconductor element is adjusted, thereby forming a stressed channel.
Description
半导体结构 技术领域 Semiconductor structure
本实用新型涉及半导体结构， 特别涉及受应变的半导体元件。 背景技术 The utility model relates to a semiconductor structure, in particular to a strained semiconductor component. Background technique
半导体是一种导电能力介于导体与非导体之间的材料， 而所谓半导体 元件就是以半导体材料所特有的特性所制造出来的电子元件， 因为半导体 元件属于固态元件 (Solid State Device), 其体积可以缩小到很小的尺寸。 近 来， 称为金属氧化半导体 (Metal-Oxide-Semiconductor; MOS)的晶体管， 因 为具有耗电量少并且适合高集成度等优点， 在半导体元件中具有广泛的应 用。 MOS晶体管的基本结构除了具备由金属层、 氧化层与半导体层所构成 的电容器外， 还包含两个位于 MOS电容器两旁， 其电性与硅基材相反的半 导体区： 源极 (Source)与漏极 (Drain)。 A semiconductor is a material whose electrical conductivity is between a conductor and a non-conductor, and a so-called semiconductor component is an electronic component manufactured by the characteristics unique to a semiconductor material, because the semiconductor component belongs to a solid state device (Solid State Device), and its volume Can be reduced to a small size. Recently, a transistor called Metal-Oxide-Semiconductor (MOS) has a wide range of applications in semiconductor devices because of its low power consumption and high integration. The basic structure of the MOS transistor includes, in addition to the capacitor composed of the metal layer, the oxide layer and the semiconductor layer, two semiconductor regions which are located on both sides of the MOS capacitor and whose electrical properties are opposite to the silicon substrate: source and drain Drain.
MOS可分为 n型金属氧化半导体（NMOS)和 p型金属氧化半导体 (PMOS) , 其中 NMOS以电子来传输， PMOS以空穴来传输， 由于电子在电 场下的迁移率比空穴高， 所以在同样的设计下， NMOS元件的速度将比 PMOS的速度快， 因此为了提高元件的操作速度， 早期的 MOS元件都是以 NMOS晶体管为主来设计。 MOS can be divided into n-type metal oxide semiconductor (NMOS) and p-type metal oxide semiconductor (PMOS), in which NMOS is transmitted by electrons, PMOS is transmitted by holes, and since electron mobility under electric field is higher than that of holes, Under the same design, the speed of the NMOS device will be faster than that of the PMOS. Therefore, in order to improve the operating speed of the device, the early MOS devices are mainly designed with NMOS transistors.
由于半导体元件尺寸的不断缩微 (Scaled Down), 使得超大规模集成电 路的速度持续地提升。 然而， 当进入次微米世代， 半导体元件的缩微由于 不同的物理及技术上限制而变得困难重重。 此外， 在 CMOS电路中， 由于 空穴迁移率 (Hole Mobility)小于电子的迁移率， 为了让 CMOS中的 PMOS及 NMOS的电流驱动能够匹配， 因此通常将 PMOS的面积设计成 NMOS的 2〜3 倍。 然而， 这样的设计使的元件的整合及速度都受到影响。 因此， 为了要 进一步改善集成电路的速度， 就必须提出新的元件结构或使用新的材料。
发明内容 Due to the shrinking of the size of semiconductor components, the speed of VLSIs continues to increase. However, when entering sub-micron generations, the micronization of semiconductor components has become difficult due to various physical and technical limitations. In addition, in a CMOS circuit, since the hole mobility (Hole Mobility) is smaller than the mobility of electrons, in order to match the current driving of the PMOS and the NMOS in the CMOS, the area of the PMOS is usually designed to be 2 to 3 times that of the NMOS. . However, such a design affects the integration and speed of components. Therefore, in order to further improve the speed of the integrated circuit, it is necessary to propose a new component structure or use a new material. Summary of the invention
为了制造高速度的次微米 CMOS元件， 因此， 本实用新型的目的为提 供一种半导体结构， 利用具压缩应力与伸张应力的半导体材料层的搭配， 可应用于一般基材或绝缘层上硅晶基材中， 借以调整通道应力。 In order to manufacture a high-speed sub-micron CMOS device, the object of the present invention is to provide a semiconductor structure that can be applied to a general substrate or a silicon layer on an insulating layer by using a combination of a semiconductor material layer having a compressive stress and a tensile stress. In the substrate, the channel stress is adjusted.
根据以上所述的目的， 本实用新型的半导体结构可包括： 第一半导体 材料层， 以及堆栈于第一半导体材料层上的与第一半导体材料层具不同应 力的第二半导体材料层。 此第一半导体材料层与第二半导体材料层分别具 有不同晶格常数， 因此会在第一半导体材料层压缩且第二半导体材料层伸 张或者第一半导体材料层伸张且第二半导体材料层压缩的情况下， 借以互 相牵制而调整应力。 上述半导体可应用于一般无绝缘层的基材或者绝缘层 上石圭晶基材。 In accordance with the above objects, a semiconductor structure of the present invention can include: a first layer of semiconductor material, and a second layer of semiconductor material stacked on the first layer of semiconductor material that is different from the first layer of semiconductor material. The first semiconductor material layer and the second semiconductor material layer respectively have different lattice constants, and thus the first semiconductor material layer is compressed and the second semiconductor material layer is stretched or the first semiconductor material layer is stretched and the second semiconductor material layer is compressed. In this case, the stress is adjusted by mutual restraint. The above semiconductor can be applied to a substrate which is generally free of an insulating layer or a substrate of an insulating layer.
将本实用新型的结构应用在电子元件中， 由于可调整通道应力以改善 载子迁移率， 从而提升现有集成电路技术。 附图简要说明 The structure of the present invention is applied to electronic components, and the existing integrated circuit technology can be improved by adjusting channel stress to improve carrier mobility. BRIEF DESCRIPTION OF THE DRAWINGS
下面结合附图对本实用新型的具体实施方式作进一步详细的描述。 附图中， The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. In the drawings,
图 1为本实用新型半导体结构应用于绝缘层上硅基材的剖面示意图； 图 2为本实用新型半导体结构一实施例剖面图； 1 is a schematic cross-sectional view showing a semiconductor structure applied to a silicon substrate on an insulating layer; FIG. 2 is a cross-sectional view showing an embodiment of the semiconductor structure of the present invention;
图 3为本实用新型半导体结构另一实施例剖面图； 以及 Figure 3 is a cross-sectional view showing another embodiment of the semiconductor structure of the present invention;
图 4为本实用新型半导体结构再一实施例剖面图。 具体实施方式 4 is a cross-sectional view showing still another embodiment of the semiconductor structure of the present invention. detailed description
为了制造高速度次微米 CMOS 元件， 必须增加通道的载子迁移率 (Carrier Mobility)并降低源极与漏极的寄生电容 (Parasitic Capacitance)。硅材 料中的载子迁移率， 特别是空穴迁移率， 会因为次微米 CMOS元件的应变 速率 (Switching Speed)的发展限制而非常低。 为了克服这样的问题， 本实用 新型揭露一种受应变的半导体结构， 利用具有不同应力的半导体材料层间 的互相影响， 以进行通道的应力调整。 In order to fabricate high-speed sub-micron CMOS components, it is necessary to increase the carrier Mobility of the channel and reduce the parasitic capacitance of the source and drain (Parasitic Capacitance). The carrier mobility in silicon materials, especially hole mobility, is very low due to the developmental limitations of the secondary micron CMOS components' switching speed. In order to overcome such problems, the present invention discloses a strained semiconductor structure that utilizes the mutual influence of layers of semiconductor materials having different stresses to perform stress adjustment of the channels.
本实用新型揭露一种半导体结构，利用具压缩应力 (Compressive Stress)
的半导体材料与伸张应力 (Tensile Stress)的半导体材料相互堆栈而形成一 半导体结构。 其中， 由于一半导体材料具有不同应力， 两者的晶格常数并 不相同。 因此， 在一半导体材料压缩且另一半导体材料伸张的情况下， 互 相牵制而形成张力通道 (Strained-Channel) , 从而可增加电子或空穴迁移率。 The utility model discloses a semiconductor structure using Compressive Stress The semiconductor material and the semiconductor material of Tensile Stress are stacked on each other to form a semiconductor structure. Among them, since a semiconductor material has different stresses, the lattice constants of the two are not the same. Therefore, in the case where one semiconductor material is compressed and the other semiconductor material is stretched, it is mutually restrained to form a strained channel, thereby increasing electron or hole mobility.
上述的具压缩应力的半导体材料以及具伸张应力的半导体材料都可选 自于合金半导体（Alloy Semiconductor)、元素半导体（Element Semiconductor) 或是化合物半导体 (Compound Semiconductor)材料。一般合金半导体材料例 如有锗化硅 (SiGe)、 碳锗硅 (SiGeC)或碳化硅 (SiC)等； 元素半导体材料则有 硅和锗等等； 而化合物半导体则例如有砷化镓 (GaAs)、 砷铝化镓 (GaAlAs) 或磷化铟 (InP)等分别由 III V族或 II VI族化合物所构成的半导体材料等。 上 述材料可互相搭配利用， 本实用新型不限于此。 The above-mentioned semiconductor materials having compressive stress and semiconductor materials having tensile stress can be selected from alloy semiconductors, element semiconductors or compound semiconductor materials. Generally, alloy semiconductor materials are, for example, silicon germanium (SiGe), silicon germanium (SiGeC) or silicon carbide (SiC); elemental semiconductor materials include silicon and germanium; and compound semiconductors such as gallium arsenide (GaAs). A semiconductor material composed of a group III V or a group II VI compound, such as gallium arsenide (GaAlAs) or indium phosphide (InP). The above materials can be used in combination with each other, and the present invention is not limited thereto.
本实用新型的半导体结构可先利用具压缩应力或具伸张应力的半导体 材料为基材， 再将另一具相反应力的半导体材料沉积于其上。 或者， 可在 一般基材或绝缘层上硅基材 (Silicon-On-Insulator; SOI)结构上， 形成本实用 新型的半导体结构， 本实用新型不限于此。 The semiconductor structure of the present invention may first utilize a semiconductor material having compressive stress or tensile stress as a substrate, and then deposit another semiconductor material of opposite stress on it. Alternatively, the semiconductor structure of the present invention may be formed on a silicon substrate (Silicon-On-Insulator; SOI) structure on a general substrate or an insulating layer, and the present invention is not limited thereto.
图 1 为本实用新型半导体结构应用于绝缘层上硅基材结构的剖面示意 图。 请参照图 1， 绝缘层上硅基材一般由硅基材 100以及绝缘层 102所构 成， 并且在绝缘层上具有含硅薄膜层 (未绘示)。但是， 本实用新型在此利用 第一半导体材料层 106以及位于第一半导体材料层 106上的第二半导体材 料层 108， 来取代一般的含硅薄膜层。 其中， 第一半导体材料层 106具有 压缩应力， 而第二半导体材料层 108具有伸张应力， 由于第一半导体材料 层 106与第二半导体材料层 108的互相影响， 从而可调整第一半导体材料 层 106与第二半导体材料层 108中的通道应力。 Fig. 1 is a schematic cross-sectional view showing the structure of a semiconductor substrate applied to a silicon substrate on an insulating layer. Referring to FIG. 1, the silicon substrate on the insulating layer is generally composed of a silicon substrate 100 and an insulating layer 102, and has a silicon-containing film layer (not shown) on the insulating layer. However, the present invention utilizes a first layer of semiconductor material 106 and a second layer of semiconductor material 108 on the first layer of semiconductor material 106 in place of a typical silicon-containing film layer. Wherein, the first semiconductor material layer 106 has a compressive stress, and the second semiconductor material layer 108 has a tensile stress. Due to the mutual influence of the first semiconductor material layer 106 and the second semiconductor material layer 108, the first semiconductor material layer 106 can be adjusted. The channel stress in the second layer of semiconductor material 108.
在本实用新型较佳实施例中， 上述绝缘层 102 由埋入氧化层所构成， 一般为二氧化硅材质， 而第一半导体材料层 106 由锗化硅材料所构成， 第 二半导体材料层 108则由硅材料所构成。 并且， 第一半导体材料层 106与 第二半导体材料层 108的较佳厚度都小于 400人。 值得注意的是， 本实用新 型上述材料与厚度仅为举例，可根据实际产品与所调整的应力值加以改变， 本实用新型不限于此。 In a preferred embodiment of the present invention, the insulating layer 102 is formed of a buried oxide layer, generally of silicon dioxide, and the first semiconductor material layer 106 is composed of a silicon germanide material, and the second semiconductor material layer 108. It is made of silicon material. Moreover, the preferred thickness of the first semiconductor material layer 106 and the second semiconductor material layer 108 are less than 400. It should be noted that the above-mentioned materials and thicknesses of the present utility model are merely examples, and may be changed according to actual products and adjusted stress values, and the present invention is not limited thereto.
另外， 当本实用新型的半导体结构仅使用一般的硅基材 100时， 第一
半导体材料层 106则直接位于硅基材 100上方， 而第二半导体材料层 108 再位于第一半导体材料层 106上。 此时， 第一半导体材料层会与一主动区 域 (Active Area) (未绘示)连接， 并与硅基材之间， 以空气隧道 (Air Tunnel)来 进行绝缘。 In addition, when the semiconductor structure of the present invention uses only the general silicon substrate 100, the first The layer of semiconductor material 106 is directly over the silicon substrate 100, and the second layer of semiconductor material 108 is again over the first layer of semiconductor material 106. At this time, the first semiconductor material layer is connected to an active area (not shown) and insulated from the silicon substrate by an air tunnel.
不论上述本实用新型半导体结构、 位于绝缘层上硅基材的结构或位于 一般硅基材的结构， 都可进行后续制造而形成半导体元件。 本实用新型以 数个实施例来进行说明。 Regardless of the above-described semiconductor structure of the present invention, the structure of the silicon substrate on the insulating layer, or the structure of the general silicon substrate, subsequent fabrication can be performed to form the semiconductor device. The invention has been described in terms of several embodiments.
在本实用新型一实施例中， 在上述半导体结构中形成数个绝缘区域 110， 如图 2所示。 一般来说， 这些绝缘区域 110可为浅沟渠隔离结构， 但 这些绝缘区域 110位于第一半导体材料层 106或第二半导体材料层 108中 时， 可选择让其带有不同的应力， 而分别导致这些半导体材料层具有更多 应力。 例如， 当绝缘区域 110具有伸张应力， 则会导致第一半导体材料层 106具有更多的压缩应力； 而绝缘区域 110具有压缩应力， 会导致第二半 导体材料层 108具有更多的伸张应力。 In an embodiment of the invention, a plurality of insulating regions 110 are formed in the semiconductor structure, as shown in FIG. In general, the insulating regions 110 may be shallow trench isolation structures, but when the insulating regions 110 are located in the first semiconductor material layer 106 or the second semiconductor material layer 108, they may be selected to have different stresses, respectively These layers of semiconductor material have more stress. For example, when the insulating region 110 has a tensile stress, the first semiconductor material layer 106 is caused to have more compressive stress; and the insulating region 110 has a compressive stress, which causes the second semiconductor material layer 108 to have more tensile stress.
或者在本实用新型另一实施例中， 还在图 2 的结构中形成电性与基材 100相反的半导体区， 源极 112与漏极 114， 如图 3所示。 并且同样的， 如 上述的绝缘区域 100， 若源极 112与漏极 114具有伸张应力， 则会导致第 一半导体材料层 106具有更多的压缩应力； 若源极 112与漏极 114具有压 缩应力， 则会导致第二半导体材料层 108具有更多的伸张应力。 Or in another embodiment of the present invention, a semiconductor region opposite to the substrate 100, the source 112 and the drain 114 are formed in the structure of FIG. 2, as shown in FIG. And similarly, as the insulating region 100 described above, if the source 112 and the drain 114 have tensile stress, the first semiconductor material layer 106 has more compressive stress; if the source 112 and the drain 114 have compressive stress This will result in the second layer of semiconductor material 108 having more tensile stress.
而在本实用新型再一实施例中， 还在图 3 的结构上形成例如为覆盖层 ( Cap Layer) 的沉积层 116等等， 如图 4所示， 该沉积层 116覆盖于源极 112与漏极 114上， 或仅覆盖其中之一。 若沉积层 116具有压缩应力， 则 会导致第一半导体材料层 106具有更多的压缩应力； 若沉积层 116具有伸 张应力， 则会导致第二半导体材料层 106具有更多的伸张应力。 In still another embodiment of the present invention, a deposition layer 116 such as a cap layer is formed on the structure of FIG. 3, and as shown in FIG. 4, the deposition layer 116 covers the source 112 and On the drain 114, or only one of them is covered. If the deposited layer 116 has compressive stress, it will cause the first semiconductor material layer 106 to have more compressive stress; if the deposited layer 116 has tensile stress, the second semiconductor material layer 106 will have more tensile stress.
或者， 如图 3所示， 更可形成硅化合物 （图未示） ， 此硅化合物可位 于源极 112或漏极 114上。 而当此硅化合物具有伸张应力， 则会导致第一 半导体材料层 106具有更多的压缩应力； 若硅化合物具有压缩应力， 则会 导致第二半导体材料层 106具有更多的伸张应力。 Alternatively, as shown in FIG. 3, a silicon compound (not shown) may be formed, and the silicon compound may be located on the source 112 or the drain 114. When the silicon compound has tensile stress, the first semiconductor material layer 106 has more compressive stress; if the silicon compound has compressive stress, the second semiconductor material layer 106 has more tensile stress.
值得注意的是， 上述第一半导体材料层具有压缩应力， 而第二半导体 材料层 108具有伸张应力仅为举例， 在其他实施例中， 也可让第一半导体
材料层具有伸张应力， 并在其上形成具有压缩应力的第二半导体材料层。 并且， 上述本实用新型的半导体结构并非仅限于单一第一半导体材料层与 单一第二半导体材料层的相互堆栈， 可根据产品或工艺需要而以更多数量 相互堆栈而成， 本实用新型不限于此。 It should be noted that the first semiconductor material layer has a compressive stress, and the second semiconductor material layer 108 has a tensile stress. For example, in other embodiments, the first semiconductor may also be used. The material layer has a tensile stress and a second layer of semiconductor material having a compressive stress is formed thereon. Moreover, the semiconductor structure of the present invention is not limited to the mutual stacking of a single first semiconductor material layer and a single second semiconductor material layer, and may be stacked in a larger amount according to product or process requirements, and the present invention is not limited to this.
本实用新型的特点在于， 以具有压缩应力的材料与具有伸张应力的材 料的互相搭配， 因此可根据需要而调节所制造的半导体元件的通道应力， 从而形成受应变的通道。 由于本实用新型的半导体结构可增加电子或空穴 的迁移率， 因此不论在 NMOS或 PMOS晶体管中， 都可具有较现有半导体 元件高的操作速度。 而这些优点， 对现有半导体技术来说， 实为一大进步。 The present invention is characterized in that the material having the compressive stress and the material having the tensile stress are matched with each other, so that the channel stress of the manufactured semiconductor element can be adjusted as needed to form a strained passage. Since the semiconductor structure of the present invention can increase the mobility of electrons or holes, it can have a higher operating speed than existing semiconductor elements in either NMOS or PMOS transistors. These advantages are a big step forward for existing semiconductor technologies.
可以理解的是,对于本领域的普通技术人员来说,可以根据本实用新型 的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变 和变形都应属于本实用新型所附的权利要求的保护范围。
It should be understood that various other changes and modifications may be made in accordance with the technical solutions and technical concept of the present invention, and all such changes and modifications are included in the present invention. The scope of protection of the claims.
Claims
1、 一种半导体结构， 至少包括： 1. A semiconductor structure, at least including:
至少一第一半导体材料层； 以及 at least one first semiconductor material layer; and
至少一第二半导体材料层位于该第一半导体材料层上，其中该第一半导体 材料层与该第二半导体材料层具有不同性质的应力，并且该第一半导体材料层 与该第二半导体材料层相互堆栈，借以在该第一半导体材料层与该第二半导体 材料层分别压缩与伸张或伸张与压缩的情况下， 互相牵制造成应变。 At least a second semiconductor material layer is located on the first semiconductor material layer, wherein the first semiconductor material layer and the second semiconductor material layer have stresses of different properties, and the first semiconductor material layer and the second semiconductor material layer Stacked on each other, so that when the first semiconductor material layer and the second semiconductor material layer are compressed and stretched or stretched and compressed respectively, they are entangled with each other to cause strain.
2、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第一半导体 材料层由合金半导体所构成， 并且该第一半导体材料层的材料选自于由锗化 硅、 碳锗化硅与碳化硅所组成的一族群。 2. The semiconductor structure according to claim 1, wherein the first semiconductor material layer is composed of an alloy semiconductor, and the material of the first semiconductor material layer is selected from the group consisting of silicon germanium and silicon carbon germanium. A group composed of silicon carbide.
3、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第二半导体 材料层由合金半导体所构成， 并且该第二半导体材料层的材料选自于由锗化 硅、 碳锗化硅与碳化硅所组成的一族群。 3. The semiconductor structure according to claim 1, wherein the second semiconductor material layer is composed of an alloy semiconductor, and the material of the second semiconductor material layer is selected from the group consisting of silicon germanium and silicon carbon germanium. A group composed of silicon carbide.
4、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第一半导体 材料层由元素半导体所构成，并且该第一半导体材料层的材料选自于由硅与锗 所组成的一族群。 4. The semiconductor structure according to claim 1, wherein the first semiconductor material layer is composed of an elemental semiconductor, and the material of the first semiconductor material layer is selected from a group consisting of silicon and germanium. .
5、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第二半导体 材料层由元素半导体所构成，并且该第二半导体材料层的材料选自于由硅与锗 所组成的一族群。 5. The semiconductor structure according to claim 1, wherein the second semiconductor material layer is composed of elemental semiconductor, and the material of the second semiconductor material layer is selected from a group consisting of silicon and germanium. .
6、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第一半导体 材料层由化合物半导体所构成，并且该第一半导体材料层的材料选自于由砷化 镓、 砷铝化镓与磷化铟等 III V族与 II VI族化合物所组成的一族群。 6. The semiconductor structure according to claim 1, wherein the first semiconductor material layer is composed of a compound semiconductor, and the material of the first semiconductor material layer is selected from the group consisting of gallium arsenide and gallium arsenide aluminum. A group composed of III V and II VI compounds such as indium phosphide.
7、 根据权利要求 1所述的半导体结构， 其特征在于， 上述的第二半导体 材料层由化合物半导体所构成， 且该第二半导体材料层的材选自于由砷化镓、 砷铝化镓与磷化铟等 III V族与 II VI族化合物所组成的一族群。 7. The semiconductor structure according to claim 1, wherein the second semiconductor material layer is composed of a compound semiconductor, and the material of the second semiconductor material layer is selected from the group consisting of gallium arsenide and gallium arsenide aluminum. A group composed of III V and II VI compounds such as indium phosphide.
8、 根据权利要求 1所述的半导体结构， 其特征在于， 还包括数个绝缘区 域，该绝缘区域具有伸张应力，并导致该第一半导体材料层具有更多压缩应力。 8. The semiconductor structure according to claim 1, further comprising a plurality of insulating regions, the insulating regions having tensile stress and causing the first semiconductor material layer to have more compressive stress.
9、 根据权利要求 8所述的半导体结构， 其特征在于， 上述的绝缘区域具
有压缩应力， 并导致该第二半导体材料层具有更多伸张应力。 9. The semiconductor structure according to claim 8, characterized in that the above-mentioned insulating region has There is compressive stress, resulting in more tensile stress in the second semiconductor material layer.
10、根据权利要求 1所述的半导体结构， 其特征在于， 还包括至少一源极 区域与至少一漏极区域， 上述的源极区域或漏极区域具有伸张应力， 并导致该 第一半导体材料层具有更多压缩应力。
10. The semiconductor structure of claim 1, further comprising at least one source region and at least one drain region, the source region or the drain region having tensile stress, causing the first semiconductor material to The layer has more compressive stress.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2779620Y (en) * | 2004-07-22 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN100446270C (en) * | 2003-04-03 | 2008-12-24 | 台湾积体电路制造股份有限公司 | Semiconductor-structure |
| CN102292811A (en) * | 2009-01-26 | 2011-12-21 | 格罗方德半导体公司 | Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446270C (en) * | 2003-04-03 | 2008-12-24 | 台湾积体电路制造股份有限公司 | Semiconductor-structure |
| CN2779620Y (en) * | 2004-07-22 | 2006-05-10 | 台湾积体电路制造股份有限公司 | Semiconductor structure |
| CN102292811A (en) * | 2009-01-26 | 2011-12-21 | 格罗方德半导体公司 | Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions |
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