WO2015033417A1

WO2015033417A1 - Semiconductor storage device and data writing method

Info

Publication number: WO2015033417A1
Application number: PCT/JP2013/073917
Authority: WO
Inventors: 白川　政信
Original assignee: 株式会社東芝
Priority date: 2013-09-05
Filing date: 2013-09-05
Publication date: 2015-03-12
Also published as: CN105518794A; JPWO2015033417A1

Abstract

A semiconductor storage device according to one embodiment is equipped with multiple memory cells, word lines, bit lines, and a row decoder. The memory cells are stacked on a semiconductor substrate. The word lines are connected to the gates of the memory cells. The bit lines are electrically connected to the current paths of the memory cells, and are capable of transmitting data. The row decoder applies a voltage to the word lines. Data is written to a memory cell by multiple repetitions of a program loop that includes a program operation and a verification operation. In one program loop the row decoder sequentially applies the program voltage M times (where M is a natural number of 1 or greater) to a selected word line, and then sequentially applies a verification voltage N times (where N is larger than M and is a natural number of 3 or greater) to the selected word line.

Description

Semiconductor memory device and data writing method

Embodiments described herein relate generally to a semiconductor memory device and a data writing method.

A NAND flash memory in which memory cells are arranged three-dimensionally is known.

Provide a semiconductor memory device and a data writing method capable of improving the data writing speed.

The semiconductor memory device according to the embodiment includes a plurality of memory cells, a word line, a bit line, and a row decoder. Memory cells are stacked on a semiconductor substrate. The word line is connected to the gate of the memory cell. The bit line is electrically connected to the current path of the memory cell and can transfer data. The row decoder applies a voltage to the word line. Data writing to the memory cell is executed by repeating a program loop including a program operation and a verify operation a plurality of times. In one program loop, the row decoder sequentially applies a first program voltage and a second program voltage different from the first program voltage to the selected word line.

FIG. 1 is a block diagram of the semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram of the memory cell array according to the first embodiment. FIG. 3 is a perspective view of the memory cell array according to the first embodiment. FIG. 4 is a plan view of the memory cell array according to the first embodiment. FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. FIG. 6 is a cross-sectional view taken along line 6-6 in FIG. FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. FIG. 8 is a graph showing the threshold distribution of the memory cell according to the first embodiment. FIG. 9 is a circuit diagram of the memory cell array according to the first embodiment. FIG. 10 is a flowchart showing a data writing method according to the first embodiment. FIG. 11 is a timing chart of word line potentials at the time of data writing according to the first embodiment. FIG. 12 is a timing chart showing changes in the word line potential during data writing. FIG. 13 is a flowchart showing a data writing method according to the second embodiment. FIG. 14 is a timing chart showing changes in the word line potential when data is written according to the second embodiment. FIG. 15 is a flowchart showing a data writing method according to the third embodiment. FIG. 16 is a timing chart showing changes in the word line potential at the time of data writing according to the third embodiment. FIG. 17 is a flowchart showing a data writing method according to the fourth embodiment. FIG. 18 is a timing chart showing changes in the word line and bit line potentials when writing data according to the fourth embodiment. FIG. 19 is a circuit diagram of a memory cell array according to the fourth embodiment. FIG. 20 is a graph showing a threshold value change of the memory cell according to the fourth embodiment. FIG. 21 is a block diagram of a sense amplifier module, an arithmetic module, and a data latch module according to the fifth embodiment. FIG. 22 is a graph showing changes in the word line potential during data writing according to the fifth embodiment. FIG. 23 is a graph showing changes in word line and bit line potentials during data writing according to the fifth embodiment. FIG. 24 is a block diagram of a memory system according to the sixth embodiment. FIG. 25 is a timing chart of various signals during the write operation in the first mode according to the sixth embodiment. FIG. 26 is a timing chart of various signals during the write operation in the second mode according to the sixth embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

1. First embodiment
A semiconductor memory device according to the first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cells are stacked on a semiconductor substrate will be described as an example.

1.1 Configuration of semiconductor memory device
First, the configuration of the semiconductor memory device according to this embodiment will be described.

1.1.1 Overall configuration of semiconductor memory device
FIG. 1 is a block diagram of the semiconductor memory device according to the present embodiment. As illustrated, the NAND flash memory 1 includes a memory cell array 10, a row decoder 11, a sense amplifier module 12, an arithmetic module 13, a data latch module 14, and a control unit 17.

The memory cell array 10 includes a plurality of nonvolatile memory cells. The memory cell is, for example, a MOS transistor having a stacked gate including a charge storage layer and a control gate, and each is associated with a row and a column. The control gates of the memory cells located in the same row are connected to the same word line WL, the drains of the memory cells located in the same column are connected to the same bit line BL, and the sources are connected to the source line SL. . Details of the memory cell array 10 will be described later.

The row decoder 11 selects the row direction of the memory cell array 10. That is, the row decoder 11 selects the word line WL at the time of data writing, reading, and erasing, and applies an appropriate voltage to the selected word line and the non-selected word line.

The sense amplifier module 12 includes a sense circuit provided for each bit line. Each of the sense circuits senses and amplifies data read from the memory cell to the bit line BL when reading data. The sense circuit transfers data to be written in the memory cell to the bit line BL when data is written.

The arithmetic module 13 includes an arithmetic circuit provided for each bit line. Each of the arithmetic circuits performs an operation using data sensed and amplified by the sense circuit when reading data. Further, the arithmetic circuit performs an operation using the write data at the time of data writing, and transfers the operation result to the sense circuit.

The data latch module 14 includes a latch circuit provided for each bit line. Each of the latch circuits holds read data transferred from the sense circuit via the arithmetic circuit when reading data. The latch circuit outputs read data to the outside. The latch circuit temporarily holds write data received from the outside during data writing. The latch circuit transfers write data to the sense circuit via the arithmetic circuit.

The control unit 15 controls the operation of the entire flash memory 1.

1.1.2 Configuration of memory cell array
FIG. 2 is a circuit diagram of the memory cell array 10 according to the present embodiment. As shown in the drawing, the memory cell array 10 includes a plurality of memory units MU (MU1, MU2). Although only two memory units MU are illustrated in FIG. 2, the number may be three or more, and the number is not limited.

Each of the memory units MU includes, for example, four string loops GR (GR1 to GR4). When distinguishing between the memory units MU1 and MU2, the string groups GR of the memory unit MU1 are referred to as GR1-1 to GR4-1, respectively, and the string groups GR of the memory unit MU2 are respectively referred to as GR1-2 to GR4-2. Call it.

Each of the string groups GR includes, for example, three NAND strings SR (SR1 to SR3). Of course, the number of NAND strings SR is not limited to three and may be four or more. Each of the NAND strings SR includes select transistors ST1 and ST2 and four memory cell transistors MT (MT1 to MT4). The number of memory cell transistors MT is not limited to four, but may be five or more, or may be three or less. The memory cell transistor MT includes a stacked gate including a control gate and a charge storage layer, and holds data in a nonvolatile manner. The memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

In the string group GR, the three NAND strings SR1 to SR3 are sequentially stacked on the semiconductor substrate, the NAND string SR1 is formed in the lowermost layer, and the NAND string SR3 is formed in the uppermost layer. The select transistors ST1 and ST2 included in the same string group GR are connected to the same select gate lines GSL1 and GSL2, respectively, and the control gates of the memory cell transistors MT located in the same column are connected to the same word line WL. Is done. Further, the drains of the three selection transistors ST1 in a certain string group GR are connected to different bit lines BL, and the sources of the selection transistors ST2 are connected to the same source line SL.

In the odd-numbered string groups GR1 and GR3 and the even-numbered string groups GR2 and GR4, the selection transistors ST1 and ST2 are arranged so that their positional relationships are reversed. That is, in the example of FIG. 2, the select transistors ST1 of the string groups GR1 and GR3 are arranged at the left end of the NAND string SR, and the select transistors ST2 are arranged at the right end of the NAND string SR. On the other hand, the select transistors ST1 of the string groups GR2 and GR4 are arranged at the right end of the NAND string SR, and the select transistors ST2 are arranged at the left end of the NAND string SR.

The gates of the select transistors ST1 in the string groups GR1 and GR3 are connected to the same select gate line GSL1, and the gates of the select transistors ST2 are connected to the same select gate line GSL2. On the other hand, the gates of the select transistors ST1 of the string groups GR2 and GR4 are connected to the same select gate line GSL2, and the gates of the select transistors ST2 are connected to the same select gate line GSL1.

Further, four string groups GR1 and GR2 included in a certain memory unit MU are connected to the same bit line BL, and different memory units MU are connected to different bit lines BL. More specifically, in the memory unit MU1, the drains of the selection transistors ST1 of the NAND strings SR1 to SR3 in the string groups GR1 to GR4 are connected to the bit lines BL1 to BL3 via the column selection gates CGS (CGS1 to CGS4), respectively. Is done. The column selection gate CGS has, for example, the same configuration as the memory cell transistor MT, the selection transistors ST1 and ST2, and the like, and selects one string group GR selected for the bit line BL in each memory unit MU. Accordingly, the gates of the column selection gates CGS1 to CSG4 associated with each string group GR are controlled by different control signal lines SSL1 to SSL4, respectively.

A plurality of memory units MU having the above-described configuration are arranged in the vertical direction on the paper surface illustrated in FIG. The plurality of memory units MU share the memory unit MU1 with the word line WL and the select gate lines GSL1 and GSL2. On the other hand, the bit lines BL are independent, and for example, three bit lines BL4 to BL6 different from the memory unit MU1 are associated with the memory unit MU2. The number of bit lines BL associated with each memory unit MU corresponds to the total number of NAND strings SR included in one string group GR. Therefore, if there are four layers of NAND strings, four bit lines BL are provided, and the same applies to other numbers. The control signals SSL1 to SSL4 may be shared between the memory units MU, or may be controlled independently.

In the above configuration, a set of a plurality of memory cell transistors MT connected to the same word line WL in the string group GR selected one by one from each memory unit MU is a unit called “page”. Data writing and reading are performed in units of pages.

3 is a perspective view of the memory cell array 10, FIG. 4 is a plan view of the memory cell array 10, FIG. 5 is a cross-sectional view taken along line 5-5 in FIG. 4, and FIG. FIG. 7 is a cross-sectional view taken along line 6 and FIG. 7 is a cross-sectional view taken along line 7-7 in FIG. 3, FIG. 5, and FIG. 7 show one memory unit MU, and FIG. 4 and FIG. 6 show two memory units MU1 and MU2.

As illustrated, an insulating film 21 is formed on the semiconductor substrate 20, and the memory cell array 10 is formed on the insulating film 21.

On the insulating film 21, for example, four fin-type structures 24 (24-1 to 24-4) having a stripe shape along a second direction perpendicular to the first direction that is perpendicular to the surface of the semiconductor substrate 20 are formed. As a result, one memory unit MU is formed. Each of the fin-type structures 24 includes insulating films 22 (22-1 to 22-4) and semiconductor layers 23 (23-1 to 23-3) that are alternately stacked. Each of the fin-type structures 24 corresponds to the string group GR described with reference to FIG. The lowermost semiconductor layer 23-1 corresponds to the current path (region where a channel is formed) of the NAND string SR1, and the uppermost semiconductor layer 23-3 corresponds to the current path of the NAND string SR3. The located semiconductor layer 23-2 corresponds to the current path of the NAND string SR2.

A gate insulating film 25, a charge storage layer 26, a block insulating film 27, and a control gate 28 are sequentially formed on the upper surface and side surfaces of the fin structure 24 (see FIG. 5). The charge storage layer 26 is formed of an insulating film, for example. The control gate 28 is formed of a conductive film and functions as the word line WL or select gate lines GSL1 and GSL2. The word lines WL and select gate lines GSL1 and GSL2 are formed so as to straddle the plurality of fin-type structures 24 between the plurality of memory units MU. On the other hand, the control signal lines SSL 1 to SSL 4 are independent for each fin-type structure 24.

One end of the fin-type structure 24 is drawn to the end of the memory cell array 10 and connected to the bit line BL in the drawn region. That is, focusing on the memory unit MU1 as an example, one end portions of the odd-numbered fin-type structures 24-1 and 24-3 are drawn out to a certain region along the second direction, and are connected to this region. Plugs BC1 to BC3 are formed. The contact plug BC1 formed in this region connects the semiconductor layer 23-1 and the bit line BL1 of the string groups GR1 and GR3, and is insulated from the semiconductor layers 23-2 and 23-3. The contact plug BC2 connects the semiconductor layer 23-2 of the string groups GR1 and GR3 and the bit line BL2, and is insulated from the semiconductor layers 23-1 and 23-3. The contact plug BC3 connects the semiconductor layer 23-3 and the bit line BL3 of the string groups GR1 and GR3, and is insulated from the semiconductor layers 23-1 and 23-2.

On the other hand, one end of the even-numbered fin structures 24-2 and 24-4 is drawn out to a region facing the one end of the fin structures 24-1 and 24-3 in the second direction and connected in common. In this region, contact plugs BC1 to BC3 are formed. The contact plug BC1 formed in this region connects the semiconductor layer 23-1 and the bit line BL1 of the string groups GR2 and GR4, and is insulated from the semiconductor layers 23-2 and 23-3. The contact plug BC2 connects the semiconductor layer 23-2 of the string groups GR2 and GR4 and the bit line BL2, and is insulated from the semiconductor layers 23-1 and 23-3. The contact plug BC3 connects the semiconductor layer 23-3 and the bit line BL3 of the string groups GR2 and GR4, and is insulated from the semiconductor layers 23-1 and 23-2.

Of course, the above description is for the memory unit MU1. For example, in the case of the memory unit MU2, contact plugs BC4 to BC6 are formed, which are connected to the bit lines BL4 and the semiconductor layers 23-1 to 23-3, respectively. To BL6 (see FIG. 6).

Further, a contact plug SC is formed on the other end of the fin structure 24. The contact plug SC connects the semiconductor layers 23-1 to 23-3 to the source line SL.

In the above configuration, the memory cell transistors included in the NAND strings SR1 to SR3 have different sizes. More specifically, as shown in FIG. 5, in each fin-type structure 24, the width of the semiconductor layer 23 along the third direction is larger as it is located in the lower layer and smaller as it is located in the higher layer. That is, the width of the semiconductor layer 23-1 is the widest, the width of the semiconductor layer 23-3 is the narrowest, and the width of the semiconductor layer 23-2 is intermediate. That is, one page includes a plurality of memory cell transistors MT having different characteristics due to manufacturing variations.

1.1.3 Regarding Threshold Distribution of Memory Cell Transistor FIG. 8 shows a possible threshold distribution of the memory cell transistor MT according to the present embodiment. As shown in the drawing, the memory cell transistor MT can hold, for example, 2-bit data according to the threshold value. The 2-bit data is, for example, “Ep” level, “A” level, “B” level, and “C” level in order from the lowest threshold value.

The “EP” level is a threshold value when data is erased, and has a positive value, for example, and is lower than the verify voltage Vfy_A. The “A” to “C” levels are threshold values in a state where charges are injected into the charge storage layer. The “A” level has a threshold value higher than the verify voltage Vfy_A and lower than the verify voltage Vfy_B. The “B” level has a threshold value higher than the verify voltage Vfy_B and lower than the verify voltage Vfy_C, and the “C” level has a threshold value higher than the verify voltage Vfy_C.

Thus, by taking four threshold levels, each memory cell transistor MT can store 2-bit data (4-level data).

1.2 Data write operation
Next, a data write operation according to the present embodiment will be described. In the description of the write operation, a description will be given with reference to FIG. 9 in order to define the memory cell transistor MT based on the position (layer) and write data. FIG. 9 is a circuit diagram of the memory cell array 10. For the sake of simplicity, FIG. 9 shows a case where only two memory units MU1 and MU2 are included in the memory cell array 10, and the control signal lines SSL1 and SSL5 are selected. Thus, the case where the string group GR1-1 in the memory unit MU1 and the string group GR1-2 in the memory unit MU2 are selected is shown. Accordingly, a page is formed by the six memory cell transistors MT connected to the same word line WL in the string groups GR1-1 and GR1-2. For the sake of space, only the selected string groups GR1-1 and GR1-2 are shown, and the column selection gate CGS is not shown. The following description is the same when other combinations of string groups are selected.

As described above, in a certain string group GR, the memory cell transistor MT (NAND string SR1) located in the lowermost layer has the largest width of the semiconductor layer 23. Therefore, the data writing speed is the highest. On the other hand, the width of the semiconductor layer 23 of the memory cell transistor MT (NAND string SR3) located in the uppermost layer is the smallest. Therefore, the data writing speed is the lowest.

Therefore, when writing data in units of pages, the memory cell transistor in which writing is completed earliest (high writing speed) is located in the lowermost layer in the fin-type structure 24 and the memory cell transistor MT in which “A” level is written. It is. Such a memory cell transistor MT will be referred to as a first cell in the following description. On the other hand, the memory cell transistor in which writing ends most slowly (low writing speed) is the memory cell transistor MT in which the “C” level is written while being positioned in the uppermost layer in the fin-type structure 24. Such a memory cell transistor MT is referred to as a third cell. The other memory cell transistor MT is called a second cell.

Next, a data writing method will be described with reference to FIGS. FIG. 10 is a flowchart of the writing method, and FIG. 11 is a timing chart of voltages applied to the selected word line WL during writing.

First, in response to an instruction from the control unit 15, the row decoder 11 selects one of the word lines WL and applies a program voltage VPGM to the selected word line WL to program data. In the example of FIG. 9, the word line WL1 is selected, and data is programmed in the six memory cell transistors MT connected to the word line WL1 in the string groups GR1-1 and GR1-2 (step S10).

At this time, the row decoder 11 sequentially applies the program voltages VPGM1, VPGM2, and VPGM3 to the selected word line WL1 as shown in FIG. The voltages VPGM1 to VPGM3 are programming voltages for the first to third cells, respectively, and have a relationship of VPGM1 <VPGM2 <VPGM3. The row decoder 11 applies the voltage VPASS to the unselected word lines WL2 to WL4. The voltage VPASS is a voltage for turning on the memory cell transistor MT regardless of the retained data, and is a voltage lower than the program voltages VPGM1 to VPGM3. The row decoder 11 applies the voltage VSG to the select gate line GSL1, and applies 0 V, for example, to the select gate line GSL2. The voltage VSG is a voltage that turns on the selection transistor ST1 of the NAND string SR to be programmed and turns off the selection transistor ST1 of the NAND string SR that is not to be programmed. Note that the “low” level is given to the control signal lines SSL2 to SSL4, whereby the non-selected string groups GR2 to GR4 are electrically separated from the bit line BL.

While the row decoder 11 applies the voltage VPGM1 to the selected word line WL1, the sense amplifier module 12 applies 0 V to the bit line BL (BL1 in the example of FIG. 9) to which the first cell is connected. As a result, in the NAND string SR1 including the first cell, the selection transistor ST1 is turned on, and data is programmed in the first cell. The row decoder 11 applies a voltage V1 (> 0 V) to the bit line BL (BL2 to BL6 in the example of FIG. 9) to which the second cell and the third cell are connected. Thereby, in the NAND string SR including the second cell and the third cell, the selection transistor ST1 is cut off, and the programming to the second cell and the third cell is prohibited.

Next, while the row decoder 11 applies the voltage VPGM2 to the selected word line WL1, the sense amplifier module 12 applies 0V to the bit lines BL (BL2 to BL5 in the example of FIG. 9) to which the second cell is connected. Apply. As a result, in the NAND string SR including the second cell, the selection transistor ST1 is turned on, and data is programmed in the second cell. The row decoder 11 applies the voltage V1 to the bit line BL (BL1 and BL6 in the example of FIG. 9) to which the first cell and the third cell are connected. Thereby, the programming to the first cell and the third cell is prohibited.

Subsequently, while the row decoder 11 applies the voltage VPGM3 to the selected word line WL1, the sense amplifier module 12 applies 0 V to the bit line BL (BL6 in the example of FIG. 9) to which the third cell is connected. As a result, data is programmed in the third cell. The row decoder 11 applies the voltage V1 to the bit line BL (BL1 to BL5 in the example of FIG. 9) to which the first cell and the second cell are connected. Thereby, the programming to the first cell and the second cell is prohibited.

Through the above three steps, data is sequentially programmed in the first to third cells connected to the word line WL1. Whether the memory cell transistor MT corresponds to the first to third cells can be determined according to the address of the memory cell transistor MT. That is, the control unit 15 and the row decoder 11 determine which of the first to third program voltages is applied according to the address of the memory cell transistor MT to be written and the data to be written to the memory cell transistor MT. I can decide.

Next, the control unit 15 verifies the data programmed in the memory cell transistor MT as a result of the programming in step S10 (step S11).

At this time, the row decoder 11 sequentially applies the verify voltages Vfy_A, Vfy_B, and Vfy_C to the selected word line WL1 as shown in FIG. 11 in response to an instruction from the control unit 15. The row decoder 11 applies the voltage VREAD to the unselected word lines WL2 to WL4. The voltage VREAD is a voltage that turns on the memory cell transistor MT regardless of retained data. The row decoder 11 applies a high level to the select gate lines GSL1 and GSL2 to turn on the select transistors ST1 and ST2. Note that the “low” level is given to the control signal lines SSL2 to SSL4, whereby the non-selected string groups GR2 to GR4 are electrically separated from the bit line BL.

During the verify operation, the sense amplifier module 12 applies a precharge voltage to the bit lines BL1 to BL6 to sense and amplify the current flowing through the bit lines BL1 to BL6. Thereby, the data programmed in the memory cell transistor MT is determined.

When a verify voltage Vfy_A is applied, if a current flows through the bit line BL connected to the memory cell transistor MT to which the “A” level is to be written, the threshold value of the memory cell transistor MT rises to the “A” level. Therefore, it can be seen that the program to the memory cell transistor MT has not been completed (this is called a verify failure). On the other hand, if a current flows, the threshold value of the memory cell transistor MT has risen to the “A” level, so that it can be seen that the programming of the memory cell transistor MT has been completed (this is called a verify path). . The program for the “B” level and the “C” level is the same.

As a result of step S11, the program to the first cell is completed (step S12, YES), the program to the third cell is completed (step S13, YES), and the program to the second cell is completed (step S14). , YES), the control unit 15 determines that the program of desired data for the selected page has been normally completed, and ends the write operation.

As a result of step S11, the program to the first cell is completed (step S12, YES), and if the program to the third cell is not completed (step S13, NO), the control unit 15 applies the voltage VPGM1. The process of step S10 is repeated while omitting and stepping up the voltages VPGM2 and VPGM3 (step S15).

As a result of step S11, if the programming to the first cell has not been completed (step S12, NO), and the programming to the third cell has not been completed (step S16, NO), the control unit 15 causes the voltage VPGM1˜ While stepping up VPGM3 (step S17), the process of step S10 is repeated. If the programming to the third cell is completed (step S16, YES), the control unit 15 omits the application of the voltage VPGM3 and steps up the voltages VPGM1 and VPGM2 (step S18), and the process of step S10 repeat.

As a result of step S11, the program to the first and third cells is completed (step S12, YES, step S13, YES), and if the program to the second cell is not completed (step S14, NO), the control unit 15 omits application of the voltages VPGM1 and VPGM3 and steps up the voltage VPGM2 (step S19), and repeats the process of step S10.

In the example of FIG. 11, as a result of the second program, the first cell has passed verification (time t4). Therefore, the control unit 15 omits application of the voltage VPGM1 in the third program. As a result of the third program, the third cell passes verification (time t6). Therefore, the control unit 15 further omits application of the voltage VPGM3 in the fourth program.

1.3 Effects of this embodiment
With the configuration according to the present embodiment, the data writing speed can be improved. This effect will be described below.

FIG. 12 is a timing chart of the word line voltage in the normal writing method of the NAND flash memory. As shown in the figure, at the time of data programming, a program voltage VPGM is applied to the selected word line, and data is programmed to the memory cell transistors MT to be written with the “A” to “C” levels. The verify operation is executed. That is, one program loop is formed by one application of the program voltage VPGM and the verify operation, and this program loop is repeated while the program voltage is stepped up.

However, when such a writing method is applied to the flash memory described with reference to FIGS. 2 to 6, the time required for writing may be very long. As shown in FIGS. 2 to 6, when memory cell transistors MT connected in series in the NAND string SR are arranged in parallel to the semiconductor substrate surface, and the NAND string SR is stacked in a direction perpendicular to the semiconductor substrate surface, one page The memory cell transistors MT included in the memory cell transistors MT have different current path widths, resulting in variations in writing speed. That is, in the same page, a fast write memory cell transistor MT and a slow write memory cell transistor MT are mixed. This reason is due to the manufacturing process of the memory cell array 10. That is, in the memory cell array 10, after the insulating films 22-1 to 22-4 and the semiconductor layers 23-1 to 23-4 are stacked on the semiconductor substrate 20, these layers 22-1 to 22-4 and 23-1 are stacked. 23-4 are formed by patterning all at once. As a result, a taper angle is generated in the fin-type structure 24 as shown in FIG.

Therefore, when data is written, care must be taken not to overprogram the memory cell transistor MT having the highest data writing speed. That is, the voltage VPGM used in the first program loop of FIG. 12 is set to a sufficiently low value so that the memory cell transistor MT in which the “A” level is written is positioned in the lowermost layer and is not overprogrammed. Is set.

Then, as shown in FIG. 12, the first half program operation in the write operation contributes only to the memory cell transistor MT (ie, the first cell) having a substantially high write speed, and the program pulse in this period is the write pulse. It hardly affects the threshold voltage of the third cell having a low speed. Only after the program operation in the latter half of the write operation, the substantial program for the third cell is started.

That is, the data program is collectively executed in units of pages, but the first to third cells in the page are actually programmed in order. Therefore, the number of program loops becomes very large, and a long time is required for writing.

On the other hand, in the present embodiment, by preparing a plurality of types of program voltages in one program loop, it is possible to substantially program the third cell even in the first program loop, and to reduce the write time. Can be shortened.

That is, in the present embodiment, the program voltage VPGM is separated into the following three pulses.
(1) A pulse applied to the “A” level write cell (first cell) located in a fast write layer: VPGM1
(2) A pulse applied to the “C” level write cell (third cell) located in the slow write layer: VPGM3
(3) Pulse applied to cells (second cell) other than (1) and (2) above: VPGM2.

Then, the pulses (1) to (3) are sequentially applied in one program loop. The initial values of these pulses are optimum values according to the write speed and write data of the memory cell transistor MT programmed by these pulses. That is, the initial value of the voltage VPGM3 may be a value that overprograms the first cell and the second cell as long as the third cell is not overprogrammed. Of course, the initial value of the voltage VPGM1 is set to a value that does not overprogram the first cell in one program operation.

Thus, a substantial program can be executed for all of the first to third cells from the first program loop. In other words, the threshold voltage of the third cell can be effectively increased even in the first program loop. As a result, the number of program loops can be greatly reduced and the writing speed can be improved.

Although FIG. 11 shows an example in which VPGM1 is omitted first, and then VPGM3 is omitted, the reverse case may be possible, or VPGM1 and VPGM3 may be omitted at the same time.

As a result of employing the above write method, in any program loop, the row decoder 11 sequentially applies the program voltage to the selected word line WL M times (M is a natural number of 1 or more) (t5 in FIG. 11). T6, t7 to t8), and subsequently, the verify voltage Vfy is sequentially applied to the selected word line WL N times (N is greater than M and a natural number of 3 or more) (from t6 to t7, t7 in FIG. 11). In any program loop, the number of application times of the program voltage does not exceed the number of application times of the verify voltage, and is equal to or less than the number of application times of the verify voltage.

In other words, data is written into the memory cell by repeating a program loop including a program operation for applying a program voltage to the selected word line WL and a verify operation for applying a verify voltage to the selected word line a plurality of times. Is done. Among the program loops that are repeated a plurality of times, the row decoder 11 does not change the number of times of application of the verify voltage Vfy between two consecutive program loops (t3 to t5 and t5 to t6 in FIG. 11). The number of program voltage applications (3 times: VPGM1-VPGM3) in the program loop (t5 to t6 in Fig. 11) is reduced from the first program loop (t3 to t5 in Fig. 11) (2 times: VPGM2, VPGM3) ).

For example, the row decoder 11 sequentially applies a program voltage to the selected word line M times in a certain program loop. When any one of the M times of the program voltage (VPGM1 in FIGS. 11 and 16) is applied to the selected word line WL, the first memory cell located in the lowermost layer is set as a program target, and at least in the uppermost layer. The third memory cell located is not targeted for programming. In the next program loop, the row decoder 11 omits application of any one of the program voltages (VPGM1 in FIGS. 11 and 16) to the selected word line (t5-t6 in FIG. 11 and t5 in FIG. 16). Or later). In this example, the application of VPGM1 is stopped before VPGM3.

On the other hand, when another program voltage (VPGM3 in FIGS. 11 and 14) of M times is applied to the selected word line WL, the third memory cell located in the uppermost layer is set as a program target, and at least in the lowermost layer. The first memory cell located is not programmed. Then, in the next program loop, the row decoder 11 omits application of any of the program voltages (VPGM3 in FIGS. 11 and 14) (after t5 in FIG. 14). In this example, the application of VPGM3 is stopped before VPGM1.

Of course, in the next program loop, the application of a plurality of program voltages may be stopped simultaneously.

Also in the example of FIG. 12, the program voltage may be applied multiple times in one program loop. However, in the case of FIG. 12, the program voltage and the write level are associated with each other. Therefore, the reduction in the application of the program voltage completely coincides with the completion of writing to a certain level. In other words, when the application of a certain program voltage is stopped, the application of a certain verify voltage is also stopped at the same time.

On the other hand, according to the present embodiment, not only the write level but also the position of the memory cell is associated with the program voltage. Therefore, even if application of a certain program voltage is stopped, application of the verify voltage is not necessarily stopped.

2. Second embodiment
Next, a semiconductor memory device according to the second embodiment will be described. In this embodiment, the number of program pulses used in one program loop is reduced to two by including the program voltage VPGM1 in the VPGM2 in the data writing method described in the first embodiment. Below, only a different point from 1st Embodiment is demonstrated.

2.1 Data write operation
A data write operation according to the present embodiment will be described with reference to FIGS. FIG. 13 is a flowchart of the writing method, and FIG. 14 is a timing chart of voltages applied to the selected word line WL at the time of writing.

First, in response to a command from the control unit 15, the row decoder 11 selects any one of the word lines WL, applies a program voltage VPGM to the selected word line WL, and programs data (step S20).

At this time, the row decoder 11 sequentially applies the program voltages VPGM2a and VPGM3 to the selected word line WL. The voltage VPGM2a is a program voltage for the first and second cells, and has a relationship of VPGM2a <VPGM3. Further, for example, VPGM1 ≦ VPGM2a ≦ VPGM2, but VPGM2a is a value that does not cause an overprogram to the first cell in one program, for example.

While the row decoder 11 applies the voltage VPGM2a to the selected word line WL, the sense amplifier module 12 applies 0V to the bit lines BL (BL1 to BL5 in the example of FIG. 9) to which the first and second cells are connected. Is applied. As a result, in the NAND string SR including the first and second cells, the selection transistor ST1 is turned on, and data is programmed in the first and second cells. The row decoder 11 applies the voltage V1 to the bit line BL (BL6 in the example of FIG. 9) to which the third cell is connected. As a result, programming to the third cell is prohibited.

Through the above two steps, data is sequentially programmed in the first and second cells and the third cell connected to the selected word line WL.

Next, the control unit 15 verifies the data programmed in the memory cell transistor MT (step S21). Step S21 is the same as step S11 described in the first embodiment.

As a result of step S21, if the programming to the first and second cells is completed (step S22, YES), and the programming to the third cell is also completed (step S23, YES), the control unit 15 selects the desired page for the selected page. It is determined that the data program has been completed normally, and the write operation is terminated.

As a result of step S21, the program to the first and second cells is completed (step S22, YES), and if the program to the third cell is not completed (step S23, NO), the control unit 15 controls the voltage VPGM2a. Is omitted and the voltage VPGM3 is stepped up (step S24), and the process of step S20 is repeated.

As a result of step S21, programming to at least one of the first and second cells has not been completed (step S22, NO), and programming to the third cell has not been completed (step S25, NO). The controller 15 repeats the process of step S20 while stepping up the voltages VPGM2a and VPGM3 (step S26). If the programming to the third cell is completed (step S25, YES), the control unit 15 repeats the process of step S20 while omitting the application of the voltage VPGM3 and stepping up the voltage VPGM2a (step S27). .

2.2 Effects of this embodiment
According to the present embodiment, the first and second cells are simultaneously programmed using the program voltage VPGM2a. Therefore, as in the first embodiment, the number of program loops can be reduced, the types of program voltages can be reduced, and the circuit configuration can be simplified.

3. Third embodiment
Next, a semiconductor memory device according to a third embodiment will be described. In this embodiment, the number of program pulses used in one program loop is reduced to two by including the program voltage VPGM3 in the VPGM2 in the data writing method described in the first embodiment. Below, only a different point from 1st Embodiment is demonstrated.

3.1 Data write operation
A data write operation according to the present embodiment will be described with reference to FIGS. 15 and 16. FIG. 15 is a flowchart of the writing method, and FIG. 16 is a timing chart of voltages applied to the selected word line WL at the time of writing.

First, in response to an instruction from the control unit 15, the row decoder 11 selects any one of the word lines WL. Then, the row decoder 11 applies the program voltage VPGM to the selected word line WL to program data (step S30).

At this time, the row decoder 11 sequentially applies the program voltages VPGM1 and VPGM2b to the selected word line WL. The voltage VPGM2b is a program voltage for the second and third cells, and has a relationship of VPGM2b> VPGM1. Also, for example, VPGM2 ≦ VPGM2b ≦ VPGM3. For example, VPGM2b is a value that does not cause an overprogram to the second cell in one program. While the row decoder 11 applies the voltage VPGM2b to the selected word line WL, the sense amplifier module 12 applies 0V to the bit lines BL (BL2 to BL6 in the example of FIG. 9) to which the second and third cells are connected. Is applied. As a result, in the NAND string SR including the second and third cells, the selection transistor ST1 is turned on, and data is programmed in the second and third cells. The row decoder 11 applies the voltage V1 to the bit line BL (BL1 in the example of FIG. 9) to which the first cell is connected. As a result, programming to the first cell is prohibited.

Through the above two steps, data is sequentially programmed in the first cell connected to the selected word line WL, and the second and third cells.

Next, the control unit 15 verifies the data programmed in the memory cell transistor MT (step S31). Step S31 is the same as step S11 described in the first embodiment.

As a result of step S31, when the program to the first cell is completed (step S32, YES) and the program to the second and third cells is also completed (step S33, YES), the control unit 15 selects the desired page for the selected page. It is determined that the data program has been completed normally, and the write operation is terminated.

As a result of step S31, the program to the first cell is completed (step S32, YES), and if the program to at least one of the second and third cells is not completed (step S33, NO), the control unit 15 Omits the application of the voltage VPGM1, and repeats the process of step S30 while stepping up the voltage VPGM2b (step S34).

As a result of step S31, the program to the first cell is not completed (step S32, NO), and the program to at least one of the second and third cells is not completed (step S35, NO). The controller 15 repeats the process of step S30 while stepping up the voltages VPGM1 and VPGM2b (step S36). If the programming to the second and third cells is completed (step S35, YES), the control unit 15 omits the application of the voltage VPGM2b and steps up the voltage VPGM1 (step S37). Repeat the process.

3.2 Effects of this embodiment
According to this embodiment, the program for the second and third cells is simultaneously performed using the program voltage VPGM2b. Therefore, the same effect as the second embodiment can be obtained.

4). Fourth embodiment
Next, a semiconductor memory device according to the fourth embodiment will be described. In the data write method described in the first embodiment, this embodiment increases the channel potential of the first cell when the program voltage VPGM2 is applied, thereby omitting the application of VPGM1 and using it in one program loop. The number of program pulses to be reduced is two. Below, only a different point from 1st Embodiment is demonstrated.

4.1 Data write operation
A data write operation according to the present embodiment will be described with reference to FIGS. FIG. 17 is a flowchart of the writing method, and FIG. 18 is a timing chart of voltages applied to the selected word line WL and the bit line BL during programming.

First, in response to an instruction from the control unit 15, the row decoder 11 selects one of the word lines WL, applies a program voltage VPGM to the selected word line WL, and programs data (step S40).

At this time, the row decoder 11 sequentially applies the program voltages VPGM2 and VPGM3 to the selected word line WL. As described in the first embodiment, the voltage VPGM2 is a voltage optimized for programming the second cell. The voltage VPGM1 is not applied.

FIG. 19 is a circuit diagram of the memory cell array 10 when the voltage VPGM2 is applied. In the present embodiment, when the voltage VPGM2 is applied, not only the second cell but also the program to the first cell is executed. At that time, the sense amplifier module 12 applies the voltage V _QPW to the bit line BL (BL1 in the example of FIG. 19) to which the first cell is connected. The voltage V _QPW is higher than the voltage applied to the bit line BL (BL2 to BL5 in the example of FIG. 19) to which the second cell is connected, and for example, V _QPW > 0V. V _QPW is also a voltage that can be transferred by the select transistor ST1 having the gate applied with the voltage VSG.

Accordingly, during the period when the voltage VPGM2 is applied, the first and second cells are programmed with V _QPW and 0 V applied to each channel, respectively.

The subsequent processing is the same as that obtained by replacing VPGM2a with VPGM2 in the description made with reference to FIG. 13 of the second embodiment. Steps S41 to S47 in FIG. 17 correspond to steps S21 to S27 in FIG.

4.2 Effects of this embodiment
According to the present embodiment, the number of program loops can be reduced while the number of program voltages can be reduced and the circuit configuration can be simplified as in the second embodiment. In addition, since the initial value of the program voltage VPGM2 can be optimized for the second cell, writing can be performed faster than in the second embodiment. This effect will be described with reference to FIG. FIG. 20 is a graph showing changes in threshold voltages of the first cell and the second cell during programming.

As shown in the figure, since the program voltage VPGM2 is optimized for the programming of the second cell, the threshold value of the second cell increases in a desired step (ΔVth1). However, VPGM2 is a voltage that is too large for the first cell. Therefore, when VPGM2 is applied to the first cell as it is, the threshold value increases in a step (ΔVth2) larger than the desired step. Depending on the case, there is a possibility that the threshold value increases too much in one program.

Therefore, in this embodiment, the voltage V _QPW is applied to the bit line BL to which the first cell is connected. That is, the potential difference between the control gate and the channel is reduced by applying the voltage V _QPW . As a result, the threshold fluctuation width of the first cell is controlled (the fluctuation width is reduced), and is raised by an optimum step (ΔVth3).

That is, while omitting the application of VPGM1, an optimal program can be executed not only for the second cell but also for the first cell, and high-speed writing to these cells is possible.

5. Fifth embodiment
Next, a semiconductor memory device according to a fifth embodiment will be described. The present embodiment relates to the configuration and operation of the column peripheral circuit in the first embodiment.

5.1 Configuration of column peripheral circuit
FIG. 21 is a block diagram of the sense amplifier module 12, the arithmetic module 13, and the data latch module 14 according to the present embodiment.

As shown in the figure, the sense amplifier module 12 includes a latch circuit SDL associated with each bit line BL. In the drawing, “_B”, “_M”, and “_T” added after “SDL” indicate that the latch circuit SDL has the bottom layer cell, the middle layer cell, and the bottom layer cell of the fin-type structure 24, respectively. It corresponds to the upper cell. Signals SEL_BOT, SEL_MID, and SEL_TOP indicating which cell corresponds to each latch circuit SDL are given by, for example, the control unit 15. That is, SEL_BOT = “H” is given to the latch circuit SDL_B, SEL_MID = “H” is given to the latch circuit SDL_M, and SEL_TOP = “H” is given to the latch circuit SDL_T. Similarly, signals CLAMP_BOT, CLAMP_MID, and CLAMP_TOP for controlling the bit line precharge voltage for each layer at the time of reading are supplied to each latch circuit SDL. That is, CLAMP_BOT = “H” is given to the latch circuit SDL_B, CLAMP_MID = “H” is given to the latch circuit SDL_M, and CLAMP_TOP = “H” is given to the latch circuit SDL_T.

The latch circuit SDL holds the write data transferred from the arithmetic module 13 when writing data. The latch circuit SDL applies a predetermined voltage to the corresponding bit line BL according to the write data. The latch circuit SDL precharges the bit line BL to a voltage corresponding to the signals CLAMP_BOT, CLAMP_MID, and CLAMP_TOP when reading data. That is, when reading data, the latch circuit SDL controls the precharge potential applied to the bit line BL according to which layer the read target cell is located.

The arithmetic module 13 includes an arithmetic circuit 40 associated with each bit line BL. The arithmetic circuit 40 also receives any of the corresponding signals SEL (SEL_TOP, SEL_MID, and SEL_BOT). Each of the arithmetic circuits 40 generates write data by an operation using the data supplied from the data latch module 14 and the corresponding signal SEL when writing data. Then, the generated write data is transferred to the corresponding latch circuit SDL.

The data latch module 14 includes a set of latch circuits DL0 and DL1, and this set is associated with each bit line BL. When writing data, each bit of 2-bit data given from an external device such as a host device via the data line DAT is held in the latch circuits DL0 and DL1. These data are transferred to the arithmetic circuit 13. At the time of reading, each bit of the 2-bit data read from the memory cell transistor MT is held in the latch circuits DL0 and DL1. The latch circuits DL0 and DL1 output each bit of 2-bit data to the external device via the data line DAT.

5.2 Operation during writing
Next, the operation of the column peripheral circuit at the time of data writing will be described with reference to FIGS. FIG. 22 is a timing chart showing changes in the word line voltage during writing, and FIG. 23 is a timing chart showing changes in the word line and bit line voltages during programming.

In writing, first, write data is transferred to the latch circuits DL0 and DL1. The relationship between the write data and the data in the latch circuits DL0 and DL1 is as follows.
Data: (DL0, DL1)
“Ep” level (non-write): (1, 1)
“A” level: (1, 0)
“B” level: (0, 0)
“C” level: (0, 1)
The data in the latch circuit SDL has the following relationship.
SDL = 1: Non-write cell (BL = V1)
SDL = 0: Write cell (BL = 0V)
Hereinafter, the processing steps at the time of writing will be described in order.

(1) Step 1
When data is transferred to the latch circuits DL0 and DL1, each of the arithmetic circuits 40 executes a data set for the first program. The first program is a program performed only on the first cell. In the data set, the arithmetic circuit 40 executes the following logical operation. That is,
/ (DL0 & / DL1 & SEL_BOT) → SDL
In the arithmetic expression, “/” indicates inversion and “&” indicates logical product. By this calculation, DL0 = 1 and DL = 0, and “0” is set only to the latch circuit SDL corresponding to the lowermost memory cell. “1” is set in the other latch circuits SDL. As a result, 0 V is applied only to the bit line BL to which the first cell that has not passed verification is connected, and the other second and third cells, and the bit to which the non-write target cell and the write completion cell are connected. A voltage V1 is applied to the line BL. Then, the voltage VPGM1 is applied to the selected word line WL, and the “A” level data is programmed only in the first cell.

(2) Step 2
Next, each of the arithmetic circuits 40 executes a data set for the second program. The second program is a program performed only on the second cell. In the data set, the arithmetic circuit 40 executes the following logical operation. That is,
(DL0 & DL1) | (DL0 & / DL1 & SEL_BOT) | (/ DL0 & DL1 & SEL_TOP) → SDL
In the arithmetic expression, “|” represents a logical sum. By this calculation, “1” is set in the latch circuit SDL corresponding to the first cell, the third cell, and the non-write target cell. In other words, “0” is set only in the latch circuit SDL corresponding to the second cell. As a result, 0 V is applied only to the bit line BL to which the second cell that has not passed verification is connected, and the voltage V1 is applied to the other bit lines BL. Then, the voltage VPGM2 is applied to the selected word line WL, and data is programmed only in the second cell.

(3) Step 3
Next, each of the arithmetic circuits 40 executes a data set for the third program. The third program is a program performed only for the third cell. In the data set, the arithmetic circuit 40 executes the following logical operation. That is,
/ (/ DL0 & DL1 & SEL_TOP) → SDL
As a result of this calculation, “0” is set only in the latch circuit SDL corresponding to the memory cell in the uppermost layer with DL0 = 0 and DL = 1. “1” is set in the other latch circuits SDL. As a result, 0 V is applied only to the bit line BL to which the third cell that has not passed verification is connected, and the other first cell and second cell, and the bit to which the non-write target cell and the write completion cell are connected. A voltage V1 is applied to the line BL. Then, the voltage VPGM3 is applied to the selected word line WL, and the “C” level data is programmed only in the third cell.

(4) Step 4
Next, a verify operation for the “A” level is executed. That is, data is read from the memory cell transistor MT with the verify level Vfy_A applied to the selected word line WL. If the memory cell transistor MT is turned off, that is, if the threshold value has reached the “A” level, “1” is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, if the threshold value has not reached the “A” level, “0” is stored in the latch circuit SDL.

The arithmetic circuit 40 performs the following logical operation. That is,
(SDL & DL0 & / DL1) | DL1 → DL1
In the above equation, (DL0 & / DL1) is “1” only in the bit line BL to which the “A” level is written. Therefore, (SDL & DL0 & / DL1) becomes "1" only for the bit line BL whose write data is at the "A" level and has passed verification. Thereafter, a logical sum operation is performed on the calculation result and the original DL1, and the result is set again in DL1. As a result, the data in the latch circuits DL0 and DL1 are as follows.
“Ep” level (non-write): (1, 1)
“A” level: (1, 0/1)
“B” level: (0, 0)
“C” level: (0, 1)
That is, the data of the latch circuits DL0 and DL1 that do not correspond to the “A” level is set to the original value by the final OR operation.

Next, the arithmetic circuit 40 executes the logical operation of the following equation (1). That is,
(DL0 & / DL1 & SEL_BOT) (1)
As a result, a verify result of the memory cell transistor MT corresponding to the “A” level and located in the lowermost layer is obtained. That is, if the calculation result is “0”, it can be seen that the first cell corresponding to the column has passed verification. On the other hand, only the operation result corresponding to the column corresponding to the first cell and failing to verify becomes “1”.

Therefore, for example, the control unit 15 counts the number of bits for which the operation result is “1”, and if the number is equal to or less than a certain reference value (for example, determined by the number of error correctable bits in the ECC circuit), the first cell is Judge that the verification pass. In this case, the control unit 15 issues the signal COMP_A_BOT (COMP_A_BOT = “H”) and does not apply the voltage VPGM1 from the next program loop.

Subsequently, the arithmetic circuit 40 executes the logical operation of the following equation (2). That is,
(DL0 & / DL1 & (SEL_MID | SEL_TOP)) (2)
As a result, a verify result of the memory cell transistor MT corresponding to the “A” level and located in a layer other than the lowest layer is obtained. That is, when the calculation result is “0”, it is understood that the memory cell transistor corresponding to the column has passed verification. On the other hand, only the operation result corresponding to the verify failure among the memory cell transistors MT corresponding to the “A” level and located in a layer other than the lowest layer is “1”.

Thus, for example, the control unit 15 counts the number of bits for which the calculation result is “1”, and if the number is equal to or less than a certain reference value, the control unit 15 should be located in a layer other than the lowest layer and write the “A” level. It is determined that the memory cell transistor MT has passed verification.

If the verify results based on the above formulas (1) and (2) both pass, programming to all the memory cell transistors MT to which the “A” level is to be written is completed. Therefore, the control unit 15 issues the signal COMP_A_MIDTOP (COMP_A_MIDTOP = “H”). Then, when both the signals COMP_A_BOT and COMP_A_MIDTOP are issued, the control unit 15 does not perform the “A” level verify operation from the next program loop.

(5) Step 5
Next, a verify operation for the “B” level is executed. That is, data is read from the memory cell transistor MT in a state where the verify level Vfy_B is applied to the selected word line WL. If the memory cell transistor MT is turned off, that is, if the threshold value has reached the “B” level, “1” is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, if the threshold value has not reached the “B” level, “0” is stored in the latch circuit SDL.

The arithmetic circuit 40 executes the following logical operations simultaneously. That is,
(SDL & / DL0 & / DL1) | DL0 → DL0
(SDL & / DL0 & / DL1) | DL1 → DL1
In the above equation, (/ DL0 & / DL1) is “1” only in the bit line BL to which the “B” level is written. Therefore, (SDL & / DL0 & / DL1) becomes "1" only for the bit line BL whose write data is at the "B" level and has passed verification. Thereafter, a logical sum operation between these calculation results and the original DL0 and DL1 is performed, and these are set in DL0 and DL1 again. As a result, the data in the latch circuits DL0 and DL1 are as follows.
“Ep” level (non-write): (1, 1)
“A” level: (1, 0/1)
“B” level: (0, 0/1)
“C” level: (0, 1)
Note that the value of the latch circuit DL0 corresponding to the “A” level is reset to “0” or “1” in step (4).

Next, the arithmetic circuit 40 executes the logical operation of the following equation (3). That is,
(/ DL0 & / DL1) (3)
It can be seen that if the calculation result is “0”, the memory cell transistor MT to which the “B” level is to be written passes verification, and if it is “1”, the verification fails.

Therefore, for example, the control unit 15 counts the number of bits for which the calculation result is “1”, and determines that the “B” level program has passed the verify if the number is equal to or less than a certain reference value. In this case, the control circuit issues a signal COMP_B (COMP_B = “H”) and does not perform the “B” level verify operation from the next program loop.

(6) Step 6
Next, a verify operation for the “C” level is executed. That is, data is read from the memory cell transistor MT in a state where the verify level Vfy_C is applied to the selected word line WL. If the memory cell transistor MT is turned off, that is, if the threshold value has reached the “C” level, “1” is stored in the latch circuit SDL. On the other hand, if the memory cell transistor MT is turned on, that is, if the threshold value has not reached the “C” level, “0” is stored in the latch circuit SDL. The operation of step 6 is basically the same as that of step 4 except that the data to be read is different.

First, the arithmetic circuit 40 executes the following logical operation. That is,
(SDL & / DL0 & DL1) | DL0 → DL0
In the above equation, (/ DL0 & DL1) becomes “1” only in the bit line BL to which the “C” level is written. Therefore, (SDL & / DL0 & DL1) becomes "1" only for the bit line BL whose write data is at the "C" level and has passed verification. Thereafter, a logical sum operation is performed between the operation result and the original DL0, and the result is reset to DL0. As a result, the data in the latch circuits DL0 and DL1 are as follows.
“Ep” level (non-write): (1, 1)
“A” level: (1, 0/1)
“B” level: (0/1, 0/1)
“C” level: (0/1, 1).

Next, the arithmetic circuit 40 performs a logical operation of the following equation (4). That is,
(/ DL0 & DL1 & SEL_TOP) (4)
As a result, a verify result of the memory cell transistor MT (third cell) corresponding to the “C” level and located in the uppermost layer is obtained. That is, if the calculation result is “0”, it can be seen that the third cell corresponding to the column has passed verification. On the other hand, only the operation result corresponding to the third cell and corresponding to the column failed in the verification is “1”.

Thus, for example, the control unit 15 counts the number of bits for which the calculation result is “1”, and determines that the third cell has passed the verification if the number is equal to or less than a certain reference value. In this case, the control circuit issues a signal COMP_C_TOP (COMP_C_TOP = “H”) and does not apply the voltage VPGM3 from the next program loop.

Subsequently, the arithmetic circuit 40 executes the logical operation of the following equation (5). That is,
(/ DL0 & DL1 & (SEL_MID | SEL_BOT)) (5)
As a result, a verify result of the memory cell transistor MT corresponding to the “C” level and located in a layer other than the uppermost layer is obtained. That is, when the calculation result is “0”, it is understood that the memory cell transistor corresponding to the column has passed verification. On the other hand, only the operation result corresponding to the verify failure among the memory cell transistors MT corresponding to the “C” level and located in a layer other than the uppermost layer is “1”.

Therefore, for example, the control unit 15 counts the number of bits whose operation result is “1”, and if the number is equal to or less than a certain reference value, the memory cell transistor MT located in a layer other than the uppermost layer has passed verification. Judge.

If the verify result based on the above formulas (4) and (5) is a pass, programming to all the memory cell transistors MT to which the “C” level is to be written is completed. Therefore, the control unit 15 issues the signal COMP_C_MIDBOT (COMP_C_MIDBOT = “H”). When both signals COMP_C_TOP and COMP_C_MIDBOT are issued, the control unit 15 does not perform the “C” level verify operation from the next program loop.

(7) Step 7
The control unit 15 repeats the above operation, and when all of the five control signals COMP_A_BOT, COMP_A_MIDTOP, COMP_B, COMP_C_TOP, and COMP_C_MIDTOP become “H” level, it is assumed that the program is normally completed (program pass), and the write operation is performed. To complete. If the number of program loops reaches the maximum value while any of the control signals remains at “L” level, the control unit 15 assumes that the program has not been completed normally (program fail) and completes the write operation.

5.3 Effects of the present embodiment
The writing method described in the first embodiment can be realized by the configuration according to the present embodiment, for example. The same applies to the second to fourth embodiments, and the potential of the bit line BL can be appropriately controlled by calculation using the control signals SEL_BOT, SEL_MID, SEL_TOP, DL0, and DL1.

6). Sixth embodiment
Next, a semiconductor memory device according to a sixth embodiment will be described. The present embodiment relates to a memory system including the semiconductor memory device 1 according to any one of the first to fifth embodiments.

6.1 Memory system configuration
FIG. 24 is a block diagram of the memory system according to the present embodiment. As illustrated, the memory system includes the semiconductor memory device 1 described in the first to fifth embodiments, and a controller 2 that controls the semiconductor memory device 1.

In response to a command from a host device (not shown), the controller 2 commands the NAND flash memory 1 to read, write, erase, and the like. The memory space of the NAND flash memory 1 is managed. For example, the controller 2 and the NAND flash memory 1 may constitute the same semiconductor device. The memory system 1 may be a single device, and examples thereof include a memory card such as an SD ^TM card, an SSD (solid state drive), and the like. The memory system 1 may have a configuration in which the NAND flash memory 1 and the controller 2 are built in a personal computer, and is not limited as long as it is an application in which the NAND flash memory 1 is mounted.

The controller 2 includes a host interface circuit 210, a built-in memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, a NAND interface circuit 250, and an ECC circuit 260.

The host interface circuit 210 is connected to the host device via the controller bus and manages communication with the host device. Then, the command and data received from the host device are transferred to the CPU 230 and the buffer memory 240, respectively. In response to a command from the CPU 230, the data in the buffer memory 240 is transferred to the host device.

The NAND interface circuit 250 is connected to the NAND flash memory 1 via the NAND bus and manages communication with the NAND flash memory 1. Then, the command received from the CPU 230 is transferred to the NAND flash memory 1, and the write data in the buffer memory 240 is transferred to the NAND flash memory 1 at the time of writing. Further, at the time of reading, the data read from the NAND flash memory 1 is transferred to the buffer memory 240.

CPU 230 controls the entire operation of the controller 2. For example, when a write / read command is received from the host device, a write command based on the NAND interface is issued in response thereto. The same applies to reading and erasing. The CPU 230 executes various processes for managing the NAND flash memory 1 such as wear leveling. Further, the CPU 230 executes various calculations. For example, data encryption processing, randomization processing, and the like are executed. The ECC circuit 260 executes a data error correction (ECC: Error Checking andrectCorrecting) process. That is, the ECC circuit 260 generates a parity based on the write data at the time of data writing, generates a syndrome from the parity at the time of reading, detects an error, and corrects this error. Note that the CPU 230 may have the function of the ECC circuit 260.

The built-in memory 220 is a semiconductor memory such as a DRAM, and is used as a work area for the CPU 230. The built-in memory 220 holds firmware for managing the NAND flash memory 1 and various management tables.

6.2 Controller operation
Next, the operation of the controller 2 according to the present embodiment, particularly the write operation will be described. The controller 2 can write data into the NAND flash memory 1 in two write modes, ie, the first mode and the second mode.

FIG. 25 is a timing chart of signals transmitted and received between the NAND flash memory 1 and the controller 2 when writing data in the first mode. The controller 2 transmits a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE to the NAND flash memory 1. The NAND flash memory 1 transmits a ready / busy signal / R / B to the controller 2. The input / output signals I / O1 to I / O8 are, for example, 8-bit data transmitted / received between the controller 1 and the NAND flash memory.

The chip enable signal / CE is a signal for enabling the NAND flash memory 1 and is asserted at a low level. The address latch enable signal ALE is a signal indicating that the input / output signals I / O1 to I / O8 are addresses, and is asserted at a high level. The command latch enable signal CLE is a signal indicating that the input / output signals I / O1 to I / O8 are commands, and is asserted at a high level. The write enable signal / WE is a signal for writing each data in the NAND flash memory 1, and is asserted at a low level. The read enable signal / RE is a signal for reading each data from the NAND flash memory 1 and is asserted at a low level. The ready / busy signal / R / B is a signal indicating whether or not the NAND flash memory 1 is in a busy state (whether or not a signal can be received), and becomes a low level in the busy state.

As shown in the figure, when writing data in the first mode, the controller 1 issues a first write command 80H and writes it in a command register (not shown) of the NAND flash memory 1. The command 80H is a command for notifying that a writing operation will be executed from now on. After that, the column address (address specifying the bit line) and the row address (address specifying the word line (page)) are written in the address register. Thereafter, data D0 to D527 to be programmed are transferred. Finally, the controller 2 writes the command 10H into the command register. In response to this command, the control unit 15 of the NAND flash memory 1 writes data by the method described in the first to fifth embodiments.

FIG. 26 is a timing chart of signals transmitted and received between the NAND flash memory 1 and the controller 2 when writing data in the second mode. The difference from the first mode is that the controller 2 issues a prefix command and writes it to the command register before the first write command 80H. By receiving the prefix command, the NAND flash memory writes data in the second mode. Data writing in the second mode is executed by the method of FIG. 12 described in the first embodiment.

In the second mode, the program voltage VPGM is not classified according to the first to third cells, and the program is executed for all the memory cells to be written at the “A” to “C” level in the page. . That is, the VPGM is simply stepped up as shown in FIG. In the case of FIG. 12, a case where VPGM is applied only once in one program loop is shown as an example, but it may be applied continuously twice or more. However, the VPGM applied twice or more does not correspond to the position (address) of the memory cell or the write data, and is used for programming data in all the write target cells. That is, in the second mode, the number of VPGM applications in one program loop is the same as or less than the number of verify voltage applications.

That is, as described in the first embodiment, when the application of a certain program voltage is stopped, the application of the verify voltage corresponding to it is also stopped.

6.3 Effects of this embodiment
With the configuration according to the present embodiment, the writing speed and power consumption can be changed according to the user's needs.

That is, in the first mode, the booster circuit in the NAND flash memory 1 generates the low voltage VPGM1 after generating the high voltage VPGM3. Accordingly, the booster circuit needs to be discharged during the verify operation, and after the discharge, the boost operation from the low voltage VPGM1 is required again. That is, current consumption increases because charging and discharging are repeated in the booster circuit. Instead, a high-speed write operation is possible as described in the first to fifth embodiments.

On the other hand, in the second mode, the boosted voltage simply needs to step up VPGM, discharge at the boosted voltage is unnecessary, and the voltage wiring may be left floating during the verify operation. Therefore, although the writing speed is inferior to that in the first mode, the current consumption can be reduced.

In the present embodiment, the first mode and the second mode can be switched by a command from the controller 2. For example, in contrast to the NAND flash memory 1 that is shipped as a product (MLC: multi-level cell) in which the memory cell holds data of 2 bits or more, SLC (single-level cell: 1 memory cell is 1 The second mode is preferably employed when it is desired to operate (holding bit data) or when it is desired to perform SLC operation for writing important data with high reliability.

As described above, according to the present embodiment, the NAND flash memory 1 can be used by switching between a mode in which high-speed operation is possible but relatively high power consumption and a mode in which low-speed operation is low but low power consumption. .

7). Modifications etc.
As described above, the semiconductor memory device 1 according to the embodiment includes the plurality of memory cells MT, the word lines WL, the bit lines BL, and the row decoder 11. Memory cells are stacked on a semiconductor substrate. The word line WL is connected to the gate of the memory cell. The bit line BL is electrically connected to the current path of the memory cell and can transfer data. The row decoder 11 applies a voltage to the word line. Data writing to the memory cell MT is executed by repeating a program loop including a program operation and a verify operation a plurality of times (FIG. 11). In one program loop, the row decoder applies the program voltage M times (M is a natural number of 1 or more), sequentially applies the selected word line (t5 to t6, t7 to t8 in FIG. 11), and then continues the verify voltage. Are applied sequentially to the selected word line N times (N is larger than M and is a natural number of 2 or more) (t6 to t7, t7 and after in FIG. 11).

In other words, data writing to the memory cell is executed by repeating a program loop including a program operation for applying a program voltage to a selected word line and a verify operation for applying a verify voltage a plurality of times. The row decoder 11 performs the second program loop (t5 to t6 in FIG. 11) while keeping the number of application of the verify voltage unchanged between two consecutive program loops (t3 to t5 and t5 to t6 in FIG. 11). The number of application of the program voltage at (3 times: VPGM1-VPGM3) is decreased from the first program loop (t3 to t5 in FIG. 11) (2 times: VPGM2, VPGM3).

This configuration can reduce the number of program loops and improve the data writing speed. However, the embodiment is not limited to the embodiment described above, and various modifications are possible. For example, in the above-described embodiment, the case where the application of VPGM1 and VPGM3 ends before the application of VPGM2 has been described as an example, but the application of VPGM2 may end before the application of VPGM1 and / or VPGM3. May be.

In the above embodiment, the first cell is defined as a cell that is located in the lowest layer and is programmed to the “A” level. However, the first cell may be a cell located from the first layer to the Nth layer (N is a natural number of 2 or more). If the memory cell can hold data of 4 bits or more (“Ep”, “A”, “B”, “C”, “D”,..., “16” levels), the first cell is , A cell programmed in a range from “A” level to “C” level, for example. The same applies to the third cell. That is, the third cell may be a cell located from the (N + M) th layer (M is a natural number of 4 or more) to the Lth layer (L is a natural number of 6 or more). It may be a cell programmed in the range of “O” level.

Furthermore, in the first embodiment, the case where the program pulses are classified into three types has been described as an example (VPGM1 to VPGM3). However, it may be classified into four or more types, and these four or more types of pulses may be sequentially applied in one program loop.

Furthermore, the concept of the fourth embodiment can be applied to the third embodiment. That is, in FIG. 16 described in the third embodiment, V _QPW may be applied to the bit line connected to the second cell while applying VPGM3 instead of the voltage VPGM2b.

Furthermore, the structure of the memory cell array 10 is not limited to the configuration described with reference to FIGS. In the above embodiment, as shown in FIG. 4, the bit line contacts BC of the odd-numbered string groups GR1 are collected on the left side of the memory cell array 10, and the bit line contacts BC of the even-numbered string groups GR2 are on the right side of the memory cell array 10. The case where they are collected and arranged is described as an example. However, these bit line contacts BC may be arranged together on the right side or the left side.

Furthermore, the above-described embodiment can be applied to a configuration in which data writing speed varies within a page, which is a set of memory cells that are simultaneously selected at the time of data writing, and is applicable not only to NAND flash memories but also to storage devices in general. I can do it.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10 ... Memory cell array, 11 ... Row decoder, 12 ... Sense amplifier module, 13 ... Arithmetic module, 14 ... Data latch module, 15 ... Control part, 20 ... Semiconductor substrate, 21, 22-1 to 22-4, 25-27 ... Insulating film, 23-1 to 23-3, 28 ... Semiconductor layer, 24 ... Fin type laminated structure

Claims

A plurality of memory cells stacked on a semiconductor substrate;
A word line connected to the gate of the memory cell;
A bit line electrically connected to the current path of the memory cell and capable of transferring data;
A row decoder for applying a voltage to the word line, and data writing to the memory cell is executed by repeating a program loop including a program operation and a verify operation a plurality of times,
In one program loop, the row decoder sequentially applies a program voltage to the selected word line M times (M is a natural number of 1 or more), and subsequently applies a verify voltage N times (N is greater than M and 2 or more). The natural number) is sequentially applied to the selected word line.
The semiconductor memory device according to claim 1, wherein the data is programmed to a plurality of memory cells stacked on a semiconductor substrate in one program loop.
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the lowest layer among the plurality of stacked memory cells is set as a program target, and at least in the uppermost layer. The semiconductor memory device according to claim 2, wherein the memory cell located is not programmed.
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the uppermost layer among the plurality of stacked memory cells is set as a program target, and at least in the lowermost layer. The semiconductor memory device according to claim 2, wherein the memory cell located is not programmed.
When one of the M program voltages is applied to the selected word line, both the first memory cell and the second memory cell are targeted for programming,
The semiconductor memory device according to claim 2, wherein first and second voltages different from each other are respectively applied to channels of the first and second memory cells.
A semiconductor memory device according to claim 1;
A controller for controlling the semiconductor memory device, the semiconductor memory device comprising a first write mode and a second write mode,
In the first write mode, in any program loop, the row decoder sequentially applies a program voltage to the selected word line M times, and then sequentially applies a verify voltage to the selected word line N times. And
In the second write mode, the number of times that the verify voltage is applied is equal to or less than the number of times that the program voltage is applied in any program loop.
A method of writing data in a semiconductor memory device in which a plurality of memory cells are stacked on a semiconductor substrate,
Sequentially applying a program voltage to the selected word line M times (M is a natural number of 1 or more);
Subsequent to applying the program voltage, sequentially applying a verify voltage to the selected word line N times (N is greater than M and a natural number of 2 or more),
A data writing method comprising:
The data is collectively written in a plurality of memory cells stacked on a semiconductor substrate by applying the program voltage M times and applying the verify voltage N times. The data writing method described.
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the lowest layer among the plurality of stacked memory cells is set as a program target, and at least in the uppermost layer. 9. The data writing method according to claim 8, wherein the memory cell located is not targeted for programming.
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the uppermost layer among the plurality of stacked memory cells is set as a program target, and at least in the lowermost layer. 9. The data writing method according to claim 8, wherein the memory cell located is not targeted for programming.
A plurality of memory cells stacked on a semiconductor substrate;
A word line connected to the gate of the memory cell;
A bit line electrically connected to the current path of the memory cell and capable of transferring data;
A row decoder for applying a voltage to the word line, and for writing data to the memory cell, a program operation for applying a program voltage to the selected word line and a verify operation for applying a verify voltage to the selected word line Is executed by repeating a program loop including
The row decoder reduces the number of application times of the program voltage in the second program loop from that of the first program loop while keeping the number of application of the verify voltage unchanged between two consecutive program loops. A semiconductor memory device.
The semiconductor memory device according to claim 11, wherein the data is programmed to a plurality of memory cells stacked on the semiconductor substrate in one program loop.
The row decoder sequentially applies the program voltage to the selected word line M times in the first program loop,
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the lowest layer among the plurality of stacked memory cells is set as a program target, and at least in the uppermost layer. The memory cell located is not subject to programming,
The semiconductor memory device according to claim 12, wherein the application of any one of the program voltages to the selected word line is omitted in the second program loop.
The row decoder sequentially applies the program voltage to the selected word line M times in the first program loop,
When any one of the M times of the program voltage is applied to the selected word line, a memory cell located in the uppermost layer among the plurality of stacked memory cells is set as a program target, and at least in the lowermost layer. The memory cell located is not subject to programming,
The semiconductor memory device according to claim 12, wherein the application of any one of the program voltages to the selected word line is omitted in the second program loop.
The row decoder sequentially applies the program voltage to the selected word line M times in the first program loop,
When one of the M program voltages is applied to the selected word line, both the first memory cell and the second memory cell are targeted for programming,
The semiconductor memory device according to claim 12, wherein different first and second voltages are respectively applied to the channels of the first and second memory cells.
The first memory cell is a memory cell located in a lowermost layer,
The semiconductor memory device according to claim 5, wherein the first voltage is higher than the second voltage.
A semiconductor memory device according to claim 11;
A controller for controlling the semiconductor memory device, the semiconductor memory device comprising a first write mode and a second write mode,
In the first write mode, the row decoder sets the number of times of application of the program voltage in the second program loop while the number of times of application of the verify voltage remains unchanged between two successive program loops. Less than the program loop,
In the second write mode, the row decoder decreases the number of times of application of the verify voltage when the number of times of application of the program voltage is decreased in two consecutive program loops. system.
18. The memory system according to claim 6, wherein the semiconductor memory device operates in one of the first and second write modes according to a command given from the controller.
A method of writing data in a semiconductor memory device in which a plurality of memory cells are stacked on a semiconductor substrate,
By sequentially applying the program voltage to the selected word line M times (M is a natural number of 2 or more) and then sequentially applying the verify voltage to the selected word line N times (N is a natural number of 2 or more), Executing one program loop;
A program voltage is sequentially applied to the selected word line L times (L is a natural number of 1 or more, L <M), and then a verify voltage is sequentially applied to the selected word line N times. A data writing method comprising: executing a program loop.
The data writing method according to claim 19, wherein data is collectively written into a plurality of memory cells stacked on the semiconductor substrate by the first program loop and the second program loop.
When any one of the M program voltages in the first program loop is applied to the selected word line, a memory cell located in the lowest layer among the plurality of stacked memory cells is set as a program target. And at least the memory cells located in the uppermost layer are not programmed.
The data write method according to claim 20, wherein the application of any one of the program voltages to the selected word line is omitted in the second program loop.
When any one of the M times of the program voltage in the first program loop is applied to the selected word line, a memory cell located in the uppermost layer among the plurality of stacked memory cells is set as a program target. And at least memory cells located in the lowermost layer are not targeted for programming,
The data write method according to claim 20, wherein the application of any one of the program voltages to the selected word line is omitted in the second program loop.
When one of the M program voltages is applied to the selected word line, both the first memory cell and the second memory cell are targeted for programming,
21. The data writing method according to claim 7, wherein different first and second voltages are respectively applied to the channels of the first and second memory cells.
The first memory cell is a memory cell located in a lowermost layer,
The data write method according to claim 23, wherein the first voltage is higher than the second voltage.