WO2015015561A1

WO2015015561A1 - Control/monitor signal transmission system

Info

Publication number: WO2015015561A1
Application number: PCT/JP2013/070555
Authority: WO
Inventors: 錦戸憲治
Original assignee: 株式会社エニイワイヤ
Priority date: 2013-07-30
Filing date: 2013-07-30
Publication date: 2015-02-05
Also published as: JPWO2015015561A1; JP5744341B1

Abstract

[Problem] To provide a control/monitor signal transmission system that can establish a desired number of channels in a transmission synchronization scheme. [Solution] In a control/monitor signal transmission system of the present invention, a master station is connected to a plurality of slave stations via a common data signal line, and a transmission clock signal, one period of which comprises a first status signal and a second status signal following the first status signal, is transmitted to the common data signal line under the control of a timing signal generated by a timing generation means of the master station. A plurality of consecutive periods of the transmission clock signal are used as a unit, and each of the periods included in the unit is allocated to a respective predetermined channel.

Description

Control and monitoring signal transmission system

The present invention reduces the number of signal lines between a master station connected to a control unit and a plurality of output units and input units, or a plurality of slave stations corresponding to a plurality of controlled devices, and connects them with a common data signal line. In addition, the present invention relates to a control / monitor signal transmission system that transmits data by a transmission synchronization method such as synchronization by a transmission clock signal.

In a control system including a control unit, a plurality of output units and input units, or a plurality of controlled devices, so-called wiring saving, which reduces the number of wirings, is widely implemented. As a general technique for reducing the wiring, a parallel signal and a serial signal are used instead of a parallel connection that directly connects a plurality of output units and input units or signal lines extending from a controlled device to the control unit. The master station and the plurality of slave stations having the conversion function are connected to the control unit, the plurality of output units and the input unit, or the plurality of controlled devices, respectively, and common data between the master station and the plurality of slave stations. A method of exchanging data with a serial signal via a signal line is widely adopted.

Also, a transmission synchronization method such as synchronization with a transmission clock is widely adopted as a method for transferring data using a serial signal, and studies for applying it to various situations have been made. For example, when bit data and word data are transmitted independently, it is necessary to perform transmission using a plurality of logically different transmission paths (channels), but a plurality of channels are also provided in the transmission synchronization method. Techniques for this are being considered.

For example, in the control / monitor signal transmission system disclosed in Japanese Patent Application Laid-Open No. 2002-271878, the first control signal from the control unit to the controlled device is a binary signal having a predetermined pulse width (duty ratio). 2 The control signal is a signal of a predetermined level in a period of a level other than the level of the power supply voltage, the first monitoring signal from the input unit to the control unit is the presence or absence of a current signal, and the second control signal is a frequency signal Thus, two channels can be provided in the transmission synchronization method.

JP 2002-271878 A

However, in the prior art including the control / monitor signal transmission system described above, the limit is to superimpose several kinds of multiplexed signals in one cycle of the transmission clock signal, and the number of channels that can be set is limited.

Therefore, an object of the present invention is to provide a control / monitor signal transmission system capable of setting a desired number of channels in a transmission synchronization method.

In the control / monitoring signal transmission system according to the present invention, a master station and a plurality of slave stations are connected by a common data signal line, and one cycle is controlled under the control of a timing signal generated by a timing generator included in the master station. A transmission clock signal composed of a first state signal and a second state signal following the first state signal is transmitted to the common data signal line. Then, a plurality of consecutive cycles of the transmission clock signal are defined as a unit, and each cycle included in the unit is assigned to a predetermined channel.

In the present invention, the first state signal and the second state signal indicate that each is in a different state as a signal, and the type of the signal is not specified. Any signal such as a voltage amplitude modulation signal, a current amplitude modulation signal, a voltage pulse width modulation signal, a current pulse width modulation signal, and a phase modulation signal may be used. For example, in the case of a voltage amplitude modulation signal, the high potential level is the first state signal and the low potential level is the second state signal. Alternatively, the low potential level is the first state signal and the high potential level is the second state signal. Similarly, in the case of a current amplitude modulation signal, the presence of current is the first state signal (or second state signal), and the absence of current is the second state signal (or first state signal). In the case of a voltage pulse width modulation signal, one of the periods of the pulse width signal divided by rising or falling at a timing shifted from the timing of dividing one period of the pulse into two equals is the first state signal, and the other is Second state signal.

At least one of the channels is a high-speed transmission channel, and the slave station belonging to the high-speed transmission channel starts counting transmission addresses based on the transmission clock signal, starting from the end of the start signal of the transmission clock signal, An address counter having a number smaller than an address count value corresponding to the number of periods of one frame cycle between the start signal of the transmission clock signal and the next start signal as a maximum address count value is shorter than the one frame cycle. Data may be exchanged with the master station in a cycle.

Further, one cycle of the transmission clock signal may include a control data signal in one of the first state signal and the second state signal and a monitoring signal in the other state signal. Good.

The terminal according to the present invention is connected to a master station and is in a second state in which one cycle follows the first state signal and the first state signal under the control of a timing signal generated by a timing generator included in the master station. And an address setting means for setting the address of the local station, connected to a common data signal line through which a transmission clock signal composed of the signal is transmitted. And a control data extraction process for counting the period of the transmission clock signal and extracting control data superimposed on the transmission clock signal at a timing coincident with the data of the local station address, and an input unit at the coincidence timing. A slave station input / output unit that performs monitoring data transmission processing to superimpose monitoring data corresponding to an input signal from the transmission signal as a monitoring signal, or a slave station output unit that performs control data extraction processing and the monitoring data transmission Either one of the slave station input units for processing is provided. The address setting means sets an address with a plurality of consecutive periods of the previous transmission clock signal as a unit.

In the control / monitoring signal transmission system according to the present invention, a plurality of consecutive cycles of the transmission clock signal are defined as one unit, and each cycle included in one unit is assigned to a predetermined channel. A number of channels can be provided.

Further, the period between the start signal of the transmission clock signal and the next start signal is defined as one period of the maximum frame, and the frame period defined for the own channel is repeated for each channel within the range of one period of the maximum frame. If the station and the slave station exchange data of the channel to which the station belongs in a unit-by-unit period, the station and the slave station are predetermined in a time shorter than one frame cycle of the transmission clock signal (one period of the maximum frame). Can be scanned at high speed.

Since the terminal according to the present invention includes address setting means for setting an address with a plurality of consecutive periods of the transmission clock signal as a unit, it is possible to accurately obtain the arrival timing of the period assigned to the channel to which the station belongs. It becomes possible. Therefore, it can be used in the control / monitor signal transmission system according to the present invention.

1 is a system configuration diagram showing a schematic configuration of a control / monitor signal transmission system according to the present invention. It is a system configuration | structure figure of a master station. It is a block diagram of a slave station input unit in a slave station belonging to the first channel. It is a block diagram of a slave station output unit in a slave station belonging to the first channel. It is a figure which shows the absolute address generation table of a 1st channel. It is a block diagram of a slave station input unit in a slave station belonging to the second channel. It is a block diagram of a slave station output unit in a slave station belonging to the second channel. It is a figure which shows the absolute address generation table of a 2nd channel. It is a block diagram of a slave station input unit in a slave station belonging to the third channel. It is a block diagram of a slave station output unit in a slave station belonging to the third channel. It is a figure which shows the absolute address generation table of a 3rd channel. FIG. 5 is a schematic diagram of a transmission clock signal that shows data extracted from a transmission clock signal exchanged between a master station and a slave station, divided into first channel data, second channel data, and third channel data. It is a schematic diagram of the transmission clock signal which shows the period of each channel. It is a time chart of a transmission clock signal.

An embodiment of a control / monitor signal transmission system according to the present invention will be described with reference to FIGS.
As shown in FIG. 1, the control / monitor signal transmission system includes a single master station 2 connected to a control unit 1 and common data signal lines DP and DN (hereinafter also referred to as transmission lines), First CH I / O slave station 4a, first CH output slave station 6a, second CH output slave station 6b, third CH output slave station 6c, and first CH input slave station 7a, second CH connected to the common data signal lines DP and DN It is composed of a plurality of input slave stations 7b and a third CH input slave station 7c. In FIG. 1, for convenience of illustration, each slave station is shown one by one, but there is no limitation on the type and number of slave stations connected to the common data signal lines DP and DN.

First CH I / O slave station 4a, first CH output slave station 6a, second CH output slave station 6b, third CH output slave station 6c, first CH input slave station 7a, second CH input slave station 7b, third CH input slave station 7c Performs either or both of signal output processing for the output unit 8 that operates in response to an output instruction of the control unit 1 and input signal processing from the input unit 9 that incorporates input information to the control unit 1. And it is classified into three groups by the transmission data according to the purpose of use. Specifically, the first CH input / output slave station 4a, the first CH output slave station 6a, and the first CH input slave station 7a include a second CH output slave station 6b and a second CH input slave station. 7b is classified into a high-speed transmission group for transmitting high-speed data, and the third CH output slave station 6c and the third CH input slave station 7c are classified into a word transmission group for transmitting multi-bit word data. The periods of the transmission clock signals assigned to the low-speed transmission group, the high-speed transmission group, and the word transmission group are referred to as the first channel (first CH), the second channel (second CH), and the third channel (third CH), respectively. In the following, the parts corresponding to these groups will be labeled “first CH”, “second CH”, and “third CH”, respectively.

The output unit 8 is, for example, an actuator, a (stepping) motor, a solenoid, a solenoid valve, a relay, a thyristor, or a lamp. The input unit 9 is, for example, a reed switch, a micro switch, a push button switch, a photoelectric switch, various sensors, or the like. It is. The first CH input / output slave station 4a is connected to the controlled device 5 including the output unit 8 and the input unit 9, and the first CH output slave station 6a, the second CH output slave station 6b, and the third CH output slave station 6c are output. The first CH input slave station 7 a, the second CH input slave station 7 b, and the third CH input slave station 7 c are connected only to the input unit 9. The first CH output slave station 6a, the second CH output slave station 6b, and the third CH output slave station 6c may include the output unit 8 (output unit integrated slave station 80). 7a, the second CH input slave station 7b, and the third CH input slave station 7c may include the input unit 9 (input unit integrated slave station 90).

The control unit 1 is, for example, a programmable controller, a computer, and the like, and includes a first CH output unit 11a, a second CH output unit 11b, a second CH output parallel data 13c, a second CH control parallel data 13b, and a third CH control parallel data 13c. The 3CH output unit 11c, the first CH input / output slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the first data obtained based on the monitoring data extracted from the monitoring signals from the third CH input slave station 7c. It has a first CH input unit 12a, a second CH input unit 12b, and a third CH input unit 12c that receive the 1CH monitoring parallel data 14a, the second CH monitoring parallel data 14b, and the third CH monitoring parallel data 14c. The first CH output unit 11a, the second CH output unit 11b, the third CH output unit 11c, the first CH input unit 12a, the second CH input unit 12b, and the third CH input unit 12c are connected to the master station 2.

As shown in FIG. 2, the master station 2 includes a first CH output data unit 21a, a second CH output data unit 21b, a third CH output data unit 21c, a timing generation unit 23, a master station output unit 24, a master station input unit 25, A first CH input data unit 26a, a second CH input data unit 26b, and a third CH input data unit 26c are provided. A control signal, which is connected to the common data signal lines DP and DN and is a series of pulse signals corresponding to the transmission clock signal of the present invention, is sent to the common data signal lines DP and DN, and the first CH input / output slave station 4a, first CH input slave station 7a, second CH input slave station 7b, first CH monitoring parallel data 14a, second CH monitoring parallel data 14b, third CH monitoring parallel extracted from the monitoring signal transmitted from the third CH input slave station 7c The data 14c is sent to the first CH input unit 12a, the second CH input unit 12b, and the third CH input unit 12c of the control unit 1.

The first CH output data unit 21a delivers the first CH control parallel data 13a from the first CH output unit 11a of the control unit 1 to the master station output unit 24 as serial data. The second CH output data unit 21b delivers the second CH control parallel data 13b from the second CH output unit 11b of the control unit 1 to the master station output unit 24 as serial data. The third CH output data unit 21c delivers the third CH control parallel data 13c from the third CH output unit 11c of the control unit 1 to the master station output unit 24 as serial data.

The timing generation unit 23 includes an oscillation circuit (OSC) 31 and a timing generation unit 32. The timing generation unit 32 generates a timing clock of the system based on the oscillation circuit (OSC) 31, and generates a master station output unit 24, Delivered to the station input unit 25.

The master station output unit 24 includes control data generation means 33 and a line driver 34. Based on the data received from the first CH output data unit 21a, the second CH output data unit 21b, the third CH output data unit 21c, and the timing clock received from the timing generation unit 23, the control data generation means 33 passes through the line driver 34. The transmission clock signal is sent as a series of pulse signals to the common data signal lines DP and DN.

The transmission clock signal has a control / monitor data area following the start signal ST. The control / monitoring data area includes control signal data transmitted from the master station 2, the first CH input / output slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c. And monitoring signal data to be transmitted. As shown in FIG. 14, the pulse of the transmission clock signal (transmission clock) has a high potential level of the power supply voltage in the second half of one cycle (corresponding to the second state signal of the present invention, +24 V in this embodiment). The first half of the pulse of the low potential level (corresponding to the first state signal of the present invention) that is not at the power supply voltage level is used as the data signal area. The low potential level indicates whether the length of the pulse width represents the data of the control signal and the current superimposed thereon is larger or smaller than a predetermined value (in this embodiment, 10 mA, but the current value is not limited). It represents monitoring signal data. In this embodiment, when one cycle of the transmission clock signal is t0, the pulse width of the low potential level is extended from (1/4) t0 to (1/2) t0. As long as it corresponds to the value of each data of the input first CH control parallel data 13a, second CH control parallel data 13b, and third CH control parallel data 13c, the length is not limited and may be determined appropriately. Furthermore, the first half of one cycle of the transmission clock signal may be the power supply voltage level, and the second half may be the low potential level.

Since the high potential level of the transmission clock signal is the power supply voltage, the first CH input / output slave station 4a, the first CH output slave station 6a, the first CH input slave station 7a, the second CH output slave station 6b, and the second CH The input slave station 7b, the third CH output slave station 6c, and the third CH input slave station 7c all generate internal circuit power from the transmission clock signal.

As shown in FIGS. 12 and 13, the number of pulses (transmission clock) in one frame cycle of the transmission clock signal is 192, and the absolute address is set to 191 because the start address is 0. ing. Also, the transmission clock signal cycle of the absolute addresses (# 0, # 3, # 6...) Of 3 intervals from 0 to 189 is set to the first channel, and the absolute addresses (# 1, # 4, #) of 3 intervals from 1 to 190 are set. 7) is assigned to the second channel, and transmission clock signal periods of absolute addresses (# 2, # 5, # 8,...) Of 3 intervals from 2 to 191 are assigned to the third channel. A transmission clock signal cycle assigned to the first channel, a transmission clock signal cycle assigned to the second channel, and a plurality of consecutive cycles of the transmission clock signal cycle assigned to the third channel (three transmission clock signal cycles) Is a unit of the present invention.

The start signal ST is a signal having the same potential level as the high potential level of the transmission clock signal and longer than one cycle of the transmission clock signal.

The master station input unit 25 includes monitoring signal detection means 35, first CH monitoring data extraction means 36a, second CH monitoring data extraction means 36b, and third CH monitoring data extraction means 36c. The monitoring signal detection means 35 is transmitted from the first CH input / output slave station 4a, the first CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c via the common data signal lines DP and DN. Detect supervisory signals. As described above, the data of the monitoring signal is represented by whether the current superimposed on the low potential level is larger or smaller than 10 mA. After the start signal ST is transmitted, the first CH input / output slave station 4a, the first A monitoring signal is received from each of the 1CH input slave station 7a, the second CH input slave station 7b, and the third CH input slave station 7c. Then, the monitoring signal detected by the monitoring signal detection means 35 is delivered to the first CH monitoring data extraction means 36a, the second CH monitoring data extraction means 36b, and the third CH monitoring data extraction means 36c.

The first CH monitoring data extracting unit 36a extracts the first CH monitoring data in synchronization with the timing from the timing generating unit 32, and sends it to the first CH input data unit 26a as serial input data.

The second CH monitoring data extracting means 36b extracts the second CH monitoring data in synchronization with the timing from the timing generating means 32, and sends it to the second CH input data section 26b as serial input data.

The third CH monitoring data extracting unit 36c extracts the third CH monitoring data in synchronization with the timing from the timing generating unit 32, and sends it to the third CH input data unit 26c as serial input data.

The first CH input data unit 26a converts the serial input data received from the first CH monitoring data extraction unit 36a into parallel data, and sends it to the first CH input unit 12a of the control unit 1 as the first CH monitoring parallel data 14a. To do. Further, the second CH input data unit 26b converts the serial input data received from the second CH monitoring data extracting unit 36b into parallel data, and the second CH input data 12b of the control unit 1 is converted into the second CH monitoring parallel data 14b. To send. Further, the third CH input data unit 26c converts the serial input data received from the third CH monitoring data extracting unit 36c into parallel data, and the third CH input data 12c of the control unit 1 is converted into the third CH monitoring parallel data 14c. To send.

As shown in FIG. 3, the first CH input slave station 7a includes transmission reception means 41, address extraction means 43, first CH monitoring data transmission means 45, CH number setting means 47, first CH address data storage means 51, first CH final address. An address data storage unit 52 and a first CH slave station input unit 70 a having an input unit 71 are provided. The input slave station 7a of this embodiment includes an MCU which is a microcomputer control unit as an internal circuit, and this MCU functions as the first CH slave station input unit 70a. Calculations and storages necessary for the processing are executed using the CPU, RAM, and ROM included in the MCU. The CPU, RAM, and processing in each processing of each of the above-described units constituting the first CH slave station input unit 70a. The relationship with the ROM is not shown for convenience of explanation.

The transmission receiving means 41 receives the transmission clock signal transmitted to the common data signal lines DP and DN and delivers it to the address extracting means 43.

The CH number setting means 47 designates the number of channels to be used, and the set channel number is delivered to the address extraction means 43.

The first CH address data storage means 51 designates the data of the logical address of the first channel (1 # 0, 1 # 1, etc. shown in FIG. 12). The data of the set logical address of the first channel is It is delivered to the address extracting means 43.

The first CH final address data storage means 52 sets the maximum value of the logical address data of the first channel, and the set maximum value of the logical address data of the first channel is delivered to the address extracting means 43. .

The address extraction means 43 has an absolute address generation table 48 and is based on data obtained from the CH number setting means 47 at the time of system startup in this embodiment (in this embodiment, the number of channels is 3) as shown in FIG. The address is developed in the 3CH column (S1 shown in FIG. 5). Next, based on the setting data 1 # 63 (maximum value of the logical address) in the first CH final address data storage means 52, the logical address is expanded from 1 # 0 to 1 # 63 (S2 in FIG. 5). Then, a predetermined absolute address corresponding to the logical address data matching the setting data (logical address data) in the first CH address data storage means 51 is obtained (S3 in FIG. 5).

For example, in the embodiment shown in FIG. 5, since the setting data (logical address data) of the first CH address data storage means 51 is 1 # 0, the data at three intervals up to the absolute addresses # 0, # 3, # 6, # 9 Get. Data of a predetermined absolute address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts transmission clock signal pulses starting from the end of the start signal ST indicating the start of the transmission clock signal. The absolute address counter 44 is data of a predetermined absolute address (# 0, # 3, # 6, # in the embodiment shown in FIG. 5) corresponding to the setting data (logical address data) of the first CH address data storage means 51. Each time, the transmission transmission signal of that period is transferred to the first CH monitoring data transmitting means 45, and the first CH monitoring data transmitting means 45 is made valid. Note that the data of a predetermined plurality of absolute addresses corresponding to 1 # 0 obtained in the absolute address generation table 48 is first the absolute address data handed over to the absolute address counter (# 0 in the embodiment shown in FIG. 5). Is the output timing that coincides with the data of the absolute address counter 44, the data of the next absolute address (# 3 in the embodiment shown in FIG. 5) is delivered to the absolute address counter 44, and the subsequent absolute address data is also sequentially sequentially. Delivered.

The first monitoring data transmission unit 45 sets the base current of the transistor TR to “on” or “off” based on the data delivered from the input unit 71 when it is validated by the address extraction unit 43. When the base current is “on”, the transistor TR is “on”, and a current signal in units of 20 mA, which is a monitoring signal, is output to the common data signal lines DP and DN.

The input unit 71 delivers the monitoring data to the first monitoring data transmission unit 45 based on the input data from the input unit 9.

As shown in FIG. 4, the first CH output slave station 6a includes a transmission receiving means 41, an address extracting means 43, a first CH control data extracting means 46, a CH number setting means 47, a first CH address data storage means 51, and a first CH final data. A first CH slave station output unit 60 a having address data storage means 52 and output means 61 is provided. Similarly to the first CH input slave station 7a, the first CH output slave station 6a also includes an MCU that is a microcomputer control unit as an internal circuit. This MCU functions as the first CH slave station output unit 60a. The calculations and storages required for the processing are executed using the CPU, RAM, and ROM included in the MCU. The CPU, RAM, and processing in each processing of each of the above-described means constituting the first CH slave station output unit 60a. The relationship with the ROM is not shown for convenience of explanation. Further, in FIG. 4, the same reference numerals are given to substantially the same parts as those of the first CH input slave station 7a, and the description thereof will be simplified or omitted.

The first CH control data extraction means 46 controls the transmission received signal delivered from the address extraction means 43 at the timing when the absolute address (# 0) obtained in the absolute address generation table 48 matches the count data of the absolute address counter 44. Extract data. Then, the data is delivered to the output means 61 as the first CH control data.

The output unit 61 converts the first CH control data delivered from the first CH control data extraction unit 46 into parallel data, outputs the parallel data to the output unit 8, and causes the output unit 8 to perform a predetermined operation.

Similarly to the first CH input slave station 7a, the second CH input slave station 7b shown in FIG. 6 includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU serves as a second CH slave station input unit 70b. It is supposed to function. As with the MCU of the first CH slave station input unit 70a, the calculations and storages required for the processing of the second CH input slave station 7b are executed using the CPU, RAM and ROM included in this MCU. It has become.

As shown in FIG. 6, the functional configuration of the second CH slave station input unit 70b includes the first CH address data storage unit 51 and the first CH final address data storage unit 52 of the first CH slave station input unit 70a shown in FIG. These are replaced with the second CH address data storage means 53 and the second CH final address data storage means 54, respectively, and the others are the same as the first CH slave station input unit 70a. Therefore, in FIG. 6, the same reference numerals are given to substantially the same parts as the first CH slave station input unit 70a shown in FIG. 3, and the description thereof is simplified or omitted. The second CH monitoring data transmitting unit 45 has the same function as the first CH monitoring data transmitting unit 45, and therefore the reference numerals are the same, but the names are different for convenience of explanation of the drawing.

The second CH address data storage means 53 designates the logical address (2 # 0, 2 # 1, 2 # 2, 2 # 3) of the second channel, and the set logical address of the second channel Is transferred to the address extracting means 43.

In the second CH final address data storage means 54, 2 # 3 is set as the maximum value of the logical address of the second channel.

The address extracting unit 43 of the second CH slave station input unit 70b has an absolute address generation table 48, and is based on data obtained from the CH number setting unit 47 when the system of the present invention is started (in this embodiment, the number of channels is 3). As shown in FIG. 8, the absolute address is developed in a 3CH column (S1 shown in FIG. 8). Next, the logical addresses 2 # 0 to 2 # 3 are repeatedly expanded based on the setting data 2 # 3 (maximum value of the logical address) in the second CH final address data storage means 54 (S2 in FIG. 8). Then, a predetermined absolute address corresponding to the logical address data matching the setting data (logical address data) in the second CH address data storage means 53 is obtained (S3 in FIG. 8).

For example, in the embodiment shown in FIG. 8, since the setting data (logical address data) of the second CH address data storage means 53 is 2 # 0, absolute addresses # 1, # 13, # 25, etc. Obtain predetermined data for the interval. Data of a predetermined absolute address obtained in the absolute address generation table 48 is sequentially delivered to the absolute address counter 44. The absolute address counter 44 counts transmission clock signal pulses starting from the end of the start signal ST indicating the start of the transmission clock signal. The absolute address counter 44 has predetermined absolute address data corresponding to the setting data (logical address data) of the second CH address data storage means 53 (# 1, # 13, # 25, etc. in the embodiment shown in FIG. Each time, the transmission transmission signal of that cycle is handed over to the second CH monitoring data transmitting means 45, and the second CH monitoring data transmitting means 45 is validated. Note that the data of a predetermined plurality of absolute addresses corresponding to 2 # 0 obtained in the absolute address generation table 48 is first the absolute address data handed over to the absolute address counter (# 1 in the embodiment shown in FIG. 8). Is the output timing that coincides with the data of the absolute address counter 44, the data of the next absolute address (# 13 in the embodiment shown in FIG. 8) is delivered to the absolute address counter 44, and the subsequent absolute address data is also sequentially sequentially. Delivered.

Note that the smaller the logical address data set in the second CH final address data storage means 54, the faster the transmission response.

Similarly to the first CH input slave station 7a, the third CH input slave station 7c shown in FIG. 9 includes an MCU that is a microcomputer control unit as an internal circuit, and this MCU serves as the third CH slave station input unit 70c. It is supposed to function. Similar to the MCU of the first CH slave station input unit 70a, the computation and storage necessary for the processing of the third CH input slave station 7c are executed using the CPU, RAM, and ROM provided in this MCU. It has become.

9 also includes a first CH address data storage unit 51 and a first CH final address data storage unit 52 of the first CH slave station input unit 70a shown in FIG. The third CH address data storage means 55 and the third CH final address data storage means 56 are replaced, and the others are the same as the first CH slave station input unit 70a. Therefore, in FIG. 9, parts that are substantially the same as those of the first CH slave station input unit 70a are denoted by the same reference numerals, and description thereof is simplified or omitted. Note that the third CH monitoring data transmission unit 45 has the same function as the first CH monitoring data transmission unit 45, and therefore the reference numerals are the same, but the names are different for convenience of explanation of the drawing.

The third CH address data storage means 55 designates the third channel logical address (3 # 0, 3 # 1, etc. shown in FIG. 12), and the set third channel logical address data is address extracted. Delivered to means 43. As shown in FIG. 12 and FIG. 13, the third channel is a word composed of 16 transmission clock signal periods as one unit, and four words with one frame cycle of the transmission clock signal as one period Twc. Is intended for transmission. Then, the third CH address data storage means 55 is set with the first logical address of the word to be exchanged, 3 # 0, 3 # 16, and the like.

The third CH final address data storage means 56 sets the maximum value of the logical address data of the third channel, and the set maximum value of the logical address data of the third channel is delivered to the address extraction means 43. .

The address extracting means 43 of the third CH slave station input unit 70c has an absolute address generation table 48, and is based on data obtained from the CH number setting means 47 when the system of the present invention is started (in this embodiment, the number of channels is 3). As shown in FIG. 11, the data of the absolute address is developed in the 3CH column (S1 shown in FIG. 11). Next, based on the setting data 3 # 63 (maximum value of the logical address) in the third CH final address data storage means 56, the logical addresses are expanded from 3 # 0 to 3 # 63 (S2 in FIG. 11). Then, a predetermined absolute address corresponding to the logical address that matches the setting data (logical address data) in the third CH address data storage means 55 is obtained (S3 in FIG. 11).

For example, in the embodiment shown in FIG. 11, since the setting data (logical address data) of the third CH address data storage means 55 is 3 # 0, data at intervals of 3 from # 2 to # 51, such as absolute addresses # 2, # 5, etc. Get. Data of a predetermined absolute address obtained in the absolute address generation table 48 is delivered to the absolute address counter 44. The absolute address counter 44 counts transmission clock signal pulses starting from the end of the start signal ST indicating the start of the transmission clock signal, and predetermined absolute address data corresponding to the setting data in the third CH address data storage means 55 (see FIG. In the embodiment shown in FIG. 11, the transmission transmission signal of that cycle is handed over to the third CH monitoring data transmitting means 45 at the timing that coincides with the data of three intervals from # 2 to # 51), and the third CH monitoring data transmitting means 45 Enable The data of a predetermined plurality of absolute addresses corresponding to 3 # 0 obtained in the absolute address generation table 48 is first the absolute address data handed over to the absolute address counter (# 2 in the embodiment shown in FIG. 11). Is the output timing that coincides with the data of the absolute address counter 44, the data of the next absolute address (# 5 in the embodiment shown in FIG. 8) is delivered to the absolute address counter 44, and the subsequent absolute address data is also sequentially sequentially. Delivered.

Both the output unit 8 and the input unit 9 having a corresponding relationship are connected to the first CH input / output slave station 4a. Similarly to the first CH output slave station 6a and the first CH input slave station 7a, the first CH input / output slave station 4a also includes an MCU that is a microcomputer control unit as an internal circuit. It functions as the station input / output unit 40a. Similar to the MCU of the first CH slave station output unit 60a and the MCU of the first CH slave station input unit 70a, the computation and storage required in the processing of the first CH input / output slave station 4a are performed by the CPU and RAM of this MCU. And is executed using a ROM. The first CH slave station input / output unit 40a has a configuration in which both the first CH slave station output unit 60a and the first CH slave station input unit 70a are combined, and each component includes the first CH slave station output unit 60a or the first CH slave unit. Since it is the same as the component of the station input part 70a, description is abbreviate | omitted.

Similarly to the first output slave station 6a, the second CH output slave station 6b and the third CH output slave station 6c include an MCU that is a microcomputer control unit as an internal circuit, and this MCU is the second CH slave station. It functions as the output unit 60b and the third CH slave station output unit 60c. Similar to the MCU of the first CH slave station output unit 60a, the computation and storage required in the processing of the second CH output slave station 6b and the third CH output slave station 6c are performed by the CPU, RAM and ROM provided in this MCU. It is meant to be used and executed.

As shown in FIGS. 7 and 10, the functional configurations of the second CH slave station output unit 60b and the third CH slave station output unit 60c are the same as the first CH address data storage means 51 of the first CH slave station output unit 60a shown in FIG. The second CH address data storage means 53 and the third CH address data storage means 55 are replaced with the first CH final address data storage means 52 by the second CH final address data storage means 54 and the third CH final address data storage means 56. Yes, the others are the same as the first CH slave station output unit 60a. Therefore, the description is omitted.

In this control / monitor signal transmission system, the first transmission clock signal period starting from the end of the start signal is the first channel, the second is the second channel, and the third is the third channel. Allocated. Also, the first CH logical addresses 1 # 0 to 1 # 63 are assigned to one unit (hereinafter referred to as a first CH unit) whose transmission clock signal period allocated to the first channel is the head. Furthermore, the second CH logical addresses 2 # 0, 2 # 1, 2 # 2 and 2 # 3 are assigned to one unit (hereinafter referred to as a second CH unit) whose transmission clock signal period allocated to the second channel is the head. Is assigned. Furthermore, the third CH logical addresses 3 # 0 to 3 # 63 are assigned as word addresses to one unit (hereinafter referred to as a third CH unit) whose transmission clock signal period allocated to the third channel is the head. .

Any one of the first CH addresses 1 # 0 to 1 # 63 is assigned to the first CH input / output slave station 4a, the first CH output slave station 6a, and the first CH input slave station 7a belonging to the first channel. Data is exchanged in the first transmission clock signal period of one unit of the first CH to which the first CH address assigned to the own station is assigned. In FIG. 12, the first CH control data is data received by the first CH input / output slave station 4a or the first CH output slave station 6a from the master station, and the first CH monitoring data is the first CH input / output slave station 4a or the first CH. This is data received by the master station from the input slave station 7a.

Any one of the second CH logical addresses 2 # 0, 2 # 1, 2 # 2, and 2 # 3 is assigned to the second CH output slave station 6b and the second CH input slave station 7b belonging to the second channel. Data is exchanged in the first transmission clock signal period of one unit of the second CH to which the assigned second CH logical address is assigned. The logical frame period Thc of the second channel is repeated 16 times within one frame period Tc (period from the start signal to the next start signal) of the transmission clock signal. On the other hand, the logical frame period of the first channel is equal to the frame period Tc of the transmission clock signal. Therefore, the transmission response speed of the second channel is 16 times the transmission response speed of the first channel.

Any one of the third CH logical addresses 3 # 0 to 3 # 63 is assigned to the third CH output slave station 6c and the third CH input slave station 7c belonging to the third channel, and the third CH logical address assigned to the own channel is assigned. Data is exchanged in the first transmission clock signal period of the allocated third CH unit. The 1-word data transmitted in the third channel is composed of 16-bit data, and by specifying the head logical address (for example, 3 # 0) of the word data to be transmitted, a predetermined absolute value corresponding to it is designated. Data can be exchanged at each address, and word data can be exchanged.

The word data transmitted on the third channel may be obtained as a plurality of words in a plurality of transmission cycles.

The order of the transmission clock signal period of one unit starting from the end of the start signal assigned to each channel is set to a predetermined arbitrary order (for example, the third channel first, the first channel second , Third, second channel) may be allocated.

In this control / monitor signal transmission system, control data from the control unit side and monitor data from the slave station side can be transmitted simultaneously in one cycle of the transmission clock signal, and three channels are provided. This is a transmission system in which data transmission and reception are performed at the same time, a so-called six-fold. However, the number of channels is not limited, and a two-channel full-quad scheme may be used.

1 Control Unit 2 Master Station 4a First CH I / O Slave Station 5 Controlled Device 6a First CH Output Slave Station 6b Second CH Output Slave Station 6c Third CH Output Slave Station 7a First CH Input Slave Station 7b Second CH Input Slave Station 7c Third CH Input slave station 8 Output unit 9 Input unit 11a First CH output unit 11b Second CH output unit 11c Third CH output unit 12a First CH input unit 12b Second CH input unit 12c Third CH input unit 13a First CH control parallel data 13b Second CH control parallel Data 13c Third CH control parallel data 14a First CH monitoring parallel data 14b Second CH monitoring parallel data 14c Third CH monitoring parallel data 21a First CH output data unit 21b Second CH output data unit 21c Third CH output data unit 23 Timing generating unit 24 Master station Output unit 25 Master station input unit 26a CH input data section 26b first 2CH input data section 26c first 3CH input data unit 31 OSC (oscillation circuit)
32 Timing generating means 33 Control data generating means 34 Line driver 35 Monitoring signal detecting means 36a First CH monitoring data extracting means 36b Second CH monitoring data extracting means 36c Third CH monitoring data extracting means 40a First CH slave station input / output unit 41 Transmission receiving means 43 Address extraction means 44 Absolute address counter 45 Monitoring data transmission means 46 Control data extraction means 47 CH number setting means 48 Absolute address generation table 51 First CH address data storage means 52 First CH final address data storage means 53 Second CH address data storage means 54 Second CH final address data storage means 55 Third CH address data storage means 56 Third CH final address data storage means 60a First CH slave station output section 60b Second CH slave station output section 60c Third CH slave station output section 61 Output Means 70a First CH slave station input section 70b Second CH slave station input section 70c Third CH slave station input section 71 Input means 80 Output section integrated slave station 90 Input section integrated slave station TR Transistor

Claims

The master station and multiple slave stations are connected by a common data signal line.
Under the control of the timing signal generated by the timing generator included in the master station, a transmission clock signal consisting of a first state signal and a second state signal following the first state signal is one cycle. Transmitted to the line
A control / monitoring signal transmission system characterized in that a plurality of consecutive periods of the transmission clock signal are defined as one unit, and each period included in the unit is assigned to a predetermined channel.
At least one of the channels is a high-speed transmission channel, and a slave station belonging to the high-speed transmission channel starts counting transmission addresses based on the transmission clock signal, starting from the end of the start signal of the transmission signal, A cycle shorter than the one frame cycle, comprising an address counter having a maximum address count value smaller than the address count value corresponding to the number of periods of one frame cycle between the start signal of the transmission clock signal and the next start signal 2. The control / monitor signal transmission system according to claim 1, wherein data is exchanged with the master station.
The control / control circuit according to claim 1, wherein one cycle of the transmission clock signal includes a control signal in one of the first state signal and the second state signal, and a monitoring signal in the other state signal. Monitoring signal transmission system.
A transmission clock signal comprising a first state signal and a second state signal following the first state signal under the control of a timing signal generated by a timing generating means of the parent station connected to the parent station Is connected to the common data signal line to be transmitted,
Address setting means for setting the address of the own station;
Control data extraction processing that counts the cycle of the transmission clock signal and extracts control data superimposed on the transmission clock signal at a timing that matches the data of the local station address, and from the input unit at the timing that matches. A slave station input / output unit that performs monitoring data transmission processing that superimposes monitoring data corresponding to an input signal as a monitoring signal on the transmission clock signal, or a slave station output unit that performs control data extraction processing and the monitoring data transmission processing One of the slave station input parts to perform
The terminal according to claim 1, wherein the address setting means sets an address with a plurality of consecutive periods of the transmission clock signal as a unit.