WO2014181777A1 - Thin-film transistor and method for manufacturing same - Google Patents
Thin-film transistor and method for manufacturing same Download PDFInfo
- Publication number
- WO2014181777A1 WO2014181777A1 PCT/JP2014/062188 JP2014062188W WO2014181777A1 WO 2014181777 A1 WO2014181777 A1 WO 2014181777A1 JP 2014062188 W JP2014062188 W JP 2014062188W WO 2014181777 A1 WO2014181777 A1 WO 2014181777A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- oxide
- layer
- film transistor
- thin film
- dielectric constant
- Prior art date
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- 239000010409 thin film Substances 0.000 title claims abstract description 193
- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 193
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 193
- 239000004065 semiconductor Substances 0.000 claims abstract description 152
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 81
- 239000001301 oxygen Substances 0.000 claims abstract description 79
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 79
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 77
- 239000012212 insulator Substances 0.000 claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 36
- 239000010408 film Substances 0.000 claims description 96
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 76
- 238000000926 separation method Methods 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 17
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 13
- 229910052796 boron Inorganic materials 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 10
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 10
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 239000011701 zinc Substances 0.000 claims description 9
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 8
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- 229910052725 zinc Inorganic materials 0.000 claims description 8
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 239000000395 magnesium oxide Substances 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 6
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- UZLYXNNZYFBAQO-UHFFFAOYSA-N oxygen(2-);ytterbium(3+) Chemical compound [O-2].[O-2].[O-2].[Yb+3].[Yb+3] UZLYXNNZYFBAQO-UHFFFAOYSA-N 0.000 claims description 5
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 4
- 229910000484 niobium oxide Inorganic materials 0.000 claims description 4
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 4
- 229910001404 rare earth metal oxide Inorganic materials 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 229910003454 ytterbium oxide Inorganic materials 0.000 claims description 4
- 229940075624 ytterbium oxide Drugs 0.000 claims description 4
- 108091006149 Electron carriers Proteins 0.000 claims description 3
- 229910000410 antimony oxide Inorganic materials 0.000 claims description 3
- TXKMVPPZCYKFAC-UHFFFAOYSA-N disulfur monoxide Inorganic materials O=S=S TXKMVPPZCYKFAC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052746 lanthanum Inorganic materials 0.000 claims description 3
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 3
- 229910000464 lead oxide Inorganic materials 0.000 claims description 3
- VTRUBDSFZJNXHI-UHFFFAOYSA-N oxoantimony Chemical compound [Sb]=O VTRUBDSFZJNXHI-UHFFFAOYSA-N 0.000 claims description 3
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 claims description 3
- HBEQXAKJSGXAIQ-UHFFFAOYSA-N oxopalladium Chemical compound [Pd]=O HBEQXAKJSGXAIQ-UHFFFAOYSA-N 0.000 claims description 3
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical compound [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 claims description 3
- 229910003445 palladium oxide Inorganic materials 0.000 claims description 3
- 229910003446 platinum oxide Inorganic materials 0.000 claims description 3
- XTQHKBHJIVJGKJ-UHFFFAOYSA-N sulfur monoxide Chemical compound S=O XTQHKBHJIVJGKJ-UHFFFAOYSA-N 0.000 claims description 3
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052777 Praseodymium Inorganic materials 0.000 claims 1
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000010494 dissociation reaction Methods 0.000 abstract 2
- 230000005593 dissociations Effects 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 363
- 238000004544 sputter deposition Methods 0.000 description 48
- 239000000463 material Substances 0.000 description 45
- 239000000758 substrate Substances 0.000 description 42
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 36
- 229910004298 SiO 2 Inorganic materials 0.000 description 34
- 229910003437 indium oxide Inorganic materials 0.000 description 26
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical group [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 25
- 239000007789 gas Substances 0.000 description 21
- 239000012535 impurity Substances 0.000 description 19
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 17
- 229910018557 Si O Inorganic materials 0.000 description 16
- 229910007541 Zn O Inorganic materials 0.000 description 16
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 16
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
- 230000008569 process Effects 0.000 description 12
- -1 polyethylene terephthalate Polymers 0.000 description 11
- 238000007740 vapor deposition Methods 0.000 description 11
- 239000011135 tin Substances 0.000 description 10
- 229910010413 TiO 2 Inorganic materials 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 239000000843 powder Substances 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 206010021143 Hypoxia Diseases 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 239000013077 target material Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910003077 Ti−O Inorganic materials 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005259 measurement Methods 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 238000011282 treatment Methods 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- 238000003795 desorption Methods 0.000 description 5
- 238000011156 evaluation Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052810 boron oxide Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 229920001748 polybutylene Polymers 0.000 description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 description 4
- 239000005020 polyethylene terephthalate Substances 0.000 description 4
- 229910003447 praseodymium oxide Inorganic materials 0.000 description 4
- 238000005546 reactive sputtering Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000002834 transmittance Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 3
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 3
- 238000002441 X-ray diffraction Methods 0.000 description 3
- 230000002411 adverse Effects 0.000 description 3
- 229910002090 carbon oxide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 3
- 229910001195 gallium oxide Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052755 nonmetal Inorganic materials 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 229910002656 O–Si–O Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052910 alkali metal silicate Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- 238000001659 ion-beam spectroscopy Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- MMKQUGHLEMYQSG-UHFFFAOYSA-N oxygen(2-);praseodymium(3+) Chemical compound [O-2].[O-2].[O-2].[Pr+3].[Pr+3] MMKQUGHLEMYQSG-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005668 polycarbonate resin Polymers 0.000 description 2
- 239000004431 polycarbonate resin Substances 0.000 description 2
- 229920001225 polyester resin Polymers 0.000 description 2
- 239000004645 polyester resin Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- KKEYFWRCBNTPAC-UHFFFAOYSA-L terephthalate(2-) Chemical compound [O-]C(=O)C1=CC=C(C([O-])=O)C=C1 KKEYFWRCBNTPAC-UHFFFAOYSA-L 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910004140 HfO Inorganic materials 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- PIRAJFSIUUNUPY-UHFFFAOYSA-N [Sn]=O.[In].[Sn]=O.[In] Chemical compound [Sn]=O.[In].[Sn]=O.[In] PIRAJFSIUUNUPY-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000011276 addition treatment Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- WKMKTIVRRLOHAJ-UHFFFAOYSA-N oxygen(2-);thallium(1+) Chemical compound [O-2].[Tl+].[Tl+] WKMKTIVRRLOHAJ-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910003438 thallium oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
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Definitions
- the present invention relates to a thin film transistor and a method for manufacturing the same.
- TFTs Thin film transistors
- EL organic electroluminescence
- TFT a semiconductor layer (channel layer) using amorphous silicon or polysilicon is known.
- an In (indium) -Zn (zinc) -O (IZO) system, an In-Ga (gallium) -Zn-O (IGZO) system, or Sn (tin) is used for a semiconductor layer.
- IZO In (indium) -Zn (zinc) -O
- IGZO In-Ga (gallium) -Zn-O
- Sn titanium oxide
- TFT using a —Zn—O (SZO) -based metal oxide has been studied (for example, see Patent Document 1).
- Such a thin film transistor has n-type conductivity and exhibits higher channel mobility than amorphous silicon or polysilicon, it can be suitably used as a switching element for a high-definition display or a large-screen display.
- oxygen vacancies are mainly introduced by desorption of oxygen to the indium oxide structure, and as a result, charge is generated to serve as a semiconductor layer.
- a semiconductor layer using a metal oxide as a forming material does not exhibit p-type conduction in principle, an off current is extremely small. Therefore, when a thin film transistor is used, power consumption can be reduced.
- IZO, IGZO, and SZO metal oxides which are metal oxides described in Patent Document 1
- IZO, IGZO, and SZO metal oxides tend to react with the water in the Zn, Ga, and Sn contained therein.
- As a physical structure unstable suboxide is formed, and the amount of oxygen vacancies cannot be adjusted, and there is a problem that transistor characteristics including drain current and threshold voltage are greatly deteriorated.
- silicon oxide (SiO 2 ) is used as the gate insulating film, but a thick film is necessary to suppress the leakage current between the gates, and as a result, the electron mobility is controlled. Therefore, there is a problem that the gate voltage to be applied is increased.
- Patent Document 2 discloses, as a metal oxide, a substance containing at least one element of zinc and tin, yttrium, niobium, tantalum, hafnium, lanthanum, scandium, vanadium, titanium, magnesium. It is disclosed that at least one of aluminum, gallium and silicon is used. In addition, in order to suppress fluctuations in threshold voltage caused by the destruction effect due to plasma damage and the increase in carriers due to radiation effects in the thin film transistor manufacturing stage, at least one of gallium, indium, tin, zirconium, hafnium, and vanadium is added to zinc oxide. It is disclosed to dope one ion (Patent Document 3).
- Non-Patent Document 1 electrical characteristics of an oxide film transistor of an IZO metal oxide doped with tantalum have been reported.
- Non-Patent Document 1 since zinc and tin are included as main elements, there is a great problem that a considerable limitation is imposed on the process in order to suppress the formation of suboxides in the thin film transistor manufacturing stage.
- Patent Document 4 there is a report that indium oxide doped with either tin, titanium, or tungsten is used as a metal oxide instead of IZO or IGZO (Patent Document 4).
- the oxide film transistor using indium oxide doped with either titanium or tungsten described in the above document as the metal oxide the amount of oxygen vacancies introduced into the main structure indium oxide is adjusted at the metal oxide production stage. There is a big problem that the manufacturing process is limited because it is very difficult to do.
- Non-Patent Document 2 IGZO system using large yttrium oxide and dielectric constant than the SiO 2 dielectric constant of 3.9 is 16 (Y 2 O 3) as a gate insulating film It has been reported that the thickness of the gate insulating film can be reduced and the gate voltage can be lowered by manufacturing a thin film transistor. In addition, transistor characteristics of an IGZO thin film transistor using aluminum oxide (Al 2 O 3 ) as a gate insulating film have been reported (Non-patent Document 3). Furthermore, it is disclosed that the gate insulating film of a thin film transistor has a laminated structure of a high dielectric constant film and a low dielectric constant film (Patent Document 5).
- CMOS complementary metal oxide semiconductor
- CMOS complementary metal oxide semiconductor
- a gate insulating film of Al 2 O 3 / SiO 2 laminated as a high dielectric constant film when a gate insulating film of Al 2 O 3 / SiO 2 laminated as a high dielectric constant film is used, an Al 2 O 3 / SiO 2 interface is used. It has been reported that the flat band voltage is shifted by the dipole (Non-Patent Document 4).
- a dipole opposite to that of Al 2 O 3 / SiO 2 is generated. It has been reported that the flat band voltage shifts in the reverse direction (Non-Patent Document 5).
- CMOSs have a Si channel / SiO 2 / high dielectric constant film structure, and there are no reports of flat band voltage shifts in the Si channel / high dielectric constant film / SiO 2 structure. There is a big problem of being imposed.
- the present invention has been made in view of such circumstances, and based on the knowledge of the present inventors, a metal (Me) -O bond or a nonmetal-O bond to a first metal oxide such as indium oxide.
- a metal (Me) -O bond or a nonmetal-O bond to a first metal oxide such as indium oxide.
- a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are provided.
- a first metal oxide capable of generating an electron carrier by introducing an oxygen deficiency by providing a gate electrode provided and an insulator layer provided between the gate electrode and the semiconductor layer;
- a thin film transistor which is a composite metal oxide in which an oxide is added with an oxide having an oxygen release energy of 200 kJ / mol or more higher than that of the first metal oxide.
- the oxygen separation energy of the oxide may be greater than the oxygen separation energy of the first metal oxide by 255 kJ / mol or more.
- the first metal oxide may include at least one selected from the group consisting of indium, gallium, zinc, and tin.
- the oxide may include a second metal oxide composed of an oxide of at least one metal selected from the group consisting of zirconium (Zr) and praseonium (Pr).
- the oxide includes a second metal oxide made of an oxide of at least one metal selected from the group consisting of silicon (Si), tantalum (Ta), lanthanum (La), and hafnium (Hf). It's okay.
- the content of the oxide may be greater than 0 and 50% by weight or less.
- the content of the oxide may be greater than 0 and 5% by weight or less.
- the semiconductor layer may be amorphous.
- the semiconductor layer may have a thickness in the range of 5 nm to 20 nm.
- the oxide may contain at least one element selected from the group consisting of boron (B) and carbon (C). Further, the content of boron (B) and carbon (C) contained in the composite metal oxide may be greater than 0 and 10% by weight or less.
- the semiconductor layer is formed at 10 ° C. or more and 600 ° C. or less.
- the semiconductor layer may be formed at 10 ° C. or more and 400 ° C. or less.
- the semiconductor layer may be formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
- an additional oxide having an oxygen separation energy smaller than the oxygen separation energy of the first metal oxide is added to the oxygen separation energy.
- a thin film transistor is provided which is added to the semiconductor layer by an amount smaller than the amount of oxide added by 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
- the content of the additional oxide may be greater than 0 and equal to or less than 10% by weight.
- the additional oxide may be at least one oxide selected from the group consisting of lead oxide, palladium oxide, platinum oxide, sulfur oxide, antimony oxide, strontium oxide, and ytterbium oxide.
- the additional oxide is added to the semiconductor layer, wherein the semiconductor layer is formed at 10 ° C. or higher and 600 ° C. or lower.
- a manufacturing method is provided.
- the semiconductor layer may be formed at 10 ° C. or more and 500 ° C. or less.
- a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are provided.
- an insulator layer provided between the gate electrode and the semiconductor layer, and the insulator layer is formed on the silicon oxide layer and the silicon oxide layer from the gate electrode side.
- a thin film transistor having a stack of a high dielectric constant first layer having a higher dielectric constant than the silicon oxide layer provided in contact therewith and a high dielectric constant second layer having a higher dielectric constant than the silicon oxide layer.
- a source electrode and a drain electrode a semiconductor layer provided in contact with the source electrode and the drain electrode; a gate electrode provided corresponding to a channel between the source electrode and the drain electrode; An insulator layer provided between a gate electrode and the semiconductor layer is provided, and the insulator layer is provided in contact with the silicon oxide layer and the silicon oxide layer from the semiconductor layer side.
- a thin film transistor having a stack of a high dielectric constant first layer having a higher dielectric constant and a high dielectric constant second layer having a higher dielectric constant than the silicon oxide layer.
- the dielectric constant of the second high dielectric constant layer may be higher than the dielectric constant of the first high dielectric constant layer.
- the first high dielectric constant layer may be one or more metal oxides selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, niobium oxide, rare earth oxide, magnesium oxide, and strontium oxide. It may be formed from a material, silicate oxide or silicon oxynitride.
- the high dielectric constant second layer may be formed of a metal oxide having a dielectric constant of 20 or more.
- the high dielectric constant first layer may have a thickness of 0.6 nm or more.
- the thickness of the silicon oxide film may be 0.6 nm or more.
- the semiconductor layer is formed at 10 ° C. or more and 400 ° C. or less.
- the semiconductor layer may be formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
- the oxygen separation energy of the metal (Me) -O bond or non-metal-O bond to the first metal oxide such as indium oxide is 200 kJ / mol than the oxygen separation energy of the first metal oxide.
- the use of a dipole generated at the interface in forming a high dielectric constant layer in contact with the SiO 2 layer and a structure using a high dielectric constant layer having a dielectric constant of 20 or more can reduce the threshold voltage with a low leakage current.
- a controlled thin film transistor can be provided.
- FIG. 1 is a schematic cross-sectional view of a thin film transistor according to a first embodiment of the present invention.
- the schematic sectional drawing of the thin-film transistor which concerns on the 2nd Embodiment of this invention.
- the schematic sectional drawing of the thin-film transistor which concerns on the 3rd Embodiment of this invention.
- FIG. 3 is a schematic cross-sectional view of a thin film transistor according to first, second, and third embodiments of the present invention.
- FIG. 6 is a diagram showing the result of Id—Vg characteristic measurement of the In—Si—O semiconductor layer of the first embodiment of the present invention.
- FIG. 6 is a diagram showing the result of Id—Vd characteristic measurement of the In—Si—O semiconductor layer of the first embodiment of the present invention.
- the figure which shows the X-ray-diffraction pattern for confirming that the semiconductor film used by the 2nd Example of this invention is amorphous.
- FIG. 10 is a schematic cross-sectional view of another thin film transistor according to the fourth embodiment of the present invention.
- Band diagram showing a Vth shift dipole in the positive direction of a thin film transistor according to a fourth embodiment of the present invention The band figure which shows the dipole of the Vth shift of the positive direction of another thin-film transistor concerning the 4th Embodiment of this invention.
- the band figure which shows the dipole of the Vth shift of the negative direction of another thin-film transistor concerning the 4th Embodiment of this invention The schematic sectional drawing of the Example of the thin-film transistor produced in order to confirm the operation
- movement of 4th Embodiment. Shows the results of the fourth embodiment of the embodiment of the p ++ -poly-Si / SiO 2 / Al 2 O 3 / IGZO TFT of Id-Vg.
- the thin film transistor of the first embodiment is provided corresponding to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode.
- This is a composite metal oxide composed of an oxide having a separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
- the thin film transistor manufacturing method of the first embodiment includes a step of forming the semiconductor layer at 10 ° C. or higher and 400 ° C. or lower or 600 ° C. or lower depending on conditions in manufacturing the thin film transistor.
- FIG. 1 is a schematic cross-sectional view of a thin film transistor 101 according to the first embodiment.
- the substrate 102 a substrate formed of a known forming material can be used, and any of those having light transmittance and those having no light transmittance can be used.
- an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene)
- Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used.
- the substrate may be a composite material formed by combining a plurality of these materials. The thickness of the substrate 102 can be appropriately set according to the design.
- the thin film transistor 101 is a so-called bottom gate type transistor.
- the thin film transistor 101 includes a gate electrode 103 provided over a substrate 102, an insulator layer 104 provided to cover the gate electrode 103, a semiconductor layer 105 provided on the top surface of the insulator layer 104, A source electrode 108 and a drain electrode 109 are provided in contact with the semiconductor layer 105 on the upper surface.
- the gate electrode 103 is provided so as to correspond to the channel region of the semiconductor layer 105 (at a position overlapping the channel region in a plan view).
- the semiconductor layer 105 is composed of a composite metal oxide obtained by adding the second metal oxide 107 to the first metal oxide 106.
- the semiconductor layer 105 (composite metal oxide) is such that the particles of the second metal oxide 107 are scattered in the first metal oxide 106.
- the second metal oxide is uniformly added to the first metal oxide, that is, doped, so that the composite metal oxide is uniform. Please note that it is a new material.
- the gate electrode 103, the source electrode 108, and the drain electrode 109 those formed of a generally known material can be used.
- the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
- the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
- metal materials such as these, alloys thereof, and conductive oxides such as indium tin oxide (ITO) and zinc oxide (ZnO).
- these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.
- the gate electrode 103, the source electrode 108, and the drain electrode 109 may be formed of the same forming material or may be formed of different forming materials.
- the source electrode 108 and the drain electrode 109 are preferably made of the same material since manufacturing is easy.
- the insulator layer 104 has an insulating property and can be formed using either an inorganic material or an organic material as long as it can electrically insulate the gate electrode 103 from the source electrode 108 and the drain electrode 109. It may be formed.
- the inorganic material include normally known insulating oxides such as SiO 2 , SiN x , SiON, Al 2 O 3 , and HfO 2 , nitrides, and oxynitrides.
- the organic material include acrylic resin, epoxy resin, silicon resin, and fluorine resin.
- the organic material is preferably a photocurable resin material because it is easy to manufacture and process.
- the semiconductor layer 105 is composed of a first metal oxide and an oxide having an oxygen separation energy greater than that of the first metal oxide by 200 kJ / mol or more.
- the first metal oxide is a substance having a semiconductor property capable of generating electron carriers by introducing oxygen vacancies.
- the first metal oxide include metal oxides containing at least one of indium, zinc, and tin.
- a metal oxide containing at least one of indium, gallium, zinc, and tin may be used as the first metal oxide. Among these, indium that can easily introduce oxygen deficiency at a low temperature is more preferable.
- the oxygen separation energy of indium oxide is as small as 346 ⁇ 30 kJ / mol, so oxygen is easily desorbed from indium oxide to generate oxygen vacancies. It's easy to do. However, if the amount of oxygen vacancies becomes too large, it changes from semiconducting properties to metallic properties, making it unsuitable as a semiconductor layer. As a result of repeated investigations to solve this problem, the inventors of the present application are metal oxides having an oxygen separation energy larger than that of indium oxide in order to control the amount of oxygen vacancies in indium oxide. It has been found that a bimetallic oxide or an equivalent nonmetallic element may be added as described later.
- the oxygen deficiency of indium oxide can be easily controlled. It becomes.
- the oxygen separation energy of the second metal oxide is 200 kJ / mol or more, more preferably 255 kJ compared to the first metal oxide. What is larger than / mol may be used. In the present embodiment, the second metal oxide is used.
- Table 1 that summarizes metal oxides having an oxygen separation energy of 780 kJ / mol or more and oxygen separation.
- Table 2 which summarizes metal oxides having energy of 725 kJ / mol or more and 780 kJ / mol or less, zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), oxidation Examples include silicon (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O).
- the second metal oxide added to make the first metal oxide a semiconductor layer having a suitable oxygen deficiency in the first embodiment
- the second metal of 780 kJ / mol or more shown in Table 1
- Oxides are more preferred. Specifically, lanthanum oxide (La—O), silicon oxide (Si—O), tantalum oxide (Ta—O), and hafnium oxide (Hf—O) can be given.
- the content of the second metal oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer having a suitable oxygen deficiency amount is in the range of more than 0 and 50% by weight or less. Good.
- the content of the second metal oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less, it can be produced at a low temperature of 200 ° C. or less.
- the content of the second metal oxide is calculated as a ratio of the weight of the second metal oxide to the total weight of the first metal oxide and the second metal oxide (second metal oxide). Weight / (weight of first metal oxide + weight of second metal oxide) ⁇ 100).
- In-Zn-O-based and In-Ga-Zn-O-based metal oxides tend to be polycrystalline when a semiconductor layer is formed. Therefore, in a generally known thin film transistor, the surface of the semiconductor layer does not become flat due to crystal grains contained in the semiconductor layer. In addition, the normally known semiconductor layer of an oxide film transistor has a reduced electrical conductivity in the plane direction due to such crystal grains. Therefore, in order to obtain planarization of the surface of the semiconductor layer and high electrical conductivity, the semiconductor layer preferably has an amorphous structure.
- the thickness of the semiconductor layer 105 is more preferably in the range of 5 nm to 20 nm. In the present embodiment, the thickness of the semiconductor layer 105 is measured using a crystal oscillation type film thickness meter disposed mainly for film thickness calibration in the sputtering chamber in which the semiconductor layer 105 is formed.
- the composite metal oxide constituting the semiconductor layer 105 is not limited to the first metal oxide added with the second metal oxide. Specifically, an element that forms an oxide having a larger separation energy than the first metal oxide may be added.
- the composite metal oxide may be, for example, an oxide of at least one element selected from boron (B) and carbon (C) (ie, “composite metal oxide” in the present application). Is used in the sense of “an oxide in which a metal oxide is combined with an element having a larger energy of separation from oxygen”).
- the thin film transistor 101 ′ of another embodiment of the present invention shown in FIG. 2 has basically the same structure as the thin film transistor 101 of FIG. 1, but the semiconductor layer 105 ′ corresponding to the semiconductor layer 105 of FIG. The difference is that it is a composite metal oxide obtained by adding boron and / or carbon oxide 110 to oxide 106. 2 that are denoted by the same reference numerals as those in FIG. 1 are the same as the corresponding elements in FIG. 1, and thus the description thereof is omitted.
- the semiconductor layer 105 ′ (composite metal oxide) is also the first metal oxide for convenience of illustration in FIG. 2. It is depicted in a form that can also be seen as having boron or carbon oxide 110 particles interspersed within the object 106, but here again, these oxidations are actually incorporated into the first metal oxide. It should be noted that the composite metal oxide becomes a uniform material because the material is uniformly added, that is, doped.
- the boron (B) oxide is added to the first metal oxide indium oxide (In 2 O 3 ) by, for example, ion implantation.
- the addition amount and depth are controlled by changing the acceleration voltage. it can.
- the content is more preferably greater than 0 and 10% by weight or less.
- the content of boron (B) is calculated as a ratio of the weight of boron (B) to the weight of the composite metal oxide (weight of boron (B) / weight of composite metal oxide ⁇ 100).
- ion implantation is performed by implanting boron ions instead of boron oxide into the first metal oxide. This boron ion becomes a boron oxide in the first metal oxide.
- the oxide when adding an oxide into the first metal oxide, it is not always necessary to add the oxide itself in the addition processing operation itself, for example, a process of adding an element other than oxygen constituting the oxide.
- the oxide can also be formed inside the first metal oxide.
- the addition in a form existing in the form of an oxide in the first metal oxide is referred to as “adding an oxide” regardless of the form of the addition treatment operation. I want.
- the addition of carbon (C) to the first metal oxide indium oxide (In 2 O 3 ) is to change the ratio of the sputtering power by a co-sputtering method using an In 2 O 3 target and a graphite target.
- the addition amount can be controlled, and the content is more preferably greater than 0 and 10% by weight or less.
- the content of carbon (C) is calculated as a ratio of the weight of carbon (C) to the weight of the composite metal oxide (weight of carbon (C) / weight of composite metal oxide ⁇ 100).
- the semiconductor layer is made of a composite metal oxide using both the second metal oxide in the first embodiment described above and the non-metal oxide described in this embodiment at the same time. It is also possible to form.
- both kinds of oxides may inevitably coexist in a semiconductor layer made of a composite metal oxide depending on the kind of the treatment. .
- a thin film of such a semiconductor layer is manufactured by a solution method such as a sol-gel method, there is a high possibility that carbon remains in the thin film. It should be noted that such a case is also included in the present invention.
- the semiconductor layer of the thin film transistor of this embodiment can also be formed by using physical vapor deposition (or physical vapor deposition).
- examples of physical vapor deposition include vapor deposition and sputtering.
- Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition.
- Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering.
- a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
- the gate electrode 103 and the insulator layer 104 are formed on the substrate 102 by a generally known method, and then the semiconductor layer 105 is formed.
- the semiconductor layer 105 includes a first metal oxide powder and an oxide powder whose oxygen separation energy is greater than the oxygen separation energy of the first metal oxide by 200 kJ / mol or more. It is manufactured by a physical vapor deposition method using a target which is a sintered body including a mixed gas of a rare gas and oxygen. Here, it demonstrates as using sputtering method as a physical vapor deposition method.
- a sintered body of indium oxide powder and silicon oxide powder may be employed as the target.
- the target may be mixed with impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide.
- impurities such as an additive (metal oxide or the like) at a weight percent or less of silicon oxide.
- metal oxides such as zinc oxide
- indium oxide and silicon oxide may be mixed into the target at a ratio (weight ratio) equal to or lower than the silicon oxide content in the entire target as unintended impurities. Absent.
- the content of silicon oxide contained in the sintered body is preferably more than 0 wt% and 50 wt% or less. Further, the content of silicon oxide is more preferably more than 0 wt% and not more than 5 wt%.
- In-Zn-O-based and In-Ga-Zn-O-based metal oxides which are generally known oxide semiconductors, if indium oxide is the "host material” and zinc oxide or gallium oxide is the “guest material”
- the guest material zinc oxide or gallium oxide
- the guest material is mixed with 20-30% of the host material (indium oxide).
- the semiconductor layer 105 of the thin film transistor 101 of this embodiment is formed into a thin film using the sintered body as described above as a target.
- the silicon oxide content is more preferably more than 0 wt% and 5 wt% or less. Therefore, the semiconductor layer 105 in this preferred composition is used.
- This oxide semiconductor has an extremely small content of the guest material (silicon oxide) with respect to the host material (indium oxide) as compared with a conventionally known oxide semiconductor.
- a mixed gas of a rare gas and oxygen is used as a process gas.
- the rare gas include helium, neon, argon, krypton, and xenon.
- the process gas does not include a compound having a hydrogen atom.
- an amorphous semiconductor layer can be formed by performing a step of forming a semiconductor layer at 10 ° C. or higher and 200 ° C. or lower. Further, by performing the treatment at a temperature higher than 200 ° C. and lower than or equal to 400 ° C., a suitable crystallized semiconductor layer can be formed. Further, the step of forming the semiconductor layer is preferably performed at room temperature.
- “implemented at room temperature” means that the semiconductor layer is not heated for the step of forming the semiconductor layer, and the temperature adjustment of the working environment is unnecessary.
- sputtering method employed in the method for manufacturing the thin film transistor of the present embodiment known methods such as RF sputtering and DC sputtering can be used.
- the target may be a sintered body of a mixture of these powders or a sintered body of each powder, as long as the target uses indium oxide powder and silicon oxide powder.
- the semiconductor layer can be formed by co-sputtering using a plurality of sintered bodies.
- Silicon oxide has been described as the second metal oxide, but instead zirconium oxide (Zr—O), praseodymium oxide (Pr—O), lanthanum oxide (La—O), tantalum oxide (Ta—O), and Even when hafnium oxide (Hf—O) is used, the semiconductor layer can be formed in a process range corresponding to the magnitude of the separation energy of oxygen.
- Zr—O zirconium oxide
- Pr—O praseodymium oxide
- La—O lanthanum oxide
- Ta—O tantalum oxide
- Hf—O hafnium oxide
- the semiconductor layer has an oxygen release energy in addition to the oxide having an energy greater than or equal to 200 kJ / mol of the first metal oxide and oxygen described above compared to the first metal oxide. Additional oxide smaller than that of the first metal oxide can be added. The addition amount of the additional oxide is set to be smaller than the addition amount of the oxide whose oxygen separation energy is 200 kJ / mol or more larger than that of the first metal oxide.
- the semiconductor layer when the semiconductor layer becomes polycrystalline, the electrical conductivity in the plane direction decreases, and the characteristics of the thin film transistor deteriorate.
- the additional oxide described above the semiconductor layer can be brought into an amorphous state up to a higher semiconductor layer formation temperature than in the case where the additional oxide is not added.
- the second metal oxide having a sufficiently high oxygen separation energy is added to the first metal oxide as described above, and the oxygen separation energy is further increased by the first metal oxide.
- the third metal oxide (additional oxide) is added, which is smaller than the product and the amount added is smaller than that of the second metal oxide.
- the inventors of the present application control the amount of oxygen vacancies with the second metal oxide and add the third metal oxide, so that the semiconductor layer becomes amorphous even in a high temperature range of 500 ° C. or 600 ° C. I found out.
- the third metal oxide is composed of lead oxide having an oxygen release energy of 382.4 ⁇ 3.3 kJ / mol, palladium oxide having 238.1 ⁇ 12.6 kJ / mol, 418.6 ⁇ 11.6 kJ / mol. mol platinum oxide, 517.90 ⁇ 0.05 kJ / mol sulfur oxide, 434 ⁇ 42 kJ / mol antimony oxide, 426.3 ⁇ 6.3 kJ / mol strontium oxide, 213 ⁇ 84 kJ / mol thallium oxide, 387 7 ⁇ 10 kJ / mol ytterbium oxide and the like.
- the content of the second metal oxide is the ratio of the weight of the second metal oxide to the sum of the weight of the first metal oxide, the weight of the second metal oxide, and the weight of the third metal oxide. Calculated (weight of the second metal oxide / (weight of the first metal oxide + weight of the second metal oxide + weight of the third metal oxide) ⁇ 100), and the content of the third metal oxide is Calculated as the ratio of the weight of the third metal oxide to the sum of the weight of the first metal oxide, the weight of the second metal oxide, and the weight of the third metal oxide (weight of the third metal oxide / ( Weight of first metal oxide + weight of second metal oxide + weight of third metal oxide) ⁇ 100).
- the thin film transistor 101 ′′ of this embodiment whose schematic cross-sectional view is shown in FIG. 3 has basically the same structure as the thin film transistor 101 of FIG. 1 of the first embodiment.
- the semiconductor layer 105 of FIG. Whereas the above-described second metal oxide 107 is added to the metal oxide 106, the corresponding semiconductor layer 105 ′′ has a further oxygen separation energy in addition to the first metal oxide in the semiconductor layer 105 of FIG. The difference is that it is a composite metal oxide in which a smaller third metal oxide 112 is added in an amount less than the amount of the second metal oxide added.
- elements having the same reference numerals as those in FIG. 1 are the same as the corresponding elements in FIG. 1, and thus description thereof is omitted.
- the semiconductor layer 105 ′′ (composite metal oxide) is also formed of the first metal oxide for convenience of illustration in FIG.
- the second metal oxide 107 and the third metal oxide 112 are drawn in a form that seems to be scattered in the object 106, but here again, these are actually included in the first metal oxide.
- the composite metal oxide becomes a uniform material by uniformly adding, that is, doping, two kinds of oxides.
- silicon oxide (SiO 2 ) of the second metal oxide and ytterbium oxide (Yb 2 O 3 ) of the third metal oxide to indium oxide (In 2 O 3 ) of the first metal oxide is, for example, This is performed at the target preparation stage of the sputtering method.
- the addition amount can be controlled by changing the ratio of the sputtering power by a co-sputtering method using an In—Si—O target and a Yb 2 O 3 target, and the content of ytterbium oxide is 0% relative to the semiconductor layer. More preferably, it is 10% by weight or less.
- the characteristic change is suppressed by using the novel composite metal oxide for the semiconductor layer.
- the thin film transistor in which the change in characteristics is suppressed has high reliability. Further, according to the method for manufacturing a thin film transistor as described above, a thin film transistor in which a change in characteristics is suppressed can be easily manufactured by using a novel composite metal oxide for a semiconductor layer.
- the thin film transistor shown in FIG. 4 was manufactured and the operation was confirmed.
- the thin film transistor shown in the figure has the same structure as that of the thin film transistor 101 shown in FIG. 1, and uses a Si layer 111 doped with a large amount of p-type impurities in place of the gate electrode 103 included in the thin film transistor 101 of FIG. It has become.
- the thin film transistor of this example uses a Si substrate doped with a p-type impurity, forms the insulator layer 104 by oxidizing the surface, and then forms a semiconductor layer 105 on the surface of the insulator layer 104 using a method described later. Manufactured by forming.
- the source electrode 108 and the drain electrode 109 were formed by mask vapor deposition on the surface of the semiconductor layer 105.
- the source electrode 108 and the drain electrode 109 were made of gold (Au) as a forming material and had a thickness of 50 nm. Further, the separation distance (gate length) between the source electrode 108 and the drain electrode 109 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
- the semiconductor layer 105 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using an In—Si—O target as a target material under the following sputtering conditions.
- DC sputtering a sputtering method
- In—Si—O target a 1 wt% Si-added In-based sample product was used.
- the thickness of the deposited semiconductor layer 105 was 20 nm.
- FIG. 5 and 6 are graphs showing the results of measuring the characteristics of the thin film transistor of the present invention.
- FIG. 5 shows the transfer characteristics and FIG. 6 shows the output characteristics.
- FIG. 5 shows the transfer characteristics of drain current when the gate voltage is applied from negative to positive and from positive to negative.
- FIG. 6 shows the drain current when the drain voltage is increased from 0V and returned to 0V. The output characteristics of are shown.
- FIG. 7 shows the electric conduction characteristics of In—Si—O and In—Ti—O based thin film transistors when the ratio of O 2 / (Ar + O 2 ) is changed in the range of 5 to 25% under the above sputtering conditions.
- Shown in In—Si—O exhibits superior electrical conductivity compared to In—Ti—O at all oxygen ratios in FIG. This is because the oxygen release energy of the Si—O bond (799.6 ⁇ 13.4 kJ / mol) is larger than the oxygen release energy of Ti—O (666.5 ⁇ 5.6 kJ / mol). This is the effect that the oxygen deficiency can be controlled by desorbing suitable oxygen from indium (In 2 O 3 ) with high accuracy.
- In-Si-O shows less change in electrical conduction characteristics with respect to change in the ratio of O 2 / (Ar + O 2 ). From this result, it can be seen that In—Si—O has a larger process margin.
- a semiconductor layer 105 ′′ (see FIG. 3) corresponding to the semiconductor layer 105 in FIG. 4 is formed by sputtering using a sputtering apparatus and an In—Si—Yb—O target as a target material under the following sputtering conditions.
- the In—Si—Yb—O target was a sample product of 10 wt% Si and 2 wt% Yb added In—O system
- the thickness of the deposited semiconductor layer 105 was as follows. It was 20 nm.
- an In—Si—Yb—O film having a thickness of 20 nm was formed on a glass substrate and heat-treated at 450 ° C. for 15 minutes in the atmosphere.
- An X-ray diffraction pattern is shown in FIG.
- an In—Si—O film that is, a semiconductor film to which no additional oxide is added
- heat-treated at 450 ° C. for 15 minutes in the air is also shown.
- a crystal peak based on In 2 O 3 is identified in the In—Si—O film, whereas the In—Si—Yb—O film is amorphous because no peak is observed. I understood.
- FIG. 9 shows the results of measuring the characteristics of the thin film transistor of the present invention.
- FIG. 9 shows the transfer characteristics of the drain current when the gate voltage is applied from negative to positive and from positive to negative.
- a thin film transistor having the basic structure shown in FIG. 4 was formed by a sputtering method (DC sputtering) using a sputtering apparatus and using an In—Si—O target as a target material under the following sputtering conditions.
- a sputtering method DC sputtering
- an In—Si—O target an In—O based sample product containing 11.5% by weight of SiO 2 was used.
- the thickness of the deposited semiconductor layer 105 was 20 nm.
- the formed In—Si—O film was heat-treated at 600 ° C. for 1 hour in the air.
- FIG. 10 the measurement result of the root mean square roughness (RMS) measured with the atomic force microscope with respect to the semiconductor layer 105 after heat processing is shown. The roughness was as small as 0.197 nm, and X-ray diffraction measurement showed that it did not crystallize even when heat-treated at 600 ° C. and maintained amorphous.
- RMS root mean square roughness
- FIG. 11 shows the drain current transfer characteristic when the gate voltage of the thin film transistor before oxygen treatment is applied from negative to positive and from positive to negative.
- FIG. 12 shows the gate voltage of the thin film transistor after oxygen treatment from negative to positive, The transfer characteristic of the drain current when applied from positive to negative is shown.
- the operation of the thin film transistor of the present invention was confirmed, and the usefulness of the present invention was confirmed. Further, in the second and third examples, since the semiconductor layer further has a preferable feature that it is amorphous, a thin film transistor having good characteristics was obtained.
- the present invention provides a thin film transistor having a threshold voltage adjusted by utilizing the fact that a flat band voltage is shifted by a dipole formed between a SiO 2 layer and another dielectric layer adjacent thereto. . That is, a dielectric material that gives a flat band voltage shift for achieving a desired threshold voltage or a shift close thereto is selected and used for the other dielectric layer used for the other dielectric layer.
- the first two layers can be made sufficiently thin, so that the dielectric of the entire film can be achieved without increasing the total thickness of the gate insulating film.
- the present invention has been completed with the idea that the rate can be maintained at a high value, and therefore both threshold voltage control and leakage current suppression can be satisfied.
- the thin film transistor of this embodiment includes a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a gate provided corresponding to a channel between the source electrode and the drain electrode.
- An electrode and an insulator layer provided between the gate electrode and the semiconductor layer, the insulator layer having a higher dielectric constant than the silicon oxide layer and the silicon oxide layer from the gate electrode side; It is a composite metal oxide composed of a laminate of a dielectric constant first layer and a high dielectric constant second layer having a dielectric constant higher than that of the silicon oxide layer.
- the method for manufacturing a thin film transistor according to this embodiment includes a step of forming the semiconductor layer at 10 ° C. or higher and 400 ° C. or lower when manufacturing the thin film transistor.
- FIG. 13 is a schematic cross-sectional view of the thin film transistor 201 according to this embodiment.
- the substrate 202 a substrate formed using a known forming material can be used, and any of those having light transmittance and those having no light transmittance can be used.
- an inorganic substrate made of alkali silicate glass, quartz glass, silicon nitride, or the like; a silicon substrate; a metal substrate whose surface is insulated; acrylic resin, polycarbonate resin, PET (polyethylene terephthalate), or PBT (polybutylene)
- Various substrates such as a resin substrate made of a polyester resin such as terephthalate) or a paper substrate can be used.
- the substrate may be a composite material formed by combining a plurality of these materials.
- the thickness of the substrate 202 can be appropriately set according to the design.
- the thin film transistor 201 is a so-called bottom gate type transistor.
- the thin film transistor 201 includes a gate electrode 203 provided over the substrate 202, an insulator layer 207 provided so as to cover the gate electrode 203, a semiconductor layer 208 provided on the top surface of the insulator layer 207, A source electrode 209 and a drain electrode 210 are provided in contact with the semiconductor layer 208 on the upper surface.
- the gate electrode 203 is provided so as to correspond to the channel region of the semiconductor layer 208 (at a position overlapping the channel region in plan view).
- the insulator layer 207 includes a stack of a silicon oxide layer 204, a high dielectric constant first layer 205 having a dielectric constant higher than that of the silicon oxide layer, and a high dielectric constant second layer 206 having a dielectric constant higher than that of the silicon oxide layer. It is composed of As a matter of course, components other than the high dielectric constant first layer 205 and the high dielectric constant second layer 206 and inevitable impurities are present in the insulator layer 207 as long as the adverse effects of the present invention are not adversely affected. It may be included.
- FIG. 14 shows a thin film transistor 201 'according to another embodiment.
- This thin film transistor is a bottom-gate transistor as in FIG. 13, and includes a gate electrode 203 provided over the substrate 202, an insulator layer 207 provided to cover the gate electrode 203, and an upper surface of the insulator layer 207. And the source electrode 209 and the drain electrode 210 provided in contact with the semiconductor layer 208 on the upper surface of the semiconductor layer 208.
- the gate electrode 203 is provided so as to correspond to the channel region of the semiconductor layer 208 (at a position overlapping the channel region in plan view).
- the insulator layer 207 includes a high dielectric constant second layer 206 having a dielectric constant higher than that of the silicon oxide layer, a high dielectric constant first layer 205 having a dielectric constant higher than that of the silicon oxide layer, and a silicon oxide layer. It is composed of 204 layers.
- the gate electrode 203, the source electrode 209, and the drain electrode 210 can be made of a generally known material.
- the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
- the material for forming these electrodes include aluminum (Al), gold (Au), silver (Ag), copper (Cu), nickel (Ni), molybdenum (Mo), tantalum (Ta), and tungsten (W).
- metal materials such as these and alloys thereof, and conductive oxides such as indium tin oxide (Indium) Tin Oxide (ITO)) and zinc oxide (ZnO).
- these electrodes may form the laminated structure of two or more layers, for example by plating the surface with a metal material.
- the gate electrode 203, the source electrode 209, and the drain electrode 210 may be formed of the same forming material, or may be formed of different forming materials. Since manufacture becomes easy, it is preferable that the source electrode 209 and the drain electrode 210 are the same formation material.
- the semiconductor layer 208 includes In—Zn—O, In—Ga—Zn—O, Sn—Zn—O (SZO), and In—Si— in which various elements are added to indium oxide (In 2 O 3 ).
- Oxide semiconductors that generate electrons by introducing oxygen vacancies such as an O-based, In-Ti-O-based, and In-W-O-based materials can be used. Even metal oxides obtained by adding various elements to titanium oxide (TiO 2 ) without using indium oxide (In 2 O 3 ) can be used as long as they generate electrons.
- the insulator layer 207 corresponding to the thin film transistor 201 includes a silicon oxide layer 204, a high dielectric constant first layer 205 having a higher dielectric constant than silicon oxide, and a high dielectric constant second layer 206 having a dielectric constant higher than that of silicon oxide. . As shown in FIG.
- the silicon oxide layer / high dielectric constant first layer interface in order to give a dipole with a negative silicon oxide side and a positive first dielectric layer with a high dielectric constant, the material of the high dielectric constant first layer is, for example, aluminum oxide, hafnium silicate, hafnium oxide, titanium oxide, tantalum oxide or niobium oxide.
- a metal oxide may be used.
- a composite material of the above metal oxide may be used.
- the high dielectric constant first layer may be a silicate oxide film or a silicon oxynitride film containing the above elements.
- the silicon oxide layer / the high dielectric constant first layer is, for example, yttrium oxide, lanthanum oxide, magnesium oxide, strontium oxide, or a rare earth oxide metal.
- An oxide may be used.
- a composite material of the above metal oxide may be used.
- the high dielectric constant first layer may be a silicate oxide film or a silicon oxynitride film containing the above elements.
- the insulator layer 207 corresponding to the thin film transistor 201 ′ in the insulator layer composed of the high dielectric constant second layer, the high dielectric constant first layer, and the silicon oxide layer from the gate electrode side, in the insulator layer composed of the high dielectric constant second layer, the high dielectric constant first layer, and the silicon oxide layer from the gate electrode side,
- aluminum oxide or hafnium oxide silicate can be used as a material for the high dielectric constant first layer.
- a metal oxide of hafnium oxide, titanium oxide, tantalum oxide or niobium oxide may be used.
- a composite material of the above metal oxide may be used.
- the high dielectric constant first layer may be a silicate oxide film or a silicon oxynitride film containing the above elements.
- the silicon oxide layer / high dielectric constant first layer In order to provide a dipole with a positive silicon oxide side and a negative high dielectric constant first layer at the interface, metal oxide of yttrium oxide, lanthanum oxide, magnesium oxide, strontium oxide or rare earth oxide as the material of the high dielectric constant first layer Use a thing.
- a composite material of the above metal oxide may be used.
- the high dielectric constant first layer may be a silicate oxide film or a silicon oxynitride film containing the above elements.
- the directionality of the dipole generated at the interface between the silicon oxide layer and the high dielectric constant first layer is determined by the difference in density of oxygen concentration due to the crystal structure of both layers at the interface.
- the oxygen concentration on the high dielectric constant first layer side is small, negative oxygen ions on the silicon oxide side move to the high dielectric constant first layer.
- the high dielectric constant first layer side becomes negative and the silicon oxide side becomes negative.
- the direction of the positive dipole is determined by the difference in density of oxygen concentration due to the crystal structure of both layers at the interface.
- the second layer having a high dielectric constant In order to suppress the gate leakage current by increasing the physical film thickness while keeping the electrical film thickness of the insulating layer small, the second layer having a high dielectric constant must be formed of a metal oxide having a dielectric constant of 20 or more. preferable. This is because the metal oxide used for the high dielectric constant first layer for generating the dipole has a material with a dielectric constant smaller than 20 and is not necessarily suitable for increasing the physical film thickness. Suitable materials for use in the second layer of high dielectric constant include, for example, rutile TiO 2 , Sr—Ti—O, Ba—Ti—O, and Pb— (Zr / Ti) —O based metal oxides. Things.
- the thickness of the high dielectric constant first layer is more preferably 0.6 nm or more. This is a film thickness necessary for generating a dipole between the first layer having a high dielectric constant and the silicon oxide layer.
- FIG. 22 described later shows the relationship between the film thickness of the Al 2 O 3 layer and the threshold voltage. Example results are shown.
- the thickness of the silicon oxide film is more preferably 0.6 nm or more. This is because a dipole is generated by having at least two silicon oxide films.
- the O—Si—O—Si—O layer in silicon oxide is counted as one monolayer, and “two or more silicon oxide films” means that there are two or more monolayers. In the case of two monolayers, the outermost surface of the Si substrate is entirely covered with an O—Si—O—Si—O layer. In the case of one monolayer, a part of the Si substrate appears on the surface.
- the insulator layer of the thin film transistor of this embodiment can be formed by using, for example, physical vapor deposition (or physical vapor deposition).
- examples of physical vapor deposition include vapor deposition and sputtering.
- Examples of the vapor deposition method include vacuum vapor deposition, molecular beam vapor deposition (MBE), ion plating, and ion beam vapor deposition.
- Examples of the sputtering method include conventional sputtering, magnetron sputtering, ion beam sputtering, ECR (electron cyclotron resonance) sputtering, and reactive sputtering.
- a film forming method such as a reactive sputtering method, a DC (direct current) sputtering method, or a radio frequency (RF) sputtering method can be used.
- the high dielectric constant first layer can also be formed by using chemical vapor deposition.
- an atomic layer deposition method in which the film thickness can be controlled in angstrom order can be mentioned.
- the silicon oxide layer 204, the high dielectric constant first layer 205, and the high dielectric constant second layer are formed.
- the semiconductor layer 208 is formed.
- the high dielectric constant first layer 205 is manufactured by a chemical vapor deposition method using a source gas and H 2 O gas as an oxidizing agent.
- description will be made assuming that an atomic layer deposition method is used as the chemical vapor deposition method.
- an Al 2 O 3 layer may be formed as the high dielectric constant first layer 205 by an atomic layer deposition method using trimethylaluminum source gas and H 2 O gas.
- the target threshold voltage can be obtained by using the high dielectric constant first layer for the insulator layer formed in the silicon oxide layer. Can be shifted to.
- the semiconductor device having the above-described configuration it has a thin film transistor exhibiting a target threshold voltage and has high reliability.
- a thin film transistor in which the threshold voltage is shifted to a target value by using the high dielectric constant first layer for the insulator layer formed in the silicon oxide layer is obtained. It can be manufactured easily.
- the thin film transistor shown in FIG. 17 was manufactured and the operation was confirmed.
- the thin film transistor shown in the figure has the same structure as that of the thin film transistor 201 shown in FIG. 13, and uses a Si layer 211 doped with a large amount of p-type impurities instead of the gate electrode 203 included in the thin film transistor 201 shown in FIG. It has become.
- FIG. 1 A cross-sectional TEM photograph of the thin film transistor of this example is shown in FIG.
- a 4 nm thick silicon oxide (SiO 2 ) layer 204 by oxidizing the surface using a Si substrate doped with a p-type impurity, a trimethylaluminum source gas and H 2 O gas were used on the surface of the silicon oxide layer 204.
- an Al 2 O 3 layer having a thickness of 200 nm was formed as a first layer having a high dielectric constant at a film formation temperature of 200 ° C.
- a TiO 2 layer having a thickness of 24 nm was formed as a second layer having a high dielectric constant at a film formation temperature of 200 ° C.
- the semiconductor layer 208 is used as the semiconductor layer 208, an In—W—O target is used as a target material, a film formation temperature of 25 ° C., Ar 3 sccm / O 2 0.5 sccm, a degree of vacuum of 0.08 Pa, DC A sputtering power was 50 W and an In—W—O film was formed to 20 nm.
- the source electrode 209 and the drain electrode 210 are made of aluminum (Al) as a forming material and have a thickness of 300 nm. Further, the separation distance (gate length) between the source electrode 209 and the drain electrode 210 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
- the dielectric constants of the Al 2 O 3 film and the TiO 2 film were 8 and 35 as determined from the relationship between the film thicknesses and the capacitor equivalent film thicknesses of the capacitors. Therefore, the SiO 2 equivalent film thickness of the insulating film composed of SiO 2 layer (4 nm) / Al 2 O 3 layer (5 nm) / TiO 2 layer (24 nm) of this thin film transistor was 9.1 nm.
- a leakage current was examined by applying a voltage between Si doped with p-type impurities and an Al source electrode, a small current value of 1.0 nA or less was shown even at 40V.
- the equivalent SiO 2 film thickness of the insulating film is 9.1 nm.
- a leak current was examined by applying a voltage between Si doped with the p-type impurity and the Al source electrode, a large current value of 1.0 nA or more at 20 V was obtained.
- the major difference in the leakage current characteristics is the difference in the physical film thickness of the insulating film (SiO 2 layer / Al 2 O 3 layer / TiO 2 layer 33 nm vs. SiO 2 layer / Al 2 O 3 layer 14.5 nm). to cause. This indicates that the physical film thickness can be increased as the dielectric constant of the second layer having a high dielectric constant increases, and as a result, the leakage current can be reduced.
- the high dielectric constant layer is provided with the first and second layers, but it is the high direct contact with the silicon oxide that contributes to the generation of the dipole that causes the threshold voltage shift. Only the dielectric constant first layer. Obviously, the presence or absence of the high dielectric constant second layer does not affect the generation of the dipole nor the threshold voltage shift amount. Therefore, in order to evaluate the threshold voltage shift effect in the thin film transistor of the present invention, the structure of the insulating layer of the thin film transistor is simplified, and an evaluation is made on an element formed by only the high dielectric constant first layer and the silicon oxide layer. Just do it.
- a thin film transistor with an Al 2 O 3 layer was manufactured according to the following procedure. Using a Si substrate doped with a p-type impurity to form a silicon oxide layer 204 having a thickness of 15 nm by oxidizing the surface, an atomic layer deposition method using trimethylaluminum source gas and H 2 O gas on the surface of the silicon oxide layer 204 Thus, an Al 2 O 3 layer having a film thickness of 200 ° C. was deposited as a high dielectric constant first layer with a thickness of 3 nm.
- a DC sputtering apparatus is used as the semiconductor layer 208, an In—Ga—Zn—O target is used as the target material, a film formation temperature of 25 ° C., Ar 30 sccm / O 2 1.6 sccm, and a degree of vacuum of 0.72 Pa. Then, an In—Ga—Zn—O film having a thickness of 20 nm was formed at a DC sputtering power of 100 W.
- the source electrode 209 and the drain electrode 210 are made of aluminum (Al) as a forming material and have a thickness of 300 nm.
- the separation distance (gate length) between the source electrode 209 and the drain electrode 210 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
- a thin film transistor without an Al 2 O 3 layer was produced by the following procedure.
- a silicon substrate 4 having a thickness of 16 nm was formed by oxidizing the surface using a Si substrate doped with a p-type impurity.
- a DC sputtering apparatus is used as the semiconductor layer 208, an In—Ga—Zn—O target is used as the target material, a film formation temperature of 25 ° C., Ar 30 sccm / O 2 1.6 sccm, and a degree of vacuum of 0.72 Pa.
- the source electrode 209 and the drain electrode 210 are made of aluminum (Al) as a forming material and have a thickness of 300 nm.
- the separation distance (gate length) between the source electrode 209 and the drain electrode 210 was 350 ⁇ m, and the length of the facing portion was 940 ⁇ m.
- FIG. 19 shows transfer characteristics of the thin film transistor.
- the Al 2 O 3 layer has a Id-Vg curve it can be seen that shifts in the negative direction than without the Al 2 O 3 layer. This shift is due to the effect of the dipole generated at the SiO 2 / Al 2 O 3 layer interface.
- FIG. 20 shows the variation in threshold voltage when the MgO layer, Y 2 O 3 layer, La 2 O 3 layer, and SrO layer are formed with a thickness of about 5 nm.
- the vertical axis represents the shift of the threshold voltage with respect to the threshold voltage of the thin film transistor in the absence of the high dielectric constant first layer.
- the threshold voltage shifts in the negative direction as in the case of the Al 2 O 3 layer. did.
- the size was in the following order.
- the threshold voltage of the thin film transistor using the MgO layer, the Y 2 O 3 layer, the La 2 O 3 layer, and the SrO layer showed a positive shift, and the magnitude was in the following order.
- a thin film transistor using a Si substrate doped with a p-type impurity having the same structure as that of the thin film transistor 201 ′ shown in FIG. 14 as a gate electrode was manufactured by the following method.
- An Al 2 O 3 layer having a thickness of 3 nm is formed on a Si substrate doped with a p-type impurity by an atomic layer deposition method, and then a SiO 2 film having a thickness of 28 nm by a metal organic chemical growth method using tetraethoxysilane gas. Two layers were formed.
- a DC sputtering apparatus is used as the semiconductor layer 208, an In—Ga—Zn—O target is used as the target material, a film formation temperature of 25 ° C., Ar 30 sccm / O 2 1.6 sccm, and a degree of vacuum of 0.72 Pa. Then, an In—Ga—Zn—O film having a thickness of 20 nm was formed at a DC sputtering power of 100 W.
- the source electrode 209 and the drain electrode 210 are made of aluminum (Al) as a forming material and have a thickness of 300 nm.
- FIG. 21 shows the relationship between the capacitance capacity film thickness (CET) of the Al 2 O 3 layer and the SiO 2 insulating layer and the threshold voltage normalized by the threshold voltage of the thin film transistor without the Al 2 O 3 layer.
- CET capacitance capacity film thickness
- the threshold voltage of the Si / SiO 2 / Al 2 O 3 structure doped with the p-type impurity shifts in the negative direction, whereas the Si / Al 2 O doped with the p-type impurity.
- the threshold voltage of the 3 / SiO 2 structure shifted in the positive direction. From the direction of the threshold voltage shift, it becomes clear that it depends on the direction of the dipole at the Al 2 O 3 / SiO 2 interface.
- the shift amount remains constant, so that the upper limit of the film thickness is limited in that the threshold voltage, which is the purpose of this layer, is shifted. Absent.
- the high dielectric constant first layer is made thicker with the equivalent oxide thickness of the insulating film kept constant, it is necessary to make the high dielectric constant second layer having a higher dielectric constant thinner. As a result, the entire insulating film becomes thinner and the leakage current increases. Accordingly, the thicknesses of these layers are appropriately determined based on various factors such as the convenience of the manufacturing process, the material used, and the allowable leakage current.
- the so-called top contact type thin film transistor has been described.
- the present invention can also be applied to a so-called bottom contact type thin film transistor.
- the present invention it is possible to realize a composite metal oxide semiconductor layer in which the amount of oxygen vacancies is controlled. Can be made amorphous, which can greatly contribute to improving the performance of the thin film transistor.
- the threshold voltage can be controlled with little influence on the dielectric constant of the gate insulating film using a high dielectric constant dielectric, which can greatly contribute to the improvement of the performance of the thin film transistor. .
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Abstract
Description
ここで、前記酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きくてよい。
また、前記第1金属酸化物は、インジウム、ガリウム、亜鉛、および錫からなる群から選択された少なくとも一つを含んでよい。
また、前記酸化物は、ジルコニウム(Zr)、およびプラセオニウム(Pr)からなる群から選択された少なくとも一つの金属の酸化物からなる第2金属酸化物を含んでよい。
また、前記酸化物は、シリコン(Si)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つの金属の酸化物からなる第2金属酸化物を含んでよい。
また、前記酸化物の含有量が0より大きく50重量%以下であってよい。
また、前記酸化物の含有量が0より大きく5重量%以下であってよい。
また、前記半導体層が非晶質であってよい。
また、前記半導体層の厚さが5nm以上かつ20nm以下の範囲であってよい。
また、前記酸化物がボロン(B)および炭素(C)からなる群から選択された少なくとも一つの元素を含んでよい。
また、前記複合金属酸化物に含まれるボロン(B)および炭素(C)の含有量が0より大きく10重量%以下であってよい。 According to the first aspect of the present invention, a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are provided. A first metal oxide capable of generating an electron carrier by introducing an oxygen deficiency by providing a gate electrode provided and an insulator layer provided between the gate electrode and the semiconductor layer; There is provided a thin film transistor which is a composite metal oxide in which an oxide is added with an oxide having an oxygen release energy of 200 kJ / mol or more higher than that of the first metal oxide.
Here, the oxygen separation energy of the oxide may be greater than the oxygen separation energy of the first metal oxide by 255 kJ / mol or more.
The first metal oxide may include at least one selected from the group consisting of indium, gallium, zinc, and tin.
The oxide may include a second metal oxide composed of an oxide of at least one metal selected from the group consisting of zirconium (Zr) and praseonium (Pr).
The oxide includes a second metal oxide made of an oxide of at least one metal selected from the group consisting of silicon (Si), tantalum (Ta), lanthanum (La), and hafnium (Hf). It's okay.
The content of the oxide may be greater than 0 and 50% by weight or less.
The content of the oxide may be greater than 0 and 5% by weight or less.
The semiconductor layer may be amorphous.
The semiconductor layer may have a thickness in the range of 5 nm to 20 nm.
The oxide may contain at least one element selected from the group consisting of boron (B) and carbon (C).
Further, the content of boron (B) and carbon (C) contained in the composite metal oxide may be greater than 0 and 10% by weight or less.
ここで、前記半導体層が10℃以上400℃以下で形成されてよい。
また、前記半導体層が10℃以上200℃以下で形成されてよい。 According to a second aspect of the present invention, there is provided a manufacturing method of any one of the above thin film transistors, wherein the semiconductor layer is formed at 10 ° C. or more and 600 ° C. or less.
Here, the semiconductor layer may be formed at 10 ° C. or more and 400 ° C. or less.
The semiconductor layer may be formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
ここで、前記追加の酸化物の含有量が0より大きく10重量%以下であってよい。
また、前記追加の酸化物は、酸化鉛、酸化パラジウム、酸化白金、酸化硫黄、酸化アンチモン、酸化ストロンチウム及び酸化イッテルビウムからなる群から選ばれた少なくとも一つの酸化物であってよい。 According to a third aspect of the present invention, in any one of the above thin film transistors, an additional oxide having an oxygen separation energy smaller than the oxygen separation energy of the first metal oxide is added to the oxygen separation energy. A thin film transistor is provided which is added to the semiconductor layer by an amount smaller than the amount of oxide added by 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
Here, the content of the additional oxide may be greater than 0 and equal to or less than 10% by weight.
The additional oxide may be at least one oxide selected from the group consisting of lead oxide, palladium oxide, platinum oxide, sulfur oxide, antimony oxide, strontium oxide, and ytterbium oxide.
また、前記半導体層が10℃以上500℃以下で形成されてよい。 According to a fourth aspect of the present invention, in any one of the above thin film transistor manufacturing methods, wherein the additional oxide is added to the semiconductor layer, wherein the semiconductor layer is formed at 10 ° C. or higher and 600 ° C. or lower. A manufacturing method is provided.
Further, the semiconductor layer may be formed at 10 ° C. or more and 500 ° C. or less.
更に、ソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、前記ソース電極と前記ドレイン電極との間のチャネルに対応させて設けられたゲート電極と、前記ゲート電極と前記半導体層との間に設けられた絶縁体層とを設け、前記絶縁体層が、前記半導体層側から、酸化シリコン層、前記酸化シリコン層に接して設けられた前記酸化シリコン層よりも誘電率の高い高誘電率第1層、および前記酸化シリコン層よりも誘電率の高い高誘電率第2層の積層を有する、薄膜トランジスタが与えられる。
ここで、前記何れの薄膜トランジスタにおいても、前記高誘電率第2層の誘電率が前記高誘電率第1層の誘電率より高いものであってよい。
また、前記高誘電率第1層が、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化チタン、酸化タンタル、酸化ニオビウム、希土類酸化物、酸化マグネシウム、酸化ストロンチウムからなる群から選択された一以上の金属酸化物、シリケート酸化物またはシリコンオキシナイトライドから形成されてよい。
また、前記高誘電率第2層が、誘電率が20以上の金属酸化物から形成されていてよい。
また、前記高誘電率第1層の厚さが、0.6nm以上であってよい。
また、前記酸化シリコン膜の厚さが、0.6nm以上であってよい。 According to a fifth aspect of the present invention, a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode are provided. Provided, and an insulator layer provided between the gate electrode and the semiconductor layer, and the insulator layer is formed on the silicon oxide layer and the silicon oxide layer from the gate electrode side. There is provided a thin film transistor having a stack of a high dielectric constant first layer having a higher dielectric constant than the silicon oxide layer provided in contact therewith and a high dielectric constant second layer having a higher dielectric constant than the silicon oxide layer.
A source electrode and a drain electrode; a semiconductor layer provided in contact with the source electrode and the drain electrode; a gate electrode provided corresponding to a channel between the source electrode and the drain electrode; An insulator layer provided between a gate electrode and the semiconductor layer is provided, and the insulator layer is provided in contact with the silicon oxide layer and the silicon oxide layer from the semiconductor layer side. There is provided a thin film transistor having a stack of a high dielectric constant first layer having a higher dielectric constant and a high dielectric constant second layer having a higher dielectric constant than the silicon oxide layer.
Here, in any of the thin film transistors, the dielectric constant of the second high dielectric constant layer may be higher than the dielectric constant of the first high dielectric constant layer.
The first high dielectric constant layer may be one or more metal oxides selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, niobium oxide, rare earth oxide, magnesium oxide, and strontium oxide. It may be formed from a material, silicate oxide or silicon oxynitride.
The high dielectric constant second layer may be formed of a metal oxide having a dielectric constant of 20 or more.
The high dielectric constant first layer may have a thickness of 0.6 nm or more.
The thickness of the silicon oxide film may be 0.6 nm or more.
また、前記半導体層が10℃以上200℃以下で形成されてよい。 According to a sixth aspect of the present invention, there is provided a manufacturing method of the thin film transistor according to the fifth aspect, wherein the semiconductor layer is formed at 10 ° C. or more and 400 ° C. or less.
The semiconductor layer may be formed at a temperature of 10 ° C. or higher and 200 ° C. or lower.
第1の実施形態の薄膜トランジスタは、ソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、前記ゲート電極と前記半導体層との間に設けられた絶縁体層とを設け、前記半導体層が、第1金属酸化物と、前記第1金属酸化物へ添加される酸素のかい離エネルギーが第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな酸化物から構成された複合金属酸化物である。 [Thin Film Transistor of First Embodiment]
The thin film transistor of the first embodiment is provided corresponding to a source electrode and a drain electrode, a semiconductor layer provided in contact with the source electrode and the drain electrode, and a channel between the source electrode and the drain electrode. A gate electrode; and an insulator layer provided between the gate electrode and the semiconductor layer, wherein the semiconductor layer includes a first metal oxide and oxygen added to the first metal oxide. This is a composite metal oxide composed of an oxide having a separation energy of 200 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
なお、第2金属酸化物の含有量は、第1金属酸化物の重量と第2金属酸化物の重量の合計に対する、第2金属酸化物の重量の比として計算される(第2金属酸化物の重量/(第1金属酸化物の重量+第2金属酸化物の重量)×100)。 Further, the content of the second metal oxide added to the first metal oxide in order to make the first metal oxide a semiconductor layer having a suitable oxygen deficiency amount is in the range of more than 0 and 50% by weight or less. Good. In particular, when the content of the second metal oxide added to the first metal oxide is in the range of more than 0 and 5% by weight or less, it can be produced at a low temperature of 200 ° C. or less.
The content of the second metal oxide is calculated as a ratio of the weight of the second metal oxide to the total weight of the first metal oxide and the second metal oxide (second metal oxide). Weight / (weight of first metal oxide + weight of second metal oxide) × 100).
半導体層105を構成する複合金属酸化物は第1金属酸化物に第2金属酸化物を添加したものに限定されるわけではない。具体的には第1金属酸化物に比べてかい離エネルギーが大きな酸化物を形成する元素を添加してもよい。具体的には、複合金属酸化物は、例えばボロン(B)および炭素(C)のうち少なくとも一つの元素の酸化物を添加したものであっても良い(すなわち、本願では「複合金属酸化物」を「金属酸化物に酸素のとのかい離エネルギーがより大きな元素を複合させた酸化物」という意味で使用していることに注意されたい)。これは、B-O結合の酸素かい離エネルギーが809kJ/molおよびC-O結合の酸素かい離エネルギーが1076.38±0.67kJ/molと大きいために、第1金属酸化物へ導入する酸素欠損量を容易に制御することができるからである。図2に示す本発明の別の実施形態の薄膜トランジスタ101’は図1の薄膜トランジスタ101と基本的には同一構造であるが、図1の半導体層105に対応する半導体層105’が第1の金属酸化物106にボロンおよび/または炭素の酸化物110を添加した複合金属酸化物である点が異なる。なお、図2中で図1中の要素と同じ参照番号が付されているものは対応する図1中の要素と同じであるため、それらについては説明を省略する。 [Thin Film Transistor of Second Embodiment]
The composite metal oxide constituting the
次に、本実施形態の薄膜トランジスタ101の製造方法について説明する。本実施形態の薄膜トランジスタの半導体層は、物理蒸着法(または物理気相成長法)を用いることにより形成することも可能である。 [Embodiment of Manufacturing Method of Thin Film Transistor]
Next, a method for manufacturing the
本発明の薄膜トランジスタにおいては、半導体層に、上で説明した第1金属酸化物及び酸素のかい離エネルギーが第1金属酸化物に比べて200kJ/mol以上大きな酸化物に加えて、酸素のかい離エネルギーが第1金属酸化物のそれよりも小さな追加の酸化物を添加することができる。この追加の酸化物の添加量は、酸素のかい離エネルギーが第1金属酸化物に比べて200kJ/mol以上大きな酸化物の添加量よりも少なくする。 [Thin Film Transistor of Third Embodiment]
In the thin film transistor of the present invention, the semiconductor layer has an oxygen release energy in addition to the oxide having an energy greater than or equal to 200 kJ / mol of the first metal oxide and oxygen described above compared to the first metal oxide. Additional oxide smaller than that of the first metal oxide can be added. The addition amount of the additional oxide is set to be smaller than the addition amount of the oxide whose oxygen separation energy is 200 kJ / mol or more larger than that of the first metal oxide.
ここで、第2金属酸化物の含有量は、第1金属酸化物の重量と第2金属酸化物の重量と第3金属酸化物の重量の合計に対する、第2金属酸化物の重量の比として計算され(第2金属酸化物の重量/(第1金属酸化物の重量+第2金属酸化物の重量+第3金属酸化物の重量)×100)、第3金属酸化物の含有量は、第1金属酸化物の重量と第2金属酸化物の重量と第3金属酸化物の重量の合計に対する、第3金属酸化物の重量の比として計算される(第3金属酸化物の重量/(第1金属酸化物の重量+第2金属酸化物の重量+第3金属酸化物の重量)×100)。 In the composite metal oxide constituting the semiconductor layer, the second metal oxide having a sufficiently high oxygen separation energy is added to the first metal oxide as described above, and the oxygen separation energy is further increased by the first metal oxide. The third metal oxide (additional oxide) is added, which is smaller than the product and the amount added is smaller than that of the second metal oxide. The inventors of the present application control the amount of oxygen vacancies with the second metal oxide and add the third metal oxide, so that the semiconductor layer becomes amorphous even in a high temperature range of 500 ° C. or 600 ° C. I found out. Specifically, the third metal oxide is composed of lead oxide having an oxygen release energy of 382.4 ± 3.3 kJ / mol, palladium oxide having 238.1 ± 12.6 kJ / mol, 418.6 ± 11.6 kJ / mol. mol platinum oxide, 517.90 ± 0.05 kJ / mol sulfur oxide, 434 ± 42 kJ / mol antimony oxide, 426.3 ± 6.3 kJ / mol strontium oxide, 213 ± 84 kJ / mol thallium oxide, 387 7 ± 10 kJ / mol ytterbium oxide and the like.
Here, the content of the second metal oxide is the ratio of the weight of the second metal oxide to the sum of the weight of the first metal oxide, the weight of the second metal oxide, and the weight of the third metal oxide. Calculated (weight of the second metal oxide / (weight of the first metal oxide + weight of the second metal oxide + weight of the third metal oxide) × 100), and the content of the third metal oxide is Calculated as the ratio of the weight of the third metal oxide to the sum of the weight of the first metal oxide, the weight of the second metal oxide, and the weight of the third metal oxide (weight of the third metal oxide / ( Weight of first metal oxide + weight of second metal oxide + weight of third metal oxide) × 100).
また、以上のような薄膜トランジスタの製造方法によれば、新規な複合金属酸化物を半導体層に用い、特性変化が抑制された薄膜トランジスタを容易に製造することができる。 In addition, according to the semiconductor device having the above-described configuration, the thin film transistor in which the change in characteristics is suppressed has high reliability.
Further, according to the method for manufacturing a thin film transistor as described above, a thin film transistor in which a change in characteristics is suppressed can be easily manufactured by using a novel composite metal oxide for a semiconductor layer.
以下に上記[第1の実施形態の薄膜トランジスタ][第2の実施形態の薄膜トランジスタ][薄膜トランジスタの製造方法の実施形態][第3の実施形態の薄膜トランジスタ]を実施例により説明するが、本発明はこれらの実施例に限定されるものではない。 [Example]
The above [thin film transistor of the first embodiment] [thin film transistor of the second embodiment] [embodiment of a method of manufacturing a thin film transistor] [thin film transistor of the third embodiment] will be described below by way of examples. It is not limited to these examples.
本実施例においては、図4に示す薄膜トランジスタを作製し、動作確認を行った。図に示す薄膜トランジスタは、図1に示した薄膜トランジスタ101と同様の構成になっており、図1の薄膜トランジスタ101が有するゲート電極103の代わりに、p型不純物を多量にドープしたSi層111を用いる構成となっている。 [First embodiment]
In this example, the thin film transistor shown in FIG. 4 was manufactured and the operation was confirmed. The thin film transistor shown in the figure has the same structure as that of the
DC power :50W
真空度 :0.08Pa
プロセスガス流量 :Ar 3sccm/O2 0.5sccm
(sccm:Standard Cubic Centimeter per Minute)
基板温度 :25℃。加熱なし (Sputtering conditions)
DC power: 50W
Degree of vacuum: 0.08 Pa
Process gas flow rate:
(Sccm: Standard Cubic Centimeter per Minute)
Substrate temperature: 25 ° C. Without heating
本発明の第3の実施形態に対して、図4に基本構造を示す薄膜トランジスタに対応する構造の薄膜トランジスタを作製し、動作確認を行った。図4の半導体層105に対応する半導体層105”(図3を参照のこと)は、スパッタリング装置を用い、ターゲット材として、In-Si-Yb-Oターゲットを用いて以下のスパッタ条件でスパッタリング法(DCスパッタリング)により成膜した。In-Si-Yb-Oターゲットは、10重量%Siおよび2%重量Yb添加In-O系のサンプル品を用いた。成膜した半導体層105の厚さは20nmであった。 [Second Embodiment]
With respect to the third embodiment of the present invention, a thin film transistor having a structure corresponding to the thin film transistor having the basic structure shown in FIG. A
DC power :100W
真空度 :0.2Pa
プロセスガス流量 :Ar 20sccm/O2 2sccm
(sccm:Standard Cubic Centimeter per Minute)
基板温度 :25℃。加熱なし (Sputtering conditions)
DC power: 100W
Degree of vacuum: 0.2 Pa
Process gas flow rate:
(Sccm: Standard Cubic Centimeter per Minute)
Substrate temperature: 25 ° C. Without heating
更に、本発明の第1の実施形態に対して、図4に基本構造を示す薄膜トランジスタを作製し、動作確認を行った。図4の半導体層105は、スパッタリング装置を用い、ターゲット材として、In-Si-Oターゲットを用いて以下のスパッタ条件でスパッタリング法(DCスパッタリング)により成膜した。In-Si-O ターゲットは、SiO2を11.5重量%添加In-O系のサンプル品を用いた。成膜した半導体層105の厚さは20nmであった。 [Third embodiment]
Furthermore, for the first embodiment of the present invention, a thin film transistor having the basic structure shown in FIG. The
DC power :200W
真空度 :0.2Pa
プロセスガス流量 :Ar 7sccm/O2 7sccm
(sccm:Standard Cubic Centimeter per Minute)
基板温度 :25℃。加熱なし (Sputtering conditions)
DC power: 200W
Degree of vacuum: 0.2 Pa
Process gas flow rate: Ar 7 sccm / O 2 7 sccm
(Sccm: Standard Cubic Centimeter per Minute)
Substrate temperature: 25 ° C. Without heating
本発明は、SiO2層とそれに接する他の誘電体層との間に形成されるダイポールによってフラットバンド電圧がシフトすることを利用して、しきい値電圧が調節された薄膜トランジスタを得るものである。すなわち、所望のしきい値電圧となるためのフラットバンド電圧シフトあるいはそれに近いシフトを与える誘電体材料を選択して上記の他の誘電体層に使用する上記の他の誘電体層に使用する。 [Thin Film Transistor of Fourth Embodiment]
The present invention provides a thin film transistor having a threshold voltage adjusted by utilizing the fact that a flat band voltage is shifted by a dipole formed between a SiO 2 layer and another dielectric layer adjacent thereto. . That is, a dielectric material that gives a flat band voltage shift for achieving a desired threshold voltage or a shift close thereto is selected and used for the other dielectric layer used for the other dielectric layer.
次に、第4の実施形態の薄膜トランジスタ201の製造方法について説明する。本実施形態の薄膜トランジスタの絶縁体層は、例えば物理蒸着法(または物理気相成長法)を用いることにより形成することが可能である。 [Method for Manufacturing Thin Film Transistor of Fourth Embodiment]
Next, a method for manufacturing the
本実施例においては、図17に示す薄膜トランジスタを作製し、動作確認を行った。図に示す薄膜トランジスタは、図13に示した薄膜トランジスタ201と同様の構成になっており、図13の薄膜トランジスタ201が有するゲート電極203の代わりに、p型不純物を多量にドープしたSi層211を用いる構成となっている。 [Example]
In this example, the thin film transistor shown in FIG. 17 was manufactured and the operation was confirmed. The thin film transistor shown in the figure has the same structure as that of the
101’ 薄膜トランジスタ
101” 薄膜トランジスタ
102 基板
103 ゲート電極
104 絶縁体層
105 半導体層
105’ 半導体層
105” 半導体層
106 第1金属酸化物
107 第2金属酸化物
108 ソース電極
109 ドレイン電極
110 ボロンおよび/または炭素の酸化物
111 p型不純物をドープしたSi基板
112 第3金属酸化物
201 薄膜トランジスタ
201’ 薄膜トランジスタ
202 基板
203 ゲート電極
204 酸化シリコン層
205 高誘電率第1層
206 高誘電率第2層
207 絶縁体層
208 半導体層
209 ソース電極
210 ドレイン電極
211 p型不純物をドープしたSi基板 101
Claims (28)
- ソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
前記ソース電極および前記ドレイン電極の間のチャネルに対応させて設けられたゲート電極と、
前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
前記半導体層が、酸素欠損が導入されることで電子キャリアを生成できる第1金属酸化物に、酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな酸化物を添加した複合金属酸化物である、
薄膜トランジスタ。 A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
The first metal oxide capable of generating electron carriers by introducing oxygen vacancies in the semiconductor layer is an oxide having an oxygen separation energy greater than that of the first metal oxide by 200 kJ / mol or more. Is a composite metal oxide to which is added,
Thin film transistor. - 前記酸化物の酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも255kJ/mol以上大きい、請求項1に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the oxygen separation energy of the oxide is 255 kJ / mol or more larger than the oxygen separation energy of the first metal oxide.
- 前記第1金属酸化物は、インジウム、ガリウム、亜鉛、および錫からなる群から選択された少なくとも一つを含む、請求項1に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the first metal oxide includes at least one selected from the group consisting of indium, gallium, zinc, and tin.
- 前記酸化物は、ジルコニウム(Zr)、およびプラセオジム(Pr)からなる群から選択された少なくとも一つの金属の酸化物からなる第2金属酸化物を含む、請求項1に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the oxide includes a second metal oxide made of an oxide of at least one metal selected from the group consisting of zirconium (Zr) and praseodymium (Pr).
- 前記酸化物は、シリコン(Si)、タンタル(Ta)、ランタン(La)、およびハフニウム(Hf)からなる群から選択された少なくとも一つの金属の酸化物からなる第2金属酸化物を含む、請求項2に記載の薄膜トランジスタ。 The oxide includes a second metal oxide made of an oxide of at least one metal selected from the group consisting of silicon (Si), tantalum (Ta), lanthanum (La), and hafnium (Hf). Item 3. The thin film transistor according to Item 2.
- 前記酸化物の含有量が0より大きく50重量%以下である、請求項1から5の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein the oxide content is greater than 0 and 50 wt% or less.
- 前記酸化物の含有量が0より大きく5重量%以下である、請求項1から5の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 5, wherein the oxide content is greater than 0 and 5 wt% or less.
- 前記半導体層が非晶質である、請求項1から7の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 7, wherein the semiconductor layer is amorphous.
- 前記半導体層の厚さが5nm以上かつ20nm以下の範囲である、請求項1から8の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 8, wherein a thickness of the semiconductor layer is in a range of 5 nm to 20 nm.
- 前記酸化物がボロン(B)および炭素(C)からなる群から選択された少なくとも一つの元素を含む、請求項1に記載の薄膜トランジスタ。 The thin film transistor according to claim 1, wherein the oxide contains at least one element selected from the group consisting of boron (B) and carbon (C).
- 前記複合金属酸化物に含まれるボロン(B)および炭素(C)の含有量が0より大きく10重量%以下である、請求項10に記載の薄膜トランジスタ。 The thin film transistor according to claim 10, wherein the content of boron (B) and carbon (C) contained in the composite metal oxide is greater than 0 and 10 wt% or less.
- 請求項1から11の何れかに記載の薄膜トランジスタの製造方法において、前記半導体層が10℃以上600℃以下で形成される、製造方法。 12. The method of manufacturing a thin film transistor according to claim 1, wherein the semiconductor layer is formed at 10 ° C. or higher and 600 ° C. or lower.
- 前記半導体層が10℃以上400℃以下で形成される、請求項12に記載の薄膜トランジスタの製造方法。 The method of manufacturing a thin film transistor according to claim 12, wherein the semiconductor layer is formed at a temperature of 10 ° C to 400 ° C.
- 前記半導体層が10℃以上200℃以下で形成される、請求項13に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 13, wherein the semiconductor layer is formed at 10 ° C. or more and 200 ° C. or less.
- 酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも小さい追加の酸化物を、前記酸素のかい離エネルギーが前記第1金属酸化物の酸素のかい離エネルギーよりも200kJ/mol以上大きな酸化物の添加量よりも少ない量だけ前記半導体層に添加した、請求項1から11の何れかに記載の薄膜トランジスタ。 An additional oxide whose oxygen separation energy is smaller than the oxygen separation energy of the first metal oxide is oxidized with an oxygen separation energy larger than the oxygen separation energy of the first metal oxide by 200 kJ / mol or more. The thin film transistor according to any one of claims 1 to 11, wherein the thin film transistor is added to the semiconductor layer by an amount smaller than an added amount of the product.
- 前記追加の酸化物の含有量が0より大きく10重量%以下である、請求項15に記載の薄膜トランジスタ。 The thin film transistor according to claim 15, wherein the content of the additional oxide is greater than 0 and equal to or less than 10% by weight.
- 前記追加の酸化物は、酸化鉛、酸化パラジウム、酸化白金、酸化硫黄、酸化アンチモン、酸化ストロンチウム及び酸化イッテルビウムからなる群から選ばれた少なくとも一つの酸化物である、請求項15または16の何れかに記載の薄膜トランジスタ。 The additional oxide is at least one oxide selected from the group consisting of lead oxide, palladium oxide, platinum oxide, sulfur oxide, antimony oxide, strontium oxide, and ytterbium oxide. A thin film transistor according to 1.
- 請求項15から17の何れかに記載の薄膜トランジスタの製造方法において、前記半導体層が10℃以上600℃以下で形成される、製造方法。 18. The method for manufacturing a thin film transistor according to claim 15, wherein the semiconductor layer is formed at 10 ° C. or higher and 600 ° C. or lower.
- 前記半導体層が10℃以上500℃以下で形成される、請求項18に記載の薄膜トランジスタの製造方法。 The method for manufacturing a thin film transistor according to claim 18, wherein the semiconductor layer is formed at 10 ° C. or more and 500 ° C. or less.
- ソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
前記ソース電極と前記ドレイン電極との間のチャネルに対応させて設けられたゲート電極と、
前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
前記絶縁体層が、前記ゲート電極側から、酸化シリコン層、前記酸化シリコン層に接して設けられた前記酸化シリコン層よりも誘電率の高い高誘電率第1層、および前記酸化シリコン層よりも誘電率の高い高誘電率第2層の積層を有する、
薄膜トランジスタ。 A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
The insulator layer includes, from the gate electrode side, a silicon oxide layer, a high dielectric constant first layer having a higher dielectric constant than the silicon oxide layer provided in contact with the silicon oxide layer, and the silicon oxide layer. Having a stack of a high dielectric constant second layer with a high dielectric constant;
Thin film transistor. - ソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極に接して設けられた半導体層と、
前記ソース電極と前記ドレイン電極との間のチャネルに対応させて設けられたゲート電極と、
前記ゲート電極と前記半導体層との間に設けられた絶縁体層と
を設け、
前記絶縁体層が、前記半導体層側から、酸化シリコン層、前記酸化シリコン層に接して設けられた前記酸化シリコン層よりも誘電率の高い高誘電率第1層、および前記酸化シリコン層よりも誘電率の高い高誘電率第2層の積層を有する、
薄膜トランジスタ。 A source electrode and a drain electrode;
A semiconductor layer provided in contact with the source electrode and the drain electrode;
A gate electrode provided corresponding to a channel between the source electrode and the drain electrode;
Providing an insulator layer provided between the gate electrode and the semiconductor layer;
The insulator layer includes, from the semiconductor layer side, a silicon oxide layer, a high dielectric constant first layer having a higher dielectric constant than the silicon oxide layer provided in contact with the silicon oxide layer, and the silicon oxide layer Having a stack of a high dielectric constant second layer with a high dielectric constant;
Thin film transistor. - 前記高誘電率第2層の誘電率が前記高誘電率第1層の誘電率より高い、請求項20または21に記載の薄膜トランジスタ。 The thin film transistor according to claim 20 or 21, wherein a dielectric constant of the second high dielectric constant second layer is higher than a dielectric constant of the first high dielectric constant layer.
- 前記高誘電率第1層が、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化チタン、酸化タンタル、酸化ニオビウム、希土類酸化物、酸化マグネシウム、酸化ストロンチウムからなる群から選択された一以上の金属酸化物、シリケート酸化物またはシリコンオキシナイトライドから形成されている、請求項20から22の何れかに記載の薄膜トランジスタ。 One or more metal oxides selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, niobium oxide, rare earth oxide, magnesium oxide, strontium oxide, 23. The thin film transistor according to claim 20, wherein the thin film transistor is formed from silicate oxide or silicon oxynitride.
- 前記高誘電率第2層が、誘電率が20以上の金属酸化物から形成されていることを特徴とする、請求項20から23の何れかに記載の薄膜トランジスタ。 24. The thin film transistor according to claim 20, wherein the second high dielectric constant second layer is made of a metal oxide having a dielectric constant of 20 or more.
- 前記高誘電率第1層の厚さが、0.6nm以上である、請求項20から24の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 20 to 24, wherein a thickness of the high dielectric constant first layer is 0.6 nm or more.
- 前記酸化シリコン膜の厚さが、0.6nm以上である、請求項20から25の何れかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 20 to 25, wherein the thickness of the silicon oxide film is 0.6 nm or more.
- 請求項20から26の何れかに記載の薄膜トランジスタの製造方法において、前記半導体層が10℃以上400℃以下で形成される、製造方法。 27. The method of manufacturing a thin film transistor according to claim 20, wherein the semiconductor layer is formed at 10 ° C. or higher and 400 ° C. or lower.
- 前記半導体層が10℃以上200℃以下で形成される、請求項27に記載の薄膜トランジスタの製造方法。 28. The method of manufacturing a thin film transistor according to claim 27, wherein the semiconductor layer is formed at 10 ° C. or higher and 200 ° C. or lower.
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Also Published As
Publication number | Publication date |
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US20160365455A1 (en) | 2016-12-15 |
US9741864B2 (en) | 2017-08-22 |
JP2017041646A (en) | 2017-02-23 |
JPWO2014181777A1 (en) | 2017-02-23 |
JP6120386B2 (en) | 2017-04-26 |
US20160118501A1 (en) | 2016-04-28 |
JP6296463B2 (en) | 2018-03-20 |
US9825180B2 (en) | 2017-11-21 |
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