WO2014134515A1

WO2014134515A1 - High-efficiency, low-cost silicon-zinc oxide heterojunction solar cells

Info

Publication number: WO2014134515A1
Application number: PCT/US2014/019561
Authority: WO
Inventors: Andrei T. IANCU; Neil Dasgupta; Friedrich B. Prinz; Hitoshi Iwadate
Original assignee: The Board Of Trustees Of The Leland Stanford Junior University; Honda Patents & Technologies North America, Llc
Priority date: 2013-02-28
Filing date: 2014-02-28
Publication date: 2014-09-04

Abstract

Zinc oxide (ZnO) -Si heterostructure solar cells with an intermediate layer between the ZnO and the silicon are provided. These cells can provide reduced cost combined with enhanced performance relative to conventional silicon solar cells. By starting with a silicon substrate that is appropriately doped and subsequently depositing low cost thin film layers on top of it, a number of expensive and time consuming fabrication steps can be avoided. Additionally, the Si/ZnO band alignment provides increased open circuit voltages. Finally, the direct band gap of the ZnO contributes significantly to the solar cell external quantum efficiency in the ultraviolet region of the solar spectrum, which provides increased short circuit currents. The final devices are robust and damage resistant and have shown no performance degradation over the course of a year even without thick protective layers.

Description

High-Efficiency, Low-Cost Silicon-Zinc Oxide Heteroj unction Solar Cells

BACKGROUND Silicon has been a commonly used material for solar cells for many years, despite its less-than-ideal

properties for this application. One of the shortcomings of silicon as a solar cell material is its poor performance in the ultraviolet (UV) part of the solar spectrum. Some attempts have been made to address this issue with a heteroj unction solar cell having silicon combined with another material that provides improved UV absorption.

However, reports of such heterostructure solar cells in the literature have thus far demonstrated such large losses that any gains made in UV absorption efficiency are more than wiped out by the generally poor performance of the devices. Thus, it would be an advance in the art to provide heteroj unction solar cells having improved

performance .

SUMMARY

We have found that high performance solar cells can be obtained in a ZnO-Si heterostructure with an intermediate layer between the ZnO and the silicon. These cells can offer an attractive combination of reduced cost combined with enhanced performance relative to conventional silicon solar cells. For example, the presence of zinc oxide enables more efficient absorption of ultraviolet radiation in the solar spectrum and the band alignment of the two materials also provides a boost to the open circuit voltage, which increases overall conversion efficiency, compared to a similar homojunction silicon cell.

Although silicon solar cells have been explored in great detail over the past 40 years, very little attention has been given to silicon heteroj unction solar cells. By starting with a silicon substrate that is appropriately doped and subsequently depositing very low cost thin film layers on top of it, a number of expensive and time

consuming fabrication steps can be avoided. Additionally, the semiconductor band alignment between the silicon and zinc oxide is generally conducive to improved voltage behavior from the final devices in the form of increased open circuit voltages. Finally, the direct band gap of the zinc oxide also contributes quite significantly to the overall external quantum efficiency of the final devices in the ultraviolet region of the solar spectrum which results in increased short circuit currents.

The most direct application of this work is in the efficient and low cost conversion of incident solar power to usable electric power. This can be done through either rooftop applications or large scale power generation arrays in the field. The final devices are very robust and damage resistant and have shown no performance degradation over the course of a year even without thick protective layers. The key advantages over conventional silicon solar cells are the significantly reduced cost and moderate performance boost .

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an embodiment of the invention. Fig. 2A is a reference band diagram for a ZnO/Si heteroj unction.

Fig. 2B schematically shows an exemplary band diagram relating to embodiments of the invention.

Figs. 3A-3H, 3J-3N and 3P show an exemplary

fabrication sequence.

Figs. 4A-C are transmission electron microscope (TEM) images relating to removal of the native oxide from

silicon . Fig. 5 is a TEM image of a fabricated device.

Figs. 6A-B show experimental results relating to a titanium oxide intermediate layer.

Figs. 7A-B show experimental results relating to a copper oxide intermediate layer. Figs. 8A-B show experimental results relating to a tin oxide intermediate layer.

DETAILED DESCRIPTION

Fig. 1 shows an embodiment of the invention. In this example, a first layer 102 including silicon and a second layer 104 including zinc oxide having opposite doping are present. A third layer 106 is sandwiched between the first and second layers. Because of the opposite doping, a p-n junction is created having a depletion region 108, and the third layer is disposed entirely within depletion region 108. The third layer has a bandgap energy E_g3 that is between the bandgap energies of the first and second layers. Thus, the bandgap energy of the third layer is between about 1.12 eV (approximate band gap of silicon) and about 3.3 eV (approximate bandgap of zinc oxide) . Third layer 106 preferably has a thickness between 0.1 nm and 5 nm, and is preferably amorphous as opposed to

crystalline .

The resulting structure is applicable as a solar cell. The silicon is the primary absorber material in that it is used to capture the solar spectrum ranging from the near infrared to the ultraviolet hence it is usually the lightly doped and much thicker material. The thickness of the silicon layer can vary over a wide range (e.g., from about 2 microns to several hundred microns) . Light trapping as described below can provide efficient absorption in

relatively thin silicon layers. The zinc oxide forms the other part of the heteroj unction and is generally heavily doped in order to maximize the open circuit voltage of the final device. The zinc oxide also provides additional optical absorption in the ultraviolet portion of the spectrum due to its direct bandgap there. Additionally, the zinc oxide layer is preferably much thinner than the silicon layer, on the order of 10s of nanometers, such that carrier recombination and series resistance in the ZnO is minimized. The devices are preferably built such that the light is incident on the zinc oxide layer prior to the silicon layer in order to take advantage of the efficient ultraviolet absorption of the zinc oxide.

In order to optimize the junction between the silicon and zinc oxide, an additional layer at the interface is present. This layer is usually extremely thin, on the order of nanometers, and is a material which serves to minimize the number of donor/acceptor states and other deleterious effects resulting from imperfections at the interface of the primary junction materials. Ideally, materials such as titanium oxide, in which the bandgap is larger than silicon but smaller than zinc oxide and in which the Ti-0 bond is stronger than the Si-0 bond, work best. Additionally, titanium oxide is also well-known from literature to easily accept injected electrons which would also contribute to its efficacy in this role. Materials which could be effectively used for this layer include but are not limited to: titanium dioxide, copper oxide, tin oxide, manganese oxide, etc.

The backside electrical contact of the device is to the silicon layer and can be any metal which provides an ohmic contact, but for purposes of cost and effectiveness aluminum is usually preferred. To improve the performance of the solar cell in the near infrared portion of the spectrum, the back contact can be augmented with a back surface field which will reflect minority carriers away from the metal contact and significantly reduce local recombination losses. This can be achieved in a variety of ways, including but not limited to: 1) annealing the aluminum back contact to diffuse some of the aluminum atoms into the silicon layer effectively doping it more heavily in the region close to the metal; 2) depositing a thin (5 to 50 nm) layer of a material whose band alignment is such that it reflects minority carriers but accepts majority carriers while maintaining a low defect density at the interface; or 3) using an ultra-thin (0.1 to 5 nm) layer of a material that acts as an insulator but allows tunneling of carriers through it to the metal contact.

The topside electrical contact to the zinc oxide is more complicated because it needs to both transmit the maximum amount of light to the layers below while

maintaining as low of an added series resistance to the circuit as possible. A preferred approach is to add a thin, on the order of 10 nanometers, aluminum doped zinc oxide layer on top of the p-n junction zinc oxide layer. The aluminum doping significantly increases the conductivity of the zinc oxide while maintaining its broadband optical transparency. Other candidates to serve this function include but are not limited to materials such as tin oxide, fluorine-doped tin oxide, indium tin oxide and so forth. Finally, a metallic grid can be deposited on top of the aluminum doped zinc oxide to further reduce the resistance of the topside contact. The material for the grid can be any material that forms a high quality ohmic contact with the aluminum doped zinc oxide, but aluminum or copper are usually preferred. The design of the metallic grid should be carefully considered to optimize the ultimate

performance of the device by trading off shadowing of the solar cell absorbing layers and the added series resistance to the device. As a final step, a thin aluminum oxide layer on the order of 10s of nanometers can be deposited over the entire surface area of the device to fully passivate all exposed surfaces and substantially decrease surface

recombination losses. The fabrication sequence of

Figs. 3A-3H, 3J-3N and 3P shows an exemplary processing sequence that provides solar cells as described in this paragraph .

Any type of silicon can be used in the p-n junction ranging from amorphous to polycrystalline to single

crystal. The performance of the device will vary based on the choice, but the general features of lower cost and moderate performance boost compared to equivalent material quality silicon-only solar cells will be maintained.

The quality of the zinc oxide is also significant in that it should be heavily doped but not damaged to the point where the recombination rate and crystallinity are heavily affected. The zinc oxide should be at least

polycrystalline and aligned such that it has columnar grains perpendicularly aligned to the silicon surface in order to optimize electrical transport properties. This was accomplished through atomic layer deposition at a very low cost, but can also be achieved through other deposition techniques such as solution processing, sputtering, evaporation and general chemical vapor deposition. Postprocessing of the zinc oxide to improve its characteristics include ultraviolet radiation treatment, annealing

treatments in various environments and exposure to strong electromagnetic waves in various thermal and chemical environments .

The doping scheme of the primary p-n junction in the device is also an important variable. Extensive experiments have shown that p type silicon and n+ type zinc oxide lead to a very low cost and high performance solar cell, but it is also possible to make a similar argument for an n type silicon and p+ type zinc oxide arrangement. Though there are additional difficulties in doping the zinc oxide such that it is p+ type, the end product will compare favorably based on theoretical performance calculations.

To further improve the performance and cost of the device, the front and/or back surfaces of the silicon can be textured to provide light trapping, effectively reducing the amount of silicon needed for absorption of the incident solar spectrum. The surface texture can have various patterns, including but not limited to: hexagonal-pyramid, inverted pyramid, cylinder, cone, ring, and other irregular shapes. This texture can be fabricated by wet chemical etching using solutions including but not limited to:

sodium hydroxide (NaOH) , tetramethylammonium (TMAH) , potassium hydroxide (KOH) , and a solution of nitric acid and hydrofluoric acid (HN03:HF) . This texture can also be fabricated by dry etching using plasmas including but not limited to: fluorine (F₂) , chlorine (Cl₂) , argon (Ar) , sulfur hexafluoride (SFe) and so on. Since ALD is the preferred fabrication process for all of the other relevant device layers and it produces highly conformal films, the added texturing will not affect the overall device

fabrication process.

Fig. 2A is a reference band diagram for a ZnO/Si heteroj unction . Fig. 2B schematically shows an exemplary band diagram relating to embodiments of the invention.

Here the conduction band and valence band of first layer 102 are referenced as 102c and 102v respectively.

Similarly, the conduction band and valence band of second layer 104 are referenced as 104c and 104v respectively and the conduction band and valence band of third layer 106 are referenced as 106c and 106v respectively.

Preferably, the third layer 106 has a band gap offset relative to the first layer 102 and to the second layer 104 such that the third layer does not provide an energy barrier to electrons and holes generated in the depletion region by illumination. Fig. 2B shows an example of such a band gap offset. Since holes travel to the left in the depletion region 108 of Fig. 2B, and electrons travel to the right in this depletion region, it is apparent that third layer 106 does not impede carrier flow by providing any relevant energy barriers. The third layer will not introduce any energy barriers for carrier flow if the band gap offsets are such that: 1) the conduction band of the third layer is between the conduction bands of the first and second layers; and 2) the valence band of the third layer is between the valence bands of the first and second layers, as shown on Fig. 2B.

Figs. 3A-H, 3J-N and 3P show an exemplary fabrication sequence. This exemplary fabrication sequence provides several significant advantages. These advantages include providing a well defined solar cell area, avoidance of edge shorting, clean room processing (which avoids

contamination) , and repeatability, which facilitates comparisons of different device designs.

The first step (Fig. 3A) is a diffusion clean of p-Si 302. Unexpectedly, this initial cleaning step has been found to be an important process step, where unusual measures were employed to obtain quality results. This step is discussed in greater detail below, in connection with Figs. 4A-C. This silicon will eventually become the first layer in the finished device. The step of Fig. 3B is deposition of T1O₂ 304 via atomic layer deposition (ALD) . This T1O₂ layer will eventually become the third layer in the final device. The step of Fig. 3C is a rapid thermal anneal (RTA) for 20 minutes at 500 °C in a nitrogen

atmosphere. Here the RTA is schematically indicated by arrows 306. We have found that temperatures of greater than 500 °C for this step degrade film properties, which is attributed to increasing crystallinity in the T1O₂ layer.

The step of Fig. 3D is deposition of ZnO 308 by ALD. This ZnO will eventually become the second layer of the finished device. The step of Fig. 3E is RTA for 10 minutes at

700 °C in a nitrogen atmosphere. Here the RTA is

schematically indicated by arrows 310. We have found that temperatures of greater than 700 °C for this step degrade film properties, which is attributed to loss of zinc from the ZnO layer. The step of Fig. 3F is deposition of aluminum doped ZnO (Al:ZnO) 312. This Al : ZnO layer

provides a transparent top layer that is electrically conductive. The step of Fig. 3H is O₂ plasma for 2 hours at 300 °C. Here the plasma exposure is schematically shown by plasma 314. The step of Fig. 3H is deposition of an aluminum top contact 316 by evaporation.

The step of Fig. 3J is deposition of an aluminum oxide passivation layer 318 by ALD. The step of Fig. 3K is formation of mesa structures by dry etching to define discrete devices. The step of Fig. 3L is deposition of another aluminum oxide passivation layer, to passivate surfaces exposed by the mesa etching of the step of

Fig. 3K. The aluminum oxide of the step of Fig. 3L is also referenced as 318 on the figures. The step of Fig. 3M is back side etching (e.g., a wet etch using hydrofluoric acid (HF) ) to expose the back side of the silicon. The step of Fig. 3N is backside deposition of aluminum 320 by

evaporation. The step of Fig. 3P is a final backside-only anneal: RTA for 4 minutes at 400 °C in a nitrogen

atmosphere to create a back surface field by doping the silicon closest to the back metal contact through a limited diffusion of aluminum into the silicon. Here the RTA is schematically indicated by arrows 322. In order to minimize cost, atomic layer deposition is preferably employed in the deposition of all thin film layers including the junction zinc oxide layer, the

interfacial oxide layer, the aluminum-doped zinc oxide layer and the protective aluminum oxide layer. Even further cost savings can be achieved through atmospheric atomic layer deposition of these thin films. It should be evident that the use of a single, very simple process for all thin film deposition is a major advantage of this device

architecture and fabrication process. It should also be noted that it is not required to deposit the thin film layers using atomic layer deposition since a number of other methods, such as solution processing, sputtering, evaporation, generic chemical vapor deposition, and so on, can be used. The additional aluminum electrode components can easily be deposited using known screen printing

techniques for further simplicity and cost savings, but again other methods, such as solution processing,

sputtering, evaporation, and so on, can be used as well. Finally, the silicon can also be deposited by any means available, with the most common being single crystal growth from melt, polycrystalline growth by casting and chemical vapor deposition, and amorphous growth by chemical vapor deposition.

In order to improve the material quality of the various layers in the device, additional post processing steps after deposition or co-processing steps during deposition may be necessary. These processing steps include but are not limited to: ultraviolet radiation treatment, annealing treatments in various environments using either flash lamp, rapid thermal, laser or traditional systems and exposure to strong electromagnetic fields in various thermal and chemical environments.

The preceding fabrication sequence is given by way of example, and numerous variations on it are also suitable for making embodiments of the invention. Such variations and process optimizations are within the skill of ordinary art workers, except in connection with the initial cleaning of step (a), which is described below.

We have found that removal of the native oxide from silicon prior to ALD deposition of the third layer is an unexpectedly important part of the processing sequence. Two approaches have been developed. The first is to employ a Si (111) wafer as a starting point, as opposed to the more commonly used Si (100) wafers. For Si (111), a standard organic contaminant cleaning step, (e.g., 10 minutes in 1:1:5 NH₄OH : H₂0₂ : H₂0 at 75 or 80 °C) , a standard ionic contaminant cleaning step, (e.g., immersion in 1:1:6

HC1:H₂0₂:H₂0 at 75 or 80 °C) , plus a simple HF dip to remove the native oxide and passivate the surface with Si-H bonds was enough because that particular surface is the close- packed one of silicon and it would re-oxidize much more slowly so that only a small fraction of a monolayer of oxide would regrow during the process of transferring the wafer from the solution cleaning system to the ALD reactor.

The second approach is special processing for Si (100) wafers. Such processing for Si (100) is important because Si (100) surfaces are incredibly reactive with a wide range of materials. For example, after removal of the native oxide, a Si (100) surface will reoxidize within seconds of just exposure to rinsing water. The optimized cleaning step for Si (100) involved first performing the standard organic and ionic contaminant cleans as described for Si (111) above then transferring the wafer into an inert atmosphere glove box, followed by a dip in HF which had been sparged with Ar to remove any trace oxygen. After a minute in the HF bath, the wafer was kept in the glove box and transferred into a solution of iodine and alcohol (methanol being the most effective) which was also sparged with Ar to remove any trace oxygen. The Si-H termination of the surface created by the HF dip was replaced by an Si-OCH₃ termination in this second bath.

After rinsing and drying in the inert atmosphere of the glove box, the wafer was transferred back out into the fab room and then into the ALD reactor. The OCH₃ termination could be removed in situ within the ALD reactor by either flowing hydrogen at a >300°C wafer temperature or by heating the wafer to >700°C in the ALD system vacuum. With this process, the OCH₃ surface termination served as a protective coating to prevent any exposure of the Si (100) surface to oxygen while the wafer was transferred from the glove box to the ALD reactor. This enhanced cleaning process could also be applied to a Si (111) wafer.

silicon. Here Fig. 4A is a TEM image of a finished device. Fig. 4B is a corresponding energy filtered TEM (EFTEM) image at 456 eV, showing a well-defined Ti image confined to the third layer. Fig. 4C is a corresponding EFTEM image at 1020 eV, showing zinc in the second layer. The ability to get such properly defined layer structures via ALD on silicon was found to depend significantly on the surface preparation processes as described above. Fig. 5 is a TEM image of a fabricated device. Here it is apparent that the interfaces between Si 502 and T1O₂ 504 and between T1O₂ 504 and ZnO 506 have very high quality.

As indicated above, the third layer sandwiched between the Si and ZnO layers has a bandgap greater than that of silicon, and less than that of ZnO. Several materials for the third layer have been investigated experimentally, and have provided promising results. Figs. 6A-B show

experimental results relating to a titanium oxide

intermediate layer. Here Fig. 6A is a spectral external quantum efficiency (EQE) plot, and Fig. 6B shows the I-V curves under dark and illuminated situations (Air Mass (AM) 1.5 solar spectrum illumination) . Figs. 7A-B show

experimental results relating to a copper oxide

intermediate layer. Here Fig. 7A is a spectral EQE plot, and Fig. 7B shows the I-V curves under dark and illuminated situations. For the copper oxide case, it is not known what the stoichiometry of the copper oxide was, and the

stoichiometry is not believed to be critical, so this copper oxide can be regarded as CuO_x, or as a mixture of CU₂O and CuO. Figs. 8A-B show experimental results relating to a tin oxide intermediate layer. Here Fig. 8A is a spectral EQE plot, and Fig. 8B shows the I-V curves under dark and illuminated situations. On the EQE plots, the EQE of a reference commercial silicon solar cell is shown. In all cases, it is apparent that the EQE is substantially increased in the UV part of the spectrum (e.g., between 250 nm and 375 nm) .

Superior solar cell performance is demonstrated in these results. For example, with AM 1.5 illumination, the open circuit voltage (V_oc) is greater than 0.3 V, and the short circuit current density (J_sc) is greater than

15 mA/cm². The best results to date have been seen with a Ti0₂ intermediate layer (efficiency of 16.9%, V_oc = 0.59 V, J_sc ~ 27 mA/cm², and fill factor of 71.5%) . These results were obtained in research devices, so with well known solar cell optimizations such as improved coatings, cleaner processing, solar-grade silicon wafer usage, etc., it should be possible for fully optimized Si/ZnO solar cells with an intermediate layer to reach the following

performance level: efficiency 20-28%, V_oc > 0.68 V,

J_sc > 38 mA/cm², and fill factor 75-86%. These estimates are based on a heterostructure solar cell model between p-Si and n-ZnO using measured band offsets and assuming an ideal material interface.

Claims

1. A solar cell comprising: a first layer comprising silicon; a second layer comprising zinc oxide; a third layer sandwiched between the first and second layers ; wherein the first and second layers have opposite doping, thereby creating a p-n junction having a depletion region; wherein the third layer is disposed entirely within the depletion region; wherein the first layer has a first bandgap energy E_gi, wherein the second layer has a second bandgap energy E_g2, wherein the third layer has a third bandgap energy E_g3, and wherein E_gl < E_g3 < E_g2.

2. The solar cell of claim 1, wherein an open circuit voltage of the solar cell is greater than 0.3 V with AM 1.5 illumination.

3. The solar cell of claim 1, wherein a short circuit current density of the solar cell is greater than 15 mA/cm² with AM 1.5 illumination.

4. The solar cell of claim 1, wherein the third layer has a band gap offset relative to the first layer and to the second layer such that the third layer does not provide an energy barrier to electrons and holes generated in the depletion region by illumination.

5. The solar cell of claim 1, wherein the third layer comprises Ti0₂.

6. The solar cell of claim 1, wherein the third layer comprises SnC>2.

7. The solar cell of claim 1, wherein the third layer comprises CU₂O, CuO, or a mixture thereof.

8. The solar cell of claim 1, wherein the third layer has thickness between 0.1 nm and 5 nm.

9. The solar cell of claim 1, wherein the third layer is amorphous .

10. A method of making a solar cell, the method comprising providing a first layer comprising silicon; providing a second layer comprising zinc oxide; providing a third layer sandwiched between the first and second layers;

wherein the first and second layers have opposite doping, thereby creating a p-n junction having a depletion region ; wherein the third layer is disposed entirely within the depletion region; wherein the first layer has a first bandgap energy E_gi, wherein the second layer has a second bandgap energy E_g2, wherein the third layer has a third bandgap energy E_g3, and wherein E_gl < E_g3 < E_g2.

11. The method of claim 10, wherein deposition of the third layer on the first layer is performed with atomic layer deposition .

12. The method of claim 11, wherein deposition of the second layer on the third layer is performed with atomic layer deposition.

13. The method of claim 10, wherein native silicon oxide is completely removed from the first layer prior to deposition of the third layer.

14. The method of claim 13, wherein the first layer is kept in a non-oxidizing environment for all times between removal of the native silicon oxide and deposition of the third layer.

15. The method of claim 10, wherein the first layer is part of a silicon wafer having a (111) top surface.