WO2014131312A1

WO2014131312A1 - Frame synchronization method and system, transmitting terminal, receiving terminal and computer storage medium

Info

Publication number: WO2014131312A1
Application number: PCT/CN2013/091109
Authority: WO
Inventors: 陈煜聪
Original assignee: 中兴通讯股份有限公司
Priority date: 2013-03-01
Filing date: 2013-12-31
Publication date: 2014-09-04
Also published as: CN104023386A; CN104023386B

Abstract

Provided are a frame synchronization method and system, transmitting terminal, receiving terminal and computer storage medium, the frame synchronization method comprising: conducting zero-related area extension processing and differential processing on a synchronization sequence; utilizing the sequence obtained via the differential processing to mark the frame head of data to be synchronized; and transmitting the data to be synchronized having a marked frame head. The frame synchronization method comprises: receiving data to be synchronized; conducting differential processing on the data to be synchronized to obtain differential data; conducting correlation calculation on the differential data and a local sequence to obtain correlation value data; searching for the peak value in the correlation value data; determining whether the number of the peak value reaches a first preset value; and if yes, then conducting a synchronization operation.

Description

Frame synchronization method and system, transmitting end, receiving end and computing

The present invention relates to the field of data synchronization in communication technologies, and in particular, to a frame synchronization method and system, a transmitting end, a receiving end, and a computer storage medium. Background technique

Digital microwave communication is a point-to-point line-of-sight communication system. It is mainly used in the second generation mobile communication technology/third generation mobile communication technology (2G/3G, Second Generation/Third Generation) mobile service bearer network for voice and data. The transmission of the service; the frame synchronization technology occupies a very important position in the digital microwave communication. The signal received by the receiving end undergoes down-conversion, analog device interference cancellation, digital clock recovery processing and enters the frame synchronization phase. The frame synchronization phase is mainly used for the frame synchronization phase. The frame header flag is completed to provide synchronization information such as indication information of the frame header, system frequency offset value estimation and frequency offset compensation, and can also indicate the synchronization/out-of-synchronization state of the system, and reflect the advantages and disadvantages of the channel conditions.

In the existing synchronization technology, the receiving end determines whether to enter the synchronization state by periodically detecting the code group or the symbol, and determines whether the synchronization is performed by comparing the number of occurrences of the symbol or the code group with a set threshold, thereby marking the frame header; This kind of frame synchronization scheme has poor anti-noise and frequency offset capability. The peak detection process is prone to false alarm and missed detection probability due to false peak and low signal-to-noise ratio, which affects the system construction speed and stability after chain construction. Summary of the invention

To solve the above technical problem, an embodiment of the present invention provides a frame synchronization method and system, a transmitting end, a receiving end, and a computer storage medium.

In the embodiment of the present invention, the frame synchronization method includes: performing zero-correlation region expansion processing on the synchronization sequence; performing differential processing on the sequence obtained by the zero-correlation region expansion processing; using the difference The processed sequence marks the frame header of the data to be synchronized; the data to be synchronized after the frame header is sent.

In the embodiment of the present invention, the frame synchronization method includes: receiving data to be synchronized; performing differential processing on the synchronization data to obtain differential data; performing correlation operation on the difference data and the local sequence to obtain correlation value data; searching for correlation value data Peak value; determine whether the number of peaks reaches the first preset value; if yes, perform a synchronization operation.

In the embodiment of the present invention, the frame synchronization method includes: the transmitting end performs zero-correlation region expansion processing on the synchronization sequence; performs differential processing on the sequence obtained by the zero-related region expansion processing; and uses the difference processing to obtain a sequence of the synchronization data to be processed. The header is marked; the data to be synchronized marked by the frame header is sent to the receiving end; the receiving end receives the data to be synchronized; and differentially processes the data to be synchronized to obtain differential data; Performing a correlation operation with the local sequence to obtain correlation value data; searching for a peak value in the correlation value data; determining whether the peak number reaches the first preset value; if yes, performing a synchronization operation.

In the embodiment of the present invention, the sending end includes: a first processing module, a second processing module, and a sending module; wherein, the first processing module is configured to perform zero-correlation region expansion processing on the synchronization sequence, and the processed The sequence is subjected to differential processing; the second processing module is configured to mark the frame header of the synchronization data by using the sequence obtained by the differential processing; and the sending module is configured to send the data to be synchronized after the frame header is sent out.

In the embodiment of the present invention, the receiving end includes: a receiving module, a third processing module, a fourth processing module, a searching module, a determining module, and a synchronization module; wherein, the receiving module is configured to receive data to be synchronized; The module is configured to perform differential processing on the data to be synchronized received by the receiving module to obtain differential data. The fourth processing module is configured to perform correlation operation between the differential data obtained by the third processing module and the local sequence to obtain related value data; And configured to search for a peak value in the correlation value data obtained by the fourth processing module; the determining module is configured to determine whether the number of peaks searched by the search module reaches the first preset value; the synchronization module is configured to be judged When the judgment result of the disconnection module is that the number of peaks reaches the first preset value, the synchronization operation is performed.

In the embodiment of the present invention, the frame synchronization system includes any of the foregoing sending end and receiving end. In an embodiment of the invention, the computer storage medium stores a computer program for executing the frame synchronization method described above.

The technical solution of the embodiment of the present invention provides a frame synchronization technology, where the transmitting end performs zero-correlation region expansion and differential processing on the synchronization sequence, thereby reducing side lobes at both ends of the correlation value peak, and reducing the peak value of the correlation value when the receiving end searches for the correlation value. The false alarm and the probability of missed detection; the receiving end differentially processes the received data, restores the impact of the differential processing on the data by the transmitting end, and performs differential processing on both the transmitting end and the receiving end, so that the system enters During the synchronization phase, the calculation of the system frequency offset value and the system frequency offset compensation can be performed quickly, and the flexibility of the frequency offset correction of the system is improved; preferably, the receiving end performs the validity detection of the peak value, and according to the effective peak value The number of synchronization states is judged to avoid the influence of invalid peaks on the synchronization judgment. DRAWINGS

1 is a schematic flowchart of a frame synchronization method according to Embodiment 1 of the present invention;

2 is a schematic flowchart of a frame synchronization method according to Embodiment 2 of the present invention;

3 is a schematic flowchart of a frame synchronization method according to Embodiment 3 of the present invention;

4 is a schematic flow chart of a peak search method according to an embodiment of the present invention;

FIG. 5 is a first schematic diagram of a variation curve of a correlation value modulus according to an embodiment of the present invention; FIG.

6 is a second schematic diagram of a variation curve of a correlation value of a value according to an embodiment of the present invention;

7 is a schematic structural diagram of a frame synchronization system according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a structure of a transmitting end according to an embodiment of the present invention; FIG.

9 is a schematic structural diagram of a receiving end according to Embodiment 1 of the present invention;

FIG. 10 is a schematic structural diagram of a receiving end according to Embodiment 2 of the present invention. detailed description

The embodiments of the present invention are described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a frame synchronization method according to Embodiment 1 of the present invention. The frame synchronization method in this example is applied to a transmitting end. As shown in FIG. 1, in the embodiment, the frame synchronization method includes the following steps:

S101: Perform zero-correlation region expansion processing on the synchronization sequence.

Preferably, the frame synchronization method in the embodiment shown in FIG. 1 before step S101 further includes: selecting a synchronization sequence, where the synchronization sequence is a constant envelope zero autocorrelation series.

Zero-correlation region expansion of the synchronization sequence can achieve the effect of reducing the side lobes on both sides of the peak value in the correlation value obtained by the correlation operation at the receiving end, and there are many ways to achieve zero-correlation region expansion. In a preferred embodiment of the present invention, the selection is performed. The sequence of Constant Amplitude Zero Auto Correlation (CAZAC) is used as a synchronization sequence, and the synchronization sequence is subjected to zero correlation region expansion processing.

S102: Perform differential processing on the sequence obtained by the zero correlation region expansion processing.

After differential processing is performed on the sequence obtained by the zero-correlation region expansion processing, after the receiving end enters the synchronization state, the system frequency offset value can be quickly calculated according to the peak value when entering the synchronization state, and the frequency offset compensation is performed according to the system frequency offset value.

Preferably, the frame synchronization method in the embodiment shown in FIG. 1 before the step S102 further includes: acquiring a magnitude of the difference order M value in the difference processing; specifically, estimating the value of the M value according to the frequency offset of the system. When the frequency offset of the system is large, a smaller M value can be taken. When the frequency offset of the system is small, a larger M value can be taken. The commonly used M value range is (2, 64); The value of the M value may be determined according to the size of the system frequency offset value in the experience. If an M value can make the receiving end and the transmitting end quickly establish a link, the M value is considered to be appropriate, and The M value is notified to the receiving end and the transmitting end. If an M value makes it difficult for the receiving end and the transmitting end to establish a link, the M value is considered to be inappropriate, and other values are tried until the appropriate M value is determined, and the receiving is notified. End and sender.

By adjusting the difference order M, the frequency offset correction flexibility of the system is improved; when the M value is between (2, 64), the relative frequency offset range that can be corrected is between plus and minus 0.5 0.008, if the system operating frequency For f, the adjustable absolute value of the frequency offset ranges from 0.5 X f-0.008 X f.

S103: The sequence obtained by the differential processing marks the frame header of the data to be synchronized.

The frame synchronization technology uses the group synchronization code inserted in the signal to realize the search and labeling of the frame header. The group synchronization code has two methods of centralized insertion and distributed insertion, and the corresponding insertion signals are respectively called code groups and symbols, according to different requirements. In the microwave communication system, the two methods are used, and one type is used independently or a mixture of the two is used. In this embodiment, the sequence obtained by the differential processing is used as the group synchronization code, and the sending end is obtained by using the step S102. The sequence marks the frame header.

S104: The data to be synchronized after the frame header is sent.

After the frame header of the synchronization data is marked, the sender can send the data to be synchronized after the frame header is marked to the receiver.

2 is a schematic flowchart of a frame synchronization method according to Embodiment 2 of the present invention. The frame synchronization method in this example is applied to a receiving end. As shown in FIG. 2, in the embodiment, the frame synchronization method includes the following steps:

S201: Receive data to be synchronized.

S202: Perform differential processing on the synchronous data to obtain differential data.

After receiving the data to be synchronized, the receiving end performs down-conversion processing, analog device interference cancellation processing, and digital clock recovery processing. Since these processings are not the core points of the embodiments of the present invention, the process will not be described again; The data may be the data to be synchronized after the digital clock recovery processing, or may be the sampled data, and the sampled data refers to the data obtained by performing the optimal sampling point sampling on the data to be synchronized after the digital clock recovery processing. In this case, step S202 of The object is the sampled data;

In order to restore the influence of the differential processing performed by the transmitting end on the synchronization sequence, the receiving end performs differential processing on the synchronous data or the sampled data, and the differential order of the differential processing should be consistent with the differential order M value of the transmitting end, and the receiving end obtains the M value. In a preferred embodiment of the present invention, a field for informing the receiving end of the M value used by the data transmitting end is added to the header of the data to be synchronized; the receiving end extracts the difference before performing the differential processing. This field obtains the M value and performs differential processing according to the obtained M value. Specifically, it may be: M data to be synchronized for differential operation, that is, the first and the M+1th data are differentiated, the second and the M+2 data is differentiated, and so on.

S203: Correlate the difference data with the local sequence to obtain correlation value data. Correlating the selected local sequence with the differential data; since the transmitting end and the receiving end in the embodiment of the present invention can support multiple sets of related code group sequence configurations, the present application establishes a sequence of related code groups used by the transmitting end at the receiving end. Corresponding relationship between local sequences, the receiving end selects a corresponding local sequence according to the sequence of related code groups used by the data to be synchronized received by each branch, and performs correlation operation between the selected local sequence and the differential data, which can effectively reduce the polarization mode. The interference between multiple signals improves the anti-interference ability of the system.

The correlation operation may be a conjugate multiplication operation or the like. When the correlation operation is a conjugate multiplication operation, step S203 may specifically be: sending the differential data output obtained in S202 to the delay register, and selecting the selected local sequence and receiving The differential data is correlated to obtain correlation data. Because the local sequence is known and the value is fixed, the entire delay register can be composed mainly of the delay circuit and the addition and subtraction circuit, and the structure is simple and the processing delay is small.

S204: Search for the peak value in the correlation value data.

The purpose of searching for peaks in the correlation value data can be achieved in a plurality of ways. Since the correlation value data obtained by the processing in step S203 is a complex number, in the preferred embodiment of the present invention, it may be a root. The peak search is performed according to the modulus value of the correlation value, and the specific search process will be described in detail with reference to Figs.

S205: Determine whether the number of peaks reaches the first preset value; if yes, execute step S206, otherwise, return to step S204.

In a preferred embodiment of the present invention, the specific implementation of the step may be: setting a synchronization determination counter. When S204 searches for a peak, the value of the synchronization determination counter is increased by "1", when the synchronization determination counter is When the value n reaches the first preset value N1, the representative system enters the synchronization state, and then step S206 is performed.

S206: Perform a synchronization operation.

When the judgment result of S205 is that the value n of the synchronization determination counter reaches the first preset value N1, a synchronization operation such as a frame header flag, a system frequency offset value calculation, and a frequency offset compensation are performed.

Preferably, in other embodiments, the frame synchronization method in the embodiment shown in FIG. 2 further includes: a step of detecting whether each peak is valid after step S204; and step S205 is specifically determining whether the number of valid peaks reaches the first level. Default value; specifically:

Through the implementation of step S204, a plurality of peaks can be searched. After searching for a peak, the step of detecting whether the peak is valid is obtained. The step may specifically be: determining whether the interval between the peak to be detected and the next adjacent peak is It is equal to the frame length of the data to be synchronized; if yes, the peak to be detected is valid, and the peak is recorded as the effective peak; otherwise, the peak to be detected is invalid, and the peak is recorded as an invalid peak;

After the first peak is searched, the peak interval count is turned on. If the next peak arrives, the interval between the two peaks is equal to the frame length of the data to be synchronized, and the peak is judged to be valid, otherwise the peak is invalid; if the second If the interval between the peak and the first peak does not satisfy the frame length, the peak interval is restarted with the second peak as the starting point, and the subsequent peak is determined, and so on. When the channel condition is bad, the start The peak position may need to be moved back multiple times. After the step S206, when the system performs synchronization, the frequency offset compensation needs to be performed at this time, and to perform the frequency offset compensation, the system frequency offset value must be calculated, so the frame synchronization method in the embodiment shown in FIG. 2 is in step S206. Afterwards, the method further includes: obtaining a system frequency offset value, and performing frequency offset compensation according to the system frequency offset value; and obtaining a system frequency offset value in multiple manners. In a preferred embodiment of the present invention, acquiring a system frequency offset value The method is obtained according to the peak value, and can be calculated according to any one of the N1 effective peaks before the system is synchronized, the average value, or the N1th effective peak value; for convenience of explanation, the differential order of the differential processing is set. The number is M. When the receiving end samples the data after digital clock recovery of the data information sent by the transmitting end, the optimal sampling point interval used is ⁷ ^. The system frequency offset value is calculated according to the N1 effective peak value, then the calculation method is :

First, the inverse offset is obtained according to the correlation value of the N1 effective peaks including the I/Q two paths, and the frequency offset angle ^{w is} obtained.

Secondly, the system frequency offset value is calculated according to the system frequency offset value ^ 4 = w / (2; r _X M >< 7). After the step S206, after the system performs the data synchronization operation, it is necessary to check whether the system is out of step. Therefore, after the step S206, the frame synchronization method in the embodiment shown in FIG. 2 further includes: a step of detecting whether the system is out of synchronization; In the preferred embodiment of the present invention, the monitoring method may be to determine whether the number of invalid peaks reaches a second preset value to detect whether the system is out of step, and optimally, The number of consecutive invalid peaks is detected to detect whether the system is out of step. When the number of consecutively invalid peaks reaches the second preset value N2, the system is out of synchronization, and the out-of-step operation is performed; Sex, can be set to N2 > N1, which also improves the stability of the system after building the chain while taking into account the system construction speed.

3 is a schematic flowchart of a frame synchronization method according to Embodiment 3 of the present invention. The frame synchronization method in this example is applied to a frame synchronization system, where the frame synchronization system includes a receiving end and a transmitting end. As shown in FIG. 3, in this embodiment, The frame synchronization method includes the following steps:

S401: The transmitting end performs zero-correlation area expansion processing on the synchronization sequence.

S402: The transmitting end performs differential processing on the sequence obtained by the zero-related area expansion processing. S403: The sender uses the sequence obtained by the differential processing to mark the frame header of the data to be synchronized. S404: The sending end sends the data to be synchronized after the frame header is marked to the receiving end.

S405: The receiving end receives the data to be synchronized.

S406: The receiving end performs differential processing on the synchronous data to obtain differential data.

S407: The receiving end performs correlation operation on the differential data and the local sequence to obtain related value data.

S408: The receiving end searches for a peak in the related value data.

S409: The receiving end determines whether the number of peaks reaches the first preset value; if yes, step S410 is performed, otherwise, returns to step S208.

S410: The receiving end performs a synchronization operation.

It should be understood by those skilled in the art that steps S401 to S404 in the foregoing solution may be understood by referring to the related description of the frame synchronization method performed by the transmitting end shown in FIG. 1; Steps S405 to S410 may refer to FIG. It is understood by the relevant description of the frame synchronization method performed by the receiving end.

In order to further reduce the peak miss detection and the false alarm probability, the embodiment of the present invention further provides a technique for searching for a peak by multiple window opening, and FIG. 4 is a schematic flowchart of a peak searching method according to an embodiment of the present invention, and FIG. FIG. 6 is a schematic diagram 2 showing a variation curve of a correlation value modulus according to an embodiment of the present invention; FIG. 4 is a description of FIG. 4, FIG. 5 and FIG. The peak search method of the embodiment of the present invention includes the following steps:

S301: The detection center window value is greater than a first threshold Thl.

Referring to FIG. 5, the value of the correlation value of the center window value is Yk. In this case, step S301 is to detect the size of Yk and the first threshold Th1 in FIG. 5; if Yk > Thl, step S302 is performed, if Yk < Thl, the center window value is not the peak value, and the judgment flow of the next center window value is entered.

S302: Detect whether a difference between the center window value and its adjacent window value is greater than a second threshold Th2. Referring to FIG. 5, the setting step S302 is to detect whether the difference between the correlation value modulus of the central window value and the correlation value modulus of each of the K window values on the adjacent sides is greater than the second threshold Th2, and K on both sides. In this case, it is necessary to compare the difference between the correlation value of the central window value Yk and the 2K window values and the magnitude of the second threshold Th2. In this case, step S302 is to detect (Yk-Yl) in FIG. 5,

(Yk-Yk-1), (Yk-Yk+1), (Yk-Yk+2) (Yk-Y2k) and the magnitude of the second threshold Th2; if (Yk-Yl), (Yk -Y2 ) ( Yk-Yk-1 ),

(Yk-Yk+1), (Yk-Yk+2) (Yk-Y2k) are all greater than or equal to Th2, then step S303 is performed, and if not, the center window value is not a peak value, and the judgment of entering the next central window value is performed. Process.

S303: The maximum correlation value of the central window value is taken as the peak value.

When the system synchronization status is good, the center window value generally has only one correlation value. In this case, the correlation value is used as the peak value; when the system synchronization state is poor, it will cause multiple correlation values in one central window. As shown in FIG. 5, at this time, 2c correlation values of the central window are compared, and the correlation value corresponding to the largest modulus value among the correlation value moduli values is selected as the peak value, that is, Yk- in FIG. 5 is detected. c, Yk-c+1 Yk+cl, Yk+c, the correlation value corresponding to the maximum modulus value is taken as the peak value, in a preferred embodiment of the present invention, c < condition.

FIG. 6 is a second schematic diagram of a variation curve of a correlation value of a value according to an embodiment of the present invention. Specifically, the method in the embodiment of the present invention uses a zero-correlation region expansion process and a differentially processed sequence on a CAZAC sequence to perform frame header identification. a software simulation diagram of the correlation value modulus obtained by sampling, differential processing and related processing of the synchronous data at the receiving end; and the correlation value model obtained by sampling the data after the frame header marking using the conventional conventional synchronization sequence The change curve of the value, that is, the change graph shown in Fig. 5, can be visually seen. The side lobes on both sides of the correlation value of the center window value shown in Fig. 6 are more than the side values of the correlation values in Fig. 5. The side lobes are small and the center window value is prominent. Further explanation will be made in conjunction with Figures 4 and 6:

It can be clearly seen from Fig. 6 that the center window value is Yk, and at this time, step S301 in Fig. 4 Is to detect the magnitude of Yk and the first threshold Th1 in FIG. 6; only when Yk > Thl, step S302 is performed;

It can be clearly seen from Fig. 6 that the two sides of the center window are horizontal areas, in which there is no peak; the window values of the K windows on both sides of the center window are not much different, and the difference from Yk The value is stable. Therefore, referring to the above embodiment, step S302 in FIG. 4 is set to detect whether the difference between the center window value and the K window values on the adjacent sides thereof is greater than the second threshold Th2. In this case, step S302 is detection. The magnitude of ( Yk - Yl ) ( Yk - Y2k ) and the second threshold Th2 in Fig. 6; only if (Yk - Yl ) (Yk - Y2k ) is > 13⁄42, step S303 is performed. The correlation value of the center window of the correlation value detected by the receiving end is prominent; at this time, the comparison speed of step S303 in FIG. 4 is fast, because only less than 2c, usually 1 to 3, are required at this time. A comparison of the relative value of the values allows you to quickly determine the peak value of the center window.

FIG. 7 is a schematic structural diagram of a frame synchronization system according to an embodiment of the present invention; as shown in FIG. 7, the frame synchronization system 6 provided by the embodiment of the present invention includes: a transmitting end 61 and a receiving end 62, wherein the transmitting end 61 is configured to Performing zero-correlation region expansion processing on the synchronization sequence, and performing differential processing on the processed sequence, marking the frame header of the synchronization data by using the sequence obtained by the differential processing, and transmitting the data to be synchronized after the frame header is marked to the receiving end 62 ;

The receiving end 62 is configured to receive the data to be synchronized sent by the transmitting end 61; perform differential processing on the synchronous data to obtain differential data; perform correlation operation on the differential data and the local sequence to obtain correlation value data; and search for peak values in the correlation value data; Determine whether the number of peaks reaches the first preset value; if yes, perform a synchronization operation.

In a practical application, the transmitting end 61 and the receiving end 62 in the frame synchronization system can be implemented by a terminal such as a computer, a smart phone, a tablet computer, or a server.

8 is a schematic structural diagram of a transmitting end according to an embodiment of the present invention; as shown in FIG. 8, in the embodiment, the transmitting end 61 in the embodiment shown in FIG. 7 includes: a first processing module 611, a second a processing module 612 and a sending module 613; wherein

The first processing module 611 is configured to perform zero-correlation region expansion processing on the synchronization sequence of the data to be sent, and perform differential processing on the processed sequence;

The second processing module 612 is configured to perform label processing on the frame header of the data to be synchronized by using the sequence obtained by the differential processing of the first processing module 611;

The sending module 613 is configured to send the data to be synchronized that carries the frame header marked by the second processing module 612, that is, the data to be synchronized after the frame header is sent out.

In other embodiments, the transmitting end 61 in the embodiment shown in FIG. 8 further includes: a selecting module configured to select a synchronization sequence, the synchronization sequence is a CAZAC series, and is processed by the first processing module 611.

In other embodiments, the transmitting end 61 in the embodiment shown in FIG. 8 further includes a first obtaining module configured to acquire the order value M of the differential processing, and the first processing module 611 performs differential processing on the synchronization sequence.

In a practical application, the first processing module 611, the second processing module 612, and the sending module 613 in the sending end 61 may be a central processing unit (CPU) in the transmitting end 61, or a digital signal processor (DSP). , Digital Signal Processor ), or Programmable Gate Array 'J (FPGA, Field - Programmable Gate Array) implementation.

FIG. 9 is a schematic diagram of a receiving end according to Embodiment 1 of the present invention; as shown in FIG. 9, the receiving end 62 in the embodiment shown in FIG. 7 includes: a receiving module 621, a third processing module 622, a fourth processing module 623, and a search module. 624, a determining module 625 and a synchronization module 626; wherein

The receiving module 621 is configured to receive data to be synchronized;

The third processing module 622 is configured to perform differential processing on the data to be synchronized received by the receiving module 621 to obtain differential data.

The fourth processing module 623 is configured to perform correlation operation between the difference data obtained by the third processing module 622 and the local sequence to obtain correlation value data; The searching module 624 is configured to search for a peak value in the correlation value data obtained by the fourth processing module 623;

The determining module 625 is configured to determine whether the number of peaks searched by the search module 624 reaches a first preset value;

The synchronization module 626 is configured to perform a synchronization operation when the judgment result of the determination module 625 is that the number of peaks reaches the first preset value.

In another preferred embodiment of the present invention, the search module 624 in the embodiment shown in FIG. 8 is further configured to detect whether the center window value is greater than a first threshold; if the center window value is greater than the first threshold, detecting the center window value Whether the difference from the value of the adjacent window is greater than the second threshold; if so, the maximum correlation value of the central window value is taken as the peak value.

In a practical application, the receiving module 621, the third processing module 622, the fourth processing module 623, the searching module 624, the determining module 625, and the synchronization module 626 in the receiving end 62 can be CPU, DSP, or DSP in the receiving end 62, or FPGA implementation.

10 is a schematic diagram of a receiving end according to Embodiment 2 of the present invention; as shown in FIG. 10, the receiving end 62 of the embodiment shown in FIG. 9 further includes a second obtaining module 627 and a compensation module 628; wherein, the second obtaining module 627 is configured. Obtaining the system frequency offset value according to the peak value, and transmitting to the compensation module 628;

The compensation module 628 is configured to perform frequency offset compensation on the data according to the system frequency offset value obtained by the second obtaining module 627.

In another preferred embodiment of the present invention, the receiving end in the embodiment shown in FIG. 9 further includes a detecting module configured to detect whether each peak searched by the search module 624 is valid; the determining module 625 is further configured to determine the detecting module. The synchronization module 626 is further configured to perform a synchronization operation when the determination result of the determination module 625 is that the number of valid peaks reaches the first preset value.

In a practical application, the second obtaining module 627 and the compensation module 628 in the receiving end 62 can be It is implemented by a CPU, DSP, or FPGA in the receiving end 62.

In another preferred embodiment of the present invention, the detecting module in the foregoing embodiment is configured to determine whether the interval between the peak to be detected and the next adjacent peak is equal to the frame length of the data to be synchronized; if yes, the peak to be detected is valid. Record it as a valid peak; otherwise, the peak to be detected is invalid, and it is recorded as an invalid peak.

In another preferred embodiment of the present invention, the determining module 625 in the foregoing embodiment is further configured to determine whether the number of invalid peaks detected by the detecting module reaches a second preset value; the synchronization module 626 is further configured to be When the judgment result of the determination module 625 is that the number of invalid peaks reaches the second preset value, the out-of-synchronization operation is performed.

The modules of the transmitting end and the receiving end according to the embodiment of the present invention may also be stored in a computer readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in the form of a software product in essence or in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions. A computer device (which may be a personal computer, server, or network device, etc.) is implemented to perform all or part of the methods described in various embodiments of the present invention. The foregoing storage medium includes: a U disk, a removable hard disk, a read only memory (Read Only Memory), a magnetic disk or an optical disk, and the like, which can store program codes. Thus, embodiments of the invention are not limited to any specific combination of hardware and software.

Correspondingly, an embodiment of the present invention further provides a computer storage medium, wherein a computer program is stored, the computer program being used to execute the frame synchronization method of the embodiment of the present invention.

It can be seen from the above that the implementation of the embodiments of the present invention has at least the following beneficial effects:

By transmitting the zero-correlation region of the synchronization sequence, the transmitting end reduces the side lobes at both ends of the correlation value peak, and reduces the false alarm and missed detection probability when the receiving end searches for the correlation value peak value;

The receiving end performs the validity detection on the peak and performs the synchronous operation according to the number of effective peaks, thereby avoiding the influence of the invalid peak on the synchronous operation; The receiving end performs differential processing on the received data, which restores the influence of the differential processing of the data by the transmitting end, and improves the flexibility of the frequency offset correction of the system;

Differential processing is performed on both the transmitting end and the receiving end, so that when the data enters the synchronization phase, the system frequency offset value calculation and the system frequency offset compensation can be quickly performed, so that the system frequency offset value can be quickly calculated after the system is synchronized, In the frequency offset correction, the system construction time is shortened. Usually, the time of building the chain can reduce the time of 2 physical frames.

Strict peak-interval decision criterion is used to judge whether the peak is valid, and the decision threshold of synchronization and out-of-step is further set, taking into account the two requirements of fast system construction speed and high stability; the sender and the receiver support multiple sets of correlations. The code group sequence is configured, and a set of related code group sequences corresponds to a set of local sequences, which can effectively reduce the interference between the two signals in the polarization mode, and improve the anti-interference ability of the system;

By adjusting the two parameters of the synchronization sequence length and the difference order, the frame synchronization and frequency offset correction requirements under different wireless channels can be met, so that the embodiment of the present invention has a wider application field.

The above is only a specific embodiment of the present invention, and any equivalent changes or modifications to the present invention are not included in the scope of protection of the present invention.

Claims

claims

1. A frame synchronization method, the method includes:

Perform zero-correlation area expansion processing on the synchronization sequence;

Perform differential processing on the sequence obtained by the zero-correlation region expansion process;

Use the sequence obtained by differential processing to mark the frame header of the data to be synchronized;

Send the data to be synchronized after the frame header mark.

2. The frame synchronization method according to claim 1, wherein before performing zero correlation area expansion processing on the synchronization sequence, the method further includes:

A synchronization sequence is selected, which is a constant envelope zero autocorrelation series.

3. The frame synchronization method according to claim 1 or 2, wherein before performing differential processing on the sequence obtained by the zero correlation area expansion process, the method further includes:

Obtain the order value of the differential processing.

4. A frame synchronization method, the method includes:

Receive data to be synchronized;

Perform differential processing on the data to be synchronized to obtain differential data;

Correlate the differential data with the local sequence to obtain correlation value data; search for peaks in the correlation value data;

Determine whether the number of peaks reaches the first preset value;

If so, perform a synchronization operation.

5. The frame synchronization method according to claim 4, wherein said searching for peak values in said correlation value data includes:

Detect whether the center window value is greater than the first threshold; if the center window value is greater than the first threshold, then detect whether the difference between the center window value and its adjacent window value is greater than the second threshold; if so, change the center window The maximum correlation value of the values is taken as the peak value.

6. The frame synchronization method as claimed in claim 4, wherein when determining whether the peak number reaches Before the first preset value, the method further includes: detecting whether each peak value is valid;

Correspondingly, the step of determining whether the number of peaks reaches the first preset value is: determining whether the number of effective peaks reaches the first preset value.

7. The frame synchronization method according to claim 6, wherein the detecting whether each peak value is valid includes:

Determine whether the interval between the peak to be detected and its next adjacent peak is equal to the frame length of the data to be synchronized; if so, the peak to be detected is a valid peak; otherwise, the peak to be detected is an invalid peak.

8. The frame synchronization method according to claim 7, wherein after performing the synchronization operation, the method further includes:

Determine whether the number of invalid peaks reaches the second preset value, and if so, perform an out-of-step operation.

9. The frame synchronization method according to any one of claims 4 to 8, wherein, after performing the synchronization operation, the method further includes:

The system frequency offset value is obtained according to the peak value, and frequency offset compensation is performed according to the system frequency offset value.

10. A frame synchronization method, the method includes:

The transmitting end performs zero-correlation area expansion processing on the synchronization sequence; performs differential processing on the sequence obtained by the zero-correlation area expansion processing; uses the sequence obtained by the differential processing to mark the frame header of the data to be synchronized; marks the frame header to be synchronized Data is sent to the receiving end;

The receiving end receives the data to be synchronized; performs differential processing on the data to be synchronized to obtain differential data; performs correlation operations on the differential data and the local sequence to obtain correlation value data; searches for the correlation value data in the correlation value data Peak value; determine whether the number of peak values reaches the first preset value; if so, perform a synchronization operation.

11. A sending end, the sending end includes: a first processing module, a second processing module and a sending module; wherein,

The first processing module is configured to perform zero correlation area expansion processing on the synchronization sequence, and Perform differential processing on the processed sequence;

The second processing module is configured to use the sequence obtained by differential processing to mark the frame header of the data to be synchronized;

The sending module is configured to send the data to be synchronized after the frame header mark.

12. The transmitter of claim 11, wherein the transmitter further includes a selection module configured to select the synchronization sequence, and the synchronization sequence is a constant envelope zero autocorrelation series.

13. The sending end according to claim 11 or 12, wherein the sending end further includes a first acquisition module configured to acquire the order value of the differential processing.

14. A receiving end, the receiving end includes: a receiving module, a third processing module, a fourth processing module, a search module, a judgment module and a synchronization module; wherein,

The receiving module is configured to receive data to be synchronized;

The third processing module is configured to perform differential processing on the data to be synchronized received by the receiving module to obtain differential data;

The fourth processing module is configured to perform a correlation operation on the differential data obtained by the third processing module and the local sequence to obtain correlation value data;

The search module is configured to search for peak values in the correlation value data obtained by the fourth processing module;

The judgment module is configured to judge whether the number of peaks searched by the search module reaches a first preset value;

The synchronization module is configured to perform a synchronization operation when the judgment result of the judgment module is that the number of peaks reaches a first preset value.

15. The receiving end of claim 14, wherein the search module is further configured to detect whether the center window value is greater than a first threshold; if the center window value is greater than the first threshold, detect the center window value. Whether the difference between the window value and its adjacent window value is greater than the second threshold; if so, the maximum correlation value of the central window value is used as the peak value.

16. The receiving end of claim 14, wherein the receiving end further includes a detection module configured to detect whether each peak searched by the search module is valid;

Correspondingly, the judgment module is also configured to judge whether the number of effective peaks detected by the detection module reaches the first preset value;

The synchronization module is further configured to perform a synchronization operation when the judgment result of the judgment module is that the number of valid peaks reaches a first preset value.

17. The receiving end according to claim 16, wherein the detection module is further configured to determine whether the interval between the peak value to be detected and its next adjacent peak value is equal to the frame length of the data to be synchronized; if so, then the The peak value to be detected is a valid peak value; otherwise, the peak value to be detected is an invalid peak value.

18. The receiving end according to claim 17, wherein the judgment module is further configured to judge whether the number of invalid peaks detected by the detection module reaches a second preset value;

The synchronization module is also configured to perform an out-of-synchronization operation when the judgment result of the judgment module is that the number of invalid peaks reaches a second preset value.

19. The receiving end according to any one of claims 14 to 18, wherein the receiving end further includes a second acquisition module and a compensation module;

The second acquisition module is configured to acquire the system frequency offset value according to the peak value;

The compensation module is configured to perform frequency offset compensation according to the system frequency offset value.

20. A frame synchronization system, the frame synchronization system includes the sending end as described in any one of claims 11 to 13, and the receiving end as described in any one of claims 14 to 19.

21. A computer storage medium. Computer executable instructions are stored in the computer storage medium. The computer executable instructions are used to execute the frame synchronization method according to any one of claims 1 to 10.