WO2014123084A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2014123084A1
WO2014123084A1 PCT/JP2014/052437 JP2014052437W WO2014123084A1 WO 2014123084 A1 WO2014123084 A1 WO 2014123084A1 JP 2014052437 W JP2014052437 W JP 2014052437W WO 2014123084 A1 WO2014123084 A1 WO 2014123084A1
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metal
trench
film
semiconductor device
barrier metal
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PCT/JP2014/052437
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French (fr)
Japanese (ja)
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秀和 信藤
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ピーエスフォー ルクスコ エスエイアールエル
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Priority to US14/765,792 priority Critical patent/US20150371991A1/en
Publication of WO2014123084A1 publication Critical patent/WO2014123084A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technology that is effective when applied to a semiconductor device having a DRAM (Dynamic Random Access Memory) employing a buried word line structure.
  • DRAM Dynamic Random Access Memory
  • DRAM which is one of semiconductor memory devices
  • DRAM is mounted in various electronic devices that we use every day.
  • higher performance such as lower power consumption, higher speed, and larger capacity in DRAMs.
  • One of the most effective means for realizing a high-performance DRAM is miniaturization of memory cells.
  • miniaturizing the memory cell By miniaturizing the memory cell, the length of the word line and the bit line connected to the memory cell is shortened. Therefore, the parasitic capacitance of the word line and the bit line is reduced and low voltage operation is possible, so that low power consumption can be realized.
  • the memory cell size is reduced, the capacity can be increased and the performance of the device can be improved.
  • miniaturization of the memory cell greatly contributes to high performance of the DRAM.
  • Patent Document 1 forms an insulating film (sacrificial oxide film) on a main surface of a semiconductor substrate (silicon substrate) by a CVD (Chemical Vapor Deposition) method and nitrides the insulating film A silicon film is deposited, and using the silicon nitride film as a mask, the insulating film (sacrificial oxide film) and the semiconductor substrate (silicon substrate) are etched to form trenches, and the semiconductor substrate (silicon substrate) is thermally oxidized.
  • CVD Chemical Vapor Deposition
  • the gate insulating film of the memory cell transistor is formed on the inner wall of the trench (trench), and the conductive film for the gate electrode is formed on the insulating film (sacrificial oxide film) including the inside of the trench (trench) using the CVD method.
  • a method for manufacturing a semiconductor device is disclosed in which (polycrystalline silicon film doped with n-type impurities) is formed (deposited). Note that Patent Document 1 describes that the conductive film may be deposited with an amorphous silicon film instead of the polycrystalline silicon film and doped with p-type impurities (boron) instead of n-type impurities.
  • Patent Document 2 forms a mask insulating film having an opening pattern on an upper surface of a semiconductor substrate, etches the semiconductor substrate using the mask insulating film as a mask, and forms a gate trench.
  • a gate insulating film made of a silicon oxide film is formed on the inner surface of the gate trench by a thermal oxidation method, titanium nitride (TiN) is formed by a CVD method, tungsten (W) is formed by a CVD method, and a laminated layer made of TiN and W The film is etched back by dry etching to form an embedded gate electrode (word line) made of TiN and W embedded in the gate trench, and a new gate trench formed above the embedded gate electrode is embedded.
  • a cap insulating film made of a silicon nitride film is formed by a CVD method It discloses.
  • JP 2008-028055 A paragraphs [0048] to [0052], FIGS. 3 to 6) JP 2012-099793 A (paragraphs [0046] to [0049], FIGS. 10 to 13)
  • the 65-nm node, 25-nm node, and 20-nm node and the memory cells are being miniaturized.
  • a buried word line structure in which tungsten (W) is buried in a trench structure formed by etching a semiconductor substrate (silicon substrate) as described in Patent Document 2 is employed. ing.
  • the trench width is 65 nm at the 65 nm node, 26 nm at the 25 nm node, and 12 nm at the 20 nm node.
  • the trench width is reduced to 12 nm as described above, and therefore it is necessary to make the titanium nitride (TiN) film and the tungsten (W) nucleation film as thin as possible.
  • TiN titanium nitride
  • W tungsten
  • the conventional CVD film forming method cannot reduce the thickness of the barrier metal, ensure adhesion with the metal electrode, and cannot control and control the film thickness of the thin film. There are challenges.
  • a semiconductor device includes an active region on a semiconductor substrate, a trench having a lower portion and an upper portion in the active region, a gate insulating film covering an inner wall surface of the trench, and a lower portion of the trench through the gate insulating film.
  • the film thickness of the second barrier metal is smaller than the film thickness of the first barrier metal.
  • a trench is formed in a semiconductor substrate, a gate insulating film is formed in the trench, and a first barrier metal is formed on the gate insulating film under a first film forming condition.
  • the barrier metal can be made into a thin film, the adhesion to the metal electrode can be secured, and the film thickness can be controlled and managed with the thin film.
  • FIG. 1 is a plan view showing a semiconductor device (DRAM memory cell) according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along the line A-A ′ of the semiconductor device illustrated in FIG. 1.
  • FIG. 2 is a cross-sectional structure diagram showing a first manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 7 is a cross-sectional structure diagram showing a second manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 7 is a cross-sectional structure diagram showing a third manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 7 is a cross-sectional structure diagram showing a fourth manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 9 is a cross-sectional structure diagram showing a fifth manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 9 is a cross-sectional structure diagram showing a sixth manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 9 is a cross-sectional structure diagram showing a seventh manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 10 is a cross-sectional structure diagram showing an eighth manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1.
  • an element isolation region embedded with an insulating film made of a silicon oxide film is formed on a semiconductor substrate (silicon substrate) by a well-known STI (Shallow Trench Isolation) method.
  • STI Shallow Trench Isolation
  • a first interlayer insulating film made of a silicon nitride (SiN) film or a silicon oxide (SiO 2 ) film is formed on the entire surface of the semiconductor substrate (silicon substrate).
  • a trench (gate trench) is formed by tri-etching. Form.
  • a gate insulating film made of a silicon oxide film is formed by oxidizing the surface of the trench by thermal oxidation (ISSG: In-Site-Steam-Generation).
  • a barrier metal made of titanium nitride (TiN) is formed on the gate insulating film by a thermal CVD (Chemical Vapor Deposition) method using titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas as electrodes. Is deposited. Thereafter, a metal electrode made of tungsten (W) is embedded by CVD.
  • Tungsten (W) nucleation is conventionally accomplished by tungsten hexafluoride (WF 6 ) flow and monosilane (SiH 4 ) flow, or tungsten hexafluoride (WF 6 ) flow and diborane (B 2 H 6 ) flow, Alternatively, film formation is performed while alternately purging a tungsten hexafluoride (WF 6 ) flow and a hydrogen (H 2 ) flow.
  • the trench is completely filled with a laminated film made of titanium nitride (TiN) and tungsten (W).
  • the laminated film made of titanium nitride (TiN) and tungsten (W) is etched back by a dry etching method, and a buried gate electrode made of titanium nitride (TiN) and tungsten (W) embedded in the trench is formed.
  • This buried gate electrode constitutes a word line.
  • a new trench is formed above the buried gate electrode.
  • a cap insulating film made of a silicon nitride (SiN) film is formed on the entire surface by a CVD method so as to bury a new trench, and the silicon nitride (SiN) film on the surface is removed.
  • the trench width is reduced to 12 nm. Therefore, it is necessary to make the titanium nitride (TiN) film and the tungsten (W) nucleation film as thin as possible.
  • titanium nitride (TiN) is only up to 3 nm, which has no problem of adhesion with a metal electrode made of tungsten (W).
  • the barrier metal film cannot be made thin. Therefore, the resistance of the word line cannot be reduced.
  • the thickness of the titanium nitride (TiN) film in the trench is intentionally changed by changing the gas condition of titanium nitride (TiN) from the reaction-controlled region to the supply-controlled region and setting the coverage to about 100% to 50%. It is conceivable that the thickness of the titanium nitride (TiN) film above the trench is increased.
  • the epitaxial growth rate by the CVD method depends on the type of raw material gas, temperature, pressure and the like.
  • the temperature region where the epitaxial growth is possible (growth temperature region) is qualitatively divided into two regions of reaction rate control and supply rate control.
  • Supply rate limiting is also called diffusion rate limiting.
  • the reaction rate controlling region is on the low temperature side in the growth temperature region, and the growth rate increases as the temperature increases.
  • the supply rate limiting region is a region on the high temperature side of the region and having a small temperature dependency. Epitaxial growth is usually performed in this supply rate limiting region.
  • the barrier metal made of titanium nitride (TiN) changes when the surface area of the pattern changes, so the thickness of the barrier metal made of titanium nitride (TiN) cannot be controlled / managed. There is a problem.
  • an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the thickness of the barrier metal, ensure adhesion with the metal electrode, and can control and manage the film thickness of the thin film. It is in.
  • Titanium nitride becomes a discontinuous film when deposited at 3 nm or less, and therefore has poor adhesion to tungsten (W) on the trench surface.
  • the film thickness can be controlled under reaction-controlled conditions, the thickness of the titanium nitride (TiN) film in the trench cannot be reduced to 3 nm or less.
  • the adhesion with tungsten (W) is improved.
  • the film thickness of the titanium nitride (TiN) film in the trench can be reduced to 3 nm or less.
  • the film thickness cannot be controlled and managed because it is greatly affected by the surface area fluctuation.
  • the film thickness of the barrier metal made of the titanium nitride (TiN) film in the trench is controlled and managed under the film forming conditions with a coverage of 100%, and the metal electrode made of tungsten (W) is adhered.
  • the properties are such that the film can be formed only on the trench surface, and two-stage film formation is performed in-situ.
  • the thickness of the barrier metal made of a titanium nitride (TiN) film in the trench can be made thinner than 2 nm without degrading the processing capability, and finally the resistance of the word line can be reduced.
  • the scale and number of each structure are different from each other in order to make each configuration easy to understand.
  • an XYZ coordinate system is set and the arrangement of each component will be described.
  • the Z direction is a direction perpendicular to the surface of the silicon substrate which is a semiconductor substrate
  • the X direction is a direction perpendicular to the Z direction on a plane parallel to the surface of the silicon substrate
  • the Y direction is a silicon substrate. It is a direction orthogonal to the X direction in a plane parallel to the surface of
  • the X ′ direction is a direction inclined obliquely with respect to the X direction.
  • FIGS. 3 to 10 are views showing a structure of a semiconductor device 100 according to a first embodiment of the present invention and a manufacturing method thereof.
  • the semiconductor device 100 according to the first embodiment is a DRAM (dynamic random access memory) memory cell.
  • 1 is a plan view of the semiconductor device 100
  • FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG. 1
  • FIGS. 3 to 10 are cross-sectional views showing a series of manufacturing steps of the semiconductor device 100.
  • the semiconductor device 100 constitutes a DRAM memory cell.
  • a silicon substrate 1 which is a semiconductor substrate, an element isolation region 12 that continuously extends in the X ′ direction and an active region 13 that also extends continuously in the X ′ direction include a Y direction. A plurality of them are alternately arranged at equal intervals and at equal pitches.
  • the element isolation region 12 is composed of an element isolation insulating film embedded in the trench.
  • a buried word line 10 (10a, 10b) extending continuously in the Y direction is disposed across the plurality of element isolation regions 12 and the plurality of active regions 13.
  • the embedded word line 10 arranged on the left side in FIG. 1 is called a first word line 10a
  • the embedded word line 10 arranged on the right side in FIG. 1 is called a second word line 10b.
  • the first capacitor contact region 37a is disposed adjacent to the left side of the first word line 10a, and the second capacitor contact region 37b is disposed adjacent to the right side of the second word line 10b.
  • a bit line contact region 32 is disposed adjacent to the first word line 10a and the second word line 10b.
  • the active region 13 includes a first capacitor contact region 37a, a first word line 10a, a bit line contact region 32, a second word line 10b, and a second capacitor contact region 37b.
  • a first cell transistor Tr1 is configured by the first capacitor contact region 37a, the first word line 10a, and the bit line contact region 32.
  • the bit line contact region 32, the second word line 10b, and the second capacitor contact region 37b constitute a second cell transistor Tr2.
  • a silicon substrate 1 is provided with a gate trench 14 for a word line that also serves as a gate electrode of a transistor.
  • a first word line 10 a and a second word line 10 b are provided at the bottom of each gate trench 14 via a gate insulating film 5 formed of a thermal oxide film covering the inner surface of each word line gate trench 14. ing.
  • a cap insulating film 27 is provided so as to cover each word line and bury each gate trench 14.
  • the semiconductor pillar located on the left side of the first word line 10a becomes the first capacitor contact region 37a, and an impurity diffusion layer 29a serving as one of the source / drain is provided on the upper surface thereof.
  • the semiconductor pillar located between the first word line 10a and the second word line 10b becomes the bit line contact region 32, and an impurity diffusion layer 28 serving as the other of the source / drain is provided on the upper surface thereof.
  • the semiconductor pillar located on the right side of the second word line 10b becomes the second capacitor contact region 37b, and an impurity diffusion layer 29b serving as one of the source / drain is provided on the upper surface thereof.
  • the impurity diffusion layer 29a, the gate insulating film 5, the first word line 10a, and the impurity diffusion layer 28 constitute a first transistor Tr1 (FIG. 1).
  • the impurity diffusion layer 28, the gate insulating film 5, the second word line 10b, and the impurity diffusion layer 29b constitute the second transistor Tr2 (FIG. 1).
  • a cap insulating film 27 is provided so as to cover the upper surface of each word line.
  • a first interlayer insulating film 7 made of a silicon oxide film used as a mask for forming the gate trench 14 is provided on the upper surface of the element isolation region 12 and the upper surface of the silicon substrate 1 on which the impurity diffusion layers 29a and 29b are formed. It has been.
  • bit line (BL) 26 connected to the impurity diffusion layer 28 in the bit line contact region 32 is provided.
  • a cover insulating film 33 is provided on the upper surface of BL26.
  • a liner insulating film 34 is provided on the entire surface so as to cover the side wall of the BL 26.
  • An SOD (SpinSOOnSODielectric) film 35 is provided on the liner insulating film 34 so as to bury a recessed space formed between adjacent BLs.
  • the first and second capacitor contact plugs 38a and 38b are connected to the first and second capacitor contact regions 37a and 37b through the capacitor contact holes, respectively.
  • First and second capacitor contact pads 42a and 42b are connected to the upper portions of the first and second capacitor contact plugs 38a and 38b, respectively.
  • a stopper nitride film 43 is provided so as to cover the capacitor contact pad 42.
  • a capacitor lower electrode 44 is provided on the capacitor contact pad 42.
  • a capacitor insulating film 45 covering the inner surface of the capacitor lower electrode 44 is provided, and a capacitor upper polysilicon electrode 46 and a capacitor upper tungsten electrode 47 are provided on the capacitor insulating film 45.
  • a wiring 48 and a second interlayer insulating film 49 are provided on the capacitor upper tungsten electrode 47.
  • FIGS. 3 to 10 are cross-sectional views taken along line A-A ′ in FIG.
  • an element isolation region 12 embedded in an insulating film made of a silicon oxide film on a silicon substrate 1 which is a semiconductor substrate by a well-known STI (Shallow Trench Isolation) method. Form.
  • an active region 13 (FIG. 1) that is surrounded by the element isolation region 12 and made of the silicon substrate 1 is formed.
  • a pad oxide film 2 made of a silicon oxide film is formed on the entire surface of the silicon substrate 1, and a P well region is formed through the pad oxide film 2 by a known method.
  • a first interlayer insulating film 7 made of a silicon oxide film or the like is deposited (formed) on the silicon substrate 1.
  • the first interlayer insulating film 7 is patterned with a resist (not shown), and the silicon substrate 1 is etched by dry etching to form a gate trench 14. Thereafter, the surface (inner wall) of the gate trench 14 is oxidized by thermal oxidation (ISSG: In Site Steam Generation), thereby forming the gate insulating film 5 made of a silicon oxide film.
  • ISSG In Site Steam Generation
  • the gate trench 14 extends continuously from the active region 13 to the element isolation region 12.
  • a barrier metal made of titanium nitride (TiN) to be an electrode is formed.
  • the film formation of the barrier metal made of titanium nitride (TiN) is performed under the same gas conditions.
  • the film is divided into two stages and in-site. To do.
  • the first titanium nitride 6a is covered by an ALD (Atomic Layer Deposition) method using titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas so as to cover the gate insulating film 5.
  • the formation conditions here are reaction rate-limiting conditions with a TiCl 4 / NH 3 flow rate ratio of approximately 1.
  • the gas conditions are optimized so that the coverage is 100%.
  • the film forming conditions are, for example, titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas at a flow rate of 60 sccm.
  • the flow rate of titanium tetrachloride (TiCl 4 ) gas and the flow rate of ammonia (NH 3 ) gas can be adjusted so that the coverage does not deteriorate.
  • the first titanium nitride 6a is called a first barrier metal.
  • the reaction-controlling condition is called the first film forming condition.
  • TiN titanium nitride
  • titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) are formed on the first titanium nitride 6 a on the flat portion outside the gate trench 14.
  • the second titanium nitride 6b and the first titanium nitride 6a are formed to have a film thickness of 3 nm by an ALD (Atomic Layer Deposition) method using a gas.
  • the flow rate of titanium tetrachloride (TiCl 4 ) gas is narrowed down and the flow rate of ammonia (NH 3 ) gas is increased, so that a very small amount of film is formed inside the gate trench 14 as the supply rate limiting condition. (Coverage is 0%).
  • TiCl 4 titanium tetrachloride
  • NH 3 ammonia
  • the second titanium nitride 6b is called a second barrier metal.
  • the supply rate limiting condition is referred to as a second film forming condition.
  • the film thickness of the second barrier metal 6b is thinner than the film thickness of the first barrier metal 6a inside the gate trench 14.
  • the step coverage of the second barrier metal 6b formed under the second film formation conditions is worse than the step coverage of the first barrier metal 6a formed under the first film formation conditions.
  • the first titanium nitride 6a and the second titanium nitride 6b can be formed without reducing the processing capability by continuously growing in the same chamber.
  • a continuous film having a thick titanium nitride (barrier metal) film on the flat portion outside the gate trench 14 is formed, and a metal electrode made of tungsten (W) to be formed later is formed. Adhesion can be secured.
  • the area inside the gate trench 14 is very small compared to the wafer area and the film stress direction of tungsten (W) is perpendicular to the flat portion, even if the film thickness of titanium nitride is small. Adhesiveness with tungsten (W) does not decrease.
  • a metal electrode made of tungsten (W) 9 is buried by CVD.
  • tungsten (W) 9 is formed in two steps, a nucleus formation step and a main step.
  • tungsten hexafluoride WF 6
  • diborane B 2 H 6
  • tungsten is formed with WF 6 / H 2 .
  • a wiring body is formed.
  • monosilane (SiH 4 ) is flowed to surface-treat titanium nitride (TiN).
  • TiN titanium nitride
  • WF tungsten hexafluoride
  • Diborane (B 2 H 6 ) or hydrogen (H 2 ) may be used instead of monosilane (SiH 4 ).
  • diborane (B 2 H 6 ) can reduce the specific resistance most.
  • tungsten for example, tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) are simultaneously flowed at a temperature of 390 ° C. and a pressure of 10666 pa to form a film.
  • W tungsten hexafluoride
  • H 2 hydrogen
  • the film thickness of the first titanium nitride 6a in the gate trench 14 is as thin as 1 nm, the sectional area of the tungsten (W) 9 in the gate trench 14 is increased, and the resistance of the word line 10 can be lowered. .
  • the gate trench 14 is completely buried with a laminated film made of the first titanium nitride 6a, the second titanium nitride 6b, and tungsten (W) 9.
  • the laminated film made of the first titanium nitride 6a, the second titanium nitride 6b, and tungsten (W) is etched back by a dry etching method, and buried in the gate trench 14.
  • Embedded gate electrodes 10a and 10b made of a titanium nitride 6a, a second titanium nitride 6b, and tungsten (W) are formed.
  • the buried gate electrodes 10a and 10b constitute a word line.
  • a new trench is formed above the buried gate electrodes 10a and 10b.
  • a cap insulating film 27 made of a silicon nitride (SiN) film is formed on the entire surface by a CVD method so as to bury a new trench, and CMP (Chemical-Mechanical-Polishing) is performed to form a silicon nitride (SiN) film on the surface. Remove.
  • the first barrier metal 6a, the second barrier metal 6b, the metal electrode 9 and the cap insulating film 27 are continuously extended from the active region 13 to the element isolation region 13 in the gate trench 14. Yes.
  • bit line 26 is formed.
  • bit contact connected to the upper surface of the bit line contact region 32 (FIG. 1) is formed.
  • the bit contact is formed as a line-shaped opening pattern extending in the same direction as the word line 10 (Y direction in FIG. 1). At the intersection of the bit contact pattern and the active region, the surface of the silicon substrate 1 is exposed.
  • an N-type impurity (such as arsenic) is ion-implanted to form an N-type impurity diffusion layer 28 in the vicinity of the silicon surface.
  • the formed N-type impurity diffusion layer 28 functions as a source / drain region 28 of the transistor.
  • a laminated film such as a polysilicon film, a tungsten film, and a silicon nitride film 33 is formed by, for example, a CVD method.
  • the bit line 26 is formed by patterning into a line shape using a photolithography technique and a dry etching technique.
  • the bit line 26 is formed as a pattern extending in a direction intersecting the word line 10 (X direction in FIG. 1).
  • the polysilicon film under the bit line 26 is connected to the source / drain region 28 at the silicon surface portion exposed in the bit contact.
  • a liner film 34 covering the upper surface is formed of a silicon nitride film or the like by using, for example, a CVD method.
  • an annealing process is performed in a high-temperature steam (H 2 O) atmosphere to modify the film into a solid film.
  • the planarization is performed by CMP until the upper surface of the liner film 34 is exposed.
  • a capacitive contact is formed through the SOD film 35, the liner film 34, and the first interlayer insulating film 7 by using a photolithography technique and a dry etching technique.
  • polysilicon doped with an N-type impurity phosphorus or the like
  • N-type impurity diffusion layers 29a and 29b are formed in the vicinity of the surface of the capacitor contact regions 37a and 37b by the N-type impurities doped in the polysilicon.
  • the formed N-type impurity diffusion layers 29a and 29b function as source / drain regions of the transistor.
  • Capacitance contact pads 42a and 42b are formed using photolithography technology and dry etching technology.
  • a stopper nitride film 43 is formed using a silicon nitride film so as to cover the capacitor contact pads 42a and 42b.
  • a capacitor lower electrode 44 is formed of titanium nitride or the like on the capacitor contact pads 42a and 42b.
  • the capacitor upper polysilicon electrode 46 and the capacitor upper tungsten electrode 47 are formed.
  • a wiring 48 and a second interlayer insulating film 49 are formed on the capacitor upper tungsten electrode 47 to form the semiconductor device 100.
  • the barrier metal In the semiconductor device 100, a combination of the first barrier metal 6a and the second barrier metal 6b having a thickness smaller than that of the first barrier metal 6b is used as the barrier metal.
  • the adhesion to the metal electrode can be secured, and the film thickness can be controlled and managed with a thin film.
  • a film in which a first titanium nitride 6a, a second titanium nitride 6b, and tungsten (W) 9 are sequentially stacked is used as the buried gate electrode (word line) 10.
  • the present invention is not limited to this, and various modifications as described below can be adopted.
  • a nitrided first metal may be used instead of the first and second titanium nitrides 6a and 6b.
  • each of the first metal and the second metal may be a refractory metal.
  • the refractory metal may be selected from the group of tungsten, cobalt, titanium, molybdenum, and tantalum.
  • the present invention is not limited to the embedded gate electrode of the DRAM, but can be applied to embedded gate electrodes for all products including PRAM (Phase-Change Random Access Memory), ReRAM (Resistive Random Access Memory), and the like.

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Abstract

Provided is a semiconductor device allowing a barrier metal to be reduced in thickness, adhesion with a metal electrode to be ensured, and film thickness to be controlled/managed using the thin film. The semiconductor device is provided with an active region (13) on a semiconductor substrate (1), a trench (14) having a lower section and an upper section within the active region, a gate insulating film (5) that covers the inner wall surface of the trench, a first barrier metal (6a) that covers the lower section of the trench interposed by the gate insulating film, a second barrier metal (6b) that covers the first barrier metal, and a metal electrode (9) that covers the second barrier metal and fills up the lower section of the trench. The second barrier metal is thinner less than the first barrier metal.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置およびその製造方法に関し、特に、埋め込みワード線構造を採用したＤＲＡＭ（Dynamic Random Access Memory）を有する半導体装置に適用して有効な技術に関するものである。 The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technology that is effective when applied to a semiconductor device having a DRAM (Dynamic Random Access Memory) employing a buried word line structure.
　半導体記憶装置の一つであるＤＲＡＭは、我々が日常利用する様々な電子機器に数多く搭載されている。また、近年の機器の低消費電力化、高性能化のニーズに伴い、搭載されるＤＲＡＭも低電力化、高速化、大容量化といった高性能化が強く求められている。 DRAM, which is one of semiconductor memory devices, is mounted in various electronic devices that we use every day. In addition, with recent needs for lower power consumption and higher performance of equipment, there is a strong demand for higher performance such as lower power consumption, higher speed, and larger capacity in DRAMs.
　高性能なＤＲＡＭを実現するための最も有効な手段の一つは、メモリセルの微細化である。メモリセルを微細化することにより、メモリセルに接続されるワード線およびビット線の長さが短くなる。そのため、ワード線およびビット線の寄生容量が低減され、低電圧動作が可能となるので、低消費電力化が実現できる。また、メモリセルサイズが小さくなるので、大容量化が可能となり、機器の高性能化が実現できる。このように、メモリセルに微細化は、ＤＲＡＭの高性能化に大きく寄与する。 One of the most effective means for realizing a high-performance DRAM is miniaturization of memory cells. By miniaturizing the memory cell, the length of the word line and the bit line connected to the memory cell is shortened. Therefore, the parasitic capacitance of the word line and the bit line is reduced and low voltage operation is possible, so that low power consumption can be realized. In addition, since the memory cell size is reduced, the capacity can be increased and the performance of the device can be improved. Thus, miniaturization of the memory cell greatly contributes to high performance of the DRAM.
　このような半導体装置に備えられるセルトランジスタを含むメモリセルの微細化に伴い、ショートチャネル効果によるトランジスタ特性の悪化や、コンタクトホール径の縮小によるコンタクト抵抗の増加が問題となっている。 With the miniaturization of memory cells including cell transistors provided in such semiconductor devices, deterioration of transistor characteristics due to the short channel effect and increase in contact resistance due to reduction of the contact hole diameter have become problems.
　これらの問題を解決し、さらなる微細化を進めるため、メモリセルを構成するセルトランジスタに、半導体基板の表層にワード線となるゲート電極を埋め込んだ埋め込みゲート型のトランジスタを採用することが提案されている。 In order to solve these problems and advance further miniaturization, it has been proposed to employ a buried gate type transistor in which a gate electrode serving as a word line is buried in a surface layer of a semiconductor substrate as a cell transistor constituting a memory cell. Yes.
　たとえば、特開２００８－０２８０５５号公報（特許文献１）は、半導体基板（シリコン基板）の主面上にＣＶＤ（Chemical Vapor Deposition）法で絶縁膜（犠牲酸化膜）を形成し、その上に窒化シリコン膜を堆積し、窒化シリコン膜をマスクに用いて、絶縁膜（犠牲酸化膜）および半導体基板（シリコン基板）をエッチングして溝（トレンチ）を形成し、半導体基板（シリコン基板）を熱酸化することにより、溝（トレンチ）の内壁にメモリセルトランジスタのゲート絶縁膜を形成し、ＣＶＤ法を用いて溝（トレンチ）の内部を含む絶縁膜（犠牲酸化膜）上にゲート電極用の導電膜（ｎ型不純物がドープされた多結晶シリコン膜）を形成（堆積）する、半導体装置の製造方法を開示している。尚、特許文献１では、導電膜に関して、多結晶シリコン膜に代えてアモルファスシリコン膜を堆積し、ｎ型不純物に代えてｐ型不純物（ホウ素）をドープしてもよい、と記載している。 For example, Japanese Patent Laid-Open No. 2008-028055 (Patent Document 1) forms an insulating film (sacrificial oxide film) on a main surface of a semiconductor substrate (silicon substrate) by a CVD (Chemical Vapor Deposition) method and nitrides the insulating film A silicon film is deposited, and using the silicon nitride film as a mask, the insulating film (sacrificial oxide film) and the semiconductor substrate (silicon substrate) are etched to form trenches, and the semiconductor substrate (silicon substrate) is thermally oxidized. As a result, the gate insulating film of the memory cell transistor is formed on the inner wall of the trench (trench), and the conductive film for the gate electrode is formed on the insulating film (sacrificial oxide film) including the inside of the trench (trench) using the CVD method. A method for manufacturing a semiconductor device is disclosed in which (polycrystalline silicon film doped with n-type impurities) is formed (deposited). Note that Patent Document 1 describes that the conductive film may be deposited with an amorphous silicon film instead of the polycrystalline silicon film and doped with p-type impurities (boron) instead of n-type impurities.
　また、特開２０１２－０９９７９３号公報（特許文献２）は、半導体基板の上面に開口パターンを有するマスク絶縁膜を形成し、マスク絶縁膜をマスクとして半導体基板をエッチングしてゲートトレンチを形成し、ゲートトレンチの内面に酸化シリコン膜からなるゲート絶縁膜を熱酸化法により形成し、窒化チタン（ＴｉＮ）をＣＶＤ法により形成し、タングステン（Ｗ）をＣＶＤ法により形成し、ＴｉＮとＷからなる積層膜をドライエッチング法によりエッチバックしてゲートトレンチ内に埋設されたＴｉＮとＷからなる埋め込みゲート電極（ワード線）を形成し、埋め込みゲート電極の上方に形成された新たなゲートトレンチを埋設するように窒化シリコン膜からなるキャップ絶縁膜をＣＶＤ法により形成する、半導体装置の製造方法を開示している。 Japanese Patent Laying-Open No. 2012-099793 (Patent Document 2) forms a mask insulating film having an opening pattern on an upper surface of a semiconductor substrate, etches the semiconductor substrate using the mask insulating film as a mask, and forms a gate trench. A gate insulating film made of a silicon oxide film is formed on the inner surface of the gate trench by a thermal oxidation method, titanium nitride (TiN) is formed by a CVD method, tungsten (W) is formed by a CVD method, and a laminated layer made of TiN and W The film is etched back by dry etching to form an embedded gate electrode (word line) made of TiN and W embedded in the gate trench, and a new gate trench formed above the embedded gate electrode is embedded. For manufacturing a semiconductor device, in which a cap insulating film made of a silicon nitride film is formed by a CVD method It discloses.
特開２００８－０２８０５５号公報（段落［００４８］～［００５２］、図３～図６）JP 2008-028055 A (paragraphs [0048] to [0052], FIGS. 3 to 6) 特開２０１２－０９９７９３号公報（段落［００４６］～［００４９］、図１０～図１３）JP 2012-099793 A (paragraphs [0046] to [0049], FIGS. 10 to 13)
　６５ｎｍノード、２５ｎｍノード、２０ｎｍノードとメモリセルの微細化が進んでいる。６５ｎｍノード以降のメモリセルでは、上記特許文献２に記載されているような、半導体基板（シリコン基板）をエッチングして形成したトレンチ構造にタングステン（Ｗ）を埋め込んだ、埋め込みワード線構造が採用されている。トレンチ幅は、６５ｎｍノードで６５ｎｍ、２５ｎｍノードで２６ｎｍ、２０ｎｍノードでは１２ｎｍである。 The 65-nm node, 25-nm node, and 20-nm node and the memory cells are being miniaturized. In the memory cell after the 65 nm node, a buried word line structure in which tungsten (W) is buried in a trench structure formed by etching a semiconductor substrate (silicon substrate) as described in Patent Document 2 is employed. ing. The trench width is 65 nm at the 65 nm node, 26 nm at the 25 nm node, and 12 nm at the 20 nm node.
　２０ｎｍノードのメモリセルでは、上述したようにトレンチ幅が１２ｎｍまで縮小するので、窒化チタン（ＴｉＮ）膜及びタングステン（Ｗ）核形成膜をできる限り薄膜化する必要がある。尚、窒化チタン（ＴｉＮ）はバリアメタルとも呼ばれ、タングステン（Ｗ）は金属電極とも呼ばれる。 In the 20 nm node memory cell, the trench width is reduced to 12 nm as described above, and therefore it is necessary to make the titanium nitride (TiN) film and the tungsten (W) nucleation film as thin as possible. Titanium nitride (TiN) is also called a barrier metal, and tungsten (W) is also called a metal electrode.
　しかしながら、従来使用しているＣＶＤ法の成膜方法（製造方法）では、バリアメタルを薄膜化し、且つ金属電極との密着性を確保し、且つ薄膜での膜厚制御・管理することができないという課題がある。 However, the conventional CVD film forming method (manufacturing method) cannot reduce the thickness of the barrier metal, ensure adhesion with the metal electrode, and cannot control and control the film thickness of the thin film. There are challenges.
　本発明による半導体装置は、半導体基板上の活性領域と、活性領域内にあって下部と上部を有するトレンチと、トレンチの内壁面を覆うゲート絶縁膜と、ゲート絶縁膜を介してトレンチ下部を覆う第１のバリアメタルと、第１のバリアメタルを覆う第２のバリアメタルと、第２のバリアメタルを覆い、トレンチ下部を埋設する金属電極と、トレンチの上部を埋設するキャップ絶縁膜と、を備え、第２のバリアメタルの膜厚は第１のバリアメタルの膜厚より薄い。 A semiconductor device according to the present invention includes an active region on a semiconductor substrate, a trench having a lower portion and an upper portion in the active region, a gate insulating film covering an inner wall surface of the trench, and a lower portion of the trench through the gate insulating film. A first barrier metal; a second barrier metal that covers the first barrier metal; a metal electrode that covers the second barrier metal and buryes the lower portion of the trench; and a cap insulating film that buryes the upper portion of the trench. The film thickness of the second barrier metal is smaller than the film thickness of the first barrier metal.
　また、本発明による半導体装置の製造方法は、半導体基板にトレンチを形成し、トレンチ内にゲート絶縁膜を形成し、ゲート絶縁膜上に第１のバリアメタルを第１の成膜条件で形成し、第１のバリアメタル上に第１の成膜条件と異なる第２の成膜条件で形成し、第２のバリアメタル上にトレンチを埋設するように金属材料を形成し、トレンチの上部の第１のバリアメタル、第２のバリアメタル及び金属を除去し、トレンチの上部をキャップ絶縁膜で埋設する。 In the method of manufacturing a semiconductor device according to the present invention, a trench is formed in a semiconductor substrate, a gate insulating film is formed in the trench, and a first barrier metal is formed on the gate insulating film under a first film forming condition. Forming a metal material on the first barrier metal under a second film-forming condition different from the first film-forming condition, forming a metal material so as to bury the trench on the second barrier metal, The first barrier metal, the second barrier metal, and the metal are removed, and the upper portion of the trench is buried with a cap insulating film.
　本発明によると、バリアメタルを薄膜化し、且つ金属電極との密着性を確保し、且つ薄膜での膜厚制御・管理をすることができる。 According to the present invention, the barrier metal can be made into a thin film, the adhesion to the metal electrode can be secured, and the film thickness can be controlled and managed with the thin film.
本発明の第１の実施例による半導体装置（ＤＲＡＭメモリセル）を示す平面図である。1 is a plan view showing a semiconductor device (DRAM memory cell) according to a first embodiment of the present invention; 図１に示した半導体装置のＡ－Ａ’断面図である。FIG. 2 is a cross-sectional view taken along the line A-A ′ of the semiconductor device illustrated in FIG. 1. 図１に示した半導体装置を製造するプロセスの第１の製造工程を示す断面構造図である。FIG. 2 is a cross-sectional structure diagram showing a first manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第２の製造工程を示す断面構造図である。FIG. 7 is a cross-sectional structure diagram showing a second manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第３の製造工程を示す断面構造図である。FIG. 7 is a cross-sectional structure diagram showing a third manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第４の製造工程を示す断面構造図である。FIG. 7 is a cross-sectional structure diagram showing a fourth manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第５の製造工程を示す断面構造図である。FIG. 9 is a cross-sectional structure diagram showing a fifth manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第６の製造工程を示す断面構造図である。FIG. 9 is a cross-sectional structure diagram showing a sixth manufacturing process in the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第７の製造工程を示す断面構造図である。FIG. 9 is a cross-sectional structure diagram showing a seventh manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1. 図１に示した半導体装置を製造するプロセスの第８の製造工程を示す断面構造図である。FIG. 10 is a cross-sectional structure diagram showing an eighth manufacturing process of the process for manufacturing the semiconductor device shown in FIG. 1.
［関連技術］　
　本発明について説明する前に、本発明の理解を容易にするために、関連技術について説明する。 [Related technologies]
Prior to describing the present invention, related techniques will be described in order to facilitate understanding of the present invention.
　以下に、関連する埋め込みワード線構造の形成方法について説明する。 Hereinafter, a method for forming a related buried word line structure will be described.
　先ず、半導体基板（シリコン基板）の上に、周知のＳＴＩ（Shallow Trench Isolation）法により、酸化シリコン膜からなる絶縁膜で埋設された素子分離領域を形成する。これにより、素子分離領域で囲まれ、半導体基板（シリコン基板）からなる活性領域が形成される。 First, an element isolation region embedded with an insulating film made of a silicon oxide film is formed on a semiconductor substrate (silicon substrate) by a well-known STI (Shallow Trench Isolation) method. As a result, an active region made of a semiconductor substrate (silicon substrate) surrounded by the element isolation region is formed.
　次に、半導体基板（シリコン基板）上全面に窒化シリコン（ＳｉＮ）膜又は酸化シリコン（ＳｉＯ２）膜から成る第１層間絶縁膜を成膜し、パターニング後、トライエッチングにてトレンチ（ゲートトレンチ）を形成する。 Next, a first interlayer insulating film made of a silicon nitride (SiN) film or a silicon oxide (SiO 2 ) film is formed on the entire surface of the semiconductor substrate (silicon substrate). After patterning, a trench (gate trench) is formed by tri-etching. Form.
　次に、トレンチの表面を熱酸化（ＩＳＳＧ：In Site Steam Generation）により酸化させることによって、シリコン酸化膜からなるゲート絶縁膜を形成する。 Next, a gate insulating film made of a silicon oxide film is formed by oxidizing the surface of the trench by thermal oxidation (ISSG: In-Site-Steam-Generation).
　そして、そのゲート絶縁膜の上に、電極として、四塩化チタン（ＴｉＣｌ４）ガスとアンモニア（ＮＨ３）ガスを用いた熱ＣＶＤ（Chemical Vapor Deposition）法で、窒化チタン（ＴｉＮ）から成るバリアメタルを成膜する。その後、ＣＶＤ法でタングステン（Ｗ）から成る金属電極を埋設する。 A barrier metal made of titanium nitride (TiN) is formed on the gate insulating film by a thermal CVD (Chemical Vapor Deposition) method using titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas as electrodes. Is deposited. Thereafter, a metal electrode made of tungsten (W) is embedded by CVD.
　タングステン（Ｗ）の核形成は、従来においては、六弗化タングステン（ＷＦ６）フローとモノシラン（ＳｉＨ４）フロー、または六弗化タングステン（ＷＦ６）フローとジボラン（Ｂ２Ｈ６）フロー、または六弗化タングステン（ＷＦ６）フローと水素（Ｈ２）フローを交互にパージしながら成膜を行う。 Tungsten (W) nucleation is conventionally accomplished by tungsten hexafluoride (WF 6 ) flow and monosilane (SiH 4 ) flow, or tungsten hexafluoride (WF 6 ) flow and diborane (B 2 H 6 ) flow, Alternatively, film formation is performed while alternately purging a tungsten hexafluoride (WF 6 ) flow and a hydrogen (H 2 ) flow.
　この段階でトレンチは、窒化チタン（ＴｉＮ）とタングステン（Ｗ）とからなる積層膜で完全に埋設された状態となる。 At this stage, the trench is completely filled with a laminated film made of titanium nitride (TiN) and tungsten (W).
　次いで、窒化チタン（ＴｉＮ）とタングステン（Ｗ）とからなる積層膜をドライエッチング法によりエッチバックして、トレンチ内に埋設された窒化チタン（ＴｉＮ）とタングステン（Ｗ）とからなる埋め込みゲート電極を形成する。この埋め込みゲート電極はワード線を構成する。トレンチ内に埋め込みゲート電極が形成される結果、埋め込みゲート電極の上方に新たなトレンチが形成される。 Next, the laminated film made of titanium nitride (TiN) and tungsten (W) is etched back by a dry etching method, and a buried gate electrode made of titanium nitride (TiN) and tungsten (W) embedded in the trench is formed. Form. This buried gate electrode constitutes a word line. As a result of forming the buried gate electrode in the trench, a new trench is formed above the buried gate electrode.
　次に、新たなトレンチを埋設するように全面に窒化シリコン（ＳｉＮ）膜からなるキャップ絶縁膜をＣＶＤ法により形成し、表面の窒化シリコン（ＳｉＮ）膜を除去する。 Next, a cap insulating film made of a silicon nitride (SiN) film is formed on the entire surface by a CVD method so as to bury a new trench, and the silicon nitride (SiN) film on the surface is removed.
　次に、関連技術の問題点について説明する。 Next, the problem of related technology will be explained.
　前述したように、２０ｎｍノードのメモリセルでは、トレンチ幅が１２ｎｍまで縮小するので、窒化チタン（ＴｉＮ）膜及びタングステン（Ｗ）核形成膜をできる限り薄膜化する必要がある。 As described above, in the 20 nm node memory cell, the trench width is reduced to 12 nm. Therefore, it is necessary to make the titanium nitride (TiN) film and the tungsten (W) nucleation film as thin as possible.
　しかしながら、従来使用しているＣＶＤ法で成膜して無機窒化チタン（ＴｉＮ）から成るバリアメタルを使用すると、タングステン（Ｗ）から成る金属電極との密着性が問題無い３ｎｍまでしか窒化チタン（ＴｉＮ）膜から成るバリアメタルを薄膜化できない。そのため、ワード線の抵抗を低減することができない。 However, when a barrier metal made of inorganic titanium nitride (TiN) is used by forming a film by the conventional CVD method, titanium nitride (TiN) is only up to 3 nm, which has no problem of adhesion with a metal electrode made of tungsten (W). ) The barrier metal film cannot be made thin. Therefore, the resistance of the word line cannot be reduced.
　また、意図的に窒化チタン（ＴｉＮ）のガス条件を反応律速領域から供給律速領域に変更し、ガバレッジを１００％から５０％程度にすることによって、トレンチ内の窒化チタン（ＴｉＮ）膜の膜厚を薄膜化し、且つトレンチ上部の窒化チタン（ＴｉＮ）膜の膜厚を厚膜化することが考えられる。 In addition, the thickness of the titanium nitride (TiN) film in the trench is intentionally changed by changing the gas condition of titanium nitride (TiN) from the reaction-controlled region to the supply-controlled region and setting the coverage to about 100% to 50%. It is conceivable that the thickness of the titanium nitride (TiN) film above the trench is increased.
　次に、「反応律速」と「供給律速」について簡単に説明する。 Next, “reaction rate limiting” and “supply rate limiting” will be briefly explained.
　ＣＶＤ法によるエピタキシャル成長速度は、原料ガスの種類、温度、圧力等に依存する。エピタキシャル成長が可能な温度領域（成長温度領域）は定性的に、反応律速と供給律速の２領域に分けられる。供給律速は拡散律速とも呼ばれる。反応律速領域は成長温度領域内の低温側にあって、温度が高いほど成長速度が速くなる領域である。一方、供給律速領域は同領域の高温側にあって、温度依存性が小さい領域である。エピタキシャル成長は通常この供給律速領域で行われる。 The epitaxial growth rate by the CVD method depends on the type of raw material gas, temperature, pressure and the like. The temperature region where the epitaxial growth is possible (growth temperature region) is qualitatively divided into two regions of reaction rate control and supply rate control. Supply rate limiting is also called diffusion rate limiting. The reaction rate controlling region is on the low temperature side in the growth temperature region, and the growth rate increases as the temperature increases. On the other hand, the supply rate limiting region is a region on the high temperature side of the region and having a small temperature dependency. Epitaxial growth is usually performed in this supply rate limiting region.
　上記変更により、タングステン（Ｗ）から成る金属電極との密着性の向上と、トレンチ内の窒化チタン（ＴｉＮ）膜から成るバリアメタルの膜厚の薄膜化とが両立できる。しかしながら、供給律速条件では、パターンの表面積が変化した際に窒化チタン（ＴｉＮ）から成るバリアメタルが変化するため、窒化チタン（ＴｉＮ）膜から成るバリアメタルの膜厚を制御・管理することができないという課題がある。 By the above change, it is possible to improve both the adhesion to the metal electrode made of tungsten (W) and to reduce the thickness of the barrier metal made of the titanium nitride (TiN) film in the trench. However, under the supply rate limiting condition, the barrier metal made of titanium nitride (TiN) changes when the surface area of the pattern changes, so the thickness of the barrier metal made of titanium nitride (TiN) cannot be controlled / managed. There is a problem.
　したがって、本発明の目的は、バリアメタルを薄膜化し、且つ金属電極との密着性を確保し、且つ薄膜での膜厚制御・管理をすることができる、半導体装置およびその製造方法を提供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the thickness of the barrier metal, ensure adhesion with the metal electrode, and can control and manage the film thickness of the thin film. It is in.
［実施形態］
　次に、本発明の実施形態の要旨について説明する。 [Embodiment]
Next, the gist of the embodiment of the present invention will be described.
　窒化チタン（ＴｉＮ）は、３ｎｍ以下で成膜すると不連続膜になるため、トレンチ表面のタングステン（Ｗ）との密着性が悪い。 Titanium nitride (TiN) becomes a discontinuous film when deposited at 3 nm or less, and therefore has poor adhesion to tungsten (W) on the trench surface.
　反応律速条件では膜厚制御は可能であるが、トレンチ内の窒化チタン（ＴｉＮ）膜の膜厚を３ｎｍ以下に薄膜化できない。 Although the film thickness can be controlled under reaction-controlled conditions, the thickness of the titanium nitride (TiN) film in the trench cannot be reduced to 3 nm or less.
　また、前述したように、窒化チタン（ＴｉＮ）のガス条件を反応律速領域から反応律速領域に変更して、ガバレッジを１００％から５０％にすると、タングステン（Ｗ）との密着性は向上し、トレンチ内の窒化チタン（ＴｉＮ）膜の膜厚も３ｎｍ以下に薄膜化することは可能である。しかしながら、表面積変動の影響を大きく受けるため、膜厚制御・管理ができない、という課題がある。 Further, as described above, when the gas condition of titanium nitride (TiN) is changed from the reaction rate limiting region to the reaction rate limiting region and the coverage is changed from 100% to 50%, the adhesion with tungsten (W) is improved. The film thickness of the titanium nitride (TiN) film in the trench can be reduced to 3 nm or less. However, there is a problem that the film thickness cannot be controlled and managed because it is greatly affected by the surface area fluctuation.
　そこで、本発明の実施形態では、トレンチ内の窒化チタン（ＴｉＮ）膜から成るバリアメタルの膜厚をカバレッジ１００％の成膜条件で制御・管理し、タングステン（Ｗ）から成る金属電極との密着性はトレンチ表面のみに成膜できる条件で、且つ２段階の成膜をｉｎ－ｓｉｔｕで行っている。これにより、処理能力を落とすこと無く、トレンチ内の窒化チタン（ＴｉＮ）膜から成るバリアメタルの膜厚を２ｎｍよりも薄膜化でき、最終的にワード線の抵抗低減が可能になる。 Therefore, in the embodiment of the present invention, the film thickness of the barrier metal made of the titanium nitride (TiN) film in the trench is controlled and managed under the film forming conditions with a coverage of 100%, and the metal electrode made of tungsten (W) is adhered. The properties are such that the film can be formed only on the trench surface, and two-stage film formation is performed in-situ. As a result, the thickness of the barrier metal made of a titanium nitride (TiN) film in the trench can be made thinner than 2 nm without degrading the processing capability, and finally the resistance of the word line can be reduced.
　以下、図面を参照して、本発明の第１の実施例について詳細に説明する。 The first embodiment of the present invention will be described in detail below with reference to the drawings.
　以下の図面においては、各構成をわかりやすくするために、実際の構造と各構造における縮尺や数等が異なっている。また、ＸＹＺ座標系を設定し、各構成の配置を説明する。この座標系において、Ｚ方向は半導体基板であるシリコン基板の表面に垂直な方向であり、Ｘ方向はシリコン基板の表面と水平な面においてＺ方向と直交する方向であって、Ｙ方向はシリコン基板の表面と水平な面においてＸ方向と直交する方向である。また、Ｘ’方向は、Ｘ方向に対して斜めに傾いた方向である。 In the following drawings, the scale and number of each structure are different from each other in order to make each configuration easy to understand. In addition, an XYZ coordinate system is set and the arrangement of each component will be described. In this coordinate system, the Z direction is a direction perpendicular to the surface of the silicon substrate which is a semiconductor substrate, the X direction is a direction perpendicular to the Z direction on a plane parallel to the surface of the silicon substrate, and the Y direction is a silicon substrate. It is a direction orthogonal to the X direction in a plane parallel to the surface of The X ′ direction is a direction inclined obliquely with respect to the X direction.
　図１～図１０は、本発明の第１の実施例による半導体装置１００の構造およびその製造方法を示す図である。第１の実施例による半導体装置１００はＤＲＡＭ（dynamic random access memory）メモリセルである。図１は半導体装置１００の平面図を示し、図２は図１のＡ－Ａ’断面図を示し、図３～図１０は半導体装置１００の一連の製造工程断面図を示している。 1 to 10 are views showing a structure of a semiconductor device 100 according to a first embodiment of the present invention and a manufacturing method thereof. The semiconductor device 100 according to the first embodiment is a DRAM (dynamic random access memory) memory cell. 1 is a plan view of the semiconductor device 100, FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG. 1, and FIGS. 3 to 10 are cross-sectional views showing a series of manufacturing steps of the semiconductor device 100.
　最初に、図１の平面図を参照して、第１の実施例の半導体装置１００について説明する。 First, the semiconductor device 100 of the first embodiment will be described with reference to the plan view of FIG.
　半導体装置１００はＤＲＡＭメモリセルを構成するものである。半導体基板であるシリコン基板１（図２参照）上において、Ｘ’方向に連続して延在する素子分離領域１２と、同じくＸ’方向に連続して延在する活性領域１３とが、Ｙ方向に交互に等間隔、等ピッチで複数配置されている。素子分離領域１２は溝に埋設した素子分離絶縁膜で構成されている。複数の素子分離領域１２および複数の活性領域１３に跨って、Ｙ方向に連続して延在する埋め込みワード線１０（１０ａ、１０ｂ）が配置されている。 The semiconductor device 100 constitutes a DRAM memory cell. On a silicon substrate 1 (see FIG. 2), which is a semiconductor substrate, an element isolation region 12 that continuously extends in the X ′ direction and an active region 13 that also extends continuously in the X ′ direction include a Y direction. A plurality of them are alternately arranged at equal intervals and at equal pitches. The element isolation region 12 is composed of an element isolation insulating film embedded in the trench. A buried word line 10 (10a, 10b) extending continuously in the Y direction is disposed across the plurality of element isolation regions 12 and the plurality of active regions 13.
　ここでは、図１の左側に配置された埋め込みワード線１０を第１ワード線１０ａと呼び、図１の右側に配置された埋め込みワード線１０を第２ワード線１０ｂと呼ぶことにする。 Here, the embedded word line 10 arranged on the left side in FIG. 1 is called a first word line 10a, and the embedded word line 10 arranged on the right side in FIG. 1 is called a second word line 10b.
　第１ワード線１０ａの左側に隣接して第１容量コンタクト領域３７ａが配置され、第２ワード線１０ｂの右側に隣接して第２容量コンタクト領域３７ｂが配置されている。第１ワード線１０ａと第２ワード線１０ｂとの間に隣接してビット線コンタクト領域３２が配置されている。 The first capacitor contact region 37a is disposed adjacent to the left side of the first word line 10a, and the second capacitor contact region 37b is disposed adjacent to the right side of the second word line 10b. A bit line contact region 32 is disposed adjacent to the first word line 10a and the second word line 10b.
　活性領域１３は、第１容量コンタクト領域３７ａと、第１ワード線１０ａと、ビット線コンタクト領域３２と、第２ワード線１０ｂと、第２容量コンタクト領域３７ｂと、で構成されている。第１容量コンタクト領域３７ａと、第１ワード線１０ａと、ビット線コンタクト領域３２と、で第１セルトランジスタＴｒ１が構成されている。ビット線コンタクト領域３２と、第２ワード線１０ｂと、第２容量コンタクト領域３７ｂと、で第２セルトランジスタＴｒ２が構成されている。 The active region 13 includes a first capacitor contact region 37a, a first word line 10a, a bit line contact region 32, a second word line 10b, and a second capacitor contact region 37b. A first cell transistor Tr1 is configured by the first capacitor contact region 37a, the first word line 10a, and the bit line contact region 32. The bit line contact region 32, the second word line 10b, and the second capacitor contact region 37b constitute a second cell transistor Tr2.
　次に図２を参照すると、シリコン基板１に、トランジスタのゲート電極を兼ねるワード線用のゲートトレンチ１４が設けられている。各々のワード線用のゲートトレンチ１４の内面を覆う熱酸化膜で構成されるゲート絶縁膜５を介して、第１ワード線１０ａおよび第２ワード線１０ｂが各々のゲートトレンチ１４の底部に設けられている。各々のワード線を覆い、且つ、各々のゲートトレンチ１４を埋設してキャップ絶縁膜２７が設けられている。 Next, referring to FIG. 2, a silicon substrate 1 is provided with a gate trench 14 for a word line that also serves as a gate electrode of a transistor. A first word line 10 a and a second word line 10 b are provided at the bottom of each gate trench 14 via a gate insulating film 5 formed of a thermal oxide film covering the inner surface of each word line gate trench 14. ing. A cap insulating film 27 is provided so as to cover each word line and bury each gate trench 14.
　第１ワード線１０ａの左側に位置する半導体ピラーは、第１容量コンタクト領域３７ａとなり、その上面にはソース／ドレインの一方となる不純物拡散層２９ａが設けられている。第１ワード線１０ａと第２ワード線１０ｂの間に位置する半導体ピラーは、ビット線コンタクト領域３２となり、その上面にはソース／ドレインの他の一方となる不純物拡散層２８が設けられている。 The semiconductor pillar located on the left side of the first word line 10a becomes the first capacitor contact region 37a, and an impurity diffusion layer 29a serving as one of the source / drain is provided on the upper surface thereof. The semiconductor pillar located between the first word line 10a and the second word line 10b becomes the bit line contact region 32, and an impurity diffusion layer 28 serving as the other of the source / drain is provided on the upper surface thereof.
　また、第２ワード線１０ｂの右側に位置する半導体ピラーは、第２容量コンタクト領域３７ｂとなり、その上面にはソース／ドレインの一方となる不純物拡散層２９ｂが設けられている。 Further, the semiconductor pillar located on the right side of the second word line 10b becomes the second capacitor contact region 37b, and an impurity diffusion layer 29b serving as one of the source / drain is provided on the upper surface thereof.
　不純物拡散層２９ａとゲート絶縁膜５と第１ワード線１０ａと不純物拡散層２８とで第１のトランジスタＴｒ１（図１）が構成されている。また、不純物拡散層２８とゲート絶縁膜５と第２ワード線１０ｂと不純物拡散層２９ｂとで第２のトランジスタＴｒ２（図１）が構成されている。各々のワード線上面を覆うように、キャップ絶縁膜２７が設けられている。 The impurity diffusion layer 29a, the gate insulating film 5, the first word line 10a, and the impurity diffusion layer 28 constitute a first transistor Tr1 (FIG. 1). The impurity diffusion layer 28, the gate insulating film 5, the second word line 10b, and the impurity diffusion layer 29b constitute the second transistor Tr2 (FIG. 1). A cap insulating film 27 is provided so as to cover the upper surface of each word line.
　素子分離領域１２の上面および不純物拡散層２９ａ、２９ｂが形成されたシリコン基板１の上面には、ゲートトレンチ１４を形成する際のマスクとして用いた酸化シリコン膜からなる第１層間絶縁膜７が設けられている。 A first interlayer insulating film 7 made of a silicon oxide film used as a mask for forming the gate trench 14 is provided on the upper surface of the element isolation region 12 and the upper surface of the silicon substrate 1 on which the impurity diffusion layers 29a and 29b are formed. It has been.
　キャップ絶縁膜２７上には、ビット線コンタクト領域３２において不純物拡散層２８に接続されるビット線（ＢＬ）２６が設けられる。ＢＬ２６の上面にはカバー絶縁膜３３が設けられている。ＢＬ２６の側壁を覆うように、全面にライナー絶縁膜３４が設けられている。ライナー絶縁膜３４上には、隣接するＢＬ間に形成されている凹部空間を埋設するＳＯＤ（Spin On Dielectric）膜３５が設けられている。 On the cap insulating film 27, a bit line (BL) 26 connected to the impurity diffusion layer 28 in the bit line contact region 32 is provided. A cover insulating film 33 is provided on the upper surface of BL26. A liner insulating film 34 is provided on the entire surface so as to cover the side wall of the BL 26. An SOD (SpinＳＯOnＳＯDielectric) film 35 is provided on the liner insulating film 34 so as to bury a recessed space formed between adjacent BLs.
　ＳＯＤ膜３５、ライナー膜３４、および第１層間絶縁膜７を貫通して、２つの容量コンタクトホールが設けられている。これら容量コンタクトホールによって、第１および第２容量コンタクト領域３７ａ、３７ｂに各々第１および第２容量コンタクトプラグ３８ａ、３８ｂが接続している。第１および第２容量コンタクトプラグ３８ａ、３８ｂの上部に各々第１および第２容量コンタクトパッド４２ａ、４２ｂが接続している。容量コンタクトパッド４２を覆うように、ストッパー窒化膜４３が設けられる。容量コンタクトパッド４２上にはキャパシタ下部電極４４が設けられる。キャパシタ下部電極４４の内表面を覆う容量絶縁膜４５が設けられ、容量絶縁膜４５上にキャパシタ上部ポリシリコン電極４６、キャパシタ上部タングステン電極４７が設けられている。 Two capacitive contact holes are provided through the SOD film 35, the liner film 34, and the first interlayer insulating film 7. The first and second capacitor contact plugs 38a and 38b are connected to the first and second capacitor contact regions 37a and 37b through the capacitor contact holes, respectively. First and second capacitor contact pads 42a and 42b are connected to the upper portions of the first and second capacitor contact plugs 38a and 38b, respectively. A stopper nitride film 43 is provided so as to cover the capacitor contact pad 42. A capacitor lower electrode 44 is provided on the capacitor contact pad 42. A capacitor insulating film 45 covering the inner surface of the capacitor lower electrode 44 is provided, and a capacitor upper polysilicon electrode 46 and a capacitor upper tungsten electrode 47 are provided on the capacitor insulating film 45.
　そして、キャパシタ上部タングステン電極４７上に配線４８と第２層間絶縁膜４９とが設けられている。 A wiring 48 and a second interlayer insulating film 49 are provided on the capacitor upper tungsten electrode 47.
　以下、図３～図１０を用いて、図１～図２に示した半導体装置１００の製造方法について説明する。図３～図１０は、図１におけるＡ－Ａ’断面図を示している。 Hereinafter, a method of manufacturing the semiconductor device 100 shown in FIGS. 1 to 2 will be described with reference to FIGS. 3 to 10 are cross-sectional views taken along line A-A ′ in FIG.
　まず、図３に示すように、半導体基板であるシリコン基板１の上に、周知のＳＴＩ（Shallow Trench Isolation）法により、酸化シリコン膜からなる絶縁膜で埋設された素子分離領域１２（図１）を形成する。これにより、素子分離領域１２で囲まれ、シリコン基板１からなる活性領域１３（図１）が形成される。 First, as shown in FIG. 3, an element isolation region 12 (FIG. 1) embedded in an insulating film made of a silicon oxide film on a silicon substrate 1 which is a semiconductor substrate by a well-known STI (Shallow Trench Isolation) method. Form. Thus, an active region 13 (FIG. 1) that is surrounded by the element isolation region 12 and made of the silicon substrate 1 is formed.
　次に、シリコン基板１上全面に酸化シリコン膜からなるパッド酸化膜２を形成し、このパッド酸化膜２を通して、Ｐウェル領域を公知の方法で形成する。 Next, a pad oxide film 2 made of a silicon oxide film is formed on the entire surface of the silicon substrate 1, and a P well region is formed through the pad oxide film 2 by a known method.
　そして、図４に示すように、シリコン基板１上にシリコン酸化膜等からなる第１層間絶縁膜７を堆積（形成）する。 Then, as shown in FIG. 4, a first interlayer insulating film 7 made of a silicon oxide film or the like is deposited (formed) on the silicon substrate 1.
　次に、図５に示すように、レジスト（図示せず）にて第１層間絶縁膜７をパターニングし、シリコン基板１をドライエッチングによってエッチングし、ゲートトレンチ１４を形成する。その後、ゲートトレンチ１４の表面（内壁）を熱酸化（ＩＳＳＧ：In Site Steam Generation）により酸化させることによって、シリコン酸化膜からなるゲート絶縁膜５を形成する。 Next, as shown in FIG. 5, the first interlayer insulating film 7 is patterned with a resist (not shown), and the silicon substrate 1 is etched by dry etching to form a gate trench 14. Thereafter, the surface (inner wall) of the gate trench 14 is oxidized by thermal oxidation (ISSG: In Site Steam Generation), thereby forming the gate insulating film 5 made of a silicon oxide film.
　ここで、ゲートトレンチ１４は、活性領域１３から素子分離領域１２へ渡って連続して延在している。 Here, the gate trench 14 extends continuously from the active region 13 to the element isolation region 12.
　次に、電極となる窒化チタン（ＴｉＮ）から成るバリアメタルを成膜する。窒化チタン（ＴｉＮ）から成るバリアメタルの成膜を、関連技術では、同一ガス条件で行っていたが、本発明の第１の実施例では、後述するように、２段階に分け、ｉｎ－ｓｉｔｅで行う。 Next, a barrier metal made of titanium nitride (TiN) to be an electrode is formed. In the related art, the film formation of the barrier metal made of titanium nitride (TiN) is performed under the same gas conditions. However, in the first embodiment of the present invention, as described later, the film is divided into two stages and in-site. To do.
　まず、図６に示すように、ゲート絶縁膜５を覆うように、四塩化チタン（ＴｉＣｌ４）ガスとアンモニア（ＮＨ３）ガスを用いたＡＬＤ（Atomic Layer Deposition）法で、第１窒化チタン６ａを１ｎｍ形成する。ここでの形成条件は、ＴｉＣｌ４／ＮＨ３流量比をほぼ１とした反応律速条件となる。カバレッジが１００％となるように、ガス条件を最適化する。本例では、トレンチ幅１２ｎｍ、深さ１８０ｎｍの場合、成膜条件は、例えば、四塩化チタン（ＴｉＣｌ４）ガスとアンモニア（ＮＨ３）ガスとをそれぞれ６０ｓｃｃｍの流量で行う。但し、カバレッジが悪化しないように、四塩化チタン（ＴｉＣｌ４）ガスの流量とアンモニア（ＮＨ３）ガスの流量は、調整可能である。 First, as shown in FIG. 6, the first titanium nitride 6a is covered by an ALD (Atomic Layer Deposition) method using titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas so as to cover the gate insulating film 5. 1 nm is formed. The formation conditions here are reaction rate-limiting conditions with a TiCl 4 / NH 3 flow rate ratio of approximately 1. The gas conditions are optimized so that the coverage is 100%. In this example, when the trench width is 12 nm and the depth is 180 nm, the film forming conditions are, for example, titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) gas at a flow rate of 60 sccm. However, the flow rate of titanium tetrachloride (TiCl 4 ) gas and the flow rate of ammonia (NH 3 ) gas can be adjusted so that the coverage does not deteriorate.
　尚、第１窒化チタン６ａは、第１のバリアメタルと呼ばれる。反応律速条件は第１の成膜条件と呼ばれる。 The first titanium nitride 6a is called a first barrier metal. The reaction-controlling condition is called the first film forming condition.
　ここで、前述したように、窒化チタン（ＴｉＮ）は、３ｎｍ以下で成膜すると不連続膜となるため、後で形成するタングステン（Ｗ）との密着性が悪くなることに注意されたい。 Note that, as described above, titanium nitride (TiN) becomes a discontinuous film when deposited at 3 nm or less, so that adhesion with tungsten (W) to be formed later is deteriorated.
　そこで、本発明の第１の実施例では、図７に示すように、第１窒化チタン６ａの上部に、ゲートトレンチ１４外の平坦部において、四塩化チタン（ＴｉＣｌ４）ガスとアンモニア（ＮＨ３）ガスを用いたＡＬＤ（Atomic Layer Deposition）法で、第２窒化チタン６ｂを、第１窒化チタン６ａと合わせて膜厚３ｎｍになるように形成する。 Therefore, in the first embodiment of the present invention, as shown in FIG. 7, titanium tetrachloride (TiCl 4 ) gas and ammonia (NH 3 ) are formed on the first titanium nitride 6 a on the flat portion outside the gate trench 14. ) The second titanium nitride 6b and the first titanium nitride 6a are formed to have a film thickness of 3 nm by an ALD (Atomic Layer Deposition) method using a gas.
　ここでは、四塩化チタン（ＴｉＣｌ４）ガスの流量を絞り込んで、かつアンモニア（ＮＨ３）ガスの流量を増加させることにより、供給律速条件として、ゲートトレンチ１４内部にはごくわずかしか成膜されない条件（カバレッジが０％）を用いる。換言すれば、四塩化チタン（ＴｉＣｌ４）ガスの分圧を下げることによって、四塩化チタン（ＴｉＣｌ４）ガスの流量を低流量化し、且つ、アンモニア（ＮＨ３）ガスの流量を高流量に設定する。 Here, the flow rate of titanium tetrachloride (TiCl 4 ) gas is narrowed down and the flow rate of ammonia (NH 3 ) gas is increased, so that a very small amount of film is formed inside the gate trench 14 as the supply rate limiting condition. (Coverage is 0%). In other words, by lowering the partial pressure of titanium tetrachloride (TiCl 4) gas, the flow rate of titanium tetrachloride (TiCl 4) gas and low flow rate reduction, and, setting ammonia flow rate of (NH 3) gas at a high flow rate To do.
　尚、第２窒化チタン６ｂは、第２のバリアメタルと呼ばれる。供給律速条件は、第２の成膜条件と呼ばれる。 The second titanium nitride 6b is called a second barrier metal. The supply rate limiting condition is referred to as a second film forming condition.
　したがって、ゲートトレンチ１４の内部において、第２のバリアメタル６ｂの膜厚は、第１のバリアメタル６ａの膜厚より薄い。換言すれば、第２の成膜条件で形成した第２のバリアメタル６ｂのステップカバレージは、第１の成膜条件で形成した第１のバリアメタル６ａのステップカバレージより悪い。 Therefore, the film thickness of the second barrier metal 6b is thinner than the film thickness of the first barrier metal 6a inside the gate trench 14. In other words, the step coverage of the second barrier metal 6b formed under the second film formation conditions is worse than the step coverage of the first barrier metal 6a formed under the first film formation conditions.
　第１窒化チタン６ａおよび第２窒化チタン６ｂは、同一チャンバ内で連続成長することにより、処理能力を落とすこと無く形成できる。第２窒化チタン６ｂを追加成膜することにより、ゲートトレンチ１４外平坦部での窒化チタン（バリアメタル）の膜厚が厚い連続膜となり、後で形成するタングステン（Ｗ）から成る金属電極との密着性は確保できる。また、ゲートトレンチ１４の内部は、ウェハ面積に比較して非常に面積が小さく、かつタングステン（Ｗ）の膜応力方向が平坦部に対して直角であるので、窒化チタンの膜厚が薄くてもタングステン（Ｗ）との密着性は低下しない。 The first titanium nitride 6a and the second titanium nitride 6b can be formed without reducing the processing capability by continuously growing in the same chamber. By additionally forming the second titanium nitride 6b, a continuous film having a thick titanium nitride (barrier metal) film on the flat portion outside the gate trench 14 is formed, and a metal electrode made of tungsten (W) to be formed later is formed. Adhesion can be secured. In addition, since the area inside the gate trench 14 is very small compared to the wafer area and the film stress direction of tungsten (W) is perpendicular to the flat portion, even if the film thickness of titanium nitride is small. Adhesiveness with tungsten (W) does not decrease.
　その後、図８に示すように、ＣＶＤ法でタングステン（Ｗ）９から成る金属電極を埋設する。ここでは、タングステン（Ｗ）９を、核形成ステップとメインステップとの２ステップで成膜する。 Thereafter, as shown in FIG. 8, a metal electrode made of tungsten (W) 9 is buried by CVD. Here, tungsten (W) 9 is formed in two steps, a nucleus formation step and a main step.
　すなわち、第１および第２窒化チタン６ａ、６ｂの上部に、例えば、六弗化タングステン（ＷＦ６）をジボラン（Ｂ２Ｈ６）で還元して核を形成し、ＷＦ６／Ｈ２でタングステン配線本体を形成する。 That is, for example, tungsten hexafluoride (WF 6 ) is reduced with diborane (B 2 H 6 ) to form a nucleus on top of the first and second titanium nitrides 6a and 6b, and tungsten is formed with WF 6 / H 2 . A wiring body is formed.
　詳述すると、最初に、モノシラン（ＳｉＨ４）を流して、窒化チタン（ＴｉＮ）を表面処理し、核形成ステップでは、例えば、３５０℃の温度、１０００ｐａの圧力下で、六弗化タングステン（ＷＦ６）とモノシラン（ＳｉＨ４）をパージしながら交互にガスフローを繰り返して成膜する。モノシラン（ＳｉＨ４）の代わりに、ジボラン（Ｂ２Ｈ６）や水素（Ｈ２）を用いてもよい。トレンチ幅が１２ｎｍの場合、ジボラン（Ｂ２Ｈ６）が最も比抵抗を低減できる。その後、タングステン（Ｗ）のメインステップでは、例えば、３９０℃の温度、１０６６６ｐａの圧力下で、六弗化タングステン（ＷＦ６）と水素（Ｈ２）とを同時に流して成膜する。 More specifically, first, monosilane (SiH 4 ) is flowed to surface-treat titanium nitride (TiN). In the nucleation step, for example, tungsten hexafluoride (WF) is used at a temperature of 350 ° C. and a pressure of 1000 pa. 6 ) and film formation by alternately repeating the gas flow while purging monosilane (SiH 4 ). Diborane (B 2 H 6 ) or hydrogen (H 2 ) may be used instead of monosilane (SiH 4 ). When the trench width is 12 nm, diborane (B 2 H 6 ) can reduce the specific resistance most. Thereafter, in the main step of tungsten (W), for example, tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) are simultaneously flowed at a temperature of 390 ° C. and a pressure of 10666 pa to form a film.
　ここで、ゲートトレンチ１４内の第１窒化チタン６ａの膜厚は１ｎｍと薄いため、ゲートトレンチ１４内のタングステン（Ｗ）９の断面積が大きくなり、ワード線１０の抵抗を低くすることができる。 Here, since the film thickness of the first titanium nitride 6a in the gate trench 14 is as thin as 1 nm, the sectional area of the tungsten (W) 9 in the gate trench 14 is increased, and the resistance of the word line 10 can be lowered. .
　この時、ゲートトレンチ１４外の平坦部では、第２窒化チタン６ｂを追加成膜し厚くしているので、タングステン（Ｗ）９から成る金属電極の引っ張り応力による膜はがれは生じない。 At this time, since the second titanium nitride 6b is additionally formed and thickened in the flat portion outside the gate trench 14, no film peeling due to the tensile stress of the metal electrode made of tungsten (W) 9 occurs.
　この段階でゲートトレンチ１４は、第１窒化チタン６ａ、第２窒化チタン６ｂ、およびタングステン（Ｗ）９からなる積層膜で完全に埋設された状態となる。 At this stage, the gate trench 14 is completely buried with a laminated film made of the first titanium nitride 6a, the second titanium nitride 6b, and tungsten (W) 9.
　次いで、図９に示すように、第１窒化チタン６ａ、第２窒化チタン６ｂ、およびタングステン（Ｗ）からなる積層膜をドライエッチング法によりエッチバックして、ゲートトレンチ１４内に埋設された、第１窒化チタン６ａ、第２窒化チタン６ｂ、およびタングステン（Ｗ）からなる埋め込みゲート電極１０ａ、１０ｂを形成する。この埋め込みゲート電極１０ａ、１０ｂはワード線を構成する。ゲートトレンチ１４内に埋め込みゲート電極１０ａ、１０ｂが形成される結果、埋め込みゲート電極１０ａ、１０ｂの上方に新たなトレンチが形成される。 Next, as shown in FIG. 9, the laminated film made of the first titanium nitride 6a, the second titanium nitride 6b, and tungsten (W) is etched back by a dry etching method, and buried in the gate trench 14. Embedded gate electrodes 10a and 10b made of a titanium nitride 6a, a second titanium nitride 6b, and tungsten (W) are formed. The buried gate electrodes 10a and 10b constitute a word line. As a result of forming the buried gate electrodes 10a and 10b in the gate trench 14, a new trench is formed above the buried gate electrodes 10a and 10b.
　引き続いて、新たなトレンチを埋設するように全面に窒化シリコン（ＳｉＮ）膜からなるキャップ絶縁膜２７をＣＶＤ法により形成し、ＣＭＰ（Chemical Mechanical Polishing）を行って、表面の窒化シリコン（ＳｉＮ）膜を除去する。 Subsequently, a cap insulating film 27 made of a silicon nitride (SiN) film is formed on the entire surface by a CVD method so as to bury a new trench, and CMP (Chemical-Mechanical-Polishing) is performed to form a silicon nitride (SiN) film on the surface. Remove.
　したがって、第１のバリアメタル６ａ、第２のバリアメタル６ｂ、金属電極９およびキャップ絶縁膜２７は、ゲートトレンチ１４内にあって活性領域１３から素子分離領域１３へ渡って連続して延伸している。 Accordingly, the first barrier metal 6a, the second barrier metal 6b, the metal electrode 9 and the cap insulating film 27 are continuously extended from the active region 13 to the element isolation region 13 in the gate trench 14. Yes.
　次に図１０に示すように、ビット線２６を形成する。 Next, as shown in FIG. 10, a bit line 26 is formed.
　詳述すると、フォトリソグラフィ技術およびドライエッチング技術を用いて、第１層間絶縁膜７の一部を除去し、ビット線コンタクト領域３２（図１）の上面に接続するビットコンタクトを形成する。ビットコンタクトは、ワード線１０と同じ方向（図１のＹ方向）に延在するライン状の開口パターンとして形成される。ビットコンタクトのパターンと活性領域の交差した部分では、シリコン基板１の表面が露出する。 More specifically, a part of the first interlayer insulating film 7 is removed using a photolithography technique and a dry etching technique, and a bit contact connected to the upper surface of the bit line contact region 32 (FIG. 1) is formed. The bit contact is formed as a line-shaped opening pattern extending in the same direction as the word line 10 (Y direction in FIG. 1). At the intersection of the bit contact pattern and the active region, the surface of the silicon substrate 1 is exposed.
　ビットコンタクトを形成した後に、Ｎ型不純物（ヒ素等）をイオン注入し、シリコン表面近傍にＮ型不純物拡散層２８を形成する。形成したＮ型不純物拡散層２８は、トランジスタのソース／ドレイン領域２８として機能する。 After forming the bit contact, an N-type impurity (such as arsenic) is ion-implanted to form an N-type impurity diffusion layer 28 in the vicinity of the silicon surface. The formed N-type impurity diffusion layer 28 functions as a source / drain region 28 of the transistor.
　その後、ポリシリコン膜、タングステン膜、シリコン窒化膜３３等の積層膜をたとえばＣＶＤ法にて形成する。そして、フォトリソグラフィ技術およびドライエッチング技術を用いてライン形状にパターニングし、ビット線２６を形成する。ビット線２６は、ワード線１０と交差する方向（図１のＸ方向）に延在するパターンとして形成される。ビットコンタクト内で露出しているシリコン表面部分で、ビット線２６下層のポリシリコン膜とソース／ドレイン領域２８とが接続する。 Thereafter, a laminated film such as a polysilicon film, a tungsten film, and a silicon nitride film 33 is formed by, for example, a CVD method. Then, the bit line 26 is formed by patterning into a line shape using a photolithography technique and a dry etching technique. The bit line 26 is formed as a pattern extending in a direction intersecting the word line 10 (X direction in FIG. 1). The polysilicon film under the bit line 26 is connected to the source / drain region 28 at the silicon surface portion exposed in the bit contact.
　次に図２に示すように、ビット線２６の側面を覆うシリコン窒化膜を形成した後に、その上面を覆うライナー膜３４をシリコン窒化膜等でたとえばＣＶＤ法を用いて形成する。 Next, as shown in FIG. 2, after forming a silicon nitride film covering the side surface of the bit line 26, a liner film 34 covering the upper surface is formed of a silicon nitride film or the like by using, for example, a CVD method.
　ビット線間のスペース部を充填するように、塗布膜であるＳＯＤ膜３５を堆積した後に、高温の水蒸気（Ｈ２Ｏ）雰囲気中でアニール処理を行い、固体の膜に改質する。ライナー膜３４の上面が露出するまでＣＭＰを行って平坦化する。その後、フォトリソグラフィ技術およびドライエッチング技術を用いて、ＳＯＤ膜３５、ライナー膜３４、第１層間絶縁膜７を貫通して容量コンタクトを形成する。さらに、容量コンタクトの内部に、Ｎ型不純物（リン等）をドーピングしたポリシリコンをたとえばＣＶＤ法を用いて埋め込む。ポリシリコンにドーピングされたＮ型不純物によって、容量コンタクト領域３７ａ、３７ｂの表面近傍にＮ型不純物拡散層２９ａ、２９ｂが形成される。形成されたＮ型不純物拡散層２９ａ、２９ｂは、トランジスタのソース／ドレイン領域として機能する。 After depositing the SOD film 35, which is a coating film, so as to fill the space between the bit lines, an annealing process is performed in a high-temperature steam (H 2 O) atmosphere to modify the film into a solid film. The planarization is performed by CMP until the upper surface of the liner film 34 is exposed. Thereafter, a capacitive contact is formed through the SOD film 35, the liner film 34, and the first interlayer insulating film 7 by using a photolithography technique and a dry etching technique. Further, polysilicon doped with an N-type impurity (phosphorus or the like) is embedded in the capacitor contact by using, for example, a CVD method. N-type impurity diffusion layers 29a and 29b are formed in the vicinity of the surface of the capacitor contact regions 37a and 37b by the N-type impurities doped in the polysilicon. The formed N-type impurity diffusion layers 29a and 29b function as source / drain regions of the transistor.
　次いで、ポリシリコンをエッチバックし、容量コンタクトプラグ３８ａ、３８ｂを完成させる。フォトリソグラフィ技術およびドライエッチング技術を用いて、容量コンタクトパッド４２ａ、４２ｂを形成する。 Next, the polysilicon is etched back to complete the capacitor contact plugs 38a and 38b. Capacitance contact pads 42a and 42b are formed using photolithography technology and dry etching technology.
　次に、容量コンタクトパッド４２ａ、４２ｂ上を覆うように、シリコン窒化膜を用いてストッパー窒化膜４３を形成する。容量コンタクトパッド４２ａ、４２ｂ上に窒化チタン等でキャパシタ下部電極４４を形成する。 Next, a stopper nitride film 43 is formed using a silicon nitride film so as to cover the capacitor contact pads 42a and 42b. A capacitor lower electrode 44 is formed of titanium nitride or the like on the capacitor contact pads 42a and 42b.
　さらに、キャパシタ下部電極４４の表面を覆うように容量絶縁膜４５を形成した後に、キャパシタ上部ポリシリコン電極４６およびキャパシタ上部タングステン電極４７を形成する。 Further, after the capacitor insulating film 45 is formed so as to cover the surface of the capacitor lower electrode 44, the capacitor upper polysilicon electrode 46 and the capacitor upper tungsten electrode 47 are formed.
　その後、キャパシタ上部タングステン電極４７上に配線４８と第２層間絶縁膜４９とを形成して、半導体装置１００を形成する。 Thereafter, a wiring 48 and a second interlayer insulating film 49 are formed on the capacitor upper tungsten electrode 47 to form the semiconductor device 100.
　上記半導体装置１００では、バリアメタルとして、第１のバリアメタル６ａとこの第１のバリアメタル６ｂよりも膜厚の薄い第２のバリアメタル６ｂとの組み合わせを使用しているので、バリアメタルを薄膜化し、且つ金属電極との密着性を確保し、且つ薄膜での膜厚制御・管理をすることができる。 In the semiconductor device 100, a combination of the first barrier metal 6a and the second barrier metal 6b having a thickness smaller than that of the first barrier metal 6b is used as the barrier metal. In addition, the adhesion to the metal electrode can be secured, and the film thickness can be controlled and managed with a thin film.
　以上、本発明の好ましい実施例について説明したが、本発明は、上記の実施例に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。 The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.
　例えば、上述した第１の実施例では、埋め込みゲート電極（ワード線）１０として、第１窒化チタン６ａ、第２窒化チタン６ｂ、およびタングステン（Ｗ）９を順次積層した膜を使用しているが、本発明は、これに限定されず、以下に述べるような種々の変形例を採用することができる。 For example, in the first embodiment described above, a film in which a first titanium nitride 6a, a second titanium nitride 6b, and tungsten (W) 9 are sequentially stacked is used as the buried gate electrode (word line) 10. The present invention is not limited to this, and various modifications as described below can be adopted.
（変形例）
　第１および第２のバリアメタルとして、第１および第２窒化チタン６ａ、６ｂの代わりに窒化された第１金属を使用してよい。また、金属電極として、タングステン（Ｗ）９の代わりに第２金属を使用してよい。 (Modification)
As the first and second barrier metals, a nitrided first metal may be used instead of the first and second titanium nitrides 6a and 6b. Moreover, you may use a 2nd metal instead of tungsten (W) 9 as a metal electrode.
　この場合、第１金属および第２金属の各々は、高融点金属であればよい。高融点金属は、タングステン、コバルト、チタン、モリブデン、およびタンタルのグループから選択されるものでよい。 In this case, each of the first metal and the second metal may be a refractory metal. The refractory metal may be selected from the group of tungsten, cobalt, titanium, molybdenum, and tantalum.
　以上、実施例を参照して本発明を説明したが、本発明は上記実施例に限定されるものではない。本発明の構成や詳細には、本発明のスコープ内で当業者が理解し得る様々な変更をすることができる。 Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.
　本発明は、ＤＲＡＭの埋め込みゲート電極に限定せず、ＰＲＡＭ（Phase-Change Random Access Memory）、ＲｅＲＡＭ（Resistive Random Access Memory）等を含めた製品全般の埋め込みゲート電極に適応可能である。 The present invention is not limited to the embedded gate electrode of the DRAM, but can be applied to embedded gate electrodes for all products including PRAM (Phase-Change Random Access Memory), ReRAM (Resistive Random Access Memory), and the like.
　この出願は、２０１３年２月７日に出願された日本出願特願２０１３－０２１９７９号を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2013-021979 filed on Feb. 7, 2013, the entire disclosure of which is incorporated herein.
　　　１　　シリコン基板（半導体基板）
　　　２　　パッド酸化膜
　　　５　　ゲート絶縁膜
　　　６ａ　　第１窒化チタン（第１のバリアメタル）
　　　６ｂ　　第２窒化チタン（第２のバリアメタル）
　　　７　　第１層間絶縁膜
　　　９　　タングステン（金属電極）
　　　１０、１０ａ、１０ｂ　ワード線
　　　１２　　素子分離領域
　　　１３　　活性領域
　　　１４　　ゲートトレンチ（トレンチ）
　　　２６　　ビット線
　　　２７　　キャップ絶縁膜
　　　２８　　不純物拡散層（ソース／ドレイン領域）
　　　２９ａ、２９ｂ　　不純物拡散層
　　　３２　　ビット線コンタクト領域
　　　３４　　ライナー絶縁膜
　　　３５　　ＳＯＤ膜
　　　３７ａ　　第１容量コンタクト領域
　　　３７ｂ　　第２容量コンタクト領域
　　　３８ａ　　第１容量コンタクトプラグ
　　　３８ｂ　　第２容量コンタクトプラグ
　　　４２ａ　　第１容量コンタクトパッド
　　　４２ｂ　　第２容量コンタクトパッド
　　　４３　　ストッパー窒化膜
　　　４４　　キャパシタ下部電極
　　　４５　　容量絶縁膜
　　　４６　　キャパシタ上部ポリシリコン電極
　　　４７　　キャパシタ上部タングステン電極
　　　４８　　配線
　　　４９　　第２層間絶縁膜
　　　１００　　半導体装置
　　　Ｔｒ１　　第１セルトランジスタ
　　　Ｔｒ２　　第２セルトランジスタ 1 Silicon substrate (semiconductor substrate)
2 Pad oxide film 5 Gate insulating film 6a First titanium nitride (first barrier metal)
6b Second titanium nitride (second barrier metal)
7 First interlayer insulating film 9 Tungsten (metal electrode)
10, 10a, 10b Word line 12 Element isolation region 13 Active region 14 Gate trench (trench)
26 Bit line 27 Cap insulating film 28 Impurity diffusion layer (source / drain region)
29a, 29b Impurity diffusion layer 32 Bit line contact region 34 Liner insulating film 35 SOD film 37a First capacitor contact region 37b Second capacitor contact region 38a First capacitor contact plug 38b Second capacitor contact plug 42a First capacitor contact pad 42b First 2-capacitor contact pad 43 Stopper nitride film 44 Capacitor lower electrode 45 Capacitor insulating film 46 Capacitor upper polysilicon electrode 47 Capacitor upper tungsten electrode 48 Wiring 49 Second interlayer insulating film 100 Semiconductor device Tr1 First cell transistor Tr2 Second cell transistor

Claims (17)

  1. 　半導体基板上の活性領域と、
    　前記活性領域内にあって下部と上部を有するトレンチと、
    　前記トレンチの内壁面を覆うゲート絶縁膜と、
    　前記ゲート絶縁膜を介して前記トレンチ下部を覆う第１のバリアメタルと、
    　前記第１のバリアメタルを覆う第２のバリアメタルと、
    　前記第２のバリアメタルを覆い、前記トレンチ下部を埋設する金属電極と、
    　前記トレンチの上部を埋設するキャップ絶縁膜と、を備え、
    　前記第２のバリアメタルの膜厚は前記第１のバリアメタルの膜厚より薄い、半導体装置。     An active region on a semiconductor substrate;
    A trench in the active region and having a lower portion and an upper portion;
    A gate insulating film covering an inner wall surface of the trench;
    A first barrier metal that covers the lower portion of the trench through the gate insulating film;
    A second barrier metal covering the first barrier metal;
    A metal electrode covering the second barrier metal and burying the trench lower part;
    A cap insulating film for burying the upper portion of the trench,
    The semiconductor device, wherein a film thickness of the second barrier metal is thinner than a film thickness of the first barrier metal.
  2. 　前記半導体基板は前記活性領域を囲む素子分離領域を更に有し、
    　前記トレンチは前記活性領域から前記素子分離領域へ渡って連続して延在し、
    　前記第１のバリアメタル、前記第２のバリアメタル、前記金属電極および前記キャップ絶縁膜は前記トレンチ内にあって前記活性領域から前記素子分離領域へ渡って連続して延伸する、
    請求項１に記載の半導体装置。     The semiconductor substrate further has an element isolation region surrounding the active region,
    The trench extends continuously from the active region to the element isolation region,
    The first barrier metal, the second barrier metal, the metal electrode, and the cap insulating film are in the trench and continuously extend from the active region to the element isolation region;
    The semiconductor device according to claim 1.
  3. 　前記第１および第２のバリアメタルの各々は、窒化された第１金属から成り、
    　前記金属電極は、第２金属から成る、
    請求項１又は２に記載の半導体装置。     Each of the first and second barrier metals comprises a nitrided first metal,
    The metal electrode is made of a second metal.
    The semiconductor device according to claim 1.
  4. 　前記第１金属は、高融点金属から成る、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the first metal is made of a refractory metal.
  5. 　前記第２金属は、高融点金属から成る、請求項３に記載の半導体装置。 4. The semiconductor device according to claim 3, wherein the second metal is made of a refractory metal.
  6. 　前記高融点金属は、タングステン、コバルト、チタン、ニッケル、モリブデン、およびタンタルのグループから選択される請求項４又は５に記載の半導体装置。 6. The semiconductor device according to claim 4, wherein the refractory metal is selected from the group consisting of tungsten, cobalt, titanium, nickel, molybdenum, and tantalum.
  7. 　前記第１のバリアメタルの膜厚は、１ｎｍである請求項１又は２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the film thickness of the first barrier metal is 1 nm.
  8. 　前記トレンチ外の平坦部における、前記第１および第２のバリアメタルの総膜厚は、３ｎｍである、請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein a total film thickness of the first and second barrier metals in a flat portion outside the trench is 3 nm.
  9. 　半導体基板にトレンチを形成し、
    　前記トレンチ内にゲート絶縁膜を形成し、
    　前記ゲート絶縁膜上に第１のバリアメタルを第１の成膜条件で形成し、
    　前記第１のバリアメタル上に前記第１の成膜条件と異なる第２の成膜条件で形成し、
    　前記第２のバリアメタル上に前記トレンチを埋設するように金属材料を形成し、
    　前記トレンチの上部の前記第１のバリアメタル、前記第２のバリアメタル及び前記金属を除去し、
    　前記トレンチの上部をキャップ絶縁膜で埋設する、半導体装置の製造方法。     Forming a trench in a semiconductor substrate;
    Forming a gate insulating film in the trench;
    Forming a first barrier metal on the gate insulating film under a first film-forming condition;
    Forming on the first barrier metal under a second film-forming condition different from the first film-forming condition;
    Forming a metal material so as to bury the trench on the second barrier metal;
    Removing the first barrier metal, the second barrier metal and the metal above the trench;
    A method of manufacturing a semiconductor device, wherein an upper portion of the trench is buried with a cap insulating film.
  10. 　前記第２の成膜条件で形成した第２のバリアメタルのステップカバレージは、前記第１の成膜条件で形成した第１のバリアメタルのステップカバレージより悪い、
    請求項９に記載の半導体装置の製造方法。     The step coverage of the second barrier metal formed under the second film formation condition is worse than the step coverage of the first barrier metal formed under the first film formation condition.
    A method for manufacturing a semiconductor device according to claim 9.
  11. 　前記第１の成膜条件は反応律速条件で、前記第２の成膜条件は供給律速条件である、
    請求項１０に記載の半導体装置の製造方法。     The first film formation condition is a reaction rate-limiting condition, and the second film formation condition is a supply rate-limiting condition.
    A method for manufacturing a semiconductor device according to claim 10.
  12. 　前記第１および第２のバリアメタルの各々は、窒化された第１金属から成り、
    　前記金属電極は、第２金属から成る、
    請求項１０又は１１に記載の半導体装置の製造方法。     Each of the first and second barrier metals comprises a nitrided first metal,
    The metal electrode is made of a second metal.
    12. A method for manufacturing a semiconductor device according to claim 10 or 11.
  13. 　前記第１金属は、高融点金属から成る、請求項１２に記載の半導体装置の製造方法。 13. The method of manufacturing a semiconductor device according to claim 12, wherein the first metal is made of a refractory metal.
  14. 　前記第２金属は、高融点金属から成る、請求項１２に記載の半導体装置の製造方法。 13. The method of manufacturing a semiconductor device according to claim 12, wherein the second metal is made of a refractory metal.
  15. 　前記高融点金属は、タングステン、コバルト、チタン、ニッケル、モリブデン、およびタンタルのグループから選択される請求項１３又は１４に記載の半導体装置の製造方法。 15. The method of manufacturing a semiconductor device according to claim 13, wherein the refractory metal is selected from the group consisting of tungsten, cobalt, titanium, nickel, molybdenum, and tantalum.
  16. 　前記第１のバリアメタルの膜厚は、１ｎｍである請求項１０又は１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 10, wherein the film thickness of the first barrier metal is 1 nm.
  17. 　前記トレンチ外の平坦部における、前記第１および第２のバリアメタルの総膜厚は、３ｎｍである、請求項１６に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 16, wherein a total film thickness of the first and second barrier metals in a flat portion outside the trench is 3 nm.
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