WO2014025714A1

WO2014025714A1 - Method and apparatus for a class-e load tuned beamforming 60 ghz transmitter

Info

Publication number: WO2014025714A1
Application number: PCT/US2013/053681
Authority: WO
Inventors: Jiashu Chen
Original assignee: Tensorcom, Inc.
Priority date: 2012-08-10
Filing date: 2013-08-06
Publication date: 2014-02-13
Also published as: WO2014025713A1

Abstract

The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.

Description

Method and Apparatus for a Ciass-E Load Tuned Beamforming

60 GHz Transmitter

CROSS -REFERENCE TO RELATED APPLICATIONS

[0001 j The present application is related to the co-filed U.S. application Ser, No. 13/572,519 entitled "Method and Apparatus for a Clock and Signal Distribution Network far a 60 GHz

Transmitter System" filed on August .10, 2012, which is assigned to the same assignee as the present application and invented by the same inventor as the present application and incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] The Federal Communication s Commission (FCC) has allotted a spectrum of bandwidth in the 60GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) targets the standardization of this frequency band that will support data transmission rates up to 7 Gbps.

Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelengt range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs.

[0003] CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel transistors and P -channel transistors (MOS transistor) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS transistors. Current channel length examples are 40 nm, the power supply of VDD equals i .2Vand the number of layers of metal levels can he 8 or more. This technology typically scales with technology and can achieve operation in the 60GHz range.

[0004] Transceivers for the 60GHz system have been formed in CMOS and comprise at least one transmitter and at least one receiver which are used to interface to other transceivers in a communication system. The transceivers receive or transmit electrical signals into the L A or the power amplifier, respectively. These electrical signals are generated by or provided to an antenna. The antenna is a transducer that converts incoming electromagnetic energy from free space into electrical signals on the receive side of the transceiver or converts electrical signals into

electromagnetic energy for transfer into free space.

[0005] Conventionally, the design of circuits at 60GHz requires careful layout. One traditional way to distribute a 60GHz; clock is to use transmission line based power splitters and quadrature hybrids whose size are proportional to a quarter wavelength (~600utn). Therefore, the entire distribution network occupies significant area if the circuit components are formed using transmission lines (for example, see the passive power splitter in FIG.7 of Alberto Valdes-Garcia, et al. "A Fully integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications" IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2757-2773. Dec. 2010 and see the quadrature hybrid layout in FIG. 9 of C. Marcu et al., "A 90 van CMOS low-power όϋ-GHz transceiver with integrated baseband circuitry," IEEE J. Solid-State Circuits, vol 44, no. 12, pp. 3434-3447, Dec. 2009). ^'Ore in-phast* clock and quadrature phase clock are applied to these circuit components as these clocks are routed on the surface of the die. Furthermore, the routing from, around and between these circuit components requires power to he dissipated for each interconnect of the in-phase clock and quadrature phase clock traces. In addition, the layout needs to allow the in-phase clock and quadrature phase clock to maintain their 90° separation as these clocks are routed from the source location to their destination location. To overcome this shortcoming, a solution is herein provided that reduces the power dissipation and area of routing these clock lines on a semiconductor die.

[0006] As mentioned above, some circuit components required in multi-tens of GHz clock network distribution designs have been fabricated using transmission lines on the die. However, these circuit components formed on the die would use up valuable real-estate on the semiconductor substrate. For example, a quarter wavelength at 60GHz is 0.6mm which is a length that may equal the width of a semiconductor die. Thus, the integration of these transmission Line circuit components into the semiconductor die would use a significant portion of the are of the die. A solution to reduce the real estate of these circuit components integrated on. a die is provided to overcome this shortcoming. 0007] The transmitter needs to provide a signal to the antenna consisting of the fundamental frequency. Furthermore, the power amplifier (PA) in the transmitting circuit should be designed to minimize power dissipation and maximize the energy transfer to the antenna, in addiiioti, the power amplifier to perform these functions should minimize transistor usage particularly cascode-like structures since the available head room is only about 500-600 mV which is about half of the 1.2V power supply. A solution to maximize energy transfer and minimize second order harmonics trom appearing at the output of the power amplifier is provided to overcome this shortcoming.

[0008] Second harmonics due to the non-linear behavior of the trans istor introduces an additional difficulty in power amplifier design. These second harmonics can distort the desired waveform at the antenna and reduce the purity of the desired signal being transferred. Several solutions are presented to remove these second order distortions as well as using them advantageously to improve the quality of the signal being delivered to the antenna.

[0009] The transmitters and receivers for the 60GHz radio system can be coupled to form a SIMO (Single Input Multiple Output) system. This system would use more than one antenna at the transmitter to steer the beam to an antenna located on the receiver. The outputs generated from the multiple output antennas will be received by the single receive antenn and provide an increased data throughput and link range without increasing the total output power or signal bandwidth.

[0010] The transceivers and receivers for the 60GHz radio system can be coupled to form a MIMO

(Multiple Input Multiple Output) system. This system would use more than one antenna at the transmitter and more than one antenna for the receiver. The outputs generated from the multiple output antennas will be received by the multiple receiver antennas providing increased data throughput and link range without increasing the total output power or signal bandwidth.

BRIEF SUMM ARY OF THE INVENTION

[0011] The following is a summary and thus contains, by necessity, simplification, generalizations, and omission of detail; consequently, those skilled in the art will appreciate that this summary is illustrative only and is not intended to be in any way limiting. Various embodiments and aspects of the inventions, as defined by the appended claims, will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodi ments.

Numerous specific details are described to provide a thorough understanding of various

embodiments of the present invention.

[0012] An embodiment is presented to form the power divider and quadrature hybrid from lumped capacitors and inductors instead of using transmission lines to form these capacitors and inductors. The sinusoidal combiner also uses lumped capacitors and inductors. Transmission lines require more area to emulate the equivalent capacitance and inductance of lamped capacitors and inductors. Using lumped capacitors and inductors reduces the area usage by as much as 80%, In addition, the insertion loss would decrease by the square root of the area used since the resistive loss would be proportional to the length of the traces used to form the transmission lines or l umped elements.

[0013] Another embodiment is to combine an input in-phase clock and an input quadrature clock into a composite 60 GHz clock waveform. The circuit combines the two 60 GHz input clocks using a parallel set of cascode transistors that is coupled to an LC tank circuit timed to operate at 60 GHz. The inputs drive the gates of the cascode de vices providing gain and excitation of the tank circuit. The composite 60 GHz clock waveform is then coupled to the rest of the clock network circuit, components.

[0014] A further embodiment is to couple the composite 60 GHz clock waveform as a single transmission line between the source and destination locations. The transmission line can be formed as a Co-pianar Waveguide (CPW) to couple the circuit components of the clock network between the source and destination. Since the in-phase 1 and quadrature Q clocks have been combined in the composite clock; waveform, only one clock l ine needs to be distributed over the surface of a die. The advantage is that the phase relation between the in-phase I and quadrature Q clocks are locked or frozen within the composite clock waveform. Once the individual in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

[0015] Another embodiment creates a low power 60 GHz distributio network that can be scaled as the number of transmitters is increased. The composite 60 GHz clock offers the ability to transfer the 3 and Q clocks over the surface of the die to multiple transmitters, multiple receivers or both multiple transmitters and multiple receivers using less power and less area.

[0016] An embodiment of the transmitter is the unique design of the class-E amplifier that can e tuned to pass only the fundamental frequency to the antenna. This provides a very efficient design by optimizing the second harmonics at the drain of the PA transistor. This occurs by coupling a CPW and a series capacitor between the PA transistor and the load. The combination of these two elements forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna,

[0017] A further embodiment is to use a supply inductor to couple the drain of the PA transistor to the power supply. The supply inductor does not behave as an RF choke at either the fundamental or second harmonic. Instead, the supply inductor is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. Then, a load capacitance which is located on the output signal pad is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at. the drain of the PA transistor do not overlap. This feature minimizes the parasitic power dissipation and allows for the energy to be applied to the antenna, 0018] In another embodiment, the pre-driver stage of the PA is designed as a Class-A stage, maximizing the voitage swing delivered to the gate of the PA switch or transistor. To minimize the inductive coupling between the pre-driver stage and the PA (Power amplifier) stage and in turn ensure PA stability, the resonance network of the driver stage is implemented by a load formed by a CPW line coupled to the supply and an AC coupling capacitor coupling the drain of the pre-driver to the aate of the PA transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[001.9] Please note that the drawings shown in this specification may not necessarily be drawn to scale and the relative dimensions of various elements in the diagrams are depicted schematically. The inventions presented here may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully con vey the scope of the invention to those skilled in the art. In other instances, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the

embodiment of the invention. Like numbers refer to like elements in the diagrams.

[0020] FIG. la depicts a two-element beamforming transmitter circuit its accordance with the present invention.

[0021] FIG. lb depicts a four-element beamforming transmitter circuit in accordance with the present invention.

[0022] FIG. 2a illustrates the circuit schematic of the amplifier combining two sinusoidal, waveforms in accordance with the present invention,

[0023] FIG. 2b depicts a lumped component Wilkinson power divider in accordance with tire present invention.

[0024] FIG. 2c shows a lumped component 90° quadrature hybrid in accordance with the present invention.

[0025] FIG. 2d presents the variable gain amplifiers configured as a phase rotator in accordance with the present invention.

[0026] FIG. 2e presents a more detailed description of the mixer.

[0027] FIG. 3 depicts the circuit diagram of the transformer, pre-drive and power amplifier which iiictudes the power amplifier configured in a Class-E load tuning network in accordance with the present invention.

[0028] FIG. 4a illustrates a 3-D representation of the co-planar waveguide in. accordance with the present invention. [0029] FIG, 4 shows the cross section of the die illustrating the co-planar waveguide in accordance with the present invention.

[0030] FIG. 5a presents the location of the test point driven externally in the circuit of FIG. la in accordance with the present invention.

[003 i ] FIG. 5b illustrates the measured results of the output power at the die's pad when drive by the test point shown i FIG. 5a in accordance with the present invention.

[0032] FIG. 6 shows the variation of the I clock as the Q clock is varied in accordance with the present invention.

[0033] FIG. 7 presents a 3-D representation of the chip containing the beam.form.ing transmitters solder bumped to an LTCC (Low Temperature Ceramic Carrier) substrate which is further solder bumped to a PWB (Printed Wiring Board) board in accordance with the present invention.

DETAILED DESCRIPTIO OF THE INVENTION

[0034] FIG. la illustrates 2 two element beamfonrnng transmitter 1-1 that is applicable for a 60 Gliz system. For an example of a single transmitter circuit, see U.S. patent application Ser. No. 13/243,986, filed Sept. 23, 201 1 by Zaw Soe under the title, "Method and Apparatus of Minimizing Extrinsic Parasitic Resistance hi 60GHz Power Amplifier Circuits" commonly assigned herewith, describes a transmitter circuit and techniques, suitable for driving an antenna and is incorporated herein b reference in its entirety. The digital baseband signal 1-2 is applied to the DAC (Digital to Analog Converter) 1-3. The DAC converts the digital signal to an analog signal The variable gain amplifier 1-4 applies the amplified signal to the low pass filter 1-5. The bussed output 1-6 of the low pass filter 1-5 provides the Γ, Γ, Q \ and the Q ^' baseband signals. The in-phase ! baseband signals are 90° out of phase with the quadrature Q baseband signals. The Γ baseband signal is 180° out of phase with the Γ baseband signal and the Q^" baseband signal is 180° out of phase w i th the Q ^; baseband signal These baseband signals are carried by the bus 1-6 and are applied to the phase rotator 1-15a of the first transmitter 1-25 and the phase rotator 1-15b of the secood transmitter 1-26. The phase rotator l-15a also receives a first digital control (not shown) which shifts the phase of the input ii -phase 1 and quadrature Q baseband signals 1-6 into an output in-phase Γ and quadrature Q' baseband signals onto bus l-6a with a phase dependent on the first digital control The rotated baseband signal on bos I -6a is applied to the composite mixer l~18a. Similarly, the phase rotator Ϊ- ISh also receives a second digital control (not shown) which shifts the phase of the input in-phase I and quadrature Q baseband signals 1-6 into an output in-phase I" and quadrature Q" baseband signals onto bus l-6l with a phase dependent on the second digital, control. The first digital control and the second digital control adjust the gain of several variable gain amplifiers in each phase rotator (circuit configuration to be presented shortly) to provide the rotated signal that is comprised of a phase shifted in-phase I and quadrature Q signals. The rotated signal on bus l-6b is applied to the mixer l~l8b. The first and second digital controls are generated by unit comprising a control block and memory (not illustrated). The first and second digital controls may be different or identical and are applied to the phase rotators 1-I5a and 1-15b.

[0035] The rotated in-phase I and quadrature Q baseband output signals of the phase rotators at busses l-6a and l-6b alter the output waveform of the transmitters. These waveforms are applied to the antennas to propagate the up-converted signals into free space.. The phase relations of the two propagated signals or waveforms then cause a constructi ve or destructive interference between the waveforms such that a beam with greater intensity or less intensity, respectively, can be formed at a particular location in free space. Thus, the phase rotators allow the beam to be steered depending on the values of the first and second digital controls. The signals in FIG. la entering the

transmitters 1 -25 are the clock on transmission line 1-13a and the baseband signal on bus 1-6.

Similarly, the clock on transmission line l.-13b and the baseband signal, on bus 1-6 enter the transmitter 1-26. These digital controls are used to steer the composite beam formed by a first and a second antenna. For an example of an antenna design, see U.S. patent application Set. No.

13/552,943, filed July 19, 2012 by HongYu Yang under the title, "Method and Apparatus for a 60 GHz Endfire Antenna" commonly assigned herewith, describes an endfire antenna and is incorporated herein by reference in its entirety. 0036] The beam steering technique can be expanded to include more than two transmitters and their associated antennas as will be shown shortly. For an example of another form of steerable antenna design, see U.S. patent application Ser. No. 13/552,955, filed July 1 , 2012 by Joel Balbien et al, under the title. "Method and Apparatus for the Alignment of a 60 GHz Endfire Antenna" commonly assigned herewith, describes a way of steering endfire antennas and is incorporated herein by reference in its entirety.

[0037] The LO (local oscillator) clock path in FIG. l a to generate the high-frequency 60 GHz clock starts from the input 1-7. A F synthesizer 1-8 receives the control 1-7 to adjust the characteristics of the quadrature VCO (Voltage Controlled Osci llator) 1-9 to oscillate over the frequency range including 57-66 GHz. The quadrature VCO 1-9 is a quadrature balanced output oscillator generating an in-phase 1 clock 1-27, an inverted in-pliase Γ clock, a quadrature phase Q clock 1-28 and an inverted quadrature phase Q^" clock operating at 60 GHz. Two of these clock outputs 1.-27 and 1-28 of the quadrature VCO 1-9 are applied to a sinusoidal combiner 1-1.0. Tire remaining clock outputs of the quadrature VCO 1-9 are loaded with an equivalent dummy load to insure that the VCO outputs are equally balanced. The in-phase I clock 1 -27 and quadrature phase Q clock 1-28 are combined together by the sinusoidal combiner 1-10 into a single combined, clock and driven onto the transmission line 1-11 , This single transmission line is applied to the power divider 1-12 generating an equivalent combined clock on transmission lines I-13a and l-13b. The power of the combined clocks on transmission lines l-13a and l-13b is reduced by half (by 3dB) compared to the power on transmission line 1-11. There may also be an insertion loss due to the power divider. The combined clock on the two transmission lines l-13a and 1-13b are applied to the transmitter 1-25 and 1-26, respectively. The circuit components within both of the transmitters are substantially identical.

[0038] The clock on transmission Hue l-13a is applied to the quadrature hybrid 1-14 which recovers two output clocks on transmission lines 1-1 a and 1-1 b. The output clocks o these transmission lines are substantially separated from one another by a 90° phase shift and are substantially equivalent to the original in-phase I clock 1-27 and quadrature phase Q clock 1-28. The two recovered output clocks on transmission lines 1-14a and l-14b also suffer an insettion loss due to the quadrature hybrid. The 0° phase shift clock on transmission line l-14a is applied to the LO buffer 1-16 while the 90° phase shift clock on transmission line I -14b is applied to the LO buffer 1-17. The LO buffer receives a single clock and generates two amplified output clocks. The two outputs of the LO buffer 1-16 generate an equivalent representation of the clock I that was on transmissio line 1-27 and generates the corresponding inverse clock Γ that is 180° out of phase with the output L The local oscillator buffer 1-17 generates an equivalent representation of the clock Q that was on transmission line 1-28 and generates the corresponding inverse clock Q^* that is i 80° out of phase with the output Q.

[0039] Power is saved by transporting a combined (I and Q) clock on a single transmission line instead of two separate transmiss n lines each carrying an in-phase clock I and a quadrature clock Q. As the distance between circuit components are increased over the die, the power saving increases correspondingly. The two separate transmission lines approach would suffer; 1 ) an increased area _.penalty; and 2} difficulty in maintaining a 90° separation between the two tapped clocks from their transmission lines over the area of the die. Besides power and area savings, the phase relation between the in-phase I and quadrature Q clocks in the composite clock waveform is locked or frozen until they are separated into their component parts at the destination. This alleviates the concern discussed in the second issue provided above, 0040] The sinusoidal combiner 1-10, the power divider 1-12, the quadrature hybrid 1-14 and the local oscillator buffers 1-16 and 1-17 are circuit components that are spread out over the area of the die. The in ventive technique of transporting the single combined clock alleviates the two prior concerns. For example, the single combined clock on transmission line 1-11 from the sinusoidal combiner is applied to the power divider 1-12. The power divider 1- 2 then generates the single combined clock on transmission line 1-13a which is applied to the quadrature hybrid 1-1.4. The quadrature hybrid then transforms the single combined clock into two single recovered clocks on transmission lines l-14a and l-14b separated by 90° which are applied to the local oscillator buffers 1-16 and 1-17. The local oscillator buffers 1-16 and 1-17 generate two sets of differential outputs. The first set of differential outputs includes the first output clock of the local oscillator 1-16 which amplifies the input clock on transmission line l-14a while the other output clock is ISO^'3 out of phase with the input clock. The second set of differential outputs includes the first output clock of the local oscillator buffer 1-17 which amplifies the input clock on transmission line l-14b while the other output clock is 180° out of phase with the input clock. These two sets of differential output clocks from the local oscillator buffers are applied to the mixer 1-18 to up~convert the signal on I- 6a. Note that these two sets of differential in-phase 1 and quadrature Q signals applied to the mixer l-18a are the first occurrence of differential signals since the single combined clock has been generated at the output of the sinusoidal combiner 1-10. The power dissipation of transferring the single combined clock from the output of the sinusoidal combiner -10 to the composite mixer 1- 18a has been reduced by nearly 3 dB.

[0041] The composite mixer l-18a is formed from Gilbert multipliers. The tip-converted outputs of the Gilbert multiplier are applied to each end of the center tapped coil of the transformer 1-19. The outputs of the second coil of the transformer are AC grounded at one end while the second end is applied to the pre-driver 1-20 forming a ba!un. The output of the pre-driver 1-20 provides impedance matching and drives the power amplifier 1-21 which provides the final output up- converted signal to the pad J.~23a. Note that the signal pad l-23a is surrounded by two ground pads 1-22 and 1-24 to provide a good ground reference. The second output of the power divider on transmission line -13b is applied to the second transmitter chain 1-26 and generates an equivalent up-converted signal at its corresponding signal pad S l-23b if the digital weights applied to the phase rotators 1-15a and .1-15b are identical.

[0042] FIG. lb presents an LO clock distribution system that comprises greater than two transmitters. Although the LO clock distribution system is used for the transmitters, a similar network can also be used to clock a multiple input receiver architecture. The digital baseband signal 1-2 is apptied to the DAC (Digital to Analog Converter) 1-3. The DAC converts the digital signal to an analog signal. The variable gain amplifier 1-4 applies the amplified signal to the low pass filter 1-5. The bussed output of the low pass filter 1-6 provides the V, Γ, Q \ and the Q ^* baseband signals. These signals are carried by the bus 1-6 and are applied to the phase rotators within the transmitters 1-25, 1-26, 1-32 and 1-33, These phase rotators within these transmitters also receive a first, second, third and fourth digital controls (not shown) which combines the applied input bussed in- phase I and quadrature Q signals 1- into a composite signal with a phase between that of the applied input in-phase 1 and quadrature Q signals dependent on the values of the first, second, third and fourth digital control [0043 J The combined in-phase I and quadrature Q output si gnals of the phase rotators al ter the output waveform of each of the transmitters. These waveforms are applied to the antennas to propagate the signals into free space. The phase relations of the four propagated up-converted, signals or waveforms then cause a constructive and destructive interference between the waveforms such that a beam with greater intensity can be formed at particular locations in free space. Thus, the phase rotators allow the beam to be steered depending on the values of the first; second, third and fourth digital controls. The only signals shown entering the transmitters in FIG. lb are the clocks on the transmission lines l-13a through l-13d and the baseband signal 1-6. The first, second, third and fourth digital controls are used to steer the composite beam formed by the four antennas. The beam steering technique can be expanded to include any number of transmitters and their associated antennas.

[0044] The quadrature VCO 1-9 generates an in-phase ί clock 1-27, an inverted in-phase fclock 1- 30, a quadrature phase Q clock 1-28 and an inverted quadrature phase0^" clock 1-31 operating at 60 GHz, Two of these clock outputs 1-27 and 1-28 of the quadrature VCO 1-9 are applied to a sinusoidal combiner 1-10 while the remaining two of these clock outputs 1-30 and 1-31 of the quadrature VCO 1-9 are applied to a sinusoidal combiner J -10». This loading insures that all clock outputs of the quadrature VCO 1-9 are equally loaded and that the VCO outputs are equally balanced.

[0045] The sinusoidal combiner 1-10 driving the two transmitters 1-25 and 1-26 is equivalent to the circuit components illustrated in FIG. l . The sinusoidal combiner 1-10a combines the two clock outputs, the inverted in-phase fclock 1-30 and inverted quadrature phase Q^~ clock 1-31, together into a single combined clock which drives the single transmission line I -11a. This single transmission line is applied to the power divider 1-12a generating equivalent combined clocks on transmission lines 1-13c and l-.13d. The power of the combined clocks on transmission lines l-13c and I -13d is reduced by half (by 3dB) compared to the power on transmission line 1-11 a. There may also be an insertion loss due to the power divider. The combined clock on the two

transmission lines 1- c and 1-1 d are applied to the transmitter 1-32 and 1-33, respectively. The output of the two transmitters 1-32 and 1-33 provide their final output signal to the pads l-23c and l-23d, respectively. Note that the signal pads l~23c and l-23d are surrounded by two ground pads to provide a good ground reference. These pads are coupled to the antennas which generate a steered beam waveform that propagates into free space. The circuit components within all of the transmitters are substantially identical.

[0046] FIG. 2a illustrates the circuit diagram of the sinusoidal combiner 1-10 interfacing the quadrature oscillator 1-9 to the power divider 1-12 shown in FIG. la. This is also the circuit diagram of the sinusoidal combiner 1-lOa interfacing the quadrature oscillator 1-9 to the power divider 1-12a shown in FIG. lb. The circuit consists of two inputs 2-1 and 2-2. The output is extracted after capacitor Cj at node 2-3. Two cascode structures consisting of n-channei. transistors MN 1 and N3 connected in parallel with a second cascode structure consisting n~charme! transistors N2 and MN4. The top transistors MN3 and MN4 of the cascode structures have thei r gate coupled to the power supply voltage (VDD) while the source of the transistors MN 1 and M 2 are coupled to ground or VSS. The common drain 2-3a of the n-channei devices MN3 and MN4 is coupled to the power supply line via L_}. The gates of MN3 and MN4 are coupled to the power supply while the gates of^'MNl and MN2 are coupled to the outputs of the quadrature oscillator. One output of the quadraiirre oscillator provides a clock at 0° and a second ouipui of the quadrature oscillator provides a clock at 90*. These two outputs are applied to the input nodes 2-1 and 2-2 of the sinusoidal combiner 1-10, respecti vely. The common drain node 2~3a is coupled to capacitor Cj to generate the output. The inductor L₅ and capacitor C_\ form a tank circuit whic resonates at the frequency of the quadrature oscillator. The output consists of single clock containing the representation both input clocks 2-1 and 2-2, The clock 2-3 is between 0° and 90° and is at 45° when both cascode structures are identical. This single combined clock output 2-3 carries the two input clocks 2-1 and 2-2. The combined clock output is sent to the power splitter on the chip on a single transmission line,

[0047] FIG. 2b illustrates the Wilkinson power splitter 1-12 formed using lamped reactive components. The input is applied at the input node 2-4 which has a capacitor connected to ground and is center tapped to the combined inductor consisting of Lj and L.¾. The input impedance of the power splitter should be 50Ω. The output of La connects to the output node 2-5 to generate oiiti and has a capacitor connected to ground. The ouipui of the second i nductor of L_> is connected to out? which is node 2-6 and has a capacitor C.+ connected to ground. Both of the outputs have an LC tank circuit coupled to them. The capacitance value of Q equals the capacitance value of O. and the inductance value of Lj equals to the inductance value of L_¾. The inductor L and capacitor C_s should provide an output impedance of 50Ω at the node cmt_f . The capacitor Cz has a value which equals to the summation of C¾ and C₄. As the input clock is applied at the input node 1- 4, this circuit generates two identical output clocks at node out} 2-5 and out 2-6 reduced by 3dB when compared to the input clock 2-4. The inductors and capacitors also have resistive losses which introduces an additional insertion loss.

[0048] FIG. 2c illustrates the quadrature hybrid 1-14 shown m ^" FIG. la which is formed from lumped reactive components. The quadrature hybrid takes an input at node 2-8 and generates two outputs I at node 2-10 and Q at node 2-9, Note that the formation of the quadrature hybrid consists of two inductors that have a mutual coupling forming a transformer 2-7 where across each inductor is a capacitor. A capacitance C¾ is in parallel with the top inductor while a capacitance Cs is in parallel with the bottom inductor. The components form a tank circuit. The final output node 2-1 ί of the quadrature hybrid is coupled to a resistor R}. The quadrature hybrid generates the clocks ί and Q where the Q clock is separated from the 1 clock by 90°.

[0049] in FIG, 2a, FIG. 2b and FIG. 2c, the LC tank circuits generate a response at a center frequency with a 0° phase shift. As the input clock is adjusted in frequency from this center frequency over the operating range of 57-66 GHz, the phase shift increases. The system is designed to tolerate this phase shift. The inductors have a diameter ranging from 30 μηι to 50 pm and have a relatively small footprint or area usage,

[0050] Referring back to FIG. la, the single clock on transmission line 1-11 output of the sinusoidal combiner 1-10 is applied to the power divider 1-12. The output of the power divider 1-12 generates two clocks on transmission lines 1-13a and l~13b each going to separate transmitters 1-25 and 1-26, respectively, in the transmitter 1-25, the single clock on transmission Sine I-13a is applied to the quadrature hybrid 1-14 to generate two single ended recovered clocks where one has a phase of 0° I~14a and the second clock has a phase of 90° on transmission line l-1 b. At this point, the clocks on transmission lines l-14si and l-14b are applied to the local oscillator buffers 1-16 and 1-17, respectively. At the output of the local oscillator buffer 1-16, the 0° phase clock and its inverse phase are applied to the composite mixer l-18a. At the output of the local oscillator buffer 1-17, the 90° phase clock and its inverse phase are applied to the composite mixer 1- 8a. In essence., this entire path from the quadrature oscillator to the output of the qu adrature hybrid transforms the 0° and 90° output of the quadrature oscillator into a single clock on a single line and sends it to the quadrature hy brids of the various transmi tters. The single clock is transformed back to 0° and 90* output after the quadrature hybrid. The distance between the quadrature oscillator and the transmitter can he quite large, thereby sa ving power in sending the clock between, these two locations since only a single transmission line is used to send that clock, if the entire length has been sent by a differential line, the power dissipation would be almost twice as large along with, the corresponding area impact.

[0051 ] The baseband signal applied to the composite mixer 1-18a is the output signal l-6a of the phase rotator l~15a. Although the interconnect on l~6a is illustrated as a single line, the line actually consists of the baseband in-phase 1 and quadrature Q signals after the phase rotator. The details of the phase rotator 1-15a are provided in ¥IG. 2d. The phase rotator 1-15a illustrated accepts a signal I at node 2-12 and a signal Q at node 2-13 separated by 90°. The output of the phase rotator generates a shifted version of the signals I and Q at the two output nodes 2-18 and 1- 19. Node 2-18 provides the Γ signal and node 2-19 provided the Q' signal still separated by 90°. The prime signals consist of a combination of the two input signals I and Q after passing through the variable gain amplifiers (VGA) 2-15 through 2-17. The input signals 1 2-12 and Q 2-13 are combined by the variable gain amplifiers 2-14 and 2-15 which are connected to node 2-18 to generate the F signal. Thus, by varying the gains of the VGA's 2-14 and 2-15, the signal V can consist of only the I signal (gain of VGA 2-14 equals 1 , gain of VGA 2-15 equals 0), both the in- phase 1 and quadrature Q signals (gain of VGA 2-14 between 0 and 1 , gain of VGA 2-15 between 1 and 0}_? and only the Q signal (gain of VGA 2-14 equals 0, gain of VGA 2-15 equals 1). Similarly, by varying the gains of the VGA's 2-16 and 2-17, the signal Q^* can consist of only the I signal (gain of VGA 2-16 equals L gain of VGA 2-17 equals 0), both the in-phase I and quadrature Q signals (gain of VG A 2-16 between 0 and 1. gain of VGA 2-17 between 3 and 0), and only the Q signal ( gain of VG A 2-1.6 equals 0, gain of VG A 2-17 equals 1). Depending on the adjustable gain, of the variable gain amplifiers as illustrated by the arrows, the output signals can be shifted anywhere between 0° to 360° from their initial starting point.

[0052] FIG. 2e illustrates a portion of the circuit provided in FIG. hi and the arrow 2-28 indicates the details of the composite mixer 1-18a. in particular, the composite mixer l-18a and its inputs and outputs are labeled. The signals Γ and Γ 2-22 and signals Q ^; and Q^" 2-23 on bos 1-6 are coupled to the phase rotator to generate the signals and Γ 2-22* and signals Q ^' and Q^* 2-23' o bus l -6a. The composite mixer l»18a as indicated by the arrow 2-28 is comprised of the Gilbert rnixer 2-25, Gilbert rnixer 2-26 and the summer 2-27. The 0* clock signal generates a clock Sin 2πβ. 2-2<Ja and its inverse -Sin Ιπΐί 2-20b and is coupled to the Gilbert mixer 2-25. The frequency f is substantially equal to 60 GHz, The in-phase signals Γ and I^" 2-22* are also applied to the Gilbert mixer 2-25. The up-converted output of the mixer 2-25 is coupled to the first input of the summer 2- 27. The 90° clock signal generates a clock Cos 2πί 1 -21 a and its inverse -Cos 2πί t 2-2 l.b and is coupled to the Gilbert mixer 2-26. The quadrature signals Q^' and Q^" 2-23' are also applied to the Gilbert mixer 2-26. The up-converted output of the mixer 2-26 is coupled to the second input of the summer 2-27. The summer 2-27 adds the two up-converted outputs together to generate the output signals 2-24a and 2~24!>. These signals are applied to the inputs of the transformer 1-19 whose output drives the pre-amp.

[0053] In FIG. la, the transformer 1-19, the preamp 1-20, the power amplifier 1-21 and the signal pad !-23a in the transmitter 1-25 was presented whi le FIG. 3 provides a greater detail of these components in the accompanying schematic diagram. A 2: 1 halun 1.-19 is used at the input of the pre-driver stage to achieve the impedance matching between the high impedance mixer output and the low impedance pre-driver input. The outputs of the composite mixer t~18a of FIG. la are applied to the inputs at nodes 2-24a and 2-24fo of the baitm 1- in FIG. 3. After passing through the baltin. 1-19, the signal is applied to the gate 3-3 o N-channel transistor NS. The other output of the balun is connected to an AC ground and. is biased through a resistor R₂ which is connected to the driver bias at node 3-11. A supply by-pass capacitor C¾3 3-2 is placed across resistor R₂. The pre-driver stage of the PA is designed as a Class-A stage, maximizing the voltage swing delivered to the gate of the PA switch or transistor. To minimize the inductive coupling between the pre- driver stage and the PA (Power amplifier) stage and in turn ensure PA stability, the resonance network of the driver stage is implemented by a CPW line with an AC coupling capacitor C?. The high-Zi) CPW 3-5 has an impedance of 75 ohms. A capacitor C? AC couples the output of the drain 3-4 to the gate 3-6 of transistor MN6. The gate 3-6 of N-channel transistor MN6 is biased by the power amplifier (PA) bias through the resistor R₃ coupled to node 3-10, The co-planar waveguide impedance 3-5 and capacitor C? matches the impedance at the output 3-4 of the pre-driver transistor JVIN5 to the input 3-6 of the driver transistor MN6.

[0054] To improve the transmitter efficiency; the final driver stage of the PA adopts a Class-E topology with second harmonic timing. Harmonic tuning is an effective method to improve the parasitic capacitance tolerance of the Class-E topology and hence reduce the loss due to switching the on-resistance of transistor MN6. in theory, the efficiency keeps improving when more harmonics are tuned, however, in practice; the returns are diminished beyond the second harmonic. Therefore, this design only incorporates second harmonic impedance tuning.

[0055] The final stage of the power amplifier consisting of transistor N6, is configured in a class- £ amplifier configuration. Conventionally, the inductance L₄ is designed as a choke to short out the fundamental frequency. In order to maintain non-overlapping voltage-current waveforms at the drain of 3-7, the transistor switch MN6 needs to be presented with an open-circuit at the second harmonic of 120 GHz. This is achieved bv usina a small sinale-turn inductor L4 which resonates with the drain capacitance 3-7 of MN6 and any interconnect capacitance between the drain and the co-planar waveguide at the second harmonic. N-channel transistor N6 has a width equal to five times that of MN5. This amplifier uses the distributed inductance of the co-planar waveguide 3-9 which has a characteristic impedance of 50 Ω and the capacitance C§ to form the basis Class-E amplifier load to resonate at the fundamental frequency. The series bandpass filter is implemented by a short, length CP W in series with capacitor C_8> which provides an equivalent short circuit at the ^■fundamental frequency .

[0056] Meanwhile, the load tuning network of the PA. (Power Amplifier) still needs to satisfy the fundamental impedance constraint for waveform shaping, and this is achieved by adding a shunt capacitor C after the series bandpass filter. The combination of the C_¾ the parasitic drain capacitance of the drain 3-7 of N6 and Lj generates the required susceptaace at the fundamental frequency. Capacitor G> is blocked from influencing die second harmonic on node 3-7 since the series bandpass filter only passes the fundamental frequency. The effective inductance of the CPW line 3-9 doubles at the second harmonic and therefore provides much higher impedance blocking the drain 3-7 from the load at the output pad I -23a

[0057] The voltage and current waveforms at drain 3-7 can be shaped such that they are non- overlapping. This minimizes the loss in the transistor MN6 and maximizes the energy provided to the co-planar waveguide 3-9. Thus, the capacitor C< in conjunction with L4 can be used provide opti mize the fundamental frequency behavior of the class E amplifier.

[0058 ] FIG. 4a illustrates a 3-D representation of the co-planar waveguide. The die or chip

substrate 4-1 supports the three co-parallel lines 4-2, -3 and 4-4. The clock is carried by line 4-3 while the outside lines 4-2 and 4-4 are the ground lines. A cross-section representation of FIG. 4a is illustrated in FIG. 4b. Metal 8 which is copper is used to form the interconnect lines 4-2, 4-3 and 4- 4 of the co-planar waveguide which run over the chip or die substrate 4-1 by a distance D. D is approximately 8 microns. The dimensions of A is the width of the ground line 4-2, B is the width of the clock line 4-3 and C is the space difference between the inner clock line 4-3 to the two outside ground lines 4-2. The dimensions A, B and C set the impedance of the coplanar waveguide. For example, to achieve the co-planar waveguide of 50 ohms; A has a value of 10 pm, B has a value of 8 μπι and C has a value of 4 pm. For a 75 ohm co-planar waveguide: A equals to 10 prn, B is equal to 4 pm and C is equal to 6 p.m.

[0059] FIG. 5a illustrates a test point that is used to provide the test results of FIG. 5b. This test point is inserted between the sinusoid combiner 1-10 and the power divider 1-12 as illustrated in FIG. 5a. Amplifier 5-1 provides the local oscillator test input clock on transmission line 1-11 during the test where the sinusoidal combiner 1-iO is disabled. The test results of applying a 62GHz clock to the local oscillator test input and measuring the power output at the output signal pads 1- 23a and l-23b of the two transmitters 1-25 and 1-26, respectively , is illustrated in FIG. 5b, The dark circled dots represent transmitter I results while the open triangle results represent the

transmitter 2 results, it is very desirable to have a power output P¾p at 8 dBm at the outpu pad of the transmitter. As the power of the local oscillator test point is reduced from 0 dBm down to approximately -5 dBm, the power output at the pads remains at approximately 8 dBm which is satisfactory for proper operation at 62 GHz, Thus, a lmW input power of the clock provides 8 dBm of gain at the output pad.

[0060] FIG. 6 depicts the test results that verify the function of the phase rotator. The m-pliase I clock is stationary at 0° while the quadrature phase Q clock is swept over 360°. A single baseband frequency f_m is applied to the circuit. The power output results of the measured upper f _> + ¾B a d lower o - f½ sideband responses are presented. Two procedures are performed to adjust the digital control. An external FPGA (Field Programmable Gate Array) is programmed to generate the phased swept baseband Q signal directly. The results for the upper (open triangle) and Sower (open circle) sidebands of the FPGA measurements are provided. The second procedure calculates the value of the digital weight and uses the intemal SPI (Serial, to Parallel) interface on chip to apply the values to the phase rotator. The results for the upper (dotted line) and lower (dashed line) sidebands of the SPI measurements are provided. The digital input to the phase rotator is varied to change the quadrature phase Q clock with respect to the in-phase 1 clock to perform this sweep. As the quadrature phase Q clock is swept to 90°, the upper sidebands (open triangle and dotted line) are at a minimum while the lower sidebands (open circle and dashed line) are at a maximum. Similarity, as the Q phase is swept to 270°, the upper sideband is at a maximum while the lower sideband is at a minimum. Note the FPGA (external) results match the SPI (intemal) resiiits fairly well, indicating that the phase rotator is performing as expected.

[0061 ] FIG. 7 presents a 3-D representation 7-1 of the chip 7-4, LTCC substrate 7-3 and PWB 7-2. The chip 7-4 is solder bumped 7-6, flipped and attached to the top of the LTCC substrate 7-3. The LTCC substrate 7-3 has antennas 7-7 fabricated on its top and bottom surfaces for transmitting and receiving signals to othe transceivers in free space. The bottom of the LTCC substrate 7-3 is solder bumped 7-5 to the PWB 7-2, Some of the antennas are used to capture input signals 7-8 from free space or to send out signals 7-9 out to free space. The transmit antennas can use the techniques mentioned in this specification to provide a system of distributing the LO, generating phase rotations, amplification with a class-E amplifier to steer the output waveform into a beam. [0062] A summary of some of the inventive apparatus for a 60 GHz distribution network are provided.

[0063] A network comprising a Voltage Controlled Oscillator (VCO) connected to a sinusoidal combiner, the sinusoidal combiner coupled to a power divider, the power divider coupled to a quadrature hybrid, the quadrature hybrid coupled to a local oscillator buffer, the local oscillator buffer connected to a composite mixer, a separate transmission line for each of the couplings and the power divider and the quadrature hybrid formed trom lumped reactive components. The lumped reactive components are inductors and/or capacitors. The composite mixer is a up-con verier mixer or a down-converter mixer. The transmission line is a co-planar waveguide. The VCO is a quadrature VCO. An fa-phase clock and a quadrature clock of the quadrature VCO are applied to the sinusoidal combiner.

[0064] An apparatus comprising an in-phase clock and a quadrature clock of a Voltage Controlled Oscillator (VCO) coupled to an input of a sinusoidal combiner, a first composite clock of an output of the sinusoidal combiner coupled to an input of a power divider, a second and a third composite clock coupled to outputs of the power divider, a plurality of transmission lines to transport all the composite clocks and a quadrature hybrid to recover a first in-phase and a first quadrature clock from the second composite clock. Each transmission line transport uses a single co-planar waveguide. The power divider and the quadrature hybrid are formed from lumped reactive

components. The first in-phase clock is used to generate a first inverse in-phase clock, a first mixer clocked by the first in-phase and first inverse in-phase clock to up-convert a first signal, the first quadrature clock is used to generate a first inverse quadrature clock, a second mixer clocked by the first quadrature and first inverse quadrature clock to up-convert the first signal and a summer to combine outputs of the first and second mixers. The output of siraimer coupled to a first transmitter, the first transmitter coupled to a first antenna and the first antenna transmits the up-converted first signal into free space. A second quadrature hybrid to recover a second in-phase and a second quadrature clock from the third composite clock, the second in-phase clock is used to generate a second inverse in-phase clock, a third mixer clocked by the second in-phase and second inverse in- phase clock to up-convert a second signal, the second quadrature clock is used to generat a second inverse quadrature clock, a fourth mixer clocked by the second quadrature and second inverse quadfature clock to up-convert the second signal a second summer to combine outputs of the third and fourth mixers, the output of second summer coupled to a second transmitter, the second transmitter coupled to a second antenna, and the second antenn transmits the up-converted second signal into free space. A first phase rotator controlled by a first control to generate the first signal and a second phase rotator controlled by a second control to generate the second signal . The transmitted up-converted first signal cause a constructive or destructive interference between the transmitted tip-converted second signal such that a beam with greater intensity or less intensity, respectively; can be formed at a particular location in free space dependent on the first and second digital control values.

[006.5] A method of forming a network, comprising the steps of connec ting a Voltage Controlled Oscillator (VCO) to a sinusoidal combiner, coupling the sinusoidal combiner to a power divider, coupling the power divider to a quadrature hybrid., coupling the quadrature hybrid to a local oscillator buffer, connecting the local oscillator buffer to a composite mixer, providing a transmission line for each the couplings and forming the power divider and the quadrature hybrid from lumped reactive components. The lumped reactive components are inductors and/or capacitors. The composite mixer is an up-converter mixer or a down-converter mixer. The transmission line is a co-planar waveguide. Each of the couplings uses only a single co-planar waveguide. The VCO is a quadrature VCO.

[0066] A summary of some of the inventive apparatus for a Class E Power Amplifier are pro vided.

[0067] A Class E amplifier comprising a first transistor with a gate, source, drain and substrate, an input coupled to the gate, the source coupled to a ground supply, an inductor coupled between a power supply and the drain, the drain coupled to a first co-planar waveguide in series with a first capacitor and the first capacitor coupled to a signal pad. A second capacitor coupled between the signal pad and the ground supply. The substrate is coupled to the ground suppl . The signal pad is coupled to an antenna. An. output of a second transistor capacitively coupled to a gate of the first, transistor, A second co-planar waveguide coupled between the output of the second transistor and the power supply. An. output of a ba!un. coupled to input of the second transistor. [0068] An apparatus comprising an inductor coupled between a power supply and an output of a first transistor, the output of the first transistor coupled to a co-planar waveguide in series with a capacitor and the capacitor coupled to a signal pad. A second capacitor coupled between the signal pad and a ground supply. An output of a second transistor capacitively coupled to a gate of the first transistor. A second co-planar waveguide coupled between the output of the second transistor and the power supply. An output of a balun coupled to the input of the second transistor. The inputs of the balun driven by outputs of a composite mixer that up-con verts an input signal. An antenna coupled to the signal pad, whereby the up-converted input signal is propagated into free space from the antenna as electromagnetic radiation.

[0069] A method of passing a signal with a fundamental frequency to a signal pad, comprising the steps of coupling the signal to an input of a transistor, coupling an inductor between a power supply and an output of the transistor, coupling the output of the transistor to a co-planar waveguide in series with a first capacitor, coupling the first capacitor to a signal pad and adjusting the co-planar waveguide in series w th the first capacitor to a band pass the fundamental frequency, thereby passing the signal with the fundamental frequency to the signal pad. Coupling a second capacitor between the signal pad and a ground supply. Adjusting the inductor to resonate at a second harmonic with a drain capacitance of the transistor. Shaping the waveform at the output of a transistor to constrain the fundamental impedance. Adj usting a value of the second capacitor to achieve a desired susceptance at the fundamental frequency. The current and voltage waveforms at a drain of the transistor non-overlap.

[0070] Finally, it is understood that the above description are only illustrative of the principle of the current invention. Various alterations, improvements, and modifications will occur and are intended to be suggested hereby, and are within the spirit and scope of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and wi l l fully convey the scope of the in vention to those skilled in the arts. It is understood that the various embodiments of the invention, although different, are not mutually exclusive. In accordance with, these principles, those skilled in the art may devise numerous modifications without departing from the spirit and scope of the invention. Although the transmitters were described using a CMOS process, other technologies ca» be used as well, addition, a network and a portable system can exchange information wirelessly by using

communication techniques such as TDMA (Time Division Multiple Access), FDMA (Frequency

Division Multiple Access), CDMA (Code Division Multipie Access), OFDM (Orthogonal Frequency Division Multiplexing ), IJWB (Ultra Wide Band). WiFi, WiGig, Bluetooth, etc. The network can comprise the phone network, IP (Internet protocol) network, LA (Local Area Network), ad hoc- networks, local routers and even other portable systems.

Claims

CLAIMS What is claimed is:

1. A Class E amplifier comprising;

first transistor with a gate, source, drain and substrate;

an input cou led to said gate;

said source coupled to a ground supply;

an inductor coupled between a power supply and said drain;

said drain coupled to a first co-planar waveguide in series with a first capacitor; and

said first capacitor coupled to a signal pad.

2. The apparatus of claim 1 , further comprising:

a second capacitor coupled between said signal pad and said ground supply.

3. The apparatus of claim 1 _; whereby

said substrate is coupled to said ground supply,

4. The apparatus of claim I , whereby- said signal pad is coupled to an antenna.

5. The apparatus of claim 1, further comprising:

an output of a second transistor capacitively coupled to a gate of said first transistor,

6. The apparatus of claim 5, further comprising;

a second co-planar waveguide coupled between said output of said second transistor and said power supply.

7. The apparatus of claim 6, further comprising:

an output of a haS un coupled to input of said second transistor.

8, An apparatus comprising: an inductor coupled between a power supply and an output of a first transistor;

said output of said first transistor coupled to a co-planar waveguide in series with a capacitor; and said capacitor coupled to a signal pad.

9. The apparatus of claim 8, further comprising:

a second capacitor coupled between said signal pad and a ground supply.

10. The apparatus of claim 9, further comprising:

an output of a second transistor capacttive!y coupled to a gate of said first transistor.

11. The apparatus of claim 1 . further comprising:

12. The apparatus of claim 11 , further comprising:

an output of a baUm coupled to said input of said second transistor.

13. The apparatus of claim 12, further comprising:

inputs of said balun driven by outputs of a composite mixer that up-converts an input signal.

14. The apparatus of claim 13, further comprising:

an antenna coupled to said signal pad, whereby

said up-converted input signal is propagated into free space .from said antenna as electromagnetic radiation.

15. A method of passing a signal with a fundamental frequency to a signal pad, comprising the steps of:

coupling said signal to an input of a transistor;

coupling an inductor between a power supply and an output of said transistor;

coupling said output of said transistor to a co-planar waveguide in series with a first, capacitor; coupling said first capacitor to a signal pad; and adjusting said co-planar waveguide in series with said first capacitor to a band pass said fundamental frequency, thereby

passing said signal with said fundamental frequency to said signal pad.

1.6. The method of claim 15, further comprising the steps of:

coupling a second capacitor between said signal pad and a ground supply.

17, The method of claim J6_; further comprising the steps of:

adjusting said inductor to resonate at a second harmonic with a drain capacitance of said transistor.

18, The method of claim 17, further comprising the steps of:

shaping the waveform at said output of transistor to constrain a fundamental impedance.

19. The method of claim 18. further comprisi g the steps of:

adjusting a value of said second capacitor to achieve a desired susceptance at said fundamental frequency.

20. The method of claim 15, whereby

current and voltaue waveforms at a drain of said transistor non-overlap.