WO2013173628A1 - Power control command insertion into complex signal - Google Patents

Power control command insertion into complex signal Download PDF

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Publication number
WO2013173628A1
WO2013173628A1 PCT/US2013/041425 US2013041425W WO2013173628A1 WO 2013173628 A1 WO2013173628 A1 WO 2013173628A1 US 2013041425 W US2013041425 W US 2013041425W WO 2013173628 A1 WO2013173628 A1 WO 2013173628A1
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WO
WIPO (PCT)
Prior art keywords
power control
control sequence
complex
complex power
memory
Prior art date
Application number
PCT/US2013/041425
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French (fr)
Inventor
Otto Ville STEUDLE
Original Assignee
Nokia Corporation
Nokia, Inc.
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Publication date
Application filed by Nokia Corporation, Nokia, Inc. filed Critical Nokia Corporation
Publication of WO2013173628A1 publication Critical patent/WO2013173628A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/04—TPC
    • H04W52/54—Signalisation aspects of the TPC commands, e.g. frame structure

Definitions

  • Communication systems including third generation partnership project (3GPP) wideband code division multiple access (WCDMA), can benefit from various power control methods and signals.
  • 3GPP third generation partnership project
  • WCDMA wideband code division multiple access
  • Radio communication systems include power control methods and signals to allow for efficient use of radio resources.
  • transceivers can use separate in-phase (I) and quadrature (Q) branches, which can be combined to form complex symbols.
  • the power control command in the user equipment (UE) the power control command can be inserted into the Q branch, before performing the combining into a complex symbol and before performing the complex scrambling code multiplication.
  • Figure 1-3 illustrate power control command insertion in relation to the combination and scrambling that can occur.
  • Figure 1 illustrates a frame structure for uplink dedicated physical data channel (DPDCH)/ dedicated physical control channel (DPCCH).
  • Figure 1 shows how transmission power control (TPC) bits can be mapped to the DPCCH channel. This is discussed more fully in 3 GPP technical specification (TS) 25.211, which is hereby incorporated herein by reference in its entirety.
  • TS 3 GPP technical specification
  • a frame can include multiple slots, for example, fifteen slots.
  • DPDCH 110 on the in-phase branch can include Ndata data bits.
  • DPCCH 120 on the quadrature branch can include N p i lo t pilot bits, N TF C I transport format combination indicator (TFCI) bits, N FB i feedback indicator (FBI) bits, and N TP C transmit power control (TPC) bits.
  • TFCI transport format combination indicator
  • FBI FB i feedback indicator
  • TPC transmit power control
  • Figure 2 illustrates spreading for uplink DPCCH/DPDCHs.
  • Figure 2 shows how the DPCCH is mapped to the Q branch and how the I and Q branches are combined to form a complex symbol. This process is discussed more fully in 3 GPP TS 25.212, which is hereby incorporated herein by reference in its entirety.
  • the DPCCH and DPDCHs can be spread 310 and combined 320 with high speed DPCCH (HS-DPCCH), enhanced DPDCHs (E-DPDCHs), and enhanced DPCCH (E-DPCCH).
  • the combined complex symbol stream can be scrambled 330 by being multiplied with the complex sequence S dpchin .
  • a circuit can be configured to generate power control bits that are included on only one of an-phase channel or a quadrature channel, as described in U.S. Patent No. 7,706,332, which is incorporated herein by reference in its entirety.
  • a method can include inserting a complex power control sequence into a combined scrambled complex symbol stream.
  • the method can include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the method can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, spreading code number, scrambling code number, or offset.
  • the method can include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the method can include, in a further variant, generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • an apparatus can include at least one processor and at least one memory including computer program code.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to insert a complex power control sequence into a combined scrambled complex symbol stream.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to blank transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to provide at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to, based on input parameters, form a complex power control sequence in a complex power control sequence memory or generator.
  • the at least one memory and the computer program code can, in a variant, be configured to, with the at least one processor, cause the apparatus at least to combine the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the at least one memory and the computer program code can, in another variant, be configured to, with the at least one processor, cause the apparatus at least to generate the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • An apparatus can include providing means for providing a complex power control sequence.
  • the apparatus can also include inserting means for inserting a complex power control sequence into a combined scrambled complex symbol stream.
  • the apparatus can also include blanking means for blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the apparatus can also include parameter means for providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the apparatus can also include forming means for, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the apparatus can also, in a variant, include combining means for combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the apparatus can also, in another variant, include generating means for generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • the above-described apparatuses can be or include a user equipment.
  • a non-transitory computer readable medium can, in certain embodiments, be encoded with instructions that, when executed in hardware, perform a process.
  • the process can be any of the above-described methods in any of their variants.
  • Figure 1 illustrates a frame structure for uplink DPDCH/DPCCH.
  • Figure 2 illustrates spreading for uplink DPCCH DPDCHs.
  • Figure 3 illustrates spreading for uplink dedicated channels.
  • Figure 4 illustrates a modified DPCCH according to certain embodiments.
  • Figure 5 illustrates complex power control sequence insertion according to certain embodiments.
  • Figure 6 illustrates a method according to certain embodiments.
  • Figure 7 illustrates a system according to certain embodiments.
  • Figure 4 illustrates a modified DPCCH according to certain embodiments. As shown in Figure 4, a portion of the DPCCH that would otherwise contain TPC bits, as shown in Figure 1 , can be left blank or zeroed.
  • Figure 5 illustrates complex power control sequence insertion according to certain embodiments.
  • various parameters can be input.
  • the input parameters can include, for example, up/down, beta factor, scrambling code number and offset, and the like.
  • a complex power control sequence can be formed in a complex power control sequence memory or generator 520.
  • a complex adder 530 can be configured to combine the complex power control sequence with the complex symbols provided in the complex symbol stream. For example, this can be done symbol-by-symbol, always adding one symbol from the sequence to one symbol of the stream, with a sequence timing or alignment calculated or generated by the generator 520.
  • the sequence could be based on tabulated values, the system could contain an algorithmic generator, or a mixed approach could be employed.
  • the sequence to insert can depend, for example, on whether an "up” or “down” command should be sent, on the spreading factor used for the control channel, the signal weight or beta factor, and/or on the scrambling sequence number and the timing/offset thereof.
  • the offset can be expressed as an absolute value or a combination of some of the following: a defined offset, frame number, or a slot number.
  • the complex power control values that are being inserted into the complex stream can be expressed as
  • Figure 6 illustrates a method according to certain embodiments.
  • the method can generally be directed to the insertion of a complex power control sequence into a combined scrambled complex symbol stream.
  • the method can include, at 620, blanking (or simply leaving them blank if that is the default state) transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in- phase branch.
  • the method can additionally include, at 630, providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the method can also include at 640, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the method can include, at 645, generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • the method can further include, at 650, combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • FIG. 7 illustrates a system according to certain embodiments of the invention.
  • a system may include several devices, such as, for example, base station 710 and UE 720.
  • the system may include more than one base station 710 or UE 720, although only one of each is shown for the purposes of illustration.
  • Each of these devices may include at least one processor, respectively indicated as 714 and 724.
  • At least one memory is provided in each device, and indicated as 715 and 725, respectively.
  • the memory may include computer program instructions or computer code contained therein.
  • Transceivers 716 and 726 are provided, and each device may also include an antenna, respectively illustrated as 717 and 727. Other configurations of these devices, for example, may be provided.
  • base station 710 and UE 720 may be configured for wired communication, rather than wireless communication, and in such a case antennas 717 and 727 would illustrate any form of communication hardware, without requiring a conventional antenna.
  • Transceivers 716 and 726 can each, independently, be a transmitter, a receiver, or both a transmitter and a receiver, or a unit or device that is configured both for transmission and reception.
  • Processors 714 and 724 can be embodied by any computational or data processing device, such as a central processing unit (CPU), application specific integrated circuit (ASIC), or comparable device.
  • the processors can be implemented as a single controller, or a plurality of controllers or processors.
  • Memories 715 and 725 can independently be any suitable storage device, such as a non-transitory computer-readable medium.
  • a hard disk drive (HDD), random access memory (RAM), flash memory, or other suitable memory can be used.
  • the memories can be combined on a single integrated circuit as the processor, or may be separate therefrom.
  • the computer program instructions stored in the memory and which may be processed by the processors can be any suitable form of computer program code, for example, a compiled or interpreted computer program written in any suitable programming language.
  • the memory and the computer program instructions can be configured, with the processor for the particular device, to cause a hardware apparatus such as base station 710 and UE 720, to perform any of the processes described above (see, for example, Figures 4-6). Therefore, in certain embodiments, a non-transitory computer-readable medium can be encoded with computer instructions that, when executed in hardware, perform a process such as one of the processes described herein. Alternatively, certain embodiments of the invention can be performed entirely in hardware.
  • Figure 7 illustrates a system including an base station 710 and a UE 720
  • embodiments of the invention may be applicable to other configurations, and configurations involving additional elements, as illustrated and discussed herein.
  • the base station may be, for example, a NodeB.
  • a method includes inserting a complex power control sequence into a combined scrambled complex symbol stream.
  • the method can further include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the method can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, spreading code number, scrambling code number, or offset.
  • the method can also include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the method can further include combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the method can also include generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • an apparatus includes at least one processor and at least one memory including computer program code.
  • the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to insert a complex power control sequence into a combined scrambled complex symbol stream.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to blank transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to provide at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to, based on input parameters, form a complex power control sequence in a complex power control sequence memory or generator.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to combine the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to generate the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • the apparatus can be or include a user equipment.
  • An apparatus includes providing means for providing a complex power control sequence.
  • the apparatus also includes inserting means for inserting a complex power control sequence into a combined scrambled complex symbol stream.
  • the apparatus can further include blanking means for blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the apparatus can include parameter means for providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the apparatus can also include forming means for, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the apparatus can further include combining means for combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the apparatus can also include generating means for generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
  • the apparatus can be or include a user equipment.
  • a non-transitory computer readable medium in certain embodiments, is encoded with instructions that, when executed in hardware, perform a process.
  • the process includes inserting a complex power control sequence into a combined scrambled complex symbol stream.
  • the process can further include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
  • the process can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
  • the process can also include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
  • the process can further include combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
  • the process can also include generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.

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Abstract

Communication systems, including third generation partnership project (3GPP) wideband code division multiple access (WCDMA), can benefit from various power control methods and signals. Indeed, radio communication technologies that use power control, such as WCDMA, may benefit from techniques that allow for efficient use of radio resources. According to certain embodiments, a method can include inserting a complex power control sequence into a combined scrambled complex symbol stream.

Description

TITLE:
Power Control Command Insertion into Complex Signal
CROSS-REFERENCE TO RELATED APPLICATION:
[0001] This application is related to and claims the priority of U.S. Provisional Patent Application 61/647,839, filed May 16, 2012, which is hereby incorporated herein by reference in its entirety.
BACKGROUND:
Field:
[0002] Communication systems, including third generation partnership project (3GPP) wideband code division multiple access (WCDMA), can benefit from various power control methods and signals. Indeed, radio communication technologies that use power control, such as WCDMA, may benefit from techniques that allow for efficient use of radio resources.
Description of the Related Art:
[0003] Many radio communication systems include power control methods and signals to allow for efficient use of radio resources. Typically, such systems' transceivers can use separate in-phase (I) and quadrature (Q) branches, which can be combined to form complex symbols.
[0004] In 3 GPP WCDMA, in the user equipment (UE) the power control command can be inserted into the Q branch, before performing the combining into a complex symbol and before performing the complex scrambling code multiplication.
[0005] This approach to power control command insertion requires the power control command to be available at a particular insertion point, early in the transmitter chain. On the other hand, other factors, such as timing issues and/or chip design constraints may not similarly value this insertion point.
[0006] Figure 1-3 illustrate power control command insertion in relation to the combination and scrambling that can occur. Figure 1 illustrates a frame structure for uplink dedicated physical data channel (DPDCH)/ dedicated physical control channel (DPCCH). Figure 1 shows how transmission power control (TPC) bits can be mapped to the DPCCH channel. This is discussed more fully in 3 GPP technical specification (TS) 25.211, which is hereby incorporated herein by reference in its entirety.
[0007] For example, as shown in Figure 1, a frame can include multiple slots, for example, fifteen slots. Within a given slot, DPDCH 110 on the in-phase branch can include Ndata data bits. Likewise, DPCCH 120 on the quadrature branch can include Npilot pilot bits, NTFCI transport format combination indicator (TFCI) bits, NFBi feedback indicator (FBI) bits, and NTPC transmit power control (TPC) bits.
[0008] Figure 2 illustrates spreading for uplink DPCCH/DPDCHs. Figure 2 shows how the DPCCH is mapped to the Q branch and how the I and Q branches are combined to form a complex symbol. This process is discussed more fully in 3 GPP TS 25.212, which is hereby incorporated herein by reference in its entirety.
[0009] As shown in Figure 2, several DPDCHs and a DPCCH can be summed on the quadrature branch 210 and several DPDCHs can be summed on the in- phase branch 220. At 230, the in-phase branch 220 and the quadrature branch 210 can be combined.
[0010] Figure 3 illustrates spreading for uplink dedicated channels. Figure 3 shows how the combined complex symbol stream can scrambled, that is, multiplied with the complex sequence Sdpchin. This process is also discussed more fully in 3 GPP TS 25.212.
[0011] As shown in Figure 3, the DPCCH and DPDCHs can be spread 310 and combined 320 with high speed DPCCH (HS-DPCCH), enhanced DPDCHs (E-DPDCHs), and enhanced DPCCH (E-DPCCH). The combined complex symbol stream can be scrambled 330 by being multiplied with the complex sequence Sdpchin.
[0012] For example, in certain radio systems a circuit can be configured to generate power control bits that are included on only one of an-phase channel or a quadrature channel, as described in U.S. Patent No. 7,706,332, which is incorporated herein by reference in its entirety.
[0013] To summarize, conventionally the real-valued power control command is inserted into the Q branch or the I branch only. The command then passes through various processing steps.
SUMMARY:
[0014] According to certain embodiments, a method can include inserting a complex power control sequence into a combined scrambled complex symbol stream.
[0015] In a variant, the method can include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0016] In another variant, the method can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, spreading code number, scrambling code number, or offset.
[0017] In a further variant, the method can include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
[0018] The method can also include, in a variant, combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0019] The method can include, in a further variant, generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0020] In certain embodiments, an apparatus can include at least one processor and at least one memory including computer program code. The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to insert a complex power control sequence into a combined scrambled complex symbol stream.
[0021] In a variant, the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to blank transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0022] In another variant, the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to provide at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0023] In a further variant, the at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to, based on input parameters, form a complex power control sequence in a complex power control sequence memory or generator.
[0024] The at least one memory and the computer program code can, in a variant, be configured to, with the at least one processor, cause the apparatus at least to combine the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0025] The at least one memory and the computer program code can, in another variant, be configured to, with the at least one processor, cause the apparatus at least to generate the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0026] An apparatus, according to certain embodiments, can include providing means for providing a complex power control sequence. The apparatus can also include inserting means for inserting a complex power control sequence into a combined scrambled complex symbol stream.
[0027] In a variant, the apparatus can also include blanking means for blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch. [0028] In another variant, the apparatus can also include parameter means for providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0029] In a further variant, the apparatus can also include forming means for, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
[0030] The apparatus can also, in a variant, include combining means for combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0031] The apparatus can also, in another variant, include generating means for generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0032] The above-described apparatuses can be or include a user equipment.
[0033] A non-transitory computer readable medium can, in certain embodiments, be encoded with instructions that, when executed in hardware, perform a process. The process can be any of the above-described methods in any of their variants.
BRIEF DESCRIPTION OF THE DRAWINGS:
[0034] For proper understanding of the invention, reference should be made to the accompanying drawings, wherein:
[0035] Figure 1 illustrates a frame structure for uplink DPDCH/DPCCH.
[0036] Figure 2 illustrates spreading for uplink DPCCH DPDCHs.
[0037] Figure 3 illustrates spreading for uplink dedicated channels.
[0038] Figure 4 illustrates a modified DPCCH according to certain embodiments.
[0039] Figure 5 illustrates complex power control sequence insertion according to certain embodiments.
[0040] Figure 6 illustrates a method according to certain embodiments.
[0041] Figure 7 illustrates a system according to certain embodiments. DETAILED DESCRIPTION:
[0042] Certain embodiments, rather than inserting a real-valued power control command into the Q branch, instead insert a complex-valued power control sequence into a combined scrambled complex symbol stream.
[0043] Figure 4 illustrates a modified DPCCH according to certain embodiments. As shown in Figure 4, a portion of the DPCCH that would otherwise contain TPC bits, as shown in Figure 1 , can be left blank or zeroed.
[0044] Figure 5 illustrates complex power control sequence insertion according to certain embodiments. As shown in Figure 5, at 510, various parameters can be input. The input parameters can include, for example, up/down, beta factor, scrambling code number and offset, and the like. Based on these input parameters, a complex power control sequence can be formed in a complex power control sequence memory or generator 520.
[0045] Furthermore, a complex adder 530 can be configured to combine the complex power control sequence with the complex symbols provided in the complex symbol stream. For example, this can be done symbol-by-symbol, always adding one symbol from the sequence to one symbol of the stream, with a sequence timing or alignment calculated or generated by the generator 520.
[0046] For generating or storing the complex power control sequence, there are multiple options available. The sequence could be based on tabulated values, the system could contain an algorithmic generator, or a mixed approach could be employed. The sequence to insert can depend, for example, on whether an "up" or "down" command should be sent, on the spreading factor used for the control channel, the signal weight or beta factor, and/or on the scrambling sequence number and the timing/offset thereof. The offset can be expressed as an absolute value or a combination of some of the following: a defined offset, frame number, or a slot number.
[0047] In certain embodiments, the complex power control values that are being inserted into the complex stream can be expressed as
spread TPC * beta * j * complex scrambling, (Equation 1) where some of these values can be sequences or vectors.
[0048] Figure 6 illustrates a method according to certain embodiments. The method can generally be directed to the insertion of a complex power control sequence into a combined scrambled complex symbol stream.
[0049] The method can include, at 620, blanking (or simply leaving them blank if that is the default state) transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in- phase branch. The method can additionally include, at 630, providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0050] The method can also include at 640, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator. For example, the method can include, at 645, generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof. The method can further include, at 650, combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0051] Figure 7 illustrates a system according to certain embodiments of the invention. In one embodiment, a system may include several devices, such as, for example, base station 710 and UE 720. The system may include more than one base station 710 or UE 720, although only one of each is shown for the purposes of illustration. Each of these devices may include at least one processor, respectively indicated as 714 and 724. At least one memory is provided in each device, and indicated as 715 and 725, respectively. The memory may include computer program instructions or computer code contained therein. Transceivers 716 and 726 are provided, and each device may also include an antenna, respectively illustrated as 717 and 727. Other configurations of these devices, for example, may be provided. For example, base station 710 and UE 720 may be configured for wired communication, rather than wireless communication, and in such a case antennas 717 and 727 would illustrate any form of communication hardware, without requiring a conventional antenna.
[0052] Transceivers 716 and 726 can each, independently, be a transmitter, a receiver, or both a transmitter and a receiver, or a unit or device that is configured both for transmission and reception.
[0053] Processors 714 and 724 can be embodied by any computational or data processing device, such as a central processing unit (CPU), application specific integrated circuit (ASIC), or comparable device. The processors can be implemented as a single controller, or a plurality of controllers or processors.
[0054] Memories 715 and 725 can independently be any suitable storage device, such as a non-transitory computer-readable medium. A hard disk drive (HDD), random access memory (RAM), flash memory, or other suitable memory can be used. The memories can be combined on a single integrated circuit as the processor, or may be separate therefrom. Furthermore, the computer program instructions stored in the memory and which may be processed by the processors can be any suitable form of computer program code, for example, a compiled or interpreted computer program written in any suitable programming language.
[0055] The memory and the computer program instructions can be configured, with the processor for the particular device, to cause a hardware apparatus such as base station 710 and UE 720, to perform any of the processes described above (see, for example, Figures 4-6). Therefore, in certain embodiments, a non-transitory computer-readable medium can be encoded with computer instructions that, when executed in hardware, perform a process such as one of the processes described herein. Alternatively, certain embodiments of the invention can be performed entirely in hardware.
[0056] Furthermore, although Figure 7 illustrates a system including an base station 710 and a UE 720, embodiments of the invention may be applicable to other configurations, and configurations involving additional elements, as illustrated and discussed herein. For example, multiple user equipment devices and base stations can be present. The base station may be, for example, a NodeB.
[0057] According to certain embodiments, a method includes inserting a complex power control sequence into a combined scrambled complex symbol stream.
[0058] The method can further include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0059] The method can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, spreading code number, scrambling code number, or offset.
[0060] The method can also include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
[0061] The method can further include combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0062] The method can also include generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0063] In certain embodiments, an apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to insert a complex power control sequence into a combined scrambled complex symbol stream.
[0064] The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to blank transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0065] The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to provide at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0066] The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to, based on input parameters, form a complex power control sequence in a complex power control sequence memory or generator.
[0067] The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to combine the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0068] The at least one memory and the computer program code can be configured to, with the at least one processor, cause the apparatus at least to generate the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0069] The apparatus can be or include a user equipment.
[0070] An apparatus, according to certain embodiments, includes providing means for providing a complex power control sequence. The apparatus also includes inserting means for inserting a complex power control sequence into a combined scrambled complex symbol stream.
[0071] The apparatus can further include blanking means for blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0072] The apparatus can include parameter means for providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0073] The apparatus can also include forming means for, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
[0074] The apparatus can further include combining means for combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0075] The apparatus can also include generating means for generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0076] The apparatus can be or include a user equipment.
[0077] A non-transitory computer readable medium, in certain embodiments, is encoded with instructions that, when executed in hardware, perform a process. The process includes inserting a complex power control sequence into a combined scrambled complex symbol stream.
[0078] The process can further include blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
[0079] The process can include providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
[0080] The process can also include, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
[0081] The process can further include combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
[0082] The process can also include generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
[0083] One having ordinary skill in the art will readily understand that the invention as discussed above may be practiced with steps in a different order, and/or with hardware elements in configurations which are different than those which are disclosed. Therefore, although the invention has been described based upon these preferred embodiments, it would be apparent to those of skill in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention.

Claims

WE CLAIM:
1. A method, comprising:
inserting a complex power control sequence into a combined scrambled complex symbol stream.
2. The method of claim 1, further comprising:
blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in-phase branch.
3. The method of claim 1 or claim 2, further comprising:
providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, spreading code number, scrambling code number, or offset.
4. The method of any of claims 1-3, further comprising:
based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
5. The method of any of claims 1-4, further comprising:
combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
6. The method of any of claims 1-5, further comprising:
generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
7. An apparatus, comprising:
at least one processor; and
at least one memory including computer program code,
wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to insert a complex power control sequence into a combined scrambled complex symbol stream.
8. The apparatus of claim 7, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to blank transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in- phase branch.
9. The apparatus of claim 7 or claim 8, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to provide at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
10. The apparatus of any of claims 7-9, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to, based on input parameters, form a complex power control sequence in a complex power control sequence memory or generator.
11. The apparatus of any of claims 7-10, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to combine the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
12. The apparatus of any of claims 7-11, wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to generate the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
13. An apparatus, comprising:
providing means for providing a complex power control sequence; and inserting means for inserting a complex power control sequence into a combined scrambled complex symbol stream.
14. The apparatus of claim 13, further comprising:
blanking means for blanking transmission power control bits in a quadrature branch prior to combination of the quadrature branch and an in- phase branch.
15. The apparatus of claim 13 or claim 14, further comprising:
parameter means for providing at least one of the following parameters to a complex power control sequence generator: up/down, beta factor, scrambling code number, or offset.
16. The apparatus of any of claims 13-15, further comprising:
forming means for, based on input parameters, forming a complex power control sequence in a complex power control sequence memory or generator.
17. The apparatus of any of claims 13-16, further comprising:
combining means for combining the complex power control sequence with one or more complex symbol(s) provided in a complex symbol stream.
18. The apparatus of any of claims 13-17, further comprising:
generating means for generating the complex power control sequence based on tabulated values, an algorithmic generator, or a combination thereof.
19. The apparatus of any of claims 7-18, wherein the apparatus is or comprises a user equipment.
20. A non-transitory computer readable medium encoded with instructions that, when executed in hardware, perform a process, wherein the process comprises the method according to any of claims 1-6.
PCT/US2013/041425 2012-05-16 2013-05-16 Power control command insertion into complex signal WO2013173628A1 (en)

Applications Claiming Priority (2)

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US61/647,839 2012-05-16

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Citations (2)

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Publication number Priority date Publication date Assignee Title
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US7706332B2 (en) 1995-06-30 2010-04-27 Interdigital Technology Corporation Method and subscriber unit for performing power control

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US7706332B2 (en) 1995-06-30 2010-04-27 Interdigital Technology Corporation Method and subscriber unit for performing power control
AU2003244550A1 (en) * 1999-08-05 2003-10-02 Electronics And Telecommunications Research Institute Method and Apparatus for Orthogonal Code Hopping Multiplexing Communications

Non-Patent Citations (1)

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