WO2013168907A1

WO2013168907A1 - Semiconductor memory system and operating method for same

Info

Publication number: WO2013168907A1
Application number: PCT/KR2013/003307
Authority: WO
Inventors: 황선모
Original assignee: 주식회사 디에이아이오
Priority date: 2012-05-09
Filing date: 2013-04-18
Publication date: 2013-11-14
Also published as: KR101429183B1; KR20130125556A

Abstract

A semiconductor memory system comprises at least one DRAM device and one NAND flash memory system. The DRAM device operates connected to a host on the basis of a DRAM interface. The NAND flash memory system is provided with at least one NAND flash memory device, operates connected to a host on the basis of a DRAM interface, and runs a background operation for the NAND flash memory device when a refresh command or a power-down command is input into the DRAM device.

Description

Semiconductor memory system and operation method thereof

The present invention relates to a semiconductor memory system, and more particularly, to a semiconductor memory system having a dynamic random access memory (DRAM) device and a NAND flash memory device.

The semiconductor memory device may be classified into a volatile memory device and a nonvolatile memory device according to whether data can be stored in a state where power is not supplied. With the trend toward miniaturization and large capacity of semiconductor memory devices, DRAM devices are widely used among volatile memory devices, and NAND flash memory devices are widely used among nonvolatile memory devices.

In general, the DRAM device should perform a power down operation and a refresh operation according to the inherent characteristics of the DRAM device. For example, a DRAM device must enter a power-down mode (ie, perform a power-down operation) to minimize power consumption when not in use for some time, and the data stored in the capacitor of the memory cell. In order to prevent data loss due to spontaneous leakage, the system must enter a refresh mode (ie, perform a refresh operation).

Similarly, since a NAND flash memory device does not support an overwrite operation unlike a hard disk, an erase before write operation must be performed in units of blocks, and a background according to the inherent characteristics of the NAND flash memory device is required. You must perform the action. In this case, the background operation is a garbage collection operation (e.g., a merge operation, a compaction operation, etc.) and memory cells for efficiently processing valid and invalid pages. Wear-leveling operations to level wear.

Therefore, since a conventional semiconductor memory system having both a DRAM device and a NAND flash memory device must perform operations in accordance with their respective unique characteristics, the user or the host individually perform the operations in accordance with the unique characteristics. It can be appreciated that the overall performance of the conventional semiconductor memory system can not be optimized and efficient.

An object of the present invention includes at least one DRAM device and a NAND flash memory system connected to and operated based on a host and a DRAM interface, and when a refresh command or a power down command is input to the DRAM device, the NAND flash memory system is input. The present invention provides a semiconductor memory system for performing a background operation on at least one NAND flash memory device and a method of operating the same. However, the problem to be solved of the present invention is not limited thereto, and may be variously expanded within a range without departing from the spirit and scope of the present invention.

In order to achieve the object of the present invention, the semiconductor memory system according to the embodiments of the present invention, at least one DRAM device and connected to the host based on the DRAM interface (DRAM interface), and at least one NAND flash memory And a device connected to the host based on the DRAM interface, and when a refresh command or a power-down command is input to the DRAM device, the background of the NAND flash memory device is input. It may include a NAND flash memory system that performs a background operation.

According to an embodiment, the background operation may include at least one of a wear-leveling operation and a garbage collection operation.

In example embodiments, the NAND flash memory system may include a storage controller that converts a DRAM interface command input from the host into a NAND flash command to control the NAND flash memory device.

In example embodiments, the storage controller may receive the DRAM interface command, convert the DRAM interface command into a first internal signal, and process the first internal signal to process the NAND flash. And a processing unit for generating a second internal signal for controlling the memory device, and a NAND flash control unit for controlling the NAND flash memory device based on the second internal signal.

In order to achieve the object of the present invention, a method of operating a semiconductor memory system according to an embodiment of the present invention receives a DRAM interface (DRAM interface) command from the host, the DRAM interface command to the DRAM device (refresh) ) Is a command or a power-down command, and if the DRAM interface command is the refresh command or the power-down command for the DRAM device, a background operation for the NAND flash memory device is performed. Can be.

In example embodiments, the NAND flash memory device may be provided in a NAND flash memory system, and the host, the DRAM device, and the NAND flash memory system may be connected and operated based on a DRAM interface.

In example embodiments, the method of operating the semiconductor memory system may convert the DRAM interface command into a NAND interface command for controlling the NAND flash memory device.

A semiconductor memory system and a method of operating the same according to embodiments of the present disclosure may include at least one DRAM device and a NAND flash memory system that are connected and operated based on a host and a DRAM interface, and include a refresh command or a power to the DRAM device. When a down command is input, the background operation is performed on at least one NAND flash memory device included in the NAND flash memory system, thereby not affecting the operation of the central processing unit included in the host, and in the NAND flash memory system. Background operation can be performed. Furthermore, when the refresh operation or the power down operation is performed on the DRAM device in the semiconductor memory system, the background operation is performed on the NAND flash memory device, and thus the overall performance of the semiconductor memory system may be optimized and efficient. However, the effects of the present invention are not limited thereto, and may be variously extended within a range without departing from the spirit and scope of the present invention.

1 is a block diagram illustrating a semiconductor memory system according to example embodiments.

FIG. 2 is a flowchart illustrating an operating method of operating the semiconductor memory system of FIG. 1.

3 is a block diagram illustrating a NAND flash memory system included in the semiconductor memory system of FIG. 1.

FIG. 4 is a block diagram illustrating a storage controller of the NAND flash memory system of FIG. 3.

FIG. 5 is a flowchart illustrating an operating method of operating the NAND flash memory system of FIG. 3.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

Referring to FIG. 1, the semiconductor memory system 100 includes at least one DRAM device 120 and a NAND flash memory system 140, and the DRAM device 120 and the NAND flash memory system 140 may include a DRAM. It may be connected to the host 200 based on an interface 160 (ie, a structure using a DRAM bus). Meanwhile, the NAND flash memory system 160 may include an embedded multi-media card (EMMC), a secure digital card, a compact flash card, a memory stick, and an XD picture card. XD picture card).

The DRAM device 120 may be connected to the host 200 and operate based on the DRAM interface 160. That is, the DRAM device 120 may operate based on a DRAM interface command output from the host 200. The DRAM device 120 receives a read command to the DRAM device 120 from the host 200 to perform a read operation, and receives a write command to the DRAM device 120 to perform a write operation. Can be done. Meanwhile, the DRAM device 120 should perform a power down operation and a refresh operation according to the inherent characteristics of the DRAM device 120. For example, upon receiving a power-down command for the DRAM device 120 from the host 200, the DRAM device 120 performs a power-down operation to minimize power consumption. can do. In addition, upon receiving a refresh command for the DRAM device 120 from the host 200, the DRAM device 120 may prevent data loss due to natural leakage of data stored in a capacitor of a memory cell. The refresh operation may be performed. However, since the DRAM interface commands related to the operation of the DRAM device 120 are general to those skilled in the art, a detailed description thereof will be omitted.

The NAND flash memory system 140 may include at least one NAND flash memory device, and may be connected to the host 200 and operate based on the DRAM interface 160. That is, the NAND flash memory system 140 may also operate based on a DRAM interface command output from the host 200 like the DRAM device 120. To this end, the NAND flash memory system 140 may include a storage controller that converts a DRAM interface command input from the host 200 into a NAND flash command to control at least one NAND flash memory device. In one embodiment, the storage controller receives a DRAM interface command and converts the DRAM interface command into a first internal signal, and a second interface corresponding to the NAND flash command by processing the first internal signal. And a NAND flash control unit for controlling the NAND flash memory device based on the second internal signal and the processing unit for generating the internal signal. However, this will be described later with reference to FIGS. 3 and 4.

On the other hand, since the NAND flash memory device provided in the NAND flash memory system 140 does not support an overwrite operation unlike a hard disk, an erase operation must be performed in units of blocks before writing. You need to perform a background action based on the characteristics. In this case, the background operation may include at least one of a wear-leveling operation and a garbage collection operation. As described above, in the semiconductor memory system 100 including heterogeneous semiconductor memory devices (ie, the DRAM device 120 and the NAND flash memory system 140), each of these operations may be efficiently performed (eg, For example, at the same time, it is necessary for the user or host 200 not to feel that the operations according to the unique characteristics are performed separately. For example, when the host 200 individually performs operations according to unique characteristics of the DRAM device 120 and the NAND flash memory system 140, a central processing unit (CPU) of the host 200 may be used. ) May consume resources, which may degrade the overall performance of the semiconductor memory system 100.

Accordingly, the NAND flash memory system 140 is connected to the host 200 based on the DRAM interface 160 to operate, and when a refresh command or a power down command is input to the DRAM device 120, the NAND is provided therein. Background operations on the flash memory device may be performed. In other words, when the semiconductor memory system 100 performs a refresh operation or a power-down operation according to the characteristic of the DRAM device 120, the characteristic of the NAND flash memory device included in the NAND flash memory system 140 is provided. To perform the background operation. This is because the storage controller of the NAND flash memory system 140 converts a DRAM interface command into a NAND flash command, and performs a background operation on the NAND flash memory device by performing a refresh command or a power down command on the DRAM device 120. It can be implemented by interpreting the NAND flash command. As a result, in the semiconductor memory system 100, when the DRAM device 120 performs a refresh operation or a power down operation, the NAND flash memory system 140 may perform a background operation.

As described above, the semiconductor memory system 100 includes at least one DRAM device 120 and a NAND flash memory system 140 that are connected to and operate on the basis of a DRAM interface with the host 200. When the refresh command or the power-down command for the 120 is input, the background operation is performed on the NAND flash memory device included in the NAND flash memory system 140, and thus the operation of the central processing unit provided in the host 200 is performed. Without affecting (ie, the central processing unit provided in the host 200 does not need to perform a separate operation for a background operation on the NAND flash memory device provided in the NAND flash memory system 140). The background operation may be performed in the flash memory system 140. Further, when the refresh operation or the power down operation is performed on the DRAM device 120 in the semiconductor memory system 100, the background operation on the NAND flash memory device is performed in the NAND flash memory system 140 (that is, the NAND flash). The NAND flash memory device provided in the memory system 140 does not require a refresh operation, and when the DRAM device 120 enters a power down mode, the host 200 accesses the NAND flash memory system 140. The overall performance of the semiconductor memory system 100 can be optimized and efficient.

Referring to FIG. 2, in the method of operating the semiconductor memory system 100, a DRAM interface command is received from the host 200 (Step S120), and whether the DRAM interface command is a refresh command or a power down command for the DRAM device 120. It may be determined (Step S140). In this case, when the DRAM interface command is a refresh command or a power down command for the DRAM device 120, a background operation may be performed on the NAND flash memory device included in the NAND flash memory system 140 (Step S160). . However, the operating method of the semiconductor memory system 100 is a method for a NAND flash memory device provided in the NAND flash memory system 140 when the DRAM interface command is not a refresh command or a power down command for the DRAM device 120. The read operation or the write operation may be performed based on the DRAM interface command (ie, the read command or the write command) to the NAND flash memory system 140 without performing the background operation (Step S180). As described above, the background operation may include at least one of a wear leveling operation and a garbage collection operation. However, it should be understood that the background operation is not limited to the wear leveling operation and the garbage collection operation, and encompasses all operations according to the inherent characteristics of the NAND flash memory device except for the read operation and the write operation. Also, in the semiconductor memory system 100, the host 200, the DRAM device 120, and the NAND flash memory system 140 are connected and operated based on a DRAM interface, and the host 200, the DRAM device 120, and The NAND flash memory system 140 uses a DRAM bus. Therefore, the method of operating the semiconductor memory system 100 may further include converting a DRAM interface command into a NAND interface command for controlling the NAND flash memory device.

FIG. 3 is a block diagram illustrating a NAND flash memory system included in the semiconductor memory system of FIG. 1, and FIG. 4 is a block diagram illustrating a storage controller of the NAND flash memory system of FIG. 3.

3 and 4, the NAND flash memory system 140 may include a storage controller 141 and at least one NAND flash memory device 149_1,..., 149_n, and the storage controller 141. May include a DRAM interface command conversion unit 142, a processing unit 143, and a NAND flash control unit 147.

The storage controller 141 may control the first to nth (where n is an integer of 1 or more) NAND flash memory devices 149_1,..., 149_n by serving as a general NAND flash controller. However, in the semiconductor memory system 100, since the host 200, the DRAM device 120, and the NAND flash memory system 140 are connected and operated based on the DRAM interface, the storage controller 141 may operate from the host 200. The first to nth NAND flash memory devices 149_1 to 149_n may be controlled by converting the input DRAM interface command into a NAND flash command. To this end, the storage controller 141 receives the DRAM interface command, processes the DRAM interface command conversion unit 142 and the first internal signal IC_1 to convert the DRAM interface command into the first internal signal IC_1, and NAND. A processing unit 143 which generates a second internal signal IC_2 corresponding to the flash command, and first to nth NAND flash memory devices 149_1,..., 149_n based on the second internal signal IC_2. May include a NAND flash control unit 147.

In detail, the DRAM interface command conversion unit 142 may generate a DRAM interface command for performing a read operation or a write operation on the first to nth NAND flash memory devices 149_1,..., 149_n. 1 may be converted into an internal signal IC_1 and provided to the processing unit 143, and a DRAM interface command for performing a refresh operation or a power down operation on the DRAM device 120 may correspond to the first internal signal IC_1. ) And provide it to the processing unit 143. Thereafter, the processing unit 143 processes the first internal signal IC_1 to perform a read operation or a write operation on the first to nth NAND flash memory devices 149_1,..., 149_n. NAND flash by generating a second internal signal IC_2 or a second internal signal IC_2 for performing a background operation on the first to nth NAND flash memory devices 149_1,..., 149_n Can be provided to the control unit 147. To this end, the processing unit 143 may include an internal processor 144, an internal controller 145, an internal RAM 146, and the like. Thereafter, the NAND flash control unit 147 controls the first to nth NAND flash memory devices 149_1,..., 149_n based on the second internal signal IC_2 (ie, a read operation or a write operation). Or background operations). However, the configuration of the storage controller 141 is an example, and the configuration of the storage controller 141 is not limited to the configuration illustrated in FIG. 4.

As described above, the NAND flash memory system 140 converts a DRAM interface command input from the host 200 into a NAND flash command to be connected to and operate based on the DRAM interface with the host 200. The storage controller 141 may control the flash memory devices 149_1,..., And 149_n, and the storage controller 141 may receive a refresh command or a power-down command for the DRAM device 120. The background operations of the first to nth NAND flash memory devices 149_1,..., 149_n included in the NAND flash memory system 140 may be performed. As a result, the background operation on the first to nth NAND flash memory devices 149_1,..., 149_n may not burden the central processing unit provided in the host 200, and the DRAM device 120 When the refresh operation or the power-down operation is performed for the background operation with respect to the first to nth flash memory devices 149_1,..., 149_n, the user or the host 200 may use the DRAM device ( The operations according to the inherent characteristics of the 120 and the first to nth NAND flash memory devices 149_1,..., 149_n may not be felt to be performed separately. As a result, the overall performance of the semiconductor memory system 100 including the DRAM device 120 and the NAND flash memory system 140 may be optimized and efficient.

Referring to FIG. 5, in the operating method of the NAND flash memory system 140, the DRAM interface command conversion unit 142 receives the DRAM interface command from the host 200 (Step S220), and the DRAM interface command conversion unit 142. ) Converts the DRAM interface command into a first internal signal IC_1 and outputs it to the processing unit 143 (Step S240), and the processing unit 143 processes the first internal signal IC_1 to produce a second internal signal. IC_2 can be output to the NAND flash control unit 147 (Step S260). Subsequently, in the method of operating the NAND flash memory system 140, the NAND flash control unit 147 may include the first to nth NAND flash memory devices 149_1,..., 149_n based on the second internal signal IC_2. Can be controlled (Step S280). In this case, the operation method of the NAND flash memory system 140 may include the first to nth NAND flash memory devices 149_1,..., 149_n when a refresh command or a power down command is input to the DRAM device 120. When a read command or a write command for the first to nth NAND flash memory devices 149_1,..., 149_n is input, the first to nth NAND flash memory devices may be performed. A read operation or a write operation may be performed on 149_1,..., And 149_n.

In one embodiment, when the DRAM interface command conversion unit 142 receives a refresh command or a power down command for the DRAM device 120 from the host 200, the DRAM interface command conversion unit 142 may execute the DRAM device 120. Converts the refresh command or the power down command to the first internal signal IC_1 and outputs the converted command to the processing unit 143 (specifically, the internal controller 145), and the processing unit 143 (specifically, the internal processor ( 144) converts the first internal signal IC_1 into a second internal signal IC_2 for performing a background operation on the first to nth NAND flash memory devices 149_1,..., 149_n. It can output to the flash control unit 147. Accordingly, the NAND flash control unit 147 may perform a background operation on the first to nth NAND flash memory devices 149_1,..., 149_n based on the second internal signal IC_2.

In another embodiment, the DRAM interface command conversion unit 142 receives a read command or a write command for the first to nth NAND flash memory devices 149_1,..., 149_n from the host 200. The command conversion unit 142 converts the read command or write command for the first to nth NAND flash memory devices 149_1,..., 149_n into a first internal signal IC_1 to process the unit 143 (specifically). And output to the internal controller 145, and the processing unit 143 (specifically, the internal processor 144) transmits the first internal signal IC_1 to the first to nth NAND flash memory devices 149_1. ..., 149_n may be converted into a second internal signal IC_2 for performing a read operation or a write operation and output to the NAND flash control unit 147. Accordingly, the NAND flash control unit 147 may perform a read operation or a write operation on the first to nth NAND flash memory devices 149_1,..., 149_n based on the second internal signal IC_2. Can be.

As described above, the NAND flash memory system 140 may be connected to the host 200 with the DRAM device 120 through a DRAM interface (that is, a structure using a DRAM bus) to operate the NAND flash memory system 140. For example, when the refresh operation or the power down operation is performed on the DRAM device 120, the background operation may be performed on the first to n th flash memory devices 149_1,..., And 149_n. As a result, the overall performance of the semiconductor memory system 100 including the DRAM device 120 and the NAND flash memory system 140 may be optimized and efficient. The semiconductor memory system, the method of operating the semiconductor memory system, the NAND flash memory system, and the method of operating the NAND flash memory system according to the exemplary embodiments of the present invention have been described above with reference to the drawings. Modifications and changes may be made by those skilled in the art without departing from the spirit of the invention.

The present invention can be applied to an electronic device using a semiconductor memory system. Therefore, the present invention can be applied to a computer, a notebook, a digital camera, a mobile phone, a smart phone, a smart pad, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a navigation, a video phone, and the like.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be appreciated.

[Description of the code]

100: semiconductor memory system 120: DRAM device

140: NAND flash memory system 160: DRAM interface

200: host

Claims

At least one DRAM device connected to and operated by a host based on a DRAM interface; And

The NAND device includes at least one NAND flash memory device and is connected to the host based on the DRAM interface, and operates when a refresh command or a power-down command is input to the DRAM device. A semiconductor memory system comprising a NAND flash memory system that performs a background operation for a flash memory device.
The semiconductor memory system of claim 1, wherein the background operation comprises at least one of a wear-leveling operation and a garbage collection operation.
The NAND flash memory system of claim 2, wherein

And a storage controller converting the DRAM interface command input from the host into a NAND flash command to control the NAND flash memory device.
The method of claim 3, wherein the storage controller is

A DRAM interface command converting unit which receives the DRAM interface command and converts the DRAM interface command into a first internal signal;

A processing unit for processing the first internal signal to generate a second internal signal corresponding to the NAND flash command; And

And a NAND flash control unit for controlling the NAND flash memory device based on the second internal signal.
Receiving a DRAM interface command from a host;

Determining whether the DRAM interface command is a refresh command or a power-down command for the DRAM device; And

If the DRAM interface command is the refresh command or the power-down command for the DRAM device, performing a background operation on a NAND flash memory device.
6. The method of claim 5, wherein the background operation comprises at least one of a wear-leveling operation and a garbage collection operation.
The semiconductor memory system of claim 6, wherein the NAND flash memory device is provided in a NAND flash memory system, and the host, the DRAM device, and the NAND flash memory system are connected and operated based on a DRAM interface. How it works.
The method of claim 7, wherein

Converting the DRAM interface command into a NAND interface command for controlling the NAND flash memory device.