WO2013155845A1

WO2013155845A1 - Method for manufacturing array substrate, array substrate, and display device

Info

Publication number: WO2013155845A1
Application number: PCT/CN2012/085967
Authority: WO
Inventors: 金玟秀; 邓立赟; 周纪登
Original assignee: 京东方科技集团股份有限公司; 合肥京东方光电科技有限公司
Priority date: 2012-04-20
Filing date: 2012-12-05
Publication date: 2013-10-24
Also published as: CN102707523A

Abstract

Provided are a method for manufacturing an array substrate, the array substrate, and a display device. The array substrate may comprise a display area and a non-display area. The display area comprises a gate line, a data line (8), and multiple pixel units defined by the gate line and by the data line (8). Each pixel unit may comprise a thin-film transistor, a pixel electrode (12), and a common electrode (16). The pixel electrode (12) is connected to a drain electrode (7) of the thin-film transistor. An organic insulating film (10) may be arranged between the pixel electrode (12) and the data line (8). The array substrate is capable of reducing signal delays on the data line (8) in the array substrate and of increasing pixel aperture ratio.

Description

Array substrate manufacturing method, array substrate and display device

Embodiments of the present invention relate to a method of fabricating an array substrate, an array substrate, and a display device. Background technique

Thin film transistor liquid crystal displays (TFT-LCDs) have a small size, low power consumption, and no radiation, and they dominate the current flat panel display market. The advanced super-dimensional field switching technology (ADS) uses a field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, so that the liquid crystal cell is narrow. All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency. Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.

ADS mode TFT-LCD uses the fringe field effect between the common electrode and the pixel electrode to drive the liquid crystal. According to its electrode design and interlayer structure, the liquid crystal transmittance and other characteristics have a great change. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an array substrate of a prior art ADS mode liquid crystal display. As shown in FIG. 1, in the array substrate, a gate electrode 2 is formed on a substrate 1, a gate insulating layer 4 is formed on the gate electrode 2, and a semiconductor layer 5, a source electrode 6 and a drain electrode are formed on the gate insulating layer 4. 7 are formed on the semiconductor layer 5 and spaced apart from each other, the pixel electrode 12 is formed on the gate insulating layer 4 and electrically connected to the drain electrode 7, and the common electrode 16 is formed on the protective film 13, a gate line (not shown) and a data line 8 defines a pixel region, a gate pad 3 is formed on the substrate 1, and a data pad 9 is formed on the gate insulating layer 4. In order to prevent light leakage, a portion of the common electrode 162 is formed over the data line 8.

In the above array substrate, there is a parasitic capacitance between the common electrode 162 and the data line 8

(Cdp_data to Vcom), there is also a parasitic capacitance (Cdp_data to pixel) between the pixel electrode 12 and the data line 8. Structurally, when the distance between the pixel electrode 12 and the data line 8 is small, the parasitic capacitance is relatively large, which affects the charging characteristics of the pixel electrode 12, which in turn affects the quality of the display, resulting in stains on the screen. , afterimage or flickering. For this reason, it is necessary to increase the distance between the pixel electrode 12 and the data line 8 to reduce the parasitic capacitance, but this causes the aperture ratio of the pixel to decrease. In addition, when the parasitic capacitance between the common electrode 162 and the data line 8 is large, the signal on the data line 8 is delayed. The higher the resolution of the liquid crystal display and the larger the area, the more severe the signal delay. In the existing method of improving the signal delay, the parasitic capacitance is mainly reduced by increasing the thickness of the protective film 13 between the data line 8 and the common electrode 162, but this causes a drastic increase in manufacturing time and manufacturing cost. Summary of the invention

A technical problem to be solved by embodiments of the present invention is to provide a method for fabricating an array substrate, an array substrate, and a display device to reduce signal delay on a data line in the array substrate.

Embodiments of the present invention provide an array substrate including a display area and a non-display area, the display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, each of which The pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, and an organic insulating film is disposed between the pixel electrode and the data line.

The embodiment of the invention further provides a method for manufacturing an array substrate, comprising:

Forming a gate electrode, a gate line, and a gate pad on the substrate;

Forming a gate insulating layer on the substrate on which the gate electrode, the gate line, and the gate pad are formed;

Forming a semiconductor layer, a source electrode, a drain electrode, a data line, and a data pad on the substrate on which the gate insulating layer is formed;

Forming an organic insulating film on the substrate on which the semiconductor layer, the source electrode, the drain electrode, the data line, and the data pad are formed, and patterning the organic insulating film to Forming a first contact hole in the organic insulating film and exposing the gate insulating layer and the data pad at the gate pad;

A pixel electrode is formed on the substrate on which the organic insulating film is formed, and the pixel electrode is electrically connected to the drain electrode through the first contact hole.

The embodiment of the invention further provides a display device comprising the above array substrate.

The technical solution of the embodiment of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality. Compared with the prior art, by increasing the thickness of the protective film to reduce the parasitic capacitance, the technical solution of the present invention can also reduce the process time and reduce the manufacturing cost. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a cross-sectional view of an array substrate of a prior art ADS mode liquid crystal display; FIG. 2 to FIG. 13 are cross-sectional views of an array substrate in a method of fabricating an array substrate according to an embodiment of the present invention;

Figure 14 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Embodiments of the present invention provide an array substrate including a display area including a gate line, a data line, and a plurality of pixel units between the gate line and the data line, wherein the non-display area includes a gate a pad and a data pad, wherein the pixel unit includes a thin film transistor, a pixel electrode, and a common electrode, wherein the pixel electrode is connected to a drain electrode of the thin film transistor, wherein the common electrode includes a pixel electrode a first common electrode and a second common electrode located above the data line; a protective film is disposed between the layer where the common electrode is located and the layer where the pixel electrode is located; between the pixel electrode and the data line, and An organic insulating film is disposed between the thin film transistor and the protective film.

The technical solution of the embodiment of the present invention reduces the parasitic capacitance between the common electrode and the data line by applying a low dielectric constant organic insulating film to the array substrate, thereby reducing signal delay on the data line and improving display quality.

In the embodiment of the present invention, in addition to the above structure, the substrate structure of the array substrate may be set according to actual conditions, for example, the thin film transistor may be a top gate structure or a bottom gate structure; a connection manner of the pixel electrode and the drain electrode It may be a lap joint, a through-hole connection, or the like, which is not limited herein. The following is an exemplary example of an array substrate, which is a technical method of an embodiment of the present invention. The case is explained.

Figure 14 is a cross-sectional view of an array substrate in accordance with an embodiment of the present invention. Referring to FIG. 14, the array substrate may include: a substrate 1; a gate electrode 2, a gate line (not shown), and a gate pad 3 formed on the substrate 1; a gate insulating layer 4 formed on the gate electrode 2 and the gate line The semiconductor layer 5, the data line 8 and the data pad 9, are formed on the gate insulating layer 4; the source electrode 6 and the drain electrode 7 are formed on the semiconductor layer 5; the organic insulating film 10 is formed at the source electrode 6, and the drain electrode On the electrode 7, the data line 8 and the semiconductor layer 5, a first contact hole 11 is formed in the organic insulating film 10; a pixel electrode 12 is formed on the organic insulating film 10, and the pixel electrode 12 passes through the first contact hole 11 and the drain electrode 7 Electrically connected; a protective film 13 formed on the pixel electrode 12 and the organic insulating film 10; a common electrode 16 formed on the protective film 13, the common electrode 16 including the first common electrode 161 above the pixel electrode 12 and the data line 8 The upper second common electrode 162; the gate pad electrode 17, formed on the protective film 13 and at a position corresponding to the gate pad 3, the gate pad electrode 17 passes through the second through the protective film 13 and the organic insulating film 10. Contact hole 14 and The pad 3 is electrically connected; the data pad electrode 18 is formed on the protective film 13 and at a position corresponding to the data pad 9, the data pad electrode 18 passes through the third contact hole of the protective film 13 and the organic insulating film 10. 15 is electrically connected to the data pad 9.

According to the embodiment of the present invention, the data line 8 can be reduced by applying the low dielectric constant (2.0 to 4.0) of the organic insulating film 10 to the array substrate to reduce the parasitic capacitance between the common electrode 162 and the data line 8. Signal delay on the board to improve display quality. The embodiment of the present invention can also reduce the process time and reduce the manufacturing cost as compared with the prior art by reducing the thickness of the protective film 13 to reduce the parasitic capacitance.

According to the embodiment of the present invention, since the organic insulating film 10 having a low dielectric constant is used, it is also possible to reduce the horizontal direction (i.e., the direction parallel to the substrate 1) between the pixel electrode 12 and the data line 8 The distance is increased to increase the aperture ratio of the pixel, wherein the distance between the pixel electrode 12 and the data line 8 in the direction parallel to the substrate 1 can be reduced to 0 to 1 μπι.

In one embodiment, the material of the organic insulating film 10 may be made of polyacrylic acid or an organic insulating film.

The thickness of 10 can be 10,000 to 40,000 Α. If the thickness of the organic insulating film 10 is too small, the parasitic capacitance is not significantly reduced; if the thickness of the organic insulating film 10 is too large, the interlayer step portion will more likely cause a defect in the pixel electrode to be broken. When the thickness of the organic insulating film 10 is 10,000 40000 A, the above two problems can be well balanced, and the effect of reducing the parasitic capacitance can be better achieved on the basis of ensuring the yield. In addition to polyacrylic acid, the organic insulating film 10 can also be used with other organic materials having similar dielectric coefficients. Material. The protective film 13 may be made of an inorganic insulating material such as silicon nitride or the like, and has a thickness of 2000 4000 A; of course, a suitable organic material such as a transparent resin or the like may also be used.

In the embodiment of the present invention, the semiconductor layer may be left under the data line (as shown in FIG. 13), or the semiconductor layer may not be retained (as shown in FIG. 14); the source electrode and/or the drain electrode may be completely located above the semiconductor layer ( As shown in FIG. 13), it is also possible to extend to a region other than the semiconductor layer (as shown in FIG. 14). In the embodiment of the present invention, the semiconductor layer 5 may be a normal silicon semiconductor (intrinsic semiconductor or doped semiconductor), an organic semiconductor, or an oxide semiconductor.

In the embodiment of the present invention, the common electrode 16 may be in the shape of a slit, and the pixel electrode 12 may be in the form of a plate or a slit.

The embodiment of the invention further provides a display device, which comprises any of the array substrates described above. The display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

The method of manufacturing the above array substrate is given below.

Method embodiment 1

Step S11, providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate Forming a gate metal layer, the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the gate metal layer may be One or more layers; then, a photoresist is formed on the gate metal layer; then, the photoresist is exposed and developed by using a patterned mask to form a photoresist mask; then, photolithography is used The glue mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped. It should be noted that, in this step, the common electrode lines may be formed while forming the patterns of the gate lines, the gate electrodes, and the gate pads.

Step S12, forming a gate insulating layer on the substrate completing step S11;

As shown in Fig. 2, a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S11 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like. The gate insulating layer 4 may be made of an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S13, forming a semiconductor layer on the substrate on which step S12 is completed; Specifically, as shown in FIG. 3, first, a semiconductor material layer having a thickness of 1000 4000 A may be formed on the substrate 1 on which step S12 is completed by a method such as PECVD; then, a photoresist is formed on the semiconductor material layer; Etching and developing the photoresist with a patterned mask to form a photoresist mask; next, etching the semiconductor material layer with a photoresist mask to form a pattern of the semiconductor layer 5; , peel off the remaining photoresist.

Step S14, forming a source electrode, a drain electrode, a data line and a data pad on the substrate completing step S13;

Specifically, as shown in FIG. 4, first, a source/drain metal layer having a thickness of 1000 to 6000 A may be formed on the substrate 1 on which the step S13 is completed by using sputtering, thermal evaporation or other film forming methods, and the source/drain metal layer may be used. Using chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) or alloys thereof, and the source and drain metal layers may be one or more layers; Forming a photoresist on the source/drain metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; next, using a photoresist mask to the source The drain metal layer is etched to form a pattern of the source electrode 6, the drain electrode 7, the data line 8 and the data pad 9; finally, a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7 is etched away, and The remaining photoresist is stripped to complete the channel of the thin film transistor. When the semiconductor layer 5 is a silicon semiconductor structure composed of an intrinsic semiconductor and a doped semiconductor (ohmic contact layer), "etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7" mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is mainly due to etching of the source and drain metal layer Due to the etching, it is not necessary to etch away a part of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.

Step S15, forming an organic insulating film on the substrate on which step S14 is completed, and patterning the organic insulating film;

Specifically, as shown in FIG. 5, first, an organic insulating film 10 having a thickness of 10000-40000 A is formed on the substrate 1 on which the step S14 is completed, and the organic insulating film 10 can be made of an organic photosensitive material such as polyacrylic acid; The organic insulating film is exposed and developed by a patterned mask to form a first contact hole 11 and expose the gate insulating layer 4 and the gate pad 9 at positions corresponding to the data pad 3; finally, the organic insulating film 10 Curing (Cure) treatment.

In this step, if the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the organic insulating film If the thickness of 10 is too high, the slope of the step between the layers may increase, which may cause defects such as disconnection of the pixel electrode.

In this step, the curing temperature may be 230 to 260 ° C and the time may be 30 to 60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.

Step S16, forming a pixel electrode on the substrate of step S15, wherein the pixel electrode is electrically connected to the drain electrode through the first contact hole;

Specifically, as shown in FIG. 6, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S15 is completed by using magnetron sputtering, thermal evaporation, or other film forming methods, and the transparent conductive layer may be釆 using indium tin oxide (ITO), indium oxide (ΙΖΟ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the pixel electrode 12, the pixel electrode 12 passing through the first contact hole 11 and leakage The pole 7 is electrically connected; thereafter, the exposed gate insulating layer 4 is etched away with a photoresist mask to expose the gate pad 3; finally, the remaining photoresist is stripped. In each of the pixel units, the pixel electrode may be in the form of a plate or a slit.

In this step, if the thickness of the pixel electrode 12 is too small, the resistance thereof is too high; if the thickness of the pixel electrode 12 is too large, the transmittance is lowered.

The left half of Fig. 7 is a cross-sectional view of the array substrate after forming the pixel electrode according to the prior art, and the right half is a cross-sectional view of the array substrate after forming the pixel electrode according to an embodiment of the present invention. As shown in FIG. 7, in the prior art, in order to avoid the influence of the parasitic capacitance between the pixel electrode 12 and the data line 8 on the charging characteristics of the pixel electrode 12, the distance between the pixel electrode 12 and the data line 8 is dl. It is required to be larger, generally about 2 μπι, which results in a decrease in the aperture ratio of the pixel. In the embodiment of the present invention, since the organic insulating mold 10 is used, even between the pixel electrode 12 and the data line 8 The distance d2 in the horizontal direction is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 to 1 μm to increase the aperture ratio of the pixel.

Step S17, forming a protective film on the substrate on which step S16 is completed, and patterning the protective film; specifically, as shown in FIG. 8, first, a thickness of the substrate 1 on which the step S16 is completed may be formed by a method such as PECVD. 2000 4000 保护 protective film 13 , which can use SiNx Or a material such as SiOx; then, forming a photoresist on the protective film 13; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; The mask mask etches the protective film 13 to form second contact holes 14 and third contact holes 15 to expose the gate pads 3 and the data pads 9, respectively; finally, the remaining photoresist is stripped.

In this step, if the thickness of the protective film 13 is less than 2000 A, the storage capacitor (Cst) rises, causing an increase in signal delay; if the thickness of the protective film 13 is larger than 4000 A, the process time and manufacturing cost are excessively high.

Step S18, forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which the step S17 is completed.

Specifically, as shown in FIG. 14, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S17 is completed by using magnetron sputtering, thermal evaporation or other film forming methods, and the transparent conductive layer may be釆 using indium tin oxide (ITO), indium oxide (ΙΖΟ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, stripping Remaining photoresist.

The common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8. The common electrode 16 may have a slit shape. The gate pad electrode 17 is electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 is electrically connected to the data pad 9 through the third contact hole 15.

In this step, if the thickness of the common electrode 16 is too small, the resistance thereof is too high; if the thickness of the common electrode 16 is too large, the transmittance is lowered.

In the present embodiment, the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter, thereby being able to increase The aperture ratio of the pixel.

Method embodiment 2

Step S21, providing a substrate, forming a gate line, a gate electrode and a gate pad on the substrate; specifically, first, sputtering, thermal evaporation or other film forming method may be used on the glass substrate or other type of transparent substrate Forming a gate metal layer, the gate metal layer may be made of chromium (Cr), molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) and alloys thereof, and the gate metal layer may be One a layer or a plurality of layers; then, forming a photoresist on the gate metal layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; The glue mask etches the gate metal layer to form a pattern of gate lines, gate electrodes, and gate pads; finally, the remaining photoresist is stripped. It should be noted that, in this step, the common electrode lines may be formed while forming the patterns of the gate lines, the gate electrodes, and the gate pads.

Step S22, forming a gate insulating layer on the substrate on which step S21 is completed;

Specifically, as shown in Fig. 2, a gate insulating layer 4 having a thickness of 2000 8000 A may be deposited on the substrate 1 on which step S21 is completed by plasma enhanced chemical vapor deposition (PECVD) or the like. The gate insulating layer 4 may be selected from an oxide (e.g., SiOx) or a nitride (e.g., SiNx).

Step S23, forming a semiconductor material layer on the substrate completing step S22;

Specifically, as shown in Fig. 9, a semiconductor material layer 20 having a thickness of 1000 4000 A can be formed on the substrate 1 on which step S22 is completed by a method such as PECVD.

Step S24, forming a source/drain metal layer on the substrate of step S23;

Specifically, a source/drain metal layer having a thickness of 1000 6000 A may be formed on the substrate 1 on which the step S24 is completed by using sputtering, thermal evaporation or other film forming method, and the source/drain metal layer may be made of chromium (Cr) or molybdenum. (Mo), aluminum (Al), copper (Cu), tungsten (W), niobium (Nd) or an alloy thereof, and the source/drain metal layer may be one or more layers.

Step S25, forming a photoresist mask on the substrate completing step S24;

Specifically, as shown in FIG. 10, first, a photoresist layer 19 is formed on the source/drain metal layer; then, the photoresist layer 19 is exposed and developed by using a gray tone or halftone mask patterned with a pattern, A photoresist mask including a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region is formed.

Step S26, forming a pattern of the data line and the data pad;

Specifically, as shown in FIG. 11, the source/drain metal layer of the unretained region of the photoresist is etched by a photoresist mask to form a pattern of the data line 8 and the data pad 9.

Step S27, etching a semiconductor material layer in the unreserved region of the photoresist, and performing an ashing process; specifically, as shown in FIG. 12, first, using a photoresist mask to the semiconductor material in the unreserved region of the photoresist The layer 20 is etched to form a pattern of the semiconductor layer 5; then, the photoresist in the remaining portion of the photoresist is removed by an ashing process, and the photoresist in the completely remaining region of the photoresist is thinned to form a new photoresist. Mask. Step S28, forming a pattern of the source electrode and the drain electrode;

Specifically, as shown in FIG. 13, first, the exposed source/drain metal layer is etched by a photoresist mask to form a pattern of the source electrode 6 and the drain electrode 7; then, the source electrode 6 and the drain electrode 7 are etched away. A portion of the semiconductor layer 5 is interposed and the remaining photoresist is stripped to form a channel of the thin film transistor. When the semiconductor layer 5 is a silicon semiconductor structure composed of an intrinsic semiconductor and a doped semiconductor (ohmic contact layer), "etching away a portion of the semiconductor layer 5 between the source electrode 6 and the drain electrode 7" mainly means etching The ohmic contact layer between the source electrode 6 and the drain electrode 7 is dropped; and when the semiconductor layer 5 is an organic semiconductor or an oxide semiconductor, "etching away a portion of the semiconductor layer 5" is due to etching of the source and drain metal layer Therefore, it is not necessary to intentionally etch away a portion of the semiconductor layer 5, and it is only necessary to ensure that the source and drain metal layers of the channel region are completely etched away.

In the following steps, although not shown in the drawings, it is understood that the unetched semiconductor material remains under the data lines 8 and the data pads 9.

Step S29, forming an organic insulating film on the substrate on which step S28 is completed, and patterning the organic insulating film;

Specifically, as shown in FIG. 5, first, a thickness is formed on the substrate 1 which is completed in step S28.

10000-40000A organic insulating film 10, the organic insulating film 10 can be coated with an organic photosensitive material such as polyacrylic acid; then, the organic insulating film is exposed and developed by using a patterned mask to form a first contact hole 11, The gate insulating layer 4 and the gate pad 9 at the data pad 3 are exposed; finally, the organic insulating film 10 is subjected to a curing (Cure) process.

In this step, if the thickness of the organic insulating film 10 is too small, the effect of reducing the parasitic capacitance between the subsequent common electrode and the data line (relative to the inorganic insulating film) is not significant; if the thickness of the organic insulating film 10 is too large , the slope of the step between the layers will increase, which may cause defects such as disconnection of the pixel electrode.

In this step, the curing temperature can be 230~260 °C, and the processing time can be 30~60 minutes. If the curing temperature is lower than 230 ° C, the micro-cure of the protective film may cause contamination and film lift, etc.; if the curing temperature is higher than 260 ° C, the organic insulating film 10 may be denatured, thereby This makes the transmission rate low.

Step S30, forming a pixel electrode on the substrate completing step S29, the pixel electrode being electrically connected to the drain electrode through the first contact hole;

Specifically, as shown in FIG. 6, first, magnetron sputtering, thermal evaporation, or other film forming methods can be used. a transparent conductive layer having a thickness of 100 lOOOA formed on the substrate 1 of the step S29, the transparent conductive layer may be made of indium tin oxide (ITO), indium oxide (ΙΖΟ) or alumina, etc.; Forming a photoresist on the transparent conductive layer; then, exposing and developing the photoresist with a patterned mask to form a photoresist mask; next, using a photoresist mask to perform the transparent conductive layer Etching, forming a pattern of the pixel electrode 12, the pixel electrode 12 is electrically connected to the drain electrode 7 through the first contact hole 11; thereafter, the exposed gate insulating layer 4 is etched away by a photoresist mask to expose the gate soldering Disk 3; Finally, the remaining photoresist is stripped. In each of the pixel units, the pixel electrode may have a plate shape or a slit shape.

The left half of Fig. 7 is a cross-sectional view of the array substrate after completion of the pixel electrode according to the prior art, and the right half is a cross-sectional view of the array substrate after completion of the pixel electrode according to an embodiment of the present invention. As shown in FIG. 7, in the prior art, in order to avoid the influence of the parasitic capacitance between the pixel electrode 12 and the data line 8 on the charging characteristics of the pixel electrode 12, the distance between the pixel electrode 12 and the data line 8 is dl. It is required to be larger, generally about 2 μπι, which causes the aperture ratio of the pixel to decrease. In the embodiment of the present invention, even if the organic insulating film 10 is used, even between the pixel electrode 12 and the data line 8 The distance d2 is made smaller, and the parasitic capacitance between the pixel electrode and the data line is not too large. Therefore, the distance d2 can be reduced to 0 ~ 1 μ πι to increase the aperture ratio of the pixel.

Step S31, forming a protective film on the substrate on which step S30 is completed, and patterning the protective film; specifically, as shown in FIG. 8, first, a thickness of the substrate 1 on which the step S30 is completed may be formed by a method such as PECVD. 2000 4000 保护 protective film 13, the protective mold 13 can be made of SiNx or SiOx; then, a photoresist is formed on the protective film 13; then, the photoresist is exposed and developed by using a patterned mask. Forming a photoresist mask; next, etching the protective film 13 with a photoresist mask to form a second contact hole 14 and a third contact hole 15 to expose the gate pad 3 and the data pad 9, respectively Finally, strip the remaining photoresist.

Step S32, forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which step S31 is completed. Specifically, as shown in FIG. 14, first, a transparent conductive layer having a thickness of 100 lOOOA may be formed on the substrate 1 on which the step S32 is completed by using magnetron sputtering, thermal evaporation or other film forming methods, and the transparent conductive layer may be釆 using indium tin oxide (ITO), indium oxide (ΙΖΟ) or alumina, etc.; then, forming a photoresist on the transparent conductive layer; then, using a patterned mask to expose the photoresist And developing, forming a photoresist mask; next, etching the transparent conductive layer with a photoresist mask to form a pattern of the common electrode 16, the gate pad electrode 17, and the data pad electrode 18; finally, stripping Remaining photoresist.

The common electrode 16 may include a first common electrode 161 located above the pixel electrode 12 and a second common electrode 162 located above the data line 8. The gate pad electrode 17 may be electrically connected to the gate pad 3 through the second contact hole 14, and the data pad electrode 18 may be electrically connected to the data pad 9 through the third contact hole 15.

In this embodiment, the second common electrode 162 is located above the data line 8, and can shield the electromagnetic field between the pixel electrode 12 and the data line 8, thereby reducing the width of the black matrix on the color filter, thereby increasing The aperture ratio of the pixel. Further, in forming the semiconductor layer 5, the source electrode 6, and the drain electrode 7, since the ashing process is used, the number of masks can be reduced, thereby reducing the manufacturing cost.

(1) An array substrate comprising a display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, each of the pixel unit A thin film transistor, a pixel electrode, and a common electrode are disposed, wherein an organic insulating film is disposed between the pixel electrode and the data line.

(2) The array substrate according to (1), wherein:

a gate electrode of the thin film transistor and the gate line are formed on a substrate;

a gate insulating layer is formed on the gate electrode and the gate line;

a semiconductor layer and the data line are formed on the gate insulating layer;

A source electrode and a drain electrode of the thin film transistor are formed on the semiconductor layer;

The organic insulating film is formed on the source electrode, the drain electrode, the data line, and the semiconductor layer, and a first contact hole is formed in the organic insulating film;

The pixel electrode is formed on the organic insulating film, and the pixel electrode passes through the first connection a contact hole is electrically connected to the drain electrode;

a protective film formed on the pixel electrode and the organic insulating film;

The common electrode is formed on the protective film, and the common electrode includes a first common electrode positioned above the pixel electrode and a second common electrode positioned above the data line.

(3) The array substrate according to (2), wherein a semiconductor layer material remains under the data line, or the data line is in direct contact with the underlying gate insulating layer.

(4) The array substrate according to any one of (2) to (3), further comprising:

a gate pad in the non-display area and in the same layer as the gate line;

a data pad in the non-display area and in the same layer as the data line; a gate pad electrode formed on the protective film and at a position corresponding to the gate pad, the gate pad The electrode is electrically connected to the gate pad through a second contact hole, the second contact hole passing through the organic insulating film and the protective film;

a data pad electrode formed on the protective film and at a position corresponding to the data pad, the data pad electrode being electrically connected to the data pad through a third contact hole, the third contact hole being worn The organic insulating film and the protective film are passed through.

(5) The array substrate according to any one of (1) to (4) wherein:

The distance between the pixel electrode and the data line in the horizontal direction is 0~1 μπι.

The array substrate according to any one of (1) to (5), wherein:

The material of the organic insulating film is polyacrylic acid.

The array substrate according to any one of (1) to (6), wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

(8) The array substrate according to any one of (2) to (7) wherein:

The protective film is made of an inorganic insulating material and has a thickness of 2000 to 4000 Å.

(9) A method of manufacturing an array substrate, comprising:

Forming a gate electrode, a gate line, and a gate pad on the substrate;

Forming the semiconductor layer, the source electrode, the drain electrode, the data line, and the Forming an organic insulating film on the substrate of the data pad, patterning the organic insulating film to form a first contact hole in the organic insulating film and exposing a gate insulating layer at the gate pad and the Data pad

(10) The manufacturing method according to (9), wherein after forming the pixel electrode, further comprising: forming a protective film on the substrate on which the pixel electrode is formed, and patterning the protective film to form a second contact a hole and a third contact hole;

Forming a common electrode, a gate pad electrode, and a data pad electrode on the substrate on which the protective film is formed, the common electrode including a first common electrode above the pixel electrode and a second common electrode above the data line The gate pad electrode is electrically connected to the gate pad through a second contact hole, and the data pad electrode is electrically connected to the data pad through the third contact hole.

The manufacturing method according to any one of (9) to (10), wherein after the organic insulating film is patterned, the method further comprises:

The organic insulating film is subjected to a curing treatment, the curing treatment temperature is 230 to 260 ° C, and the curing treatment is carried out for 30 to 60 minutes.

(12) The manufacturing method according to any one of (9) to (11) wherein:

The pixel electrode and the data line have a distance of 0 to 1 μm in a direction parallel to the substrate.

(13) The manufacturing method according to any one of (9) to (12), wherein:

The material of the organic insulating film is polyacrylic acid.

(14) The manufacturing method according to any one of (9) to (13), wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

(15) The manufacturing method according to any one of (10) to (14) wherein:

The protective film is made of an inorganic insulating material and has a thickness of 2000 to 4000A.

The manufacturing method according to any one of (9) to (15), wherein the semiconductor layer, the source electrode, the drain electrode, the data line, and the semiconductor layer are formed on the substrate on which the gate insulating layer is formed Data pads, including:

Forming a semiconductor material layer on the substrate on which the gate insulating layer is formed;

Patterning the layer of semiconductor material to form a semiconductor layer; Forming a metal layer on the substrate on which the semiconductor layer is formed;

The metal layer is patterned to form a source electrode, a drain electrode, a data line, and a data pad, and a semiconductor layer between the source electrode and the drain electrode forms a channel.

Forming a semiconductor material layer and a metal layer on the substrate on which the gate insulating layer is formed; forming a photoresist layer on the metal layer;

Exposing and developing the photoresist layer with a halftone or gray tone mask to form a photoresist completely reserved region, a photoresist portion remaining region, and a photoresist unretained region;

Etching off the metal layer and the semiconductor material layer in the unretained region of the photoresist;

Removing the photoresist of the remaining portion of the photoresist by an ashing process;

A portion of the metal layer and the layer of semiconductor material in the remaining portion of the photoresist portion is etched away. (18) A display device comprising the array substrate according to any one of (1) to (8). The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

An array substrate comprising a display area including a gate line, a data line, and a plurality of pixel units defined by the gate line and the data line, each of the pixel units including A thin film transistor, a pixel electrode, and a common electrode, wherein an organic insulating film is disposed between the pixel electrode and the data line.

2. The array substrate of claim 1, wherein:

a gate insulating layer is formed on the gate electrode and the gate line;

The pixel electrode is formed on the organic insulating film, and the pixel electrode is electrically connected to the drain electrode through the first contact hole;

3. The array substrate according to claim 2, wherein a semiconductor layer material remains under the data line, or the data line is in direct contact with the underlying gate insulating layer.

The array substrate according to any one of claims 2 or 3, further comprising:

a gate pad in the non-display area and in the same layer as the gate line;

a data pad in the non-display area and in the same layer as the data line;

a gate pad electrode formed on the protective film and at a position corresponding to the gate pad, the gate pad electrode being electrically connected to the gate pad through a second contact hole, the second contact hole being worn Passing the organic insulating film and the protective film;

The array substrate according to any one of claims 1 to 4, wherein: The distance between the pixel electrode and the data line in the horizontal direction is 0 to 1 μm.

The array substrate according to any one of claims 1 to 5, wherein:

The material of the organic insulating film is polyacrylic acid.

The array substrate according to any one of claims 1 to 6, wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

The array substrate according to any one of claims 2 to 7, wherein:

9. A method of fabricating an array substrate, comprising:

Forming a gate electrode, a gate line, and a gate pad on the substrate;

10. The manufacturing method according to claim 9, further comprising: forming a protective film on the substrate on which the pixel electrode is formed, and patterning the protective film to form a second contact hole after forming the pixel electrode And a third contact hole;

The manufacturing method according to any one of claims 9 to 10, wherein after the patterning the organic insulating film, the method further comprises:

The organic insulating film is subjected to a curing treatment, the curing treatment temperature is 230 to 260 ° C, and the curing treatment is performed for 30 to 60 minutes.

The manufacturing method according to any one of claims 9 to 11, wherein: a distance between the pixel electrode and the data line in a direction parallel to the substrate is 0 to 1 μπι

The manufacturing method according to any one of claims 9 to 12, wherein:

The material of the organic insulating film is polyacrylic acid.

The manufacturing method according to any one of claims 9 to 13, wherein:

The organic insulating film has a thickness of 10,000 to 40,000 Å.

The manufacturing method according to any one of claims 10 to 14, wherein:

The manufacturing method according to any one of claims 9 to 15, wherein the semiconductor layer, the source electrode, the drain electrode, the data line, and the data pad are formed on the substrate on which the gate insulating layer is formed , including:

Patterning the layer of semiconductor material to form a semiconductor layer;

Forming a metal layer on the substrate on which the semiconductor layer is formed;

A portion of the metal layer and the layer of semiconductor material in the remaining portion of the photoresist portion is etched away.

A display device comprising the array substrate according to any one of claims 1 to 8.