WO2013118872A1

WO2013118872A1 - Method of manufacturing electron-source structure for nanocrystalline silicon electron-emitter array

Info

Publication number: WO2013118872A1
Application number: PCT/JP2013/053069
Authority: WO
Inventors: 池上　尚克; 江刺　正喜; 越田　信義
Original assignee: 国立大学法人東北大学
Priority date: 2012-02-10
Filing date: 2013-02-08
Publication date: 2013-08-15
Also published as: JP2013164996A; JP5914909B2

Abstract

Provided is a method of manufacturing an electron-source structure for a nanocrystalline silicon electron-emitter array, which is configured such that a structure section in which a nanocrystalline silicon electron-emitter array provided with a plurality of electron emitters is formed on one face of a substrate, with each of the electron emitters being electrically connected to a respective substrate-penetrating wiring that penetrates the substrate, and which comprises connection electrodes provided at end sections of the substrate-penetrating wirings, is joined to an LSI which comprises drive electrodes and which is for controlling/driving the nanocrystalline silicon electron-emitter array, via the connection electrodes and the drive electrodes. In this method, the nanocrystalline silicon electron-emitter array is formed by depositing a conductive material on both faces of the substrate that has penetration holes opened therethrough, including the inner surfaces of the penetration holes, and then electrically connecting the conductive material on one face of the substrate to a working electrode in order to anodize a portion or all of the conductive material on the opposite face.

Description

Method of manufacturing nanocrystal silicon electron emitter array electron source structure

The present invention relates to an nc-Si electron emitter in which a nanocrystal silicon (hereinafter also referred to as nc-Si) electron emitter array and a control drive LSI for on / off control of electron emission from each electron emitter are integrated. The present invention relates to a method of manufacturing an array electron source structure.

It has practical throughput as ultra-fine processing technology and inexpensive photomask manufacturing technology required for next-generation semiconductor integrated circuits and MEMS (Micro-Electrical-Mechanical-Systems) that support high-mix low-volume production In recent years, the need for a maskless, high-resolution electron beam drawing apparatus is increasing. 1 and 2 are a schematic diagram of an electron beam drawing apparatus using a single electron source, and a diagram showing a problem of throughput when using the electron beam drawing apparatus.

As the mask pattern size becomes finer and the wafer size increases with the generation, the size of the electron beam source (pixel 電子 size 描画) required for electron beam drawing has become smaller, and the electron beam that must be drawn per wafer As the density (pixels / wafer) increases exponentially, the progress of the drawing speed (pixels / sec) of the electron beam drawing apparatus cannot catch up with it, and it can be seen that the throughput decreases rapidly with the generation.

As a method for solving this problem, for example, as disclosed in Non-Patent Document 1 by T. H. P. Chang et al., A method called Multi Electron Beam Lithography that performs parallel drawing while independently controlling a plurality of electron sources. Has been proposed. FIG. 3 shows a configuration example of conventional Multi-Electron Beam Lithography according to such a technique. Various researches and developments have been conducted for the practical use of electron source structures and manufacturing methods used in systems based on such methods.

As an example, FIG. 4 shows a schematic diagram and features of the electron source structure used in PML2 (Projection Mask-Less Lithography) of IMS Nanofabrication AG, which is an example of the configuration of this type of apparatus. Here, an electron beam emitted from a single electron source is once expanded and then divided into a plurality of electron beams by irradiating an aperture array called Programmable Aperture Plate System (APS) with an acceleration voltage of 5 KeV. APS is a mechanism that can mechanically open and close the aperture in conjunction with drawing data input in advance. The electron beam divided into a plurality of parts through the APS is accelerated at 50 KeV and is reduced and projected onto the wafer. However, in this method, since the electron beam drawing pattern is controlled by APS mechanical operation control, there is a problem that the system becomes complicated and the apparatus becomes large.

On the other hand, the present inventors have been conducting research on nc-Si electron sources (Patent Documents 1 and 2). nc-Si has a nano-silicon wire array structure in which a large number of nano-silicon crystal grains with a diameter of about 3 nm are connected. Each nano-silicon grain is insulated from each other and has a thin enough SiO ₂ layer or SiON layer to allow electrons to tunnel. Covered with an insulating thin film layer. When a Ti / Au (= 1nm / 9nm) thin film electrode is formed on the outermost surface of this nc-Si and a voltage is applied to the electrode, electrons may be ballistically emitted from around 5V above the Au work function. It has been reported.

The features of electrons emitted from this nc-Si electron source are summarized in FIG.

As shown in this figure, the nc-Si electron source (1) can be turned on / off at a low voltage that can be controlled by CMOS, and (2) the energy of the emitted electron is high energy of several eV. , (3) has very high directivity, and (4) surface electron emission allows uniform and large area electron emission, and (5) the emission current is less dependent on the degree of vacuum, (6) It has the advantage that no complicated manufacturing process is required (low cost).

JP 2008-98119 A WO 2011/096439 A1

By the way, in order to produce the above-mentioned nc-Si thin film, for example, a thin film such as Poly-Si (polycrystalline silicon) is deposited on a silicon wafer substrate, and then anodized in a solution containing HF to form a nanosilicon wire. An array structure is formed. After that, it can be produced by performing rapid thermal oxidation (Rapid Thermal Oxidation: RTO) treatment at a temperature of about 900 ° C., for example.

However, since anodization in a solution containing HF and a high-temperature process of 900 ° C are difficult to match with the LSI manufacturing process, it is not possible to monolithically build an nc-Si electron source array structure on the LSI. It is extremely difficult.

In addition, the SiO ₂ film formed by oxidation treatment such as RTO generates very high internal stress on the nc-Si thin film itself, so it is easily destroyed when external mechanical stress is applied. End up. Therefore, when the nc-Si electron source and the control drive LSI circuit are separately manufactured and integrated, the nc-Si thin film itself is handled and the electrical pads are accurately electrically connected to all the electrode pads of the drive LSI. There was a problem that it was extremely difficult to obtain a proper joint.

On the other hand, an example in which an arrayed nc-Si electron source and a control IC are integrated has been reported for application to flat panel displays. There was a problem that it was difficult.

An object of the present invention is to solve these problems and to provide a method of manufacturing an electron source structure of an nc-Si electron emitter array suitable for integration with a control drive LSI circuit.

In order to achieve the above object, according to the present invention, first, a nanocrystalline silicon electron emitter array having a plurality of electron emitters is formed on one surface of a substrate, and the substrate is attached to each electron emitter. A substrate through-wiring penetrating through is electrically connected, a structure having a connection electrode provided at an end of the substrate through-wiring, and a drive electrode, for controlling and driving the nanocrystal silicon electron emitter array In a method for manufacturing a nanocrystal silicon electron emitter array structure in which an LSI is formed by bonding via respective electrodes, the nanocrystal silicon electron emitter array is disposed on the substrate having a through hole. After depositing a conductive material on both sides of the substrate including the inner surface of the through-hole, the conductive material on one side of the substrate is electrically connected to the working electrode. Method of manufacturing a nanocrystal silicon electron emitter array structure with some or all of the conductive material on the opposite surface, characterized in that it is formed by anodic oxidation is provided by taking the connection.

Secondly, in the first invention, there is provided a method for manufacturing a nanocrystal silicon electron emitter array structure, wherein an SOI substrate having an active layer is used as the substrate.

Thirdly, in the first invention, there is provided a method of manufacturing a nanocrystal silicon electron emitter array structure, wherein a silicon substrate is used as the substrate.

Fourthly, in the first invention, there is provided a method for manufacturing a nanocrystal silicon electron emitter array structure, wherein an insulating substrate is used as the substrate.

Fifth, in any one of the first to fourth inventions, a structure in which a common electrode is formed on the entire surface as a part of the nanocrystal silicon electron emitter array, and a part other than the electron emission part is provided. There is provided a method for manufacturing a nanocrystal silicon electron emitter array structure characterized in that an electrode having a film thickness larger than the electrode film thickness formed in the electron emission portion is formed.

Sixth, the first invention is characterized in that a film made of a conductive material formed on the active layer is anodized by electrically connecting the SOI active layer and the working electrode. A method of manufacturing a nanocrystalline silicon electron emitter array structure is provided.

Seventh, in the sixth aspect of the invention, there is provided a method of manufacturing a nanocrystal silicon electron emitter array structure, wherein the active layer and the working electrode are electrically connected from the side wall of the SOI substrate. .

Eighth, in any one of the first to seventh aspects of the invention, a method of manufacturing a nanocrystal silicon electron emitter array structure, wherein a portion other than the electron emission portion is covered with a Si ₃ N ₄ film or a SiC film Is provided.

In the method of manufacturing a nanocrystal silicon electron emitter array structure of the present invention, the following process is used as a typical example.

(I) After the polycrystalline silicon deposited on the wafer substrate is processed into a large number of dot arrays, a portion other than the electron emission portion is covered with an insulating film such as a Si ₃ N ₄ film or a SiC film. Thereafter, the portion where the polycrystalline silicon surface is exposed is selectively anodized in a solution containing HF to form an nc-Si layer.

(II) When the anodic oxidation described in (I) is performed on the SOI substrate, a process of anodizing by applying a voltage from the wafer side wall through the active layer is used.

(III) Si When performing anodization mentioned methods on the substrate (I), initially Si penetration (T hrough S ilicon V ia: TSV) After preparing a wiring structure, through the TSV wiring from the back surface of the substrate, A process of anodizing polycrystalline silicon processed into a dot array on the surface side is used.

(IV) After opening the through-hole in the Si substrate and oxidizing the entire surface, after depositing a conductive material on the entire surface of the Si substrate and completely filling the through-hole, the nc-Si electron emitter array structure on one side (surface) side The opposite surface (back surface) side is polished while controlling the polishing thickness. Thereafter, the Si substrate portion remaining on the back side is selectively removed by etching, and an insulator is embedded in the removed portion. A process of joining the electrode on the back of the structure and the drive electrode on the control drive LSI is used.

According to the present invention, an nc-Si electron emitter array is formed on an SOI or Si substrate or an insulating support, and a through electrode such as a TSV electrode electrically connected to each emitter is formed on the back surface of the substrate. A structure is fabricated, and the TSV electrode and the drive electrode on the LSI are joined. In addition, since the electron source is structured in this way, the nc-Si thin film is supported by the surrounding Si structure in this structure, so that the internal stress derived from the nc-Si thin film itself is alleviated. Can be demonstrated. Therefore, the resistance to mechanical stress received from the outside during the manufacturing process and mounting is dramatically improved, and the stability is improved. Furthermore, miniaturization of the TSV electrode structure and the like makes it possible to increase the density.

Therefore, the structure of the electron source of the nc-Si electron emitter array suitable for integration with the control drive LSI circuit can be realized.

It is the schematic of the conventional electron beam drawing apparatus using a single electron source. It is a figure which shows the throughput at the time of using the conventional electron beam drawing apparatus using a single electron source. It is a figure which shows the structural example of the conventional Multi * Electron * Beam * Lithography. It is the figure which shows the schematic of the electron source structure used for PML2 (Projection | Mask-Less | Lithography), and the feature. It is a figure which shows collectively the characteristic of the electron discharge | released from an nc-Si electron source. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 1st Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 1st Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 1st Example of this invention. It is a figure which shows the example of an apparatus structure in case Poly-Si is electrochemically etched by anodic oxidation, and nc-Si is produced. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 2nd Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 2nd Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 2nd Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 3rd Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 3rd Example of this invention. It is a figure explaining the manufacturing process of the nc-Si electron emitter array electron source which concerns on the 3rd Example of this invention.

<First embodiment>
FIG. 6 (FIGS. 6A to 6C) is a diagram for explaining a manufacturing process of the nc-Si electron emitter array electron source according to the first embodiment of the present invention.

In this example, the TSV electrode structure connected to the nc-Si emitter is fabricated on the SOI substrate.

First, a buried oxide film (BOX layer) 2 is provided on a P-type Si substrate 1 having a thickness of 20 μm, and an n ⁺⁺ -type SOI active layer 3 having a thickness of 2 μm, for example (resistivity is about 0.005 Ωcm). The SOI substrate 4 provided with is prepared (step (1)). Then, a Poly-Si layer 5 is deposited on the SOI substrate 4 (step (2)).

Next, the n ⁺⁺ -type SOI active layer 3 / Poly-Si layer 5 is vertically processed by dry etching to form a recess 6 (step (3)). At that time, the lower n ⁺⁺ -type SOI active layer 3 is left on the BOX layer 2 by, for example, about 0.1 μm by adjusting the etching time.

Next, an Si ₃ N ₄ film 7 is deposited on the entire surface by, for example, about 0.15 μm by LP-CVD (step (4)), and sidewall spacers 8 are formed on the pattern sidewalls by anisotropic etching on the entire surface. (Step (5)). This step is performed, for example, by etching in a CHF ₃ / CF ₄ gas plasma atmosphere using a parallel plate type RIE (Reactive Ion Etching) apparatus. Although the Si ₃ N ₄ film is used here, another protective layer such as a SiC film may be used.

Thereafter, this portion is anodized in, for example, an HF + C ₂ H ₅ OH solution, and the surface of the Poly-Si layer 5 that is not covered with the Si ₃ N ₄ film 7 is selectively electrochemically etched. Convert to nc-Si (step (6)). In the figure, 9 is an nc-Si portion. At that time, an O-ring seal mechanism that suppresses the penetration of the HF solution into this portion so that the peripheral portion that opens the contact hole for electrical connection in the subsequent step (step (15)) is not anodized. Use a device with FIG. 7 schematically shows an apparatus configuration for anodization including this mechanism.

In general, when a silicon substrate is used, as shown in this figure, a positive bias is applied from the electrode 22 from the back surface of the sample 21, and a negative potential is applied to the platinum electrode 24 placed opposite to the surface of the sample 21 in the solution 23 containing HF. Anodization can be performed by applying (or ground potential), controlling the current density flowing through the sample 21 to, for example, 25 mA / cm ² and allowing the current to flow for about 6 seconds. However, when an SOI substrate 4 is used as in this device and voltage is applied from the back side of the substrate, the Poly-Si layer 5 on the active layer 3 is not broken unless the BOX layer 2 is broken down by applying a large voltage. Cannot be anodized. Therefore, in the step (6), the sample side wall portion of the n ⁺⁺ -type active layer 3 left on the BOX layer 2 by the etching in the step (3) is bypassed, and the working electrode and the Poly-Si shown in FIG. Electrical connection with the layer 5 is made so that an anode current flows.

Thereafter, the nc-Si portion 10 is oxidized (step (7)). In this step, for example, the temperature is increased from room temperature to 800 ° C. in 10 seconds in an O ₂ gas atmosphere, and the temperature is increased from 800 ° C. to 900 ° C. in 10 seconds → 900 ° C. for 23 minutes. As a result of this oxidation treatment, an oxidized nc-Si portion 10 is formed, and the active layer 3 that electrically connected the emitters is completely insulated (SiO ₂ ) as shown in step (7). Will be isolated.

Thereafter, a CVD SiO ₂ film 11 is deposited on the back surface (step (8)), deep etching is performed up to the BOX layer 2 to form a through hole 12 (step (9)), and the SiO ₂ side wall (sidewall is formed on the pattern side wall. Spacer) 13 is formed (step (10)). Then, the through-hole 12 is embedded with, for example, Ti / Cu 14 by plating (step (11)), an adhesion polyimide film 15 is deposited and patterned (step (12)), and bump-connected to the control drive LSI 16 (step) (13)). In the figure, 16-1 is an electron source driving Al electrode portion, 16-2 is an I / O portion electrode, 16-3 is an interlayer insulating film, and 16-4 is a bump.

Thereafter, a Ti / Au (= 1 nm / 9 nm) surface electrode 17 is formed (step (14)), and electrical connection with the input / output (I / O) pad portion 18 on the control drive LSI 16 is made. An electron source of an nc-Si electron emitter array can be produced by opening the contact hole 19 and forming an electrode 20 such as tungsten (step (15)).

In the state where a constant voltage of 15 V, for example, is applied to the Au electrode formed on the outermost surface of this nc-Si electron emitter array electron source, each nc is connected from the LSI drive electrode side in conjunction with the drawing pattern data input from the outside. An arbitrary two-dimensional pattern can be drawn on a wafer at high speed by controlling the drive voltage of 15V on / off of the -Si electron source.

As described above, according to the method of the present embodiment, an nc-Si electron emitter array is formed on an SOI substrate, and a structure in which TSV electrodes electrically connected to individual emitters are formed on the back surface of the substrate is manufactured. The TSV electrode and the drive electrode on the LSI are joined. In this structure, the nc-Si thin film is supported by the surrounding Si structure, so that the internal stress derived from the nc-Si thin film itself can be reduced. be able to. Therefore, the resistance to mechanical stress received from the outside during the manufacturing process and mounting is dramatically improved, and the stability is improved. Furthermore, miniaturization of the TSV electrode structure enables high density.

On the other hand, in the above manufacturing process, a positive voltage can be applied to the surface from the wafer side wall through the SOI active layer during anodic oxidation, so that individual dots can be used regardless of the presence of the BOX layer (insulating layer). It becomes possible to nc-Si by etching the surface of polycrystalline Si electrochemically with low voltage without dielectric breakdown of the BOX layer.

<Second Example>
FIG. 8 (FIGS. 8A to 8C) is a view for explaining a manufacturing process of the nc-Si electron emitter array electron source according to the second embodiment of the present invention.

In this example, a TSV electrode structure connected to an nc-Si electron emitter is fabricated on a Si substrate.

First, a P-type Si substrate 31 having a thickness of 200 μm is prepared (step (1)). The P-type Si substrate 31 is subjected to through etching using, for example, the same RIE apparatus used in the step (5) of the first embodiment (step (2)). In the figure, 32 is a through hole. Next, a thermal oxide film (SiO ₂ film) 33 having a thickness of 1.0 μm is grown on the Si substrate 31 (step (3)), and an n ⁺⁺ -Type Doped poly-Si film is further formed on the entire surface of the through hole 32. Is deposited more than the film thickness that completely fills, and then one surface is polished to leave a Doped Poly-Si film 34 having a film thickness of, for example, about 2 μm on the surface (step (4)).

Next, a poly-Si film 35 is deposited on the polished surface (step (5)), and after patterning into a dot array until the underlying SiO ₂ is exposed (step (6)), a thermal oxide film (SiO ₂ film) 36 is grown, and an Si ₃ N ₄ film 37 is deposited on the entire surface by, for example, about 0.5 μm by LP-CVD (step (7)). Thereafter, for example, using a parallel plate type RIE apparatus, the electron emission portion 38 is opened by dry etching in a CHF ₃ / CF ₄ gas plasma atmosphere (step (8)).

Accordingly, anodization is performed, for example, in an HF + C ₂ H ₅ OH solution by using the apparatus configuration shown in FIG. 7, for example, and the Poly-Si surface not covered with the SiO ₂ / Si ₃ N ₄ film is selectively selected. Electrochemical etching is performed to convert this portion into nc-Si, and then an oxidation treatment is performed (step (9)). In the figure, 39 is an oxidized nc-Si portion. In this anodic oxidation, the working electrode shown in FIG. 7 is electrically connected to the back surface of the sample, and a platinum electrode placed opposite to the sample surface in a solution containing HF is placed at the ground potential. Similarly to the above, the current density flowing in the sample is controlled to 25 mA / cm ² , for example, and a current is applied for about 6 seconds. In this structure, the BOX layer (insulating layer) as described in the first embodiment is not present in the middle of the substrate.

In addition, since Doped Poly-Si is embedded in the silicon through hole 32 in the first stage of the process (Step (4)), the Doped Poly-Si film 34 formed on the entire back side of the sample is formed in the silicon through hole. 32 is electrically connected to the individual dot-shaped Poly-Si back surface on the sample surface side. For this reason, by passing an anodic current through the Doped Poly-Si film 34 on the back side of the sample, it becomes possible to independently and selectively anodize the individual dot-like poly-Si surfaces on the front side of the sample. As described in the first embodiment, for example, the nc-Si oxidation treatment is performed in a O ₂ gas atmosphere from room temperature to 800 ° C. in 10 seconds → 800 ° C. to 900 ° C. in 10 seconds → 900 Perform at 23 ° C. for 23 minutes.

Thereafter, the n ^{+ +} type Doped poly-Si film 34 on the back surface is patterned (rear electrode formation) (step (10)), Au bumps 40-1 fabricated on the drive electrodes on the surface of the LSI drive circuit 40, and about Si—Au eutectic bonding is performed at 400 ° C. (step (11)). In the figure, 40-2 is an electronically driven Al electrode part, 40-3 is an I / O part electrode, 40-4 is an interlayer electrode, and 40-5 is an adhesive polyimide. Then, the Ti / Au (= 1 nm / 9 nm) surface electrode 42 is formed on the surface including the electron emitting portion 38, and the Ti / Au (= 1 nm / 9 nm) ultra-thin electrode as described in the first embodiment. It was found that a portion where the Ti / Au electrode could not be completely covered was generated on the patterned electron source side wall when depositing on the entire surface. In this case, electrons may not be emitted depending on the location. In order to solve this problem, first, for example, a Cu / Au (= 10 nm / 300 nm) electrode 41 is deposited thickly on a part other than the electron emission part 38 (step (12)), and then the Ti is not formed on the electron emission part 38. By forming the thin surface electrode 42 of / Au (= 1 nm / 9 nm) (step (13)), the problem of electrode coating could be improved. Thereafter, a space 44 for making electrical contact with the input / output (I / O) pad portion 43 on the drive control LSI 40 is secured by half dicing (step (14)). The electron source of the nc-Si electron emitter array is manufactured by the above process.

As described above, according to the method of the present embodiment, an nc-Si electron emitter array is formed on a Si substrate, and a structure in which TSV electrodes electrically connected to individual emitters are formed on the back surface of the substrate is manufactured. The TSV electrode and the driving electrode on the LSI are joined to form a structure that constitutes an electron source. In this structure, since the nc-Si thin film is supported by the surrounding Si structure, the effect of relieving the internal stress derived from the nc-Si thin film itself can be exhibited. Therefore, the resistance and stability against the mechanical stress received from the outside during the manufacturing process and mounting are dramatically improved. Further miniaturization enables high density.

On the other hand, in the manufacturing process, Si through-holes are opened at the first stage of the process, and after oxidizing the entire surface, Doped-Poly-Si is deposited on the entire wafer surface to completely fill the through-holes, and then on one side (front side) A dot-like polycrystalline Si structure was formed. This makes it possible to establish electrical connection with the working electrode for anodizing from the back side, and independently etch each dot-like Poly-Si surface into nc-Si. It became possible.

In addition, in the formation of the electrode, the electrode having a thickness greater than the thickness of the electrode formed in the electron emission portion is formed in a portion other than the electron emission portion, so that step coverage is improved and uniform electron emission is achieved. Is possible.

<Third embodiment>
FIG. 9 (FIGS. 9A to 9C) is a view for explaining a manufacturing process of the nc-Si electron emitter array electron source according to the third embodiment of the present invention.

First, a P-type Si substrate 51 having a thickness of 200 μm is prepared (step (1)). The P-type Si substrate 51 is subjected to through etching using, for example, the same RIE apparatus used in the step (5) of the first embodiment (step (2)). In the figure, 52 is a through hole. Next, a thermal oxide film (SiO ₂ film) 53 having a thickness of 1.0 μm is grown on the Si substrate 51 (step (3)), and an n ⁺⁺ -Type Doped poly-Si film 54 is formed on the entire surface through the through hole. More than the film thickness in which 52 is completely buried is deposited, and then one surface is polished to leave a Doped Poly-Si film 54 having a film thickness of, for example, about 2 μm on the surface (step (4)).

Next, a poly-Si film 55 is deposited on the polished surface (step (5)), and after patterning into a dot array (step (6)), a thermal oxide film (SiO ₂ film) 56 is grown, and LP-CVD A Si ₃ N ₄ film 57 is deposited on the entire surface by, for example, about 0.5 μm (step (7)). Thereafter, for example, by using a parallel plate type RIE apparatus, the electron emission portion 58 is opened by dry etching in a CHF ₃ / CF ₄ gas plasma atmosphere (step (8)).

Accordingly, anodization is performed, for example, in an HF + C ₂ H ₅ OH solution by using the apparatus configuration shown in FIG. 7, for example, and the Poly-Si surface not covered with the SiO ₂ / Si ₃ N ₄ film is selectively selected. Electrochemical etching is performed to convert this portion into nc-Si, and then an oxidation treatment is performed (step (9)). In the figure, 59 is an oxidized nc-Si portion. In this anodic oxidation, the working electrode shown in FIG. 7 is electrically connected to the back surface of the sample, and a platinum electrode placed opposite to the sample surface in a solution containing HF is placed at the ground potential. Similarly to the above, the current density flowing in the sample is controlled to 25 mA / cm ² , for example, and a current is applied for about 6 seconds. Because doing the n ⁺⁺ Doped Poly-Si implantation into silicon through hole 53 in the first stage in the construction process (step ^{(4)), n ++ Doped} Poly-Si which is formed on the sample back the entire surface The film 54 is electrically connected to the back surface of each dot-like Poly-Si 55 on the sample surface side through the silicon through hole 52. For this reason, by flowing an anodic current through the n ⁺⁺ Doped Poly-Si film 54 on the back side of the sample, it becomes possible to independently and selectively anodize the individual dot-like poly-Si surfaces on the front side of the sample. As described in the first embodiment, for example, the nc-Si oxidation treatment is performed in an O ₂ gas atmosphere from room temperature to 800 ° C. in 10 seconds → 800 ° C. to 900 ° C. in 10 seconds → 900 Perform at 23 ° C. for 23 minutes.

Thereafter, a glass substrate 61 for supporting the wafer is attached to the device surface side using the polymer 60 (step (10)), and the polishing thickness is controlled by, for example, chemical mechanical polishing (CMP) on the opposite side (back side). The film is then thinned (step (11)). After that, the Poly-Si substrate 51 remaining on the back surface side is selectively removed by etching using, for example, SF ₆ gas plasma (step (12)). At this time, the exposed n ⁺⁺ Doped Poly-Si 54 is covered with a resist 62 so as not to be etched.

Thereafter, for example, an SiO ₂ film is sputter-deposited as the insulating film 63 to selectively embed an insulator where the Poly-Si substrate 51 is removed (step (13)). Thereafter, the resist 62 is removed, and, for example, a Cr / Au electrode 64 electrically connected to the exposed n ⁺⁺ Doped Poly-Si through-wiring surface is formed, thereby forming a through-wiring electrode 65 on the back surface ( Step (14)). Thereafter, for example, a Cr / Au / In bump structure 66 is formed on the LSI drive electrode, and the bump electrode 66 is aligned with the Cr / Au penetrating wiring electrode 65 (64) on the back side of the electron source. After temporary bonding to the control LSI 67 (step (15)), physical bonding between the bump and the through-wiring electrode is performed by performing Transient Liquid Phase Diffusion Bonding (TLP bonding) at about 200 ° C. 68 is formed (step (16)). In the figure, reference numeral 67-1 denotes an electron source drive.
An Al electrode portion, 67-2 is an I / O electrode portion, and 67-3 is an interlayer insulating film. Thereafter, the polymer 60 is removed to remove the glass substrate (step (17)), and a Ti / Au (= 1 nm / 9 nm) surface electrode 69 is formed on the surface of the electron source (step (18)), which is driven by half dicing. A space 71 is secured for electrical contact with the input / output (I / O) pad portion 70 of the control LSI 67 (step (19)). The electron source of the nc-Si electron emitter array is manufactured by the above process.

In a state where a constant voltage of 15 V, for example, is applied to the Au electrode formed on the outermost surface of the electron source of this nc-Si electron emitter array, each LSI drive electrode side individually links with the drawing pattern data input from the outside. An arbitrary two-dimensional pattern can be drawn on a wafer at high speed by controlling on / off of a driving voltage of 15 V to the nc-Si electron source.

As described above, according to the method of this embodiment the nc-Si electron emitter array is formed on the insulating SiO ₂ support, the SiO ₂ individual emitter electrically connected to the through wiring electrodes to produce a structure formed on the back surface insulating support, joining the driving electrodes on the through wiring electrodes and the LSI, by which the structure thus configuring the electron source, SiO ₂ and nc-Si thin film in this structure Since it is supported by the support, the effect of relieving the internal stress derived from the nc-Si thin film itself can be exhibited. Therefore, even if the nc-Si electron emitter array is bonded onto the drive electrode on the drive control LSI, there is an effect that the resistance to internal stress can be stably maintained. Furthermore, since the entire area around the electron emission portion is covered with an insulator, the parasitic capacitance is extremely small. For this reason, even when voltage application from the drive control LSI to the nc-Si electron emitter array is performed at high speed on / off operation, the delay time from the drive voltage output to the electron emission is practically negligible.

On the other hand, in the manufacturing process, after forming an nc-Si electron emitter array on a Poly-Si support having a through-hole electrode structure, the Poly-Si support is selectively removed by etching. A process of embedding these parts with SiO ₂ insulating film was adopted. This makes it possible to use a process for forming through-wiring electrodes on a Si substrate, which is easier to miniaturize, instead of using the direct through-wiring electrode forming process directly on fine SiO ₂ supports that are difficult to process at high aspect ratios. can do. Further, the nc-Si electron emitter array can be further miniaturized.

1, 31, 51 P-type Si substrate 2 Embedded oxide film (BOX layer)
3 n ⁺⁺ -type SOI active layer 4

SOI substrate

5, 35, 55 Poly-Si film 6

Recess

7, 37, 57 Si ₃ N ₄ film 8 Sidewall spacer
9 nc-

Si part

10, 39, 59 Oxide nc-Si part 11 SiO ₂ film 12 Through hole 13 SiO ₂ side wall (sidewall spacer)
14 Ti / Cu penetrating conductor 15

Polyimide film

16, 40, 67 Control drive LSI
17 Ti /

Au surface electrode

18, 41, 70 Input / output (I / O) pad part 19 Contact hole 20 Electrode 21 Sample 22 Electrode 23 Solution containing HF 24

Platinum electrode

32, 52 Through

hole

33, 53 Thermal oxide film (SiO ₂ membranes)
34, 54 Doped Poly-

Si film

36, 56 Thermal oxide film (SiO ₂ film)
38, 58 Electron emitting portion 60 Polymer 61 Glass substrate 62 Resist 63 Insulating film 64 Cr / Au electrode 65 Through-wiring electrode 66 Bump electrode

Claims

A nanocrystal silicon electron emitter array having a plurality of electron emitters is formed on one surface of the substrate, and through-substrate wirings penetrating the substrate are electrically connected to the individual electron emitters. A nano-structure comprising a structure part having a connection electrode provided in the part and an LSI having a drive electrode and controlling and driving the nanocrystal silicon electron emitter array via each electrode. In a method of manufacturing a crystal silicon electron emitter array structure,
After the conductive material is deposited on both sides of the substrate including the inner surface of the through-hole with respect to the substrate having the through-hole, the nanocrystal silicon electron emitter array has an action with the conductive material on one side of the substrate. A method of manufacturing a nanocrystal silicon electron emitter array structure, wherein the conductive material on the opposite surface is partly or entirely anodized by electrical connection with an electrode.
The method for manufacturing a nanocrystal silicon electron emitter array structure according to claim 1, wherein an SOI substrate having an active layer is used as the substrate.
2. The method of manufacturing a nanocrystal silicon electron emitter array structure according to claim 1, wherein a silicon substrate is used as the substrate.
2. The method of manufacturing a nanocrystal silicon electron emitter array structure according to claim 1, wherein an insulating substrate is used as the substrate.
As a portion of the nanocrystal silicon electron emitter array, a common electrode is formed on the entire surface, and the portion other than the electron emission portion is thicker than the electrode thickness formed on the electron emission portion. 5. The method of manufacturing a nanocrystal silicon electron emitter array structure according to claim 1, wherein an electrode is present.
2. The nanocrystal silicon electron according to claim 1, wherein a film made of a conductive material formed on the active layer is anodized by establishing electrical connection between the SOI active layer and the working electrode. Manufacturing method of emitter array structure.
The method for producing a nanocrystal silicon electron emitter array structure according to claim 6, wherein the active layer and the working electrode are electrically connected from the side wall of the SOI substrate.
The method for manufacturing a nanocrystal silicon electron emitter array structure according to any one of claims 1 to 7, wherein a portion other than the electron emission portion is covered with a Si 3 N 4 film or a SiC film.