WO2013069727A1 - Conductive paste and method for producing through electrode - Google Patents

Conductive paste and method for producing through electrode Download PDF

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Publication number
WO2013069727A1
WO2013069727A1 PCT/JP2012/078975 JP2012078975W WO2013069727A1 WO 2013069727 A1 WO2013069727 A1 WO 2013069727A1 JP 2012078975 W JP2012078975 W JP 2012078975W WO 2013069727 A1 WO2013069727 A1 WO 2013069727A1
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electrode
conductive paste
conductive
semiconductor substrate
type semiconductor
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PCT/JP2012/078975
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French (fr)
Japanese (ja)
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義博 川口
真歩 小川
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株式会社村田製作所
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Publication of WO2013069727A1 publication Critical patent/WO2013069727A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/20Conductive material dispersed in non-conductive organic material
    • H01B1/22Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/02245Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Definitions

  • the present invention relates to a conductive paste and a method of manufacturing a through electrode, and more particularly, a conductive paste suitable for forming a through electrode of a solar cell having an MWT (Metal Wrap Through) structure, and the conductive paste is used.
  • the present invention relates to a method for manufacturing a through electrode.
  • Si-based solar cells using silicon which have abundant resources and can save resources and reduce costs, has been actively conducted.
  • FIG. 10 is a principal part sectional view schematically showing an example of a conventional solar cell
  • FIG. 11 is a principal part plan view thereof.
  • an antireflection film 102 and a light receiving surface electrode 103 are formed on one main surface of a semiconductor substrate 101 containing Si as a main component, and a back electrode 104 is formed on the other main surface of the semiconductor substrate 101. Is formed.
  • an n-type semiconductor layer 101b is formed on an upper surface of a p-type semiconductor layer 101a, and a back surface field (hereinafter referred to as “BSF”) 101c is formed on a lower surface of the p-type semiconductor layer 101a. Is formed. A pn junction is formed by the p-type semiconductor layer 101a and the n-type semiconductor layer 101b.
  • the light-receiving surface electrode 103 is mainly formed of conductive powder such as Ag, and is electrically connected to the bus bar electrode 105 connected to the interconnector and the bus bar electrode 105 as shown in FIG. And a large number of finger electrodes 106a, 106b... 106n.
  • this type of solar cell light from the sun is blocked by the light-receiving surface electrode 103 (the bus bar electrode 105 and the finger electrodes 106a, 106b,... 106n) provided on the surface of the semiconductor substrate 101.
  • the amount of light incident on the semiconductor substrate 101 is reduced, and it is difficult to obtain sufficient power generation efficiency.
  • the power generation efficiency may be further reduced. Therefore, this type of solar cell is required to improve the power generation efficiency by reducing the area of the light-receiving surface electrode as much as possible.
  • a semiconductor substrate 111 made of a Si-based material, an antireflection film 112 and a light receiving surface electrode (finger electrode) 113 formed on one main surface of the semiconductor substrate 111
  • the semiconductor substrate 111 includes a through electrode 114 formed from one main surface to the other main surface, and a back electrode 115 formed on the back surface of the semiconductor substrate 111.
  • the through electrode 114 includes a via portion 114 a that penetrates the semiconductor substrate 111 and a bus bar portion 114 b that is formed around the through hole of the semiconductor substrate 111.
  • the semiconductor substrate 111 includes a p-type semiconductor region 111a, an n-type semiconductor region 111b formed in the outer peripheral region of the p-type semiconductor region 111a so as to surround the p-type semiconductor region 111a, and a predetermined region on the lower surface of the semiconductor substrate 111. And a BSF region 111c formed on the substrate.
  • a separation groove 116 is formed at an appropriate position on the back surface of the semiconductor substrate 111, and the n-type semiconductor region 111 b and the bus bar portion 114 b are electrically insulated from the back electrode 115 by the separation groove 116.
  • the light-receiving surface electrode 113, the through electrode 114, and the back electrode 115 are all formed by sintering a conductive paste.
  • the through electrode 114 has 1 to 10 parts by weight of P 2 with respect to 100 parts by weight of the conductive powder.
  • a conductive paste containing O 5 glass frit (insulating material) is used.
  • an insulating layer made of a P 2 O 5 glass material is provided at the interface between the n-type impurity region 111b and the through electrode 114.
  • a layer (not shown) is formed.
  • the bus bar portion 114b of the light receiving surface electrode is formed on the back surface side of the semiconductor substrate 111, thereby increasing the light receiving area of sunlight and reducing the recombination loss of carriers on the light receiving surface side. As a result, power generation efficiency is improved.
  • Patent Document 2 provides a p-type Si substrate having a through hole between a front surface and a back surface and having an n layer formed on the entire surface and the surface of the through hole, and a conductive paste is provided in the through hole.
  • a method for manufacturing a Si solar cell having an MWT structure in which the substrate is filled, dried, and fired at a maximum temperature of 700 to 900 ° C.
  • the conductive paste contains at least one metal selected from the group consisting of Ag, Cu, and Ni and an organic vehicle, and further contains 11 to 33 wt% of SiO 2 , 0 as glass frit.
  • Lead-free glass having a softening point of 550 to 611 ° C., containing ⁇ 7 wt% Al 2 O 3 , 2 to 10 wt% B 2 O 3 , 40 to 73 wt% Bi 2 O 3 , and 53 to 57 wt% Containing leaded glass with a softening point of 571-636 ° C. containing 1% PbO, 25-29% by weight SiO 2 , 2-6% by weight Al 2 O 3 , 6-9% by weight B 2 O 3 Points are listed.
  • JP 2010-80578 A (Claims 1 to 6, FIG. 1) International Publication No. 2011/0881808 (Claims 1 and 8)
  • Patent Document 1 Although an insulating layer is formed at the interface between the semiconductor substrate 111 and the through electrode 114, a large amount of conductive powder dissolves in the glass during the firing process, and thus dissolves in a large amount in the glass.
  • the deposited conductive material is deposited on the side of the semiconductor substrate 111, thereby destroying the insulating property and possibly destroying the pn junction.
  • the n-type semiconductor region 111b is formed in the outer peripheral region of the p-type semiconductor region 111a so as to surround the p-type semiconductor region 111a.
  • the n-type semiconductor region 111b is in contact with the through electrode 114.
  • the thickness of the side surface portion 111b ′ is formed thinner than the thickness of the main surface portion 111b ′′ of the p-type semiconductor region 111a. Therefore, an insulating layer is formed at the interface between the n-type semiconductor region 111b and the through electrode 114.
  • the P 2 O 5 glass frit is usually inferior in chemical durability, and there is a risk of impairing reliability.
  • Patent Document 2 since the through electrode is formed using a conductive paste containing glass frit having a high softening point of 550 to 636 ° C., the fluidity of the glass is inferior, and the through electrode and the semiconductor are fired during firing. It is considered that it is difficult to ensure sufficient insulation because glass does not sufficiently flow to the interface with the substrate.
  • the solar cell having the MWT structure has a simple structure if the n-type semiconductor region can be formed only between the antireflection film and the p-type semiconductor region and the through electrode 114 and the p-type semiconductor region can be in contact with each other.
  • the separation groove (FIG. 12, reference numeral 116) is not required, and productivity can be improved.
  • the present invention has been made in view of such circumstances, and has a good insulating property between the semiconductor substrate and the through electrode, contributes to an improvement in power generation efficiency, and is excellent in solderability and mechanical strength. It aims at providing the manufacturing method of the electroconductive paste which can obtain a battery, and the penetration electrode using this electroconductive paste.
  • the inventors of the present invention conducted intensive studies to obtain a conductive paste suitable for forming a through electrode in a solar cell having an MWT structure. Since the softening point is low and the electrical conductivity is good, it has been found that the insulating property is good and the leakage current can be suppressed, whereby a conductive paste suitable for forming the through electrode can be obtained.
  • the V oxide glass material has a low softening point and good fluidity, so that insulation can be secured with a small amount of glass, and as a result, solderability is good. It was also found that a solar cell excellent in mechanical strength can be obtained.
  • the conductive paste according to the present invention is a conductive paste for forming an electrode of a solar cell, and includes a conductive powder, a glass component, and an organic paste.
  • the glass component is characterized by being formed of a V oxide-based material containing V oxide as a main component.
  • the V content in the glass component is preferably 70% by weight or more in terms of a weight ratio in terms of oxide.
  • the content of the glass component is preferably 5 to 15% by weight.
  • glass materials that easily crystallize during heat treatment can further improve electrical conductivity, and after crystallization. It has also been found that since the fluidity is lowered, the glass material is less likely to float on the surface of the bus bar portion of the through electrode, and the solderability is improved.
  • the glass component is preferably crystallized by heat treatment.
  • the conductive paste of the present invention preferably contains a phosphoric acid compound.
  • the phosphoric acid compound may be Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 (PO 4 ). It is preferable to include at least one selected from the group of 2 .
  • the conductive powder contained in the conductive paste of the present invention has a crystallite diameter of 70 nm or more.
  • the through electrode itself is not excessively shrunk, so that even if a large amount of glass is added to the through electrode, the semiconductor substrate does not crack and prevents deterioration of electrical characteristics. be able to.
  • the conductive powder preferably contains atomized powder produced by an atomizing method.
  • the conductive powder is preferably composed mainly of Ag.
  • the conductive paste according to any one of the above is filled into the through hole to form the through conductor, and then the baking treatment is performed.
  • a through electrode is formed on the substrate.
  • the conductive paste of the present invention a conductive oxide, a glass component, and an organic vehicle are contained, and the glass component is formed of a V oxide-based material containing a V oxide as a main component. Therefore, by using the conductive paste for forming the through electrode, the insulation between the semiconductor substrate and the through electrode can be improved, the power generation efficiency can be improved, and the solderability and mechanical strength are good. A solar cell having an MWT structure can be obtained.
  • the V oxide glass material has a low softening point and good fluidity, when used for forming a through electrode, the glass component flows between the through hole and the substrate in a short period of time. Then, an insulating layer is formed. Further, the V oxide-based glass material has better electrical conductivity than other glass materials, and even if the p-type semiconductor and the through electrode are in contact with each other, the n-type semiconductor is changed to the p-type through the through electrode. Leakage current leaking to the semiconductor can be suppressed.
  • the V oxide-based glass material has a low softening point and good electrical conductivity as compared with other glass materials, so that a through electrode having good insulation from the semiconductor substrate is formed.
  • the power generation efficiency of the solar cell can be improved.
  • the glass component easily flows at the interface with the substrate as described above, the content of the glass component can be reduced, and good solderability and mechanical strength can be ensured.
  • the conductive paste according to any one of the above is filled into the through hole to form the through conductor, and then the baking treatment is performed. Since the through electrode is formed on the substrate, it is possible to obtain a through electrode having good insulation and solderability and excellent mechanical strength.
  • FIG. 6 is a cross-sectional view schematically showing a sample manufactured in Example 2.
  • FIG. 6 is a diagram showing current-voltage characteristics of Example 2. Is a diagram showing the relationship between V 2 O 5 content of the glass component in the second embodiment and the differential resistance.
  • FIG. 4 is a SEM image of crystal grains in Example 3. It is principal part sectional drawing which shows an example of the conventional solar cell typically. It is a principal part top view of FIG. 2 is a cross-sectional view of a main part of a solar cell described in Patent Document 1.
  • FIG. 2 is a cross-sectional view of a main part of a solar cell described in Patent Document 1.
  • the conductive paste as one embodiment of the present invention contains a conductive powder, a glass component, and an organic vehicle, and the glass component is a V oxide-based material containing V oxide as a main component. It is formed with. As a result, it is possible to obtain a conductive paste suitable for forming a through electrode of a solar cell electrode, particularly a solar cell having an MWT structure.
  • a V oxide glass material mainly composed of V oxide typified by V 2 O 5 has a softening point as low as 300 to 450 ° C. and easily flows in a very short baking process. Therefore, when the conductive paste containing the V-oxide glass component is filled in the through-hole formed in the semiconductor substrate and baked, the glass component easily flows in the through-hole. An insulating layer is easily formed at the interface. As a result, the conductive material such as Ag is not deposited on the semiconductor substrate side, and the pn junction of the semiconductor substrate can be prevented from being broken.
  • the V oxide glass material is superior in electrical conductivity compared to other glass materials, and therefore, a leakage current leaking from the through electrode to the semiconductor substrate side can be effectively suppressed. That is, the electrical conductivity of a normal glass material is 10 ⁇ 12 S / cm or less, which is almost an insulator, whereas the electrical conductivity of a V oxide glass material is 10 ⁇ 2 to 10 ⁇ 7 S / cm. It is as high as cm and has electrical conductivity similar to that of a semiconductor.
  • the V oxide glass material has better electrical conductivity than other glass materials, when a through electrode is formed using a conductive paste containing the V oxide glass material. Even when the n-type semiconductor layer is formed on one main surface of the p-type semiconductor layer and the through electrode is in contact with the p-type semiconductor layer, the n-type semiconductor layer is connected to the through-electrode. Electrons that have flowed into the electrode material do not leak to the p-type semiconductor layer via the electrode material, but instead form an insulating layer made of a V oxide glass component formed between the electrode material and the p-type semiconductor layer. Via, it moves again to the electrode material side. Therefore, it is possible to prevent current from leaking from the through electrode to the p-type semiconductor layer, and it is possible to suppress the occurrence of leakage current.
  • conventional glass materials such as P 2 O 5 glass materials are almost insulators and are inferior in electrical conductivity. Therefore, when a weakly insulating portion occurs, electric field concentration occurs at a stretch and leakage current increases. .
  • the V oxide glass material has good electrical conductivity, it is possible to suppress the occurrence of electric field concentration, and thus it is possible to effectively reduce the leakage current, and to achieve a desired insulating property. Can be secured.
  • the V oxide glass material has a low softening point and good electrical conductivity compared to other glass materials, a through electrode having good insulation from the semiconductor substrate may be formed. It becomes possible, and it becomes possible to improve the power generation efficiency of a solar cell. Moreover, since the glass component easily flows at the interface with the substrate as described above, the content of the glass component can be reduced, and good solderability and mechanical strength can be ensured.
  • Such a V oxide glass component is not particularly limited as long as it contains V oxide as a main component, but V 2 O 5 —BaO—ZnO that is easily crystallized by heat treatment. It is preferable to use a glass component of a V 2 O 5 —Fe 2 O 3 —BaO system. That is, by crystallizing by heat treatment, the electrical conductivity becomes higher than that of the glass component in the amorphous state, and the leakage current can be more effectively suppressed. Further, by crystallizing by heat treatment, the fluidity of the glass component decreases after crystallization, so that the glass is less likely to float on the electrode surface of the through electrode, and solderability can be improved. In particular, a V oxide-based material containing 70% by weight or more in terms of a weight ratio in terms of an oxide can improve solderability and further suppress leakage current.
  • the content of the V oxide glass component in the conductive paste is not particularly limited, but from the viewpoint of ensuring solderability and mechanical strength while ensuring insulation, it is 5 to 15% by weight is preferred. That is, when the content of the V oxide glass component is less than 5% by weight, the mechanical strength may be lowered. In addition, the glass component flowing to the interface with the semiconductor substrate is reduced, and the probability that the conductive material and the semiconductor substrate are in direct contact with each other increases, which may cause a decrease in insulation. On the other hand, when the content of the V oxide glass component exceeds 15% by weight, the V oxide glass component flowing on the surface of the conductive material increases, the glass component floats on the surface of the through electrode, and solderability. There is a risk of lowering.
  • the content of the V oxide glass component in the conductive paste is preferably 5 to 15% by weight, thereby ensuring good insulation and good solderability and mechanical strength.
  • the conductive crystallite diameter and average particle diameter D 50 of the powder is not particularly limited, and it is preferably crystallite diameter using the above conductive powder 70 nm. That is, excessive shrinkage of the through electrode can be suppressed by using conductive powder having a crystallite diameter of 70 nm or more. In addition, by suppressing excessive shrinkage of the through electrode in this way, extremely high contact resistance can be exhibited with respect to both the p-type semiconductor layer and the n-type semiconductor layer of the semiconductor substrate, and further leakage current suppression is achieved. Is possible. In addition, by suppressing excessive shrinkage of the through electrode, the glass component can easily flow between the through electrode and the semiconductor substrate, so that the glass does not flow excessively on the electrode surface and good soldering is achieved. Property and mechanical strength can be ensured. In addition, even when a large amount of glass component is contained in the through electrode, it is possible to suppress the generation of cracks in the semiconductor substrate and to prevent the electrical characteristics from deteriorating.
  • the atomizing method is a method of spraying high-pressure water or the like onto a conductive material melted by heat treatment to form liquid droplets, and solidifying while dropping the conductive material, thereby forming a conductive powder.
  • a slurry containing a metal oxide is prepared by adding an alkali to an aqueous solution containing a metal salt, and a reducing agent is added to the slurry to reduce and precipitate the metal powder, thereby making it conductive.
  • a method for producing a powder is described in detail below.
  • a fine conductive powder is likely to be produced by the wet reduction method, it is preferably produced by the atomizing method from the viewpoint of more efficiently obtaining a conductive powder having a large crystallite diameter of 70 nm or more.
  • the conductive powder is not particularly limited as long as it has a desired conductivity, but usually Ag or an Ag alloy containing Ag as a main component is preferably used.
  • the content of the conductive powder is not particularly limited as long as it has an effect as an electrode, but it is usually preferably about 70 to 90% by weight, particularly preferably 75 to 85% by weight.
  • the conductive paste of the present invention preferably further contains a phosphoric acid compound. That is, by containing a phosphoric acid compound in the conductive paste, an insulating layer having a high phosphorus concentration can be formed on the surface of the conductive powder in the through electrode after firing. Therefore, the contact resistance between the through electrode and the semiconductor substrate can be further increased, and thereby better insulation can be obtained between the through electrode and the semiconductor substrate.
  • Such a phosphoric acid compound is not particularly limited.
  • Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 ( PO 4 ) 2 or the like can be used.
  • the conductive paste is preferably weighed so that 70 to 90% by weight of the conductive powder, 5 to 15% by weight of the V 2 O 5 glass component, and the balance is an organic vehicle, and an appropriate amount as necessary.
  • These phosphoric acid compounds can be weighed and mixed, and can be easily manufactured by dispersing and kneading them using a three-roll mill or the like.
  • the organic vehicle is produced by preparing a binder resin and an organic solvent so that the volume ratio is, for example, 1 to 3: 7 to 9.
  • the binder resin is not particularly limited, and for example, ethyl cellulose resin, nitrocellulose resin, acrylic resin, alkyd resin, or a combination thereof can be used.
  • the organic solvent is not particularly limited, and ⁇ -terpineol, xylene, toluene, diethylene glycol monobutyl ether, diethylene glycol monobutyl ether acetate, diethylene glycol monoethyl ether, diethylene glycol monoethyl ether acetate, etc. alone or in combination thereof Can be used.
  • the conductive paste is formed of conductive powder, a V 2 O 5 glass material, and an organic vehicle.
  • the content of the organic vehicle is slightly reduced, and a small amount is used instead.
  • plasticizers such as di-2-ethylhexyl phthalate and dibutyl phthalate, or add rheology modifiers such as fatty acid amides and fatty acids, and more thixotropic agents, thickeners. Agents, dispersants and the like may be added as necessary.
  • the conductive paste mentioned above is filled into the said through-hole, a through-conductor is formed, and after that a baking process is performed and a through-electrode is formed in the said board
  • FIG. 1 is a cross-sectional view of an essential part showing an embodiment of a solar cell
  • FIG. 2 is a plan view of FIG.
  • an antireflection film 2 and a light receiving surface electrode 3 are formed on one main surface of a semiconductor substrate 1 containing Si as a main component, and a back electrode 4 is formed on the other main surface of the semiconductor substrate 1.
  • an n-type semiconductor layer 1b is formed on the upper surface of the p-type semiconductor layer 1a, and a BSF layer 1c is formed in a predetermined region on the lower surface of the p-type semiconductor layer 1a.
  • the n-type semiconductor layer 1a can be obtained, for example, by diffusing donor impurities on one main surface of the single-crystal or polycrystalline p-type semiconductor layer 1b.
  • the n-type semiconductor layer 1a has a high concentration on the upper surface of the p-type semiconductor layer 1a.
  • the manufacturing method is not particularly limited.
  • the BSF layer 1c is formed by Al forming the current collecting electrode 4a at the time of firing acting as an acceptor impurity and diffusing, and forming a p + layer on the opposing surface of the current collecting electrode 4a of the p-type semiconductor layer 1c. .
  • the through electrode 6 has a via portion 6 a penetrating through the semiconductor substrate 1 and a bus bar portion 6 b formed on the back surface of the semiconductor substrate 1 connected to the via portion 6 a.
  • the electric power generated in the semiconductor substrate 1 is collected by the light receiving surface electrode 3 (finger electrodes 5a to 5n), and taken out to the outside by the bus bar portion 6b through the via portion 6a of the through electrode 6.
  • the surface of the semiconductor substrate 1 is shown in a flat shape. However, in order to effectively confine sunlight to the semiconductor substrate 1, the surface is formed to have a micro uneven structure (texture). Yes.
  • the antireflection film 2 is formed of an insulating material such as silicon nitride (SiN x ), suppresses reflection of light to the light receiving surface of sunlight indicated by an arrow A, and allows sunlight to be quickly and efficiently applied to the semiconductor substrate 1. Lead.
  • the material constituting the antireflection film 2 is not limited to the above-described silicon nitride, and other insulating materials such as silicon oxide (SiO 2 ) and titanium oxide (TiO 2 ) may be used. In addition, two or more kinds of insulating materials may be used in combination. In addition, as long as it is crystalline Si, either single crystal Si or polycrystalline Si may be used.
  • the light receiving surface electrode 3 has a large number of finger electrodes 5 a, 5 b,... 5 n arranged in a comb-like shape, and the remaining area excluding the portion where the light receiving surface electrode 3 is provided.
  • the antireflection film 2 is formed.
  • the light-receiving surface electrode 3 is formed by applying a conductive paste prepared separately on the semiconductor substrate 1 by using screen printing or the like to produce a conductive film and baking it. That is, in the baking process for forming the light receiving surface electrode 3, the antireflection film 2 under the conductive film is decomposed and removed and fired through, whereby the light receiving surface electrode is formed on the semiconductor substrate 1 so as to penetrate the antireflection film 2. 3 is formed.
  • the electric power generated in the semiconductor substrate 1 is collected by the finger electrodes 5a to 5n, and the finger electrodes 5a to 5n are connected to the through electrode 6 as described above, and from the bus bar portion 6b of the through electrode 6 Electric power is taken out.
  • the back electrode 4 is made of a current collecting electrode 4a made of Al formed on the back surface of the semiconductor substrate 1, and Ag or the like formed on the back surface of the current collecting electrode 4a and electrically connected to the current collecting electrode 4a. It is comprised with the extraction electrode 4b. The electric power generated in the semiconductor substrate 1 is collected by the collecting electrode 4a, and the electric power is taken out by the extracting electrode 4b.
  • the said solar cell can be manufactured as follows.
  • 3 and 4 are manufacturing process diagrams showing one embodiment of a method for manufacturing a solar cell.
  • a p-type semiconductor substrate 1 made of monocrystalline or polycrystalline Si or the like and having a thickness of about 200 mm is prepared.
  • the semiconductor substrate 1 is obtained, for example, by cutting an ingot formed by melting and re-solidifying a semiconductor raw material such as Si in a crucible for each block and slicing it into a thin piece with a wire saw or the like.
  • an etching process is performed using an alkaline solution and / or an acidic solution, and a minute uneven structure (texture) is formed on the surface in order to effectively confine incident sunlight in the semiconductor substrate 1.
  • donor impurities are diffused on the surface of the semiconductor substrate 1 to form an n-type semiconductor layer 1b on the surface of the p-type semiconductor layer 1a.
  • a coating solution containing a donor impurity to be diffused is applied in a film shape by spin coating or the like to form a coating film, and heat treatment is performed to diffuse the donor impurity on the surface of the semiconductor substrate 1, An n-type semiconductor layer 1b having a thickness of 300 to 500 nm is formed. Thereby, the semiconductor substrate 1 forms a pn junction.
  • the donor impurity is not particularly limited as long as it can form the n-type semiconductor layer 1b having a high concentration of n + layer.
  • P is preferably used, and phosphorus oxychloride ( POCl 3 ) is preferably used.
  • Etching is then performed using an acidic solution to remove impurities such as donor impurities diffused on the edge and back surface of the semiconductor substrate 1 and phosphosilicate glass formed on the surface.
  • the film thickness of an insulating material such as silicon nitride (SiN x ) is 70 to 80 nm.
  • the antireflection film 2 is formed.
  • a predetermined position of the semiconductor substrate 1 is irradiated with laser light, and a large number of through holes 7 having an inner diameter of about 50 ⁇ m to 500 ⁇ m are formed as shown in FIG.
  • the formation method of the through hole 7 is not limited to the laser beam irradiation, and may be formed by any method such as a mechanical method using a drill or a chemical method using etching or the like. it can.
  • the through-hole 7 is formed by filling the above-described conductive paste of the present invention into the through-hole 7, and the conductive paste is applied around the through-hole 7.
  • the coating film 8b is formed.
  • an Al paste containing Al powder having an average particle diameter of 5 ⁇ m is prepared, and further an Ag paste containing Ag powder having an average particle diameter of 1.5 ⁇ m is prepared.
  • the Al paste is applied to the entire back surface of the semiconductor substrate 1, and the Ag paste is screen-printed and dried. As shown in FIG. 4 (f), from the Al film 9 and the Ag film 10 for the back electrode. A first conductive film (electrode pattern) 11 is formed.
  • the through conductor 8a has a firing profile such that Al is sintered at 500 ° C. and the maximum firing temperature is 760 ° C.
  • the coating film 8b and the first and second conductive films 11 and 12 are sintered.
  • the Al film 9 is melted and alloyed with the p-type semiconductor layer 1a to form an Al—Si layer (not shown), and Al diffuses as an acceptor impurity in the p-type semiconductor layer 1a.
  • a high-concentration p + layered BSF layer 1c is formed.
  • the finger electrodes 5a to 5n are fired through the antireflection film 2 and joined to the n-type semiconductor layer 1b.
  • the back electrode 4 which consists of the penetration electrode 6 which consists of the bus-bar part 6b, the current collection electrode 4a, and the extraction electrode 4b is produced, and a solar cell is formed by this.
  • the antireflection film 2 is formed on one main surface of the semiconductor substrate 1 and the through hole 7 is formed in the semiconductor substrate 1 on which the antireflection film 2 is formed. Since the through-hole 7 is filled with the paste to form the through-conductor 8a, and then the baking process is performed to form the through-electrode 6 on the semiconductor substrate 1, the insulating property at the interface between the through-electrode 6 and the semiconductor substrate 1 is good. Even if an interconnector or the like is soldered to the bus bar portion 6b of the through electrode 6, a solar cell having good solderability and good mechanical strength such as tensile strength can be manufactured.
  • the semiconductor substrate 1 has an n-type semiconductor layer 1b formed on one main surface of the p-type semiconductor layer 1a, and an antireflection film 2 is formed on the surface of the n-type semiconductor layer 1b.
  • a conductive paste is applied around the through hole 7 on the other main surface of the semiconductor substrate 1 to form a coating film 8b, and the first and second conductive films 11 are formed on both main surfaces of the semiconductor substrate 1. 12 is formed, and the through conductor 8a, the coating film 8b, and the first and second conductive films 11 and 12 are simultaneously fired by firing treatment, whereby a solar cell having a desired high power generation efficiency can be efficiently obtained.
  • the present invention is not limited to the above embodiment.
  • the conductive paste of the present invention is particularly useful because the structure and the manufacturing method can be simplified for a solar cell in which the through-hole 7 and the p-type semiconductor layer 1a are in contact with each other and a separation groove (see FIG. 8, reference numeral 116) is unnecessary.
  • the present invention can also be applied to a solar cell in which an n-type semiconductor layer is formed so as to surround a p-type semiconductor layer as in Patent Document 1 and a through electrode and a p-type semiconductor layer are not in contact with each other.
  • the conductive paste of the present invention is particularly suitable for forming a through electrode, but can also be used for forming an extraction electrode for a back electrode.
  • the semiconductor substrate 1 has the thin n-type semiconductor layer 1b formed on the p-type semiconductor layer 1a, but the thin p-type semiconductor layer is formed on the n-type semiconductor layer. Needless to say, the same can be applied to the case where it is applied.
  • the composition ratio of V 2 O 5 —BaO—ZnO of sample numbers A to C is as follows: V 2 O 5 : 76.6 wt%, BaO: 18.5 wt%, ZnO: 4.9 wt%
  • the composition ratio of V 2 O 5 —Fe 2 O 3 —BaO of sample number D is V 2 O 5 : 73.0 wt%, Fe 2 O 3 : 9.2 wt%, BaO: 17.6 wt% was blended.
  • the glass component contained in each sample was subjected to thermal analysis using a TG-DTA (thermogravimetric-differential thermal analyzer), and the softening point was measured. That is, 5 mg of a sample is accommodated in an alumina container, ⁇ alumina is used as a standard sample, and the measuring apparatus is heated at 20 ° C. per minute while supplying air into the measuring apparatus at a flow rate of 100 mL / min. It heated with the profile and the TG curve and the DTA curve were created from the weight change with respect to temperature. And the softening point of each glass material was measured from such TG curve and DTA curve.
  • TG-DTA thermogravimetric-differential thermal analyzer
  • Table 1 shows the paste composition, glass component type, softening point Ts, and crystallization temperature Tx of sample numbers A to G.
  • the conductive pastes A to D use a V 2 O 5 glass component mainly composed of V 2 O 5 and are conductive pastes within the scope of the present invention.
  • the conductive pastes E to G use glass components of a component system other than V 2 O 5 and are conductive pastes outside the scope of the present invention.
  • a semiconductor substrate 12a composed of a p-type Si-based semiconductor layer (hereinafter referred to as “p-Si layer”) and an n-type Si-based semiconductor layer (hereinafter referred to as “p-Si layer”) are formed on the surface of the p-Si layer 12a.
  • the semiconductor substrate 12b on which the “n-Si layer” is formed) is prepared, predetermined electrode patterns are formed on the surfaces of the semiconductor substrates 12a and 12b, and the contact resistance Rc is obtained by a TLM (Transmission Line Model) method. It was.
  • TLM Transmission Line Model
  • a semiconductor substrate 12a made of a single crystal p-Si layer having a width X of 127 mm, a length Y of 127 mm, and a thickness T of 0.2 mm was prepared. Further, POCl 3 is applied to the surface of the p-Si layer by using a spin coating method, and then heat treatment is performed to diffuse P on the surface of the p-Si layer, thereby providing an n-Si layer having a thickness of 400 ⁇ m. A semiconductor substrate 12b was produced.
  • etching is performed using an acidic solution, and formed on the surface of the P or p-Si layer diffused at the end or back surface of the p-Si layer. Removed phosphosilicate glass.
  • the distance L1 between the electrode 13a and the electrode 13b is 200 ⁇ m
  • the distance L2 between the electrode 13b and the electrode 13c is 400 ⁇ m
  • the distance L3 between the electrode 13c and the electrode 13d is 600 ⁇ m
  • the electrode 13d and the electrode 13e was 800 ⁇ m
  • the distance L5 between the electrodes 13e and 13f was 1000 ⁇ m
  • the electrode length Z was 30 mm.
  • each sample was placed in an oven set at a temperature of 150 ° C. to dry the electrodes 13a to 13f.
  • the contact resistance Rc was obtained for each of the samples Nos. 1 to 7 (1a to 7a, 1b to 7b) using the TLM method, and the insulating property was evaluated.
  • This TLM method is widely known as a method for evaluating the contact resistance of a thin film sample, and uses the transmission line theory to calculate the contact resistance Rc by regarding the electrode and the underlying semiconductor substrate as equivalent to a so-called transmission line circuit. . That is, Equation (1) is established among the length Z of the electrodes 13a to 13f, the sheet resistance R SH of the n-Si layer or the p-Si layer, the interelectrode distance L, and the interelectrode resistance R.
  • each resistance R at the interelectrode distance Ln was measured, and the contact resistance Rc was calculated for each of the samples Nos. 1 to 7, and the insulation was evaluated.
  • the sheet resistance R SH can be calculated from the slope of the straight line derived from the above equation (1) with L as the horizontal axis and R as the vertical axis. In this embodiment, the sheet resistance R SH is 30 ⁇ / cm. It was.
  • a single-crystal p-type Si-based semiconductor substrate having a horizontal X of 127 mm, a vertical Y of 127 mm, and a thickness T of 0.2 mm was separately prepared.
  • soldering iron whose tip temperature is set to 400 ° C.
  • Sn—Ag—Cu solder plating wire (SSA-TPS 0.16 ⁇ 2.0 manufactured by Hitachi Cable Finetech Co., Ltd.) is used as the electrode. After soldering, the solder plating wire was pulled at an angle of 45 ° to conduct a tensile test, and mechanical strength was evaluated.
  • Table 2 shows test results of conductive paste types of sample numbers 1 to 7 (1a to 7a, 1b to 7b, 1c to 7c), contact resistance Rc of n-Si layer and p-Si layer, and tensile strength, The overall evaluation is also shown.
  • the contact resistance Rc on the n-Si layer was determined to be 30 ⁇ or higher as a non-defective product
  • the contact resistance Rc on the p-Si layer was determined to be 10000 ⁇ or higher as a non-defective product.
  • the tensile strength 3N or more and the semiconductor substrate destroyed is judged as a non-defective product ( ⁇ ), and in other cases, that is, between the electrode and the semiconductor substrate is broken, or solder
  • non-defective product
  • x solder
  • Sample No. 5 could not obtain a sufficient contact resistance Rc. This is probably because the softening point of the glass component contained in the conductive paste E is as high as 540 ° C., which is inferior in fluidity and inferior in electrical conductivity. Therefore, with the conductive paste E, sufficient insulation cannot be secured, and it is difficult to suppress the leakage current. Moreover, it was found that Sample No. 5 was inferior in tensile strength and inferior in solderability and mechanical strength.
  • Sample Nos. 6 and 7 also have the same softening point as 524 to 580 ° C. of the glass component contained in the conductive pastes F and G, which is inferior in fluidity and inferior in electrical conductivity, as in Sample No. 5. For this reason, the contact resistance Rc is also low, and it is difficult to ensure sufficient insulation. Moreover, it turned out that these sample numbers 6 and 7 are also inferior in tensile strength similarly to sample number 5, and inferior also in solderability and mechanical strength.
  • sample numbers 1 to 4 contain a V 2 O 5 glass material as a glass component, so the softening point Ts is as low as 310 to 430 ° C., and the glass component is crystallized by firing treatment (heat treatment). Therefore, the electrical conductivity was further improved, and the contact resistance Rc was as high as 40 ⁇ or more on the n-Si layer and 27000 ⁇ or more on the p-Si layer. Therefore, even when these conductive pastes A to D are used for forming a through electrode, leakage current leaking from the n-Si layer to the p-Si layer through the through electrode can be suppressed, and the power generation efficiency can be improved. it is conceivable that.
  • Sample Nos. 1 to 4 had good tensile strength and excellent solderability and mechanical strength. This is because, in all of the conductive pastes A to D, the glass component is crystallized by the baking treatment, so that the fluidity of the glass component is reduced after crystallization, and as a result, the glass can be prevented from floating on the electrode surface. It seems that it was because of
  • Example 1 spherical atomized Ag powder having an average particle size D 50 of 5 ⁇ m, an organic vehicle, and the like were prepared, and further glass components having the composition ratios shown in Table 3 were prepared.
  • Sample No. 11 has the same composition as the conductive pastes A to C used in Example 1
  • Sample No. 12 has the same composition as the conductive paste D used in Example 1.
  • the conductive paste is formed so that finger electrodes and bus bar electrodes are formed on one main surface of a p-type Si-based semiconductor substrate (hereinafter referred to as “p-Si substrate”) 15.
  • p-Si substrate p-type Si-based semiconductor substrate
  • the screen was printed and dried.
  • an Al paste was screen printed over the other main surface of the p-Si substrate 15 and dried.
  • firing is performed using a belt-type near-infrared furnace to form a surface electrode 16 on one main surface of the p-Si substrate 15, and the other of the p-Si substrate 15.
  • a back electrode 17 was formed on the main surface, thereby preparing samples Nos. 11 to 16.
  • IV curve a current-voltage curve
  • FIG. 7 is a diagram showing an example of an IV curve, in which the horizontal axis represents voltage V (V) and the vertical axis represents current I (A).
  • the curve in the first quadrant is a forward bias, that is, a current characteristic when a positive voltage is applied to the p-Si substrate 15, and indicates a current flowing from the p-Si substrate 15 to the surface electrode 16. .
  • the curve in the third quadrant is the reverse bias, that is, the current characteristic when a positive voltage is applied to the surface electrode 16, and shows the current flowing from the surface electrode 16 to the p-Si substrate 15.
  • the leakage current from the surface electrode 16 (through electrode) to the p-Si substrate 15 is smaller as the current from the surface electrode 16 to the p-Si substrate 15 is less likely to flow.
  • Table 3 shows the glass composition, differential resistance, and solderability of each sample Nos. 11 to 16.
  • Sample No. 14 has a V 2 O 5 content of 34.6% by weight in the glass component, and contains so much V 2 O 5 that it is said to be a main component. Therefore, the solderability was inferior, and the differential resistance was as small as 0.49 ⁇ .
  • Sample Nos. 11 to 13, 15, and 16 have a V 2 O 5 content of 50% by weight or more in the glass component, and the glass component contains V 2 O 5 as a main component.
  • the solderability was good and the differential resistance was 0.70 ⁇ or higher.
  • Sample Nos. 11 to 13 with a V 2 O 5 content of 70% by weight or more in the glass component have good solderability and a differential resistance of 5.45 to 46.42 ⁇ , which is a leak. It has been found that the current can be further suppressed.
  • FIG. 8 is a diagram showing the relationship between the content of V 2 O 5 in the glass component and the differential resistance, where the horizontal axis is the content (% by weight) of V 2 O 5 and the vertical axis is the differential resistance ( ⁇ ). Is shown.
  • a predetermined electrode pattern was prepared on the surface of a semiconductor substrate having a p-Si layer and an n-Si layer by using the conductive paste of sample numbers 21 to 26 in the same manner and procedure as in Example 1, and the TLM method Thus, the contact resistance Rc, solderability, and tensile strength of the n-Si layer and the p-Si layer were determined.
  • the contact resistance Rc was substantially the same in the sample numbers 21 to 25 containing the phosphate compound in the n-Si layer and in the sample number 26 not containing the phosphate compound.
  • the sample numbers 21 to 25 containing the phosphoric acid compound are significantly higher than the sample number 26 not containing the phosphoric acid compound, indicating that the insulation is improved. It was.
  • FIG. 9 is a SEM image obtained by imaging the cross section of the p-Si layer side semiconductor substrate of sample number 25 with a SEM (scanning electron microscope).
  • an insulating layer having a high P concentration is formed on the outer peripheral surface of the Ag particles, and it is considered that high insulating properties are obtained by forming such an insulating layer.
  • Example 2 a glass component having the same composition as that of Sample No. 11 in Example 2, an organic vehicle similar to that in Example 1, and the like were prepared.
  • a predetermined electrode pattern was prepared on the surface of the semiconductor substrate having the p-Si layer and the n-Si layer by using the conductive paste of sample numbers 31 to 36 in the same manner and procedure as in Example 1, and the TLM method Thus, the contact resistance Rc, solderability, and tensile strength of the n-Si layer and the p-Si layer were determined.
  • the contact resistance Rc As for the contact resistance Rc, it was found that a good result of 50 to 56 ⁇ was obtained for the n-Si layer, and a good result of 30000 to 170000 ⁇ was obtained for the p-Si layer. This is probably because the Ag powder has a large crystallite diameter of 70 nm or more, and the electrode does not shrink excessively, so that a high contact resistance is obtained.

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Abstract

The present invention provides a conductive paste which enables the production of a solar cell that exhibits excellent solderability and excellent mechanical strength, while having good insulation between a semiconductor substrate and a through electrode, thereby achieving improved power generation efficiency. A conductive paste of the present invention contains a conductive powder such as Ag, 5-15% by weight of a glass component that is composed of a vanadium (V) oxide material mainly composed of vanadium (V) oxide, an organic vehicle and the like. The vanadium (V) oxide material is preferably one that is crystallized by a heat treatment such as a V2O5-BaO-ZnO material or a V2O5-Fe2O3-BaO material. A through electrode (6) that is formed of a via part (6a) and a bus bar part (6b) is formed using the conductive paste. The conductive paste of the present invention is suitable for the formation of a through electrode in a solar cell, wherein a p-type semiconductor layer (1a) and an n-type semiconductor layer (1b) are in contact with a through electrode (6), among solar cells having an MWT structure.

Description

導電性ペースト、及び貫通電極の製造方法Conductive paste and method for manufacturing through electrode
 本発明は、導電性ペースト、及び貫通電極の製造方法に関し、より詳しくはMWT(Metal Wrap Through)構造を有する太陽電池の貫通電極の形成に適した導電性ペースト、及びこの導電性ペーストを使用した貫通電極の製造方法に関する。 The present invention relates to a conductive paste and a method of manufacturing a through electrode, and more particularly, a conductive paste suitable for forming a through electrode of a solar cell having an MWT (Metal Wrap Through) structure, and the conductive paste is used. The present invention relates to a method for manufacturing a through electrode.
 自然再生可能エネルギーへの関心の高まりと共に、太陽光発電を利用した太陽電池が注目されている。特に、資源量が豊富で省資源・低コスト化が可能なシリコン(以下、「Si」という。)系材料を使用したSi系太陽電池の開発が盛んに行なわれている。 With the growing interest in natural renewable energy, solar cells using photovoltaic power generation are attracting attention. In particular, the development of Si-based solar cells using silicon (hereinafter referred to as “Si”)-based materials, which have abundant resources and can save resources and reduce costs, has been actively conducted.
 図10は、従来の太陽電池の一例を模式的に示す要部断面図であり、図11はその要部平面図である。 FIG. 10 is a principal part sectional view schematically showing an example of a conventional solar cell, and FIG. 11 is a principal part plan view thereof.
 すなわち、この太陽電池は、Siを主成分とした半導体基板101の一方の主面に反射防止膜102及び受光面電極103が形成されると共に、該半導体基板101の他方の主面に裏面電極104が形成されている。 That is, in this solar cell, an antireflection film 102 and a light receiving surface electrode 103 are formed on one main surface of a semiconductor substrate 101 containing Si as a main component, and a back electrode 104 is formed on the other main surface of the semiconductor substrate 101. Is formed.
 半導体基板101は、p型半導体層101aの上面にn型半導体層101bが形成されると共に、p型半導体層101aの下面には背面電界(Back Surface Field;以下、「BSF」という。) 101cが形成されている。そして、p型半導体層101aとn型半導体層101bとでpn接合が形成されている。 In the semiconductor substrate 101, an n-type semiconductor layer 101b is formed on an upper surface of a p-type semiconductor layer 101a, and a back surface field (hereinafter referred to as “BSF”) 101c is formed on a lower surface of the p-type semiconductor layer 101a. Is formed. A pn junction is formed by the p-type semiconductor layer 101a and the n-type semiconductor layer 101b.
 また、受光面電極103は、Ag等の導電性粉末を主成分として形成されており、図11に示すように、インターコネクタに接続されるバスバー電極105と、バスバー電極105と電気的に接続された多数のフィンガー電極106a、106b…106nとを有している。 The light-receiving surface electrode 103 is mainly formed of conductive powder such as Ag, and is electrically connected to the bus bar electrode 105 connected to the interconnector and the bus bar electrode 105 as shown in FIG. And a large number of finger electrodes 106a, 106b... 106n.
 しかしながら、この種の太陽電池では、半導体基板101の表面に設けられた受光面電極103(バスバー電極105及びフィンガー電極106a、106b…106n)によって、太陽からの光が遮られることから、太陽光から半導体基板101に入射される光量の減少を招き、十分な発電効率を得るのが困難である。しかも、受光面電極103の下部でキャリアの再結合損失が発生するため、発電効率のより一層の低下を招くおそれがある。したがって、この種の太陽電池では、受光面電極の面積をできるだけ小さくして発電効率を向上させることが要請されている。 However, in this type of solar cell, light from the sun is blocked by the light-receiving surface electrode 103 (the bus bar electrode 105 and the finger electrodes 106a, 106b,... 106n) provided on the surface of the semiconductor substrate 101. The amount of light incident on the semiconductor substrate 101 is reduced, and it is difficult to obtain sufficient power generation efficiency. In addition, since recombination loss of carriers occurs below the light receiving surface electrode 103, the power generation efficiency may be further reduced. Therefore, this type of solar cell is required to improve the power generation efficiency by reducing the area of the light-receiving surface electrode as much as possible.
 そこで、このような観点から、特許文献1のようにMWT構造を有する太陽電池が提案されている。 Therefore, from such a viewpoint, a solar cell having an MWT structure as in Patent Document 1 has been proposed.
 この特許文献1では、図12に示すように、Si系材料からなる半導体基板111と、半導体基板111の一方の主面上に形成された反射防止膜112及び受光面電極(フィンガー電極)113と、半導体基板111の一方の主面から他方の主面に架けて形成された貫通電極114と、半導体基板111の裏面に形成された裏面電極115とを有している。貫通電極114は、半導体基板111を貫通するビア部114aと半導体基板111の貫通孔周囲に形成されたバスバー部114bとを有している。 In Patent Document 1, as shown in FIG. 12, a semiconductor substrate 111 made of a Si-based material, an antireflection film 112 and a light receiving surface electrode (finger electrode) 113 formed on one main surface of the semiconductor substrate 111, The semiconductor substrate 111 includes a through electrode 114 formed from one main surface to the other main surface, and a back electrode 115 formed on the back surface of the semiconductor substrate 111. The through electrode 114 includes a via portion 114 a that penetrates the semiconductor substrate 111 and a bus bar portion 114 b that is formed around the through hole of the semiconductor substrate 111.
 また、半導体基板111は、p型半導体領域111aと、該p型半導体領域111aを囲むようにp型半導体領域111aの外周域に形成されたn型半導体領域111bと、半導体基板111の下面所定領域に形成されたBSF領域111cとを有している。また、半導体基板111の裏面適所には分離溝116が形成され、該分離溝116によってn型半導体領域111b及びバスバー部114bと裏面電極115とが電気的に絶縁されている。 Further, the semiconductor substrate 111 includes a p-type semiconductor region 111a, an n-type semiconductor region 111b formed in the outer peripheral region of the p-type semiconductor region 111a so as to surround the p-type semiconductor region 111a, and a predetermined region on the lower surface of the semiconductor substrate 111. And a BSF region 111c formed on the substrate. In addition, a separation groove 116 is formed at an appropriate position on the back surface of the semiconductor substrate 111, and the n-type semiconductor region 111 b and the bus bar portion 114 b are electrically insulated from the back electrode 115 by the separation groove 116.
 また、受光面電極113、貫通電極114、裏面電極115は、いずれも導電性ペーストが焼結されてなり、貫通電極114には、導電性粉末100重量部に対し1~10重量部のP系ガラスフリット(絶縁材料)を含有した導電性ペーストが使用されている。そして、半導体基板111のn型不純物領域111bと貫通電極114とが電気的に接続されないように、これらn型不純物領域111bと貫通電極114との界面にはP系ガラス材料からなる絶縁層(図示せず)が形成されている。 The light-receiving surface electrode 113, the through electrode 114, and the back electrode 115 are all formed by sintering a conductive paste. The through electrode 114 has 1 to 10 parts by weight of P 2 with respect to 100 parts by weight of the conductive powder. A conductive paste containing O 5 glass frit (insulating material) is used. In order to prevent the n-type impurity region 111b of the semiconductor substrate 111 and the through electrode 114 from being electrically connected, an insulating layer made of a P 2 O 5 glass material is provided at the interface between the n-type impurity region 111b and the through electrode 114. A layer (not shown) is formed.
 この特許文献1では、受光面電極のうちバスバー部114bを半導体基板111の裏面側に形成することにより、太陽光の受光面積を拡大させると共に、受光面側でのキャリアの再結合損失を低減させ、これにより発電効率の向上を図っている。 In Patent Document 1, the bus bar portion 114b of the light receiving surface electrode is formed on the back surface side of the semiconductor substrate 111, thereby increasing the light receiving area of sunlight and reducing the recombination loss of carriers on the light receiving surface side. As a result, power generation efficiency is improved.
 また、特許文献2には、表面と裏面との間に貫通孔を有し、表面全域及び貫通孔の表面にn層が形成されたp型Si基板を用意し、前記貫通孔に導電性ペーストを充填した後、乾燥し、最高温度700~900℃で焼成するようにしたMWT構造のSi太陽電池セルの製造方法が提案されている。 Patent Document 2 provides a p-type Si substrate having a through hole between a front surface and a back surface and having an n layer formed on the entire surface and the surface of the through hole, and a conductive paste is provided in the through hole. There has been proposed a method for manufacturing a Si solar cell having an MWT structure, in which the substrate is filled, dried, and fired at a maximum temperature of 700 to 900 ° C.
 また、特許文献2では、前記導電性ペーストが、Ag、Cu、Niからなる群から選択された少なくとも一種の金属及び有機ビヒクルを含有し、さらにガラスフリットとして11~33重量%のSiO、0~7重量%のAl、2~10重量%のB、40~73重量%のBiを含有した軟化点が550~611℃の無鉛ガラス、及び53~57重量%のPbO、25~29重量%のSiO、2~6重量%のAl、6~9重量%のBを含有した軟化点が571~636℃の有鉛ガラスを含む点が記載されている。 In Patent Document 2, the conductive paste contains at least one metal selected from the group consisting of Ag, Cu, and Ni and an organic vehicle, and further contains 11 to 33 wt% of SiO 2 , 0 as glass frit. Lead-free glass having a softening point of 550 to 611 ° C., containing ˜7 wt% Al 2 O 3 , 2 to 10 wt% B 2 O 3 , 40 to 73 wt% Bi 2 O 3 , and 53 to 57 wt% Containing leaded glass with a softening point of 571-636 ° C. containing 1% PbO, 25-29% by weight SiO 2 , 2-6% by weight Al 2 O 3 , 6-9% by weight B 2 O 3 Points are listed.
特開2010-80578号公報(請求項1~6、図1)JP 2010-80578 A (Claims 1 to 6, FIG. 1) 国際公開2011/081808号(請求項1、8)International Publication No. 2011/0881808 (Claims 1 and 8)
 しかしながら、特許文献1では、半導体基板111と貫通電極114との界面に絶縁層が形成されているものの、大量の導電性粉末が焼成処理時にガラス中に溶解するため、該ガラス中に大量に溶解した導電性材料が半導体基板111側に析出し、これにより絶縁性が破壊され、pn接合も破壊されるおそれがある。 However, in Patent Document 1, although an insulating layer is formed at the interface between the semiconductor substrate 111 and the through electrode 114, a large amount of conductive powder dissolves in the glass during the firing process, and thus dissolves in a large amount in the glass. The deposited conductive material is deposited on the side of the semiconductor substrate 111, thereby destroying the insulating property and possibly destroying the pn junction.
 すなわち、特許文献1では、n型半導体領域111bは、p型半導体領域111aを囲むようにp型半導体領域111aの外周域に形成されている。 That is, in Patent Document 1, the n-type semiconductor region 111b is formed in the outer peripheral region of the p-type semiconductor region 111a so as to surround the p-type semiconductor region 111a.
 しかしながら、n型半導体領域111bの拡散条件等を調整しても、n型半導体領域111bの厚みを均一に形成するのは困難であり、通常、n型半導体領域111bのうち、貫通電極114に接する側面部分111b′の厚みは、p型半導体領域111aの主面部分111b″の厚みよりも薄く形成されてしまう。このためn型半導体領域111bと貫通電極114との界面に絶縁層を形成しても、焼成処理時にはガラス中に大量に溶解した導電性材料がn型半導体領域111bの側面部分111b′を突き破って絶縁性を破壊するおそれがあり、さらにはp型半導体領域111aに析出し、pn接合を破壊してしまうおそれがある。 However, even if the diffusion conditions and the like of the n-type semiconductor region 111b are adjusted, it is difficult to form the n-type semiconductor region 111b to have a uniform thickness. Usually, the n-type semiconductor region 111b is in contact with the through electrode 114. The thickness of the side surface portion 111b ′ is formed thinner than the thickness of the main surface portion 111b ″ of the p-type semiconductor region 111a. Therefore, an insulating layer is formed at the interface between the n-type semiconductor region 111b and the through electrode 114. However, there is a possibility that the conductive material dissolved in a large amount in the glass during the firing process may break through the side surface portion 111b 'of the n-type semiconductor region 111b to destroy the insulation, and further precipitate in the p-type semiconductor region 111a. There is a risk of destroying the joint.
 しかも、P系ガラスフリットは、通常、化学的耐久性に劣ることから、信頼性を損なうおそれがある。 In addition, the P 2 O 5 glass frit is usually inferior in chemical durability, and there is a risk of impairing reliability.
 また、特許文献2では、550~636℃と軟化点の高いガラスフリットを含有した導電性ペーストを使用して貫通電極を形成しているため、ガラスの流動性に劣り、焼成時に貫通電極と半導体基板との界面に十分にガラスが流れず、十分な絶縁性を確保するのが困難と考えられる。 In Patent Document 2, since the through electrode is formed using a conductive paste containing glass frit having a high softening point of 550 to 636 ° C., the fluidity of the glass is inferior, and the through electrode and the semiconductor are fired during firing. It is considered that it is difficult to ensure sufficient insulation because glass does not sufficiently flow to the interface with the substrate.
 一方、MWT構造の太陽電池としては、n型半導体領域を反射防止膜とp型半導体領域との間にのみ形成し、貫通電極114とp型半導体領域とが接するように形成できれば、構造が簡素となる上、分離溝(図12、符号116)も不要となり生産性向上を図ることができる。 On the other hand, the solar cell having the MWT structure has a simple structure if the n-type semiconductor region can be formed only between the antireflection film and the p-type semiconductor region and the through electrode 114 and the p-type semiconductor region can be in contact with each other. In addition, the separation groove (FIG. 12, reference numeral 116) is not required, and productivity can be improved.
 しかしながら、このような構造を採用した場合、特許文献1や特許文献2に記載の導電性ペーストを使用して貫通電極を形成すると、n型半導体領域から貫通電極に流れてきた電子が、貫通電極からp型半導体領域にリークするおそれがある。すなわちこの場合、p型不純物領域とn型不純物領域との間で貫通電極を介した漏れ電流が発生し、このため所望の高い発電効率を得るのが困難となる。 However, when such a structure is adopted, when the through electrode is formed using the conductive paste described in Patent Document 1 or Patent Document 2, electrons flowing from the n-type semiconductor region to the through electrode are transferred to the through electrode. May leak into the p-type semiconductor region. That is, in this case, a leakage current is generated through the through electrode between the p-type impurity region and the n-type impurity region, and it is difficult to obtain a desired high power generation efficiency.
 本発明はこのような事情に鑑みなされたものであって、半導体基板と貫通電極との間の絶縁性が良好で発電効率の向上に寄与し、かつはんだ付け性や機械的強度に優れた太陽電池を得ることができる導電性ペースト、及びこの導電性ペーストを使用した貫通電極の製造方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and has a good insulating property between the semiconductor substrate and the through electrode, contributes to an improvement in power generation efficiency, and is excellent in solderability and mechanical strength. It aims at providing the manufacturing method of the electroconductive paste which can obtain a battery, and the penetration electrode using this electroconductive paste.
 本発明者らは、MWT構造の太陽電池において、貫通電極の形成に適した導電性ペーストを得るべく鋭意研究を行ったところ、V酸化物を主成分とするV酸化物系のガラス材料は、軟化点が低く、しかも電気伝導性が良好であることから、絶縁性が良好で漏れ電流を抑制でき、これにより貫通電極の形成に適した導電性ペーストを得ることができるという知見を得た。 The inventors of the present invention conducted intensive studies to obtain a conductive paste suitable for forming a through electrode in a solar cell having an MWT structure. Since the softening point is low and the electrical conductivity is good, it has been found that the insulating property is good and the leakage current can be suppressed, whereby a conductive paste suitable for forming the through electrode can be obtained.
 また、V酸化物系のガラス材料は、上述したように軟化点が低く、流動性が良好であることから、少量のガラス含有量でもって絶縁性を確保でき、その結果、はんだ付け性が良好で機械的強度にも優れた太陽電池を得ることができることも分かった。 Further, as described above, the V oxide glass material has a low softening point and good fluidity, so that insulation can be secured with a small amount of glass, and as a result, solderability is good. It was also found that a solar cell excellent in mechanical strength can be obtained.
 本発明はこのような知見に基づきなされたものであり、本発明に係る導電性ペーストは、太陽電池の電極を形成するための導電性ペーストであって、導電性粉末と、ガラス成分と、有機ビヒクルとを含有し、かつ、前記ガラス成分は、V酸化物を主成分とするV酸化物系材料で形成されていることを特徴としている。 The present invention has been made on the basis of such knowledge, and the conductive paste according to the present invention is a conductive paste for forming an electrode of a solar cell, and includes a conductive powder, a glass component, and an organic paste. The glass component is characterized by being formed of a V oxide-based material containing V oxide as a main component.
 また、本発明に係る導電性ペーストは、前記ガラス成分中のVの含有量は、酸化物に換算し重量比率で70重量%以上であるのが好ましい。 In the conductive paste according to the present invention, the V content in the glass component is preferably 70% by weight or more in terms of a weight ratio in terms of oxide.
 これにより貫通電極から半導体基板への漏れ電流をより一層抑制することが可能となる。 This makes it possible to further suppress the leakage current from the through electrode to the semiconductor substrate.
 また、本発明の導電性ペーストは、前記ガラス成分の含有量は、5~15重量%であるのが好ましい。 In the conductive paste of the present invention, the content of the glass component is preferably 5 to 15% by weight.
 これにより絶縁性を確保しつつ、良好なはんだ付け性を有する導電性ペーストを得ることができる。 This makes it possible to obtain a conductive paste having good solderability while ensuring insulation.
 また、本発明者らの更なる鋭意研究の結果、V酸化物系ガラス材料の中でも熱処理時に容易に結晶化するガラス材料は、より一層の電気伝導性向上を図ることができ、しかも結晶化後は流動性が低下することから貫通電極のバスバー部の表面にガラス材が浮き上がりにくくなり、はんだ付け性が向上することも分かった。 Further, as a result of further diligent research by the present inventors, among V oxide glass materials, glass materials that easily crystallize during heat treatment can further improve electrical conductivity, and after crystallization. It has also been found that since the fluidity is lowered, the glass material is less likely to float on the surface of the bus bar portion of the through electrode, and the solderability is improved.
 すなわち、本発明の導電性ペーストは、前記ガラス成分が、熱処理で結晶化されるのが好ましい。 That is, in the conductive paste of the present invention, the glass component is preferably crystallized by heat treatment.
 さらに、本発明者らが鋭意研究を重ねたところ、リン酸系化合物を添加することにより、導電性ペーストの焼成時にリン酸と導電性粉末とが反応して導電性粉末の粒子表面に絶縁層が形成され、これにより貫通電極と半導体基板との絶縁性を向上させることができることが分かった。 Furthermore, as a result of extensive research by the present inventors, by adding a phosphoric acid compound, phosphoric acid and conductive powder react when the conductive paste is baked, and an insulating layer is formed on the particle surface of the conductive powder. As a result, it was found that the insulation between the through electrode and the semiconductor substrate can be improved.
 すなわち、本発明の導電性ペーストは、リン酸系化合物が含有されているのが好ましい。 That is, the conductive paste of the present invention preferably contains a phosphoric acid compound.
 また、本発明の導電性ペーストは、前記リン酸系化合物が、Ag、AgPO、Zn、MnPO、及びZrWO(POの群から選択された少なくとも1種を含むのが好ましい。 In the conductive paste of the present invention, the phosphoric acid compound may be Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 (PO 4 ). It is preferable to include at least one selected from the group of 2 .
 また、本発明者らが更に鋭意研究を行なったところ、結晶子径が70nm以上の導電性粉末を使用した場合は、貫通電極自体が過度に収縮して形成されるのを抑制できることが分かった。 In addition, when the present inventors conducted further earnest studies, it was found that when a conductive powder having a crystallite diameter of 70 nm or more is used, the through electrode itself can be prevented from being excessively contracted. .
 すなわち、本発明の導電性ペーストに含有される前記導電性粉末が、結晶子径が70nm以上であるのが好ましい。 That is, it is preferable that the conductive powder contained in the conductive paste of the present invention has a crystallite diameter of 70 nm or more.
 これにより貫通電極自体が過度に収縮して形成されることがないことから、前記貫通電極中に多量のガラスを添加しても半導体基板にクラックが生じることもなく、電気特性の劣化を防止することができる。しかも、電極表面に過剰にガラスが流動することもなく、良好なはんだ付け性を有する太陽電池を得ることが可能となる。 As a result, the through electrode itself is not excessively shrunk, so that even if a large amount of glass is added to the through electrode, the semiconductor substrate does not crack and prevents deterioration of electrical characteristics. be able to. In addition, it is possible to obtain a solar cell having good solderability without excessive glass flowing on the electrode surface.
 また、本発明の導電性ペーストは、前記導電性粉末は、アトマイズ法で作製されたアトマイズ粉を含むのが好ましい。 In the conductive paste of the present invention, the conductive powder preferably contains atomized powder produced by an atomizing method.
 これにより結晶子径が70nm以上の導電性粉末を容易に得ることが可能となる。 This makes it possible to easily obtain a conductive powder having a crystallite diameter of 70 nm or more.
 また、本発明の導電性ペーストは、前記導電性粉末が、Agを主成分としているのが好ましい。 In the conductive paste of the present invention, the conductive powder is preferably composed mainly of Ag.
 また、本発明に係る貫通電極の製造方法は、基板に貫通孔を形成した後、上述したいずれかに記載の導電性ペーストを前記貫通孔に充填して貫通導体を形成し、その後焼成処理を行なって前記基板に貫通電極を形成することを特徴としている。 Further, in the method for manufacturing a through electrode according to the present invention, after forming the through hole in the substrate, the conductive paste according to any one of the above is filled into the through hole to form the through conductor, and then the baking treatment is performed. A through electrode is formed on the substrate.
 本発明の導電性ペーストによれば、導電性粉末と、ガラス成分と、有機ビヒクルとを含有し、かつ、前記ガラス成分は、V酸化物を主成分とするV酸化物系材料形成されているので、該導電性ペーストを貫通電極形成用に使用することにより半導体基板と貫通電極との間の絶縁性が良好で発電効率を向上させることができ、かつはんだ付け性や機械的強度の良好なMWT構造の太陽電池を得ることが可能となる。 According to the conductive paste of the present invention, a conductive oxide, a glass component, and an organic vehicle are contained, and the glass component is formed of a V oxide-based material containing a V oxide as a main component. Therefore, by using the conductive paste for forming the through electrode, the insulation between the semiconductor substrate and the through electrode can be improved, the power generation efficiency can be improved, and the solderability and mechanical strength are good. A solar cell having an MWT structure can be obtained.
 すなわち、V酸化物系のガラス材料は軟化点が低く流動性が良好であることから、貫通電極形成用に使用した場合、短時間の焼成で貫通孔と基板との間にガラス成分が流動し、絶縁層を形成する。また、V酸化物系のガラス材料は、他のガラス材料に比べ、電気伝導性が良好であり、p型半導体と貫通電極とが接していても、貫通電極を介してn型半導体からp型半導体にリークする漏れ電流を抑制することができる。すなわち、この場合、n型半導体から貫通電極の導電性材料に移動してきた電子は、導電性材料からp型半導体に流れずに電気伝導性の高いガラス成分側に流れ、その後、ガラス成分から導電性材料に流れる。しかも、電気伝導性が良好なガラス成分が基板の界面に存在するため、界面に絶縁性が弱い箇所が生じたとしても電界集中が起こらず、貫通電極を介してn型半導体からp型半導体に流れる漏れ電流を抑制することが可能となる。 In other words, since the V oxide glass material has a low softening point and good fluidity, when used for forming a through electrode, the glass component flows between the through hole and the substrate in a short period of time. Then, an insulating layer is formed. Further, the V oxide-based glass material has better electrical conductivity than other glass materials, and even if the p-type semiconductor and the through electrode are in contact with each other, the n-type semiconductor is changed to the p-type through the through electrode. Leakage current leaking to the semiconductor can be suppressed. That is, in this case, electrons that have moved from the n-type semiconductor to the conductive material of the through electrode do not flow from the conductive material to the p-type semiconductor, but flow to the glass component side with high electrical conductivity, and then the conductive from the glass component. Flowing into sex material. In addition, since a glass component having good electrical conductivity exists at the interface of the substrate, electric field concentration does not occur even if a weakly insulating portion occurs at the interface, and the n-type semiconductor is changed to the p-type semiconductor through the through electrode. The flowing leakage current can be suppressed.
 このようにV酸化物系のガラス材料は、軟化点が低く、しかも他のガラス材料と比べて電気伝導性が良好であることから、半導体基板との絶縁性が良好な貫通電極を形成することが可能となり、太陽電池の発電効率を向上させることが可能となる。しかも、上述したようにガラス成分が基板との界面で流動しやすいことから、ガラス成分の含有量を低減することができ、良好なはんだ付け性と機械的強度を確保することが可能となる。 As described above, the V oxide-based glass material has a low softening point and good electrical conductivity as compared with other glass materials, so that a through electrode having good insulation from the semiconductor substrate is formed. Thus, the power generation efficiency of the solar cell can be improved. Moreover, since the glass component easily flows at the interface with the substrate as described above, the content of the glass component can be reduced, and good solderability and mechanical strength can be ensured.
 また、本発明の貫通電極の製造方法によれば、基板に貫通孔を形成した後、上述したいずれかに記載の導電性ペーストを前記貫通孔に充填して貫通導体を形成し、その後焼成処理を行なって前記基板に貫通電極を形成するので、絶縁性やはんだ付け性が良好で機械的強度に優れた貫通電極を得ることができる。 Further, according to the method for manufacturing a through electrode of the present invention, after forming the through hole in the substrate, the conductive paste according to any one of the above is filled into the through hole to form the through conductor, and then the baking treatment is performed. Since the through electrode is formed on the substrate, it is possible to obtain a through electrode having good insulation and solderability and excellent mechanical strength.
本発明に係る導電性ペーストを使用して製造された太陽電池の一実施形態を示す要部断面図である。It is principal part sectional drawing which shows one Embodiment of the solar cell manufactured using the electrically conductive paste which concerns on this invention. 受光面電極側を模式的に示した拡大平面図である。It is the enlarged plan view which showed the light-receiving surface electrode side typically. 上記太陽電池の製造方法の一実施の形態を示す製造工程図(1/2)である。It is a manufacturing process figure (1/2) which shows one Embodiment of the manufacturing method of the said solar cell. 上記太陽電池の製造方法の一実施の形態を示す製造工程図(2/2)である。It is a manufacturing process figure (2/2) which shows one Embodiment of the manufacturing method of the said solar cell. 実施例1で作製された電極パターンを模式的に示した平面図である。3 is a plan view schematically showing an electrode pattern produced in Example 1. FIG. 実施例2で作製された試料を模式的に示した断面図である。FIG. 6 is a cross-sectional view schematically showing a sample manufactured in Example 2. 実施例2の電流-電圧特性を示す図である。FIG. 6 is a diagram showing current-voltage characteristics of Example 2. 実施例2におけるガラス成分中のV含有量と微分抵抗との関係を示す図である。Is a diagram showing the relationship between V 2 O 5 content of the glass component in the second embodiment and the differential resistance. 実施例3における結晶粒子のSEM像である。4 is a SEM image of crystal grains in Example 3. 従来の太陽電池の一例を模式的に示す要部断面図である。It is principal part sectional drawing which shows an example of the conventional solar cell typically. 図10の要部平面図である。It is a principal part top view of FIG. 特許文献1に記載された太陽電池の要部断面図である。2 is a cross-sectional view of a main part of a solar cell described in Patent Document 1. FIG.
 次に、本発明の実施の形態を詳説する。 Next, an embodiment of the present invention will be described in detail.
 本発明の一実施の形態としての導電性ペーストは、導電性粉末と、ガラス成分と、有機ビヒクルとを含有し、かつ、前記ガラス成分は、V酸化物を主成分とするV酸化物系材料で形成されている。そして、これにより太陽電池の電極、特にMWT構造の太陽電池の貫通電極形成に好適な導電性ペーストを得ることができる。 The conductive paste as one embodiment of the present invention contains a conductive powder, a glass component, and an organic vehicle, and the glass component is a V oxide-based material containing V oxide as a main component. It is formed with. As a result, it is possible to obtain a conductive paste suitable for forming a through electrode of a solar cell electrode, particularly a solar cell having an MWT structure.
 すなわち、Vに代表されるV酸化物を主成分としたV酸化物系ガラス材料は、軟化点が300~450℃と低く、極めて短時間の焼成処理で容易に流動する。したがって、このV酸化物系ガラス成分を含有した導電性ペーストを半導体基板に形成された貫通孔に充填し、焼成すると、ガラス成分が貫通孔内を容易に流動し、その結果、半導体基板との界面に絶縁層が形成され易くなる。そしてこれによりAg等の導電性材料が半導体基板側に析出することもなく、半導体基板のpn接合が破壊されるのを回避することができる。 That is, a V oxide glass material mainly composed of V oxide typified by V 2 O 5 has a softening point as low as 300 to 450 ° C. and easily flows in a very short baking process. Therefore, when the conductive paste containing the V-oxide glass component is filled in the through-hole formed in the semiconductor substrate and baked, the glass component easily flows in the through-hole. An insulating layer is easily formed at the interface. As a result, the conductive material such as Ag is not deposited on the semiconductor substrate side, and the pn junction of the semiconductor substrate can be prevented from being broken.
 また、V酸化物系ガラス材料は、他のガラス材料に比べて電気伝導性に優れており、このため貫通電極から半導体基板側に漏れる漏れ電流を効果的に抑制することができる。すなわち、通常のガラス材料の電気伝導度は10-12S/cm以下であり、ほぼ絶縁体であるのに対し、V酸化物系ガラス材料の電気伝導度は10-2~10-7S/cmと高く、半導体並みの電気伝導性を有する。 Further, the V oxide glass material is superior in electrical conductivity compared to other glass materials, and therefore, a leakage current leaking from the through electrode to the semiconductor substrate side can be effectively suppressed. That is, the electrical conductivity of a normal glass material is 10 −12 S / cm or less, which is almost an insulator, whereas the electrical conductivity of a V oxide glass material is 10 −2 to 10 −7 S / cm. It is as high as cm and has electrical conductivity similar to that of a semiconductor.
 このようにV酸化物系ガラス材料は、他のガラス材料に比べて電気伝導性が良好であることから、このV酸化物系ガラス材料を含有した導電性ペーストを使用して貫通電極を形成すると、p型半導体層の一方の主面上にn型半導体層を形成し、かつ、貫通電極をp型半導体層と接するような構造にした場合であっても、n型半導体層から貫通電極の電極材料に流れてきた電子は、電極材料を経由してp型半導体層にリークせずに、電極材料とp型半導体層との間に形成されたV酸化物系ガラス成分からなる絶縁層を経由し、再び電極材料側に移動する。したがって、貫通電極からp型半導体層に電流がリークするのを阻止することができ、漏れ電流の発生を抑制することが可能となる。 As described above, since the V oxide glass material has better electrical conductivity than other glass materials, when a through electrode is formed using a conductive paste containing the V oxide glass material. Even when the n-type semiconductor layer is formed on one main surface of the p-type semiconductor layer and the through electrode is in contact with the p-type semiconductor layer, the n-type semiconductor layer is connected to the through-electrode. Electrons that have flowed into the electrode material do not leak to the p-type semiconductor layer via the electrode material, but instead form an insulating layer made of a V oxide glass component formed between the electrode material and the p-type semiconductor layer. Via, it moves again to the electrode material side. Therefore, it is possible to prevent current from leaking from the through electrode to the p-type semiconductor layer, and it is possible to suppress the occurrence of leakage current.
 また、P系ガラス材料等の従来のガラス材料は、ほぼ絶縁体であり、電気伝導性に劣るため、絶縁性の弱い箇所が生じると一気に電界集中が発生して漏れ電流が大きくなる。これに対しV酸化物系ガラス材料は電気伝導性が良好であるので、電界集中が生じるのを抑制することができ、これにより漏れ電流を効果的に低減することが可能となり、所望の絶縁性を確保することができる。 In addition, conventional glass materials such as P 2 O 5 glass materials are almost insulators and are inferior in electrical conductivity. Therefore, when a weakly insulating portion occurs, electric field concentration occurs at a stretch and leakage current increases. . On the other hand, since the V oxide glass material has good electrical conductivity, it is possible to suppress the occurrence of electric field concentration, and thus it is possible to effectively reduce the leakage current, and to achieve a desired insulating property. Can be secured.
 このようにV酸化物系ガラス材料は、軟化点が低く、しかも他のガラス材料と比べて電気伝導性が良好であることから、半導体基板との絶縁性が良好な貫通電極を形成することが可能となり、太陽電池の発電効率を向上させることが可能となる。しかも、上述したようにガラス成分が基板との界面で流動しやすいことから、ガラス成分の含有量を低減することができ、良好なはんだ付け性と機械的強度を確保することが可能となる。 As described above, since the V oxide glass material has a low softening point and good electrical conductivity compared to other glass materials, a through electrode having good insulation from the semiconductor substrate may be formed. It becomes possible, and it becomes possible to improve the power generation efficiency of a solar cell. Moreover, since the glass component easily flows at the interface with the substrate as described above, the content of the glass component can be reduced, and good solderability and mechanical strength can be ensured.
 そして、このようなV酸化物系ガラス成分としては、V酸化物を主成分とするのであれば、特に限定されるものではないが、熱処理により容易に結晶化するV-BaO-ZnO系やV-Fe-BaO系のガラス成分を使用するのが好ましい。すなわち、熱処理により結晶化させることにより、非晶質状態のガラス成分よりも電気伝導度がより高くなり、漏れ電流をより一層効果的に抑制することが可能となる。また、熱処理で結晶化させることにより、結晶化後はガラス成分の流動性が低下することから、貫通電極の電極表面にガラスが浮き上がり難くなり、はんだ付け性の向上を図ることができる。特に、Vを酸化物に換算して重量比率で70重量%以上含有したV酸化物系材料は、はんだ付け性の向上と共に、更なる漏れ電流の抑制を図ることが可能となる。 Such a V oxide glass component is not particularly limited as long as it contains V oxide as a main component, but V 2 O 5 —BaO—ZnO that is easily crystallized by heat treatment. It is preferable to use a glass component of a V 2 O 5 —Fe 2 O 3 —BaO system. That is, by crystallizing by heat treatment, the electrical conductivity becomes higher than that of the glass component in the amorphous state, and the leakage current can be more effectively suppressed. Further, by crystallizing by heat treatment, the fluidity of the glass component decreases after crystallization, so that the glass is less likely to float on the electrode surface of the through electrode, and solderability can be improved. In particular, a V oxide-based material containing 70% by weight or more in terms of a weight ratio in terms of an oxide can improve solderability and further suppress leakage current.
 また、導電性ペースト中のV酸化物系ガラス成分の含有量は、特に限定されるものではないが、絶縁性を確保しつつ、はんだ付け性や機械的強度を確保する観点からは、5~15重量%が好ましい。すなわち、V酸化物系ガラス成分の含有量が5重量%未満になると、機械的強度の低下を招くおそれがある。また、半導体基板との界面に流動するガラス成分が減少して導電性材料と半導体基板とが直接接触する確率が増加し、絶縁性の低下を招くおそれもある。一方、V酸化物系ガラス成分の含有量が15重量%を超えると、導電性材料の表面を流動するV酸化物系ガラス成分が増加し、ガラス成分が貫通電極の表面に浮き上がり、はんだ付け性の低下を招くおそれがある。 Further, the content of the V oxide glass component in the conductive paste is not particularly limited, but from the viewpoint of ensuring solderability and mechanical strength while ensuring insulation, it is 5 to 15% by weight is preferred. That is, when the content of the V oxide glass component is less than 5% by weight, the mechanical strength may be lowered. In addition, the glass component flowing to the interface with the semiconductor substrate is reduced, and the probability that the conductive material and the semiconductor substrate are in direct contact with each other increases, which may cause a decrease in insulation. On the other hand, when the content of the V oxide glass component exceeds 15% by weight, the V oxide glass component flowing on the surface of the conductive material increases, the glass component floats on the surface of the through electrode, and solderability. There is a risk of lowering.
 このような観点から導電性ペースト中のV酸化物系ガラス成分の含有量は、5~15重量%が好ましく、これにより絶縁性を確保しつつ、はんだ付け性や機械的強度が良好で半導体基板にクラック等の構造欠陥の発生が抑制された信頼性の高い貫通電極を形成することが可能となる。 From this point of view, the content of the V oxide glass component in the conductive paste is preferably 5 to 15% by weight, thereby ensuring good insulation and good solderability and mechanical strength. In addition, it is possible to form a highly reliable through electrode in which occurrence of structural defects such as cracks is suppressed.
 また、導電性粉末の結晶子径や平均粒径D50は、特に限定されるものではないが、好ましくは結晶子径が70nm以上の導電性粉末を使用するのが良い。すなわち、結晶子径が70nm以上の導電性粉末を使用することにより、貫通電極の過剰な収縮を抑制することができる。そして、このように貫通電極の過剰な収縮を抑制することにより、半導体基板のp型半導体層及びn型半導体層の双方に対して極めて高い接触抵抗を示すことができ、より一層の漏れ電流抑制が可能となる。さらに、貫通電極の過剰な収縮を抑制することにより、貫通電極と半導体基板との間でガラス成分が流動し易くなることから、電極表面に過剰にガラスが流動することもなく、良好なはんだ付け性と機械的強度を確保することが可能となる。また、これにより貫通電極に多量のガラス成分を含有させても、半導体基板にクラックが生じるのを抑制でき、電気特性が劣化することを防止することができる。 The conductive crystallite diameter and average particle diameter D 50 of the powder is not particularly limited, and it is preferably crystallite diameter using the above conductive powder 70 nm. That is, excessive shrinkage of the through electrode can be suppressed by using conductive powder having a crystallite diameter of 70 nm or more. In addition, by suppressing excessive shrinkage of the through electrode in this way, extremely high contact resistance can be exhibited with respect to both the p-type semiconductor layer and the n-type semiconductor layer of the semiconductor substrate, and further leakage current suppression is achieved. Is possible. In addition, by suppressing excessive shrinkage of the through electrode, the glass component can easily flow between the through electrode and the semiconductor substrate, so that the glass does not flow excessively on the electrode surface and good soldering is achieved. Property and mechanical strength can be ensured. In addition, even when a large amount of glass component is contained in the through electrode, it is possible to suppress the generation of cracks in the semiconductor substrate and to prevent the electrical characteristics from deteriorating.
 そして、このような導電性粉末の製法としては、特に限定されるものではなく、アトマイズ法や湿式還元法を使用して得ることができ、或いは両者の混合粉(アトマイズ粉、湿式還元粉)を使用してもよい。ここで、アトマイズ法は、加熱処理して溶湯化させた導電性材料に高圧水等を噴霧して液滴化し、液滴となった導電性材料を落下させながら凝固させ、これにより導電性粉末を生成する方法である。一方、湿式還元法は、金属塩を含有した水溶液にアルカリを添加して金属酸化物を含有したスラリーを作製し、このスラリーに還元剤を添加して金属粉末を還元析出させ、これにより導電性粉末を生成する方法である。 And as a manufacturing method of such an electroconductive powder, it is not specifically limited, It can obtain using the atomization method and a wet reduction method, or both mixed powder (atomization powder, wet reduction powder) is used. May be used. Here, the atomizing method is a method of spraying high-pressure water or the like onto a conductive material melted by heat treatment to form liquid droplets, and solidifying while dropping the conductive material, thereby forming a conductive powder. Is a method of generating On the other hand, in the wet reduction method, a slurry containing a metal oxide is prepared by adding an alkali to an aqueous solution containing a metal salt, and a reducing agent is added to the slurry to reduce and precipitate the metal powder, thereby making it conductive. A method for producing a powder.
 ただし、湿式還元法では微細な導電性粉末が生成され易いことから、70nm以上の結晶子径の大きな導電性粉末をより効率良く得る観点からは、アトマイズ法で作製するのが好ましい。 However, since a fine conductive powder is likely to be produced by the wet reduction method, it is preferably produced by the atomizing method from the viewpoint of more efficiently obtaining a conductive powder having a large crystallite diameter of 70 nm or more.
 また、導電性粉末としては、所望の導電性を有するものであれば特に限定されるものではないが、通常はAg、又はAgを主成分としたAg合金が好んで使用される。 Further, the conductive powder is not particularly limited as long as it has a desired conductivity, but usually Ag or an Ag alloy containing Ag as a main component is preferably used.
 尚、導電性粉末の含有量は、電極としての作用を奏するのであれば、特に限定されるものではないが、通常は70~90重量%程度が好ましく、特に75~85重量%が好ましい。 The content of the conductive powder is not particularly limited as long as it has an effect as an electrode, but it is usually preferably about 70 to 90% by weight, particularly preferably 75 to 85% by weight.
 また、本発明の導電性ペーストは、さらにリン酸系化合物を含有するのも好ましい。すなわち、導電性ペースト中にリン酸系化合物を含有することにより、焼成後の貫通電極中における導電性粉末の表面にはリン濃度の高い絶縁層を形成することができる。したがって、貫通電極と半導体基板との間の接触抵抗をより高くすることができ、これにより貫通電極と半導体基板との間にはより良好な絶縁性を得ることが可能となる。 The conductive paste of the present invention preferably further contains a phosphoric acid compound. That is, by containing a phosphoric acid compound in the conductive paste, an insulating layer having a high phosphorus concentration can be formed on the surface of the conductive powder in the through electrode after firing. Therefore, the contact resistance between the through electrode and the semiconductor substrate can be further increased, and thereby better insulation can be obtained between the through electrode and the semiconductor substrate.
 このようなリン酸系化合物としては、特に限定されるものではなく、例えば、Ag、AgPO、Zn、MnPO、及びZrWO(PO等を使用することができる。 Such a phosphoric acid compound is not particularly limited. For example, Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 ( PO 4 ) 2 or the like can be used.
 そして、この導電性ペーストは、好ましくは70~90重量%の導電性粉末、5~15重量%のV系ガラス成分、残部が有機ビヒクルとなるように秤量し、必要に応じて適量のリン酸系化合物を秤量して混合し、三本ロールミル等を使用して分散・混練することにより、容易に製造することができる。 The conductive paste is preferably weighed so that 70 to 90% by weight of the conductive powder, 5 to 15% by weight of the V 2 O 5 glass component, and the balance is an organic vehicle, and an appropriate amount as necessary. These phosphoric acid compounds can be weighed and mixed, and can be easily manufactured by dispersing and kneading them using a three-roll mill or the like.
 尚、有機ビヒクルは、バインダ樹脂と有機溶剤とを、例えば体積比率で、1~3:7~9となるように調製することにより作製される。ここで、バインダ樹脂としては、特に限定されるものではなく、例えば、エチルセルロース樹脂、ニトロセルロース樹脂、アクリル樹脂、アルキド樹脂、又はこれらの組み合わせを使用することができる。また、有機溶剤についても特に限定されるものではなく、α―テルピネオール、キシレン、トルエン、ジエチレングリコールモノブチルエーテル、ジエチレングリコールモノブチルエーテルアセテート、ジエチレングリコールモノエチルエーテル、ジエチレングリコールモノエチルエーテルアセテート等を単独、或いはこれらを組み合わせて使用することができる。 The organic vehicle is produced by preparing a binder resin and an organic solvent so that the volume ratio is, for example, 1 to 3: 7 to 9. Here, the binder resin is not particularly limited, and for example, ethyl cellulose resin, nitrocellulose resin, acrylic resin, alkyd resin, or a combination thereof can be used. Also, the organic solvent is not particularly limited, and α-terpineol, xylene, toluene, diethylene glycol monobutyl ether, diethylene glycol monobutyl ether acetate, diethylene glycol monoethyl ether, diethylene glycol monoethyl ether acetate, etc. alone or in combination thereof Can be used.
 また、上記実施の形態では、導電性ペーストは、導電性粉末、V系ガラス材料、及び有機ビヒクルで形成されているが、有機ビヒクルの含有量を若干減少させ、その代わりに少量のフタル酸ジ2-エチルヘキシル、フタル酸ジブチル等の可塑剤を1種又はこれらの組み合わせを添加したり、脂肪酸アマイドや脂肪酸等のレオロジー調整剤を添加するのも好ましく、さらにはチクソトロピック剤、増粘剤、分散剤などを必要に応じて添加してもよい。 In the above embodiment, the conductive paste is formed of conductive powder, a V 2 O 5 glass material, and an organic vehicle. However, the content of the organic vehicle is slightly reduced, and a small amount is used instead. It is also preferable to add one or a combination of plasticizers such as di-2-ethylhexyl phthalate and dibutyl phthalate, or add rheology modifiers such as fatty acid amides and fatty acids, and more thixotropic agents, thickeners. Agents, dispersants and the like may be added as necessary.
 そして、基板に貫通孔を形成した後、上述した導電性ペーストを前記貫通孔に充填して貫通導体を形成し、その後焼成処理を行なって前記基板に貫通電極を形成することにより、絶縁性やはんだ付け性が良好で機械的強度に優れた貫通電極を得ることができる。 And after forming a through-hole in a board | substrate, the conductive paste mentioned above is filled into the said through-hole, a through-conductor is formed, and after that a baking process is performed and a through-electrode is formed in the said board | substrate, insulation property or A through electrode having good solderability and excellent mechanical strength can be obtained.
 次に、上記導電性ペーストを使用して製造された太陽電池について詳述する。 Next, the solar cell manufactured using the conductive paste will be described in detail.
 図1は、太陽電池の一実施の形態を示す要部断面図であり、図2は、図1の平面図である。 FIG. 1 is a cross-sectional view of an essential part showing an embodiment of a solar cell, and FIG. 2 is a plan view of FIG.
 この太陽電池は、Siを主成分とした半導体基板1の一方の主面に反射防止膜2及び受光面電極3が形成されると共に、該半導体基板1の他方の主面に裏面電極4が形成されている。 In this solar cell, an antireflection film 2 and a light receiving surface electrode 3 are formed on one main surface of a semiconductor substrate 1 containing Si as a main component, and a back electrode 4 is formed on the other main surface of the semiconductor substrate 1. Has been.
 半導体基板1は、p型半導体層1aの上面にn型半導体層1bが形成され、p型半導体層1aの下面所定領域にBSF層1cが形成されている。n型半導体層1aは、例えば、単結晶又は多結晶のp型半導体層1bの一方の主面にドナー不純物を拡散させることにより得ることができるが、p型半導体層1aの上面に、高濃度でn層化された薄層のn型半導体層1bが形成されるのであれば、その製法は特に限定されるものではない。 In the semiconductor substrate 1, an n-type semiconductor layer 1b is formed on the upper surface of the p-type semiconductor layer 1a, and a BSF layer 1c is formed in a predetermined region on the lower surface of the p-type semiconductor layer 1a. The n-type semiconductor layer 1a can be obtained, for example, by diffusing donor impurities on one main surface of the single-crystal or polycrystalline p-type semiconductor layer 1b. However, the n-type semiconductor layer 1a has a high concentration on the upper surface of the p-type semiconductor layer 1a. As long as a thin n-type semiconductor layer 1b having an n + layer is formed, the manufacturing method is not particularly limited.
 また、BSF層1cは、焼成時に集電電極4aを形成するAlがアクセプタ不純物として作用して拡散し、p型半導体層1cの集電電極4aの対向面にp層化されて形成される。 In addition, the BSF layer 1c is formed by Al forming the current collecting electrode 4a at the time of firing acting as an acceptor impurity and diffusing, and forming a p + layer on the opposing surface of the current collecting electrode 4a of the p-type semiconductor layer 1c. .
 さらに、半導体基板1には、一方の主面から他方の主面に架けて多数の貫通電極6が形成されている。この貫通電極6は、半導体基板1内を貫通するビア部6aと、ビア部6aに連接されて半導体基板1の裏面に形成されたバスバー部6bとを有している。そして、半導体基板1で発生した電力は、受光面電極3(フィンガー電極5a~5n)によって集電され、貫通電極6のビア部6aを経てバスバー部6bによって外部に取り出される。 Furthermore, a large number of through electrodes 6 are formed on the semiconductor substrate 1 from one main surface to the other main surface. The through electrode 6 has a via portion 6 a penetrating through the semiconductor substrate 1 and a bus bar portion 6 b formed on the back surface of the semiconductor substrate 1 connected to the via portion 6 a. The electric power generated in the semiconductor substrate 1 is collected by the light receiving surface electrode 3 (finger electrodes 5a to 5n), and taken out to the outside by the bus bar portion 6b through the via portion 6a of the through electrode 6.
 尚、図1では、半導体基板1の表面はフラット状に記載しているが、太陽光を半導体基板1に効果的に閉じ込めるために、表面は微小凹凸構造(テクスチャ)を有するように形成されている。 In FIG. 1, the surface of the semiconductor substrate 1 is shown in a flat shape. However, in order to effectively confine sunlight to the semiconductor substrate 1, the surface is formed to have a micro uneven structure (texture). Yes.
 反射防止膜2は、窒化ケイ素(SiN)等の絶縁性材料で形成され、矢印Aに示す太陽光の受光面への光の反射を抑制し、太陽光を半導体基板1に迅速かつ効率よく導く。この反射防止膜2を構成する材料としては、上述した窒化ケイ素に限定されるものではなく、他の絶縁性材料、例えば酸化ケイ素(SiO)や酸化チタン(TiO)等を使用してもよく、2種類以上の絶縁性材料を併用してもよい。また、結晶Si系であれば単結晶Si及び多結晶Siのいずれを使用してもよい。 The antireflection film 2 is formed of an insulating material such as silicon nitride (SiN x ), suppresses reflection of light to the light receiving surface of sunlight indicated by an arrow A, and allows sunlight to be quickly and efficiently applied to the semiconductor substrate 1. Lead. The material constituting the antireflection film 2 is not limited to the above-described silicon nitride, and other insulating materials such as silicon oxide (SiO 2 ) and titanium oxide (TiO 2 ) may be used. In addition, two or more kinds of insulating materials may be used in combination. In addition, as long as it is crystalline Si, either single crystal Si or polycrystalline Si may be used.
 受光面電極3は、図2に示すように、多数のフィンガー電極5a、5b、…5nが櫛歯状に並設されており、受光面電極3が設けられている部分を除く残りの領域に、反射防止膜2が形成されている。この受光面電極3は、スクリーン印刷等を使用し、別途用意した導電性ペーストを半導体基板1上に塗布して導電膜を作製し、焼成することによって形成される。すなわち、受光面電極3を形成する焼成過程で、導電膜下層の反射防止膜2が分解・除去されてファイヤースルーされ、これにより反射防止膜2を貫通する形態で半導体基板1上に受光面電極3が形成される。このようにして半導体基板1で発生した電力をフィンガー電極5a~5nによって集電すると共に、該フィンガー電極5a~5nは、上述したように貫通電極6に接続され、貫通電極6のバスバー部6bから電力を外部に取り出している。 As shown in FIG. 2, the light receiving surface electrode 3 has a large number of finger electrodes 5 a, 5 b,... 5 n arranged in a comb-like shape, and the remaining area excluding the portion where the light receiving surface electrode 3 is provided. The antireflection film 2 is formed. The light-receiving surface electrode 3 is formed by applying a conductive paste prepared separately on the semiconductor substrate 1 by using screen printing or the like to produce a conductive film and baking it. That is, in the baking process for forming the light receiving surface electrode 3, the antireflection film 2 under the conductive film is decomposed and removed and fired through, whereby the light receiving surface electrode is formed on the semiconductor substrate 1 so as to penetrate the antireflection film 2. 3 is formed. In this way, the electric power generated in the semiconductor substrate 1 is collected by the finger electrodes 5a to 5n, and the finger electrodes 5a to 5n are connected to the through electrode 6 as described above, and from the bus bar portion 6b of the through electrode 6 Electric power is taken out.
 裏面電極4は、半導体基板1の裏面に形成されたAlからなる集電電極4aと、該集電電極4aの裏面に形成されて該集電電極4aと電気的に接続されたAg等からなる取出電極4bとで構成されている。そして、半導体基板1で発生した電力は集電電極4aに集電され、取出電極4bによって電力を取り出している。 The back electrode 4 is made of a current collecting electrode 4a made of Al formed on the back surface of the semiconductor substrate 1, and Ag or the like formed on the back surface of the current collecting electrode 4a and electrically connected to the current collecting electrode 4a. It is comprised with the extraction electrode 4b. The electric power generated in the semiconductor substrate 1 is collected by the collecting electrode 4a, and the electric power is taken out by the extracting electrode 4b.
 そして、上記太陽電池は以下のようにして製造することができる。 And the said solar cell can be manufactured as follows.
 図3及び図4は太陽電池の製造方法の一実施の形態を示す製造工程図である。 3 and 4 are manufacturing process diagrams showing one embodiment of a method for manufacturing a solar cell.
 まず、図3(a)に示すように、単結晶又は多結晶のSi等からなる厚みが200mm程度のp型の半導体基板1を用意する。この半導体基板1は、例えば、Si等の半導体原料を坩堝で溶解・再固化させて形成されたインゴットをブロック毎に切断し、ワイヤーソー等で薄片状にスライスすることによって得られる。このとき、アルカリ性溶液及び/又は酸性溶液を使用してエッチング処理を行い、入射する太陽光を有効に半導体基板1内に閉じ込めるべく、表面に微小凹凸構造(テクスチャ)を形成する。 First, as shown in FIG. 3A, a p-type semiconductor substrate 1 made of monocrystalline or polycrystalline Si or the like and having a thickness of about 200 mm is prepared. The semiconductor substrate 1 is obtained, for example, by cutting an ingot formed by melting and re-solidifying a semiconductor raw material such as Si in a crucible for each block and slicing it into a thin piece with a wire saw or the like. At this time, an etching process is performed using an alkaline solution and / or an acidic solution, and a minute uneven structure (texture) is formed on the surface in order to effectively confine incident sunlight in the semiconductor substrate 1.
 次いで、図3(b)に示すように、半導体基板1の表面にドナー不純物を拡散させ、p型半導体層1aの表面にn型半導体層1bを形成する。具体的には、拡散させるべきドナー不純物を含有した塗布液をスピンコート法等により膜状に塗布して塗布膜を形成し、熱処理を行って前記ドナー不純物を半導体基板1の表面に拡散させ、厚みが300~500nmのn型半導体層1bを形成する。そしてこれにより、半導体基板1はpn接合を形成する。 Next, as shown in FIG. 3B, donor impurities are diffused on the surface of the semiconductor substrate 1 to form an n-type semiconductor layer 1b on the surface of the p-type semiconductor layer 1a. Specifically, a coating solution containing a donor impurity to be diffused is applied in a film shape by spin coating or the like to form a coating film, and heat treatment is performed to diffuse the donor impurity on the surface of the semiconductor substrate 1, An n-type semiconductor layer 1b having a thickness of 300 to 500 nm is formed. Thereby, the semiconductor substrate 1 forms a pn junction.
 尚、ドナー不純物としては、高濃度にn層化されたn型半導体層1bを形成するものであれば特に限定されないが、通常はPが好んで使用され、塗布液としてはオキシ塩化リン(POCl)が好んで使用される。 The donor impurity is not particularly limited as long as it can form the n-type semiconductor layer 1b having a high concentration of n + layer. However, P is preferably used, and phosphorus oxychloride ( POCl 3 ) is preferably used.
 そして、酸性溶液を使用してエッチングを行い、半導体基板1の端部や裏面に拡散したドナー不純物や表面に形成されたリンケイ酸ガラス等の不純物を除去する。 Etching is then performed using an acidic solution to remove impurities such as donor impurities diffused on the edge and back surface of the semiconductor substrate 1 and phosphosilicate glass formed on the surface.
 次に、プラズマ化学気相成長法(PECVD)等の薄膜形成法を使用し、図3(c)に示すように、窒化ケイ素(SiN)等の絶縁性材料からなる膜厚が70~80nmの反射防止膜2を形成する。 Next, using a thin film formation method such as plasma enhanced chemical vapor deposition (PECVD), as shown in FIG. 3C, the film thickness of an insulating material such as silicon nitride (SiN x ) is 70 to 80 nm. The antireflection film 2 is formed.
 次に、半導体基板1の所定位置にレーザ光を照射し、図3(d)に示すように、内径が50μm~500μm程度の貫通孔7を多数形成する。尚、貫通孔7の形成方法は、レーザ光照射に限定されるものではなく、例えば、ドリル等を使用した機械的方法、エッチング等を使用した化学的方法等、任意の方法で形成することができる。 Next, a predetermined position of the semiconductor substrate 1 is irradiated with laser light, and a large number of through holes 7 having an inner diameter of about 50 μm to 500 μm are formed as shown in FIG. The formation method of the through hole 7 is not limited to the laser beam irradiation, and may be formed by any method such as a mechanical method using a drill or a chemical method using etching or the like. it can.
 次に、図4(e)に示すように、上述した本発明の導電性ペーストを貫通孔7に充填して貫通導体8aを形成し、さらに貫通孔7の周囲にも導電性ペーストを塗布して塗布膜8bを形成する。 Next, as shown in FIG. 4E, the through-hole 7 is formed by filling the above-described conductive paste of the present invention into the through-hole 7, and the conductive paste is applied around the through-hole 7. Thus, the coating film 8b is formed.
 次に、平均粒径が5μmのAl粉末を含有したAlペーストを用意し、更に平均粒径1.5μmのAg粉末を含有したAgペーストを用意する。そして、該Alペーストを前記半導体基板1の裏面全面に塗布し、さらにAgペーストをスクリーン印刷して乾燥させ、図4(f)に示すように、裏面電極用のAl膜9及びAg膜10からなる第1の導電膜(電極パターン)11を形成する。 Next, an Al paste containing Al powder having an average particle diameter of 5 μm is prepared, and further an Ag paste containing Ag powder having an average particle diameter of 1.5 μm is prepared. Then, the Al paste is applied to the entire back surface of the semiconductor substrate 1, and the Ag paste is screen-printed and dried. As shown in FIG. 4 (f), from the Al film 9 and the Ag film 10 for the back electrode. A first conductive film (electrode pattern) 11 is formed.
 次に、上記Agペーストを使用してスクリーン印刷し、図4(g)に示すように、受光面上に所定パターンの第2の導電膜(電極パターン)12を形成する。 Next, screen printing is performed using the Ag paste, and a second conductive film (electrode pattern) 12 having a predetermined pattern is formed on the light receiving surface as shown in FIG.
 そしてこの後、入口から出口まで1~3分で搬送されるベルト式焼成炉を使用し、Alが500℃で焼結し、焼成最高温度が760℃となるような焼成プロファイルで貫通導体8a、塗布膜8b、第1及び第2の導電膜11、12を焼結させる。すると、Al膜9が溶融してp型半導体層1aと合金化してAl-Si層が形成されると共に(図示せず)、Alがアクセプタ不純物としてp型半導体層1a中を拡散し、図4(h)に示すように、高濃度にp層化されたBSF層1cが形成される。そしてこれと同時に、フィンガー電極5a~5nは反射防止膜2をファイヤースルーしてn型半導体層1bと接合され、多数のフィンガー電極5a~5nが並設された受光面電極3、ビア部6a及びバスバー部6bからなる貫通電極6、集電電極4a及び取出電極4bからなる裏面電極4が作製され、これにより太陽電池が形成される。 Then, using a belt-type firing furnace that is conveyed from the entrance to the exit in 1 to 3 minutes, the through conductor 8a has a firing profile such that Al is sintered at 500 ° C. and the maximum firing temperature is 760 ° C. The coating film 8b and the first and second conductive films 11 and 12 are sintered. Then, the Al film 9 is melted and alloyed with the p-type semiconductor layer 1a to form an Al—Si layer (not shown), and Al diffuses as an acceptor impurity in the p-type semiconductor layer 1a. As shown in (h), a high-concentration p + layered BSF layer 1c is formed. At the same time, the finger electrodes 5a to 5n are fired through the antireflection film 2 and joined to the n-type semiconductor layer 1b. The light receiving surface electrode 3, the via portion 6a and the plurality of finger electrodes 5a to 5n arranged in parallel. The back electrode 4 which consists of the penetration electrode 6 which consists of the bus-bar part 6b, the current collection electrode 4a, and the extraction electrode 4b is produced, and a solar cell is formed by this.
 このように上記実施の形態では、半導体基板1の一方の主面に反射防止膜2を形成し、反射防止膜2が形成された半導体基板1に貫通孔7を形成した後、上述した導電性ペーストを貫通孔7に充填して貫通導体8aを形成し、その後焼成処理を行なって半導体基板1に貫通電極6を形成するので、貫通電極6と半導体基板1との界面の絶縁性が良好で貫通電極6のバスバー部6bにインターコネクタ等をはんだ付けしてもはんだ付け性が良好で引張強度等の機械的強度の良好な太陽電池を製造することができる。 As described above, in the above embodiment, the antireflection film 2 is formed on one main surface of the semiconductor substrate 1 and the through hole 7 is formed in the semiconductor substrate 1 on which the antireflection film 2 is formed. Since the through-hole 7 is filled with the paste to form the through-conductor 8a, and then the baking process is performed to form the through-electrode 6 on the semiconductor substrate 1, the insulating property at the interface between the through-electrode 6 and the semiconductor substrate 1 is good. Even if an interconnector or the like is soldered to the bus bar portion 6b of the through electrode 6, a solar cell having good solderability and good mechanical strength such as tensile strength can be manufactured.
 しかも、半導体基板1は、p型半導体層1aの一方の主面にn型半導体層1bが形成されており、反射防止膜2をn型半導体層1bの表面に形成すると共に、p型半導体層1aと貫通電極6とを接合させることにより、貫通孔7とp型半導体層1aとの間にn型半導体層を形成しなくても、貫通電極6を介してn型半導体層1bからp型半導体層1aに電流がリークするのを抑制することができる。したがって、厚みの均一性に欠けるn型半導体層をp型半導体層を囲むように形成する必要もなく、また特許文献1のような分離溝(図8、符号116参照)を形成する必要もなく、簡素な構造及び製法で所望の高い発電効率を有する太陽電池を得ることができる。 Moreover, the semiconductor substrate 1 has an n-type semiconductor layer 1b formed on one main surface of the p-type semiconductor layer 1a, and an antireflection film 2 is formed on the surface of the n-type semiconductor layer 1b. By joining 1a and the penetration electrode 6, even if it does not form an n-type semiconductor layer between the penetration hole 7 and the p-type semiconductor layer 1a, it is p-type from the n-type semiconductor layer 1b via the penetration electrode 6. It is possible to suppress current from leaking to the semiconductor layer 1a. Therefore, it is not necessary to form an n-type semiconductor layer lacking in thickness uniformity so as to surround the p-type semiconductor layer, and it is not necessary to form a separation groove (see FIG. 8, reference numeral 116) as in Patent Document 1. A solar cell having a desired high power generation efficiency can be obtained with a simple structure and manufacturing method.
 また、半導体基板1の他方の主面の貫通孔7の周囲に導電性ペーストを塗布して塗布膜8bを形成し、前記半導体基板1の両主面に第1及び第2の導電膜11、12を形成し、焼成処理で貫通導体8a、塗布膜8b、第1及び第2の導電膜11、12を同時焼成することにより、所望の高い発電効率を有する太陽電池を効率良く得ることができる。 Further, a conductive paste is applied around the through hole 7 on the other main surface of the semiconductor substrate 1 to form a coating film 8b, and the first and second conductive films 11 are formed on both main surfaces of the semiconductor substrate 1. 12 is formed, and the through conductor 8a, the coating film 8b, and the first and second conductive films 11 and 12 are simultaneously fired by firing treatment, whereby a solar cell having a desired high power generation efficiency can be efficiently obtained. .
 尚、本発明は上記実施の形態に限定されるものではない。本発明の導電性ペーストは、貫通孔7とp型半導体層1aとが接触し、分離溝(図8、符号116参照)を不要とする太陽電池について、構造及び製法を簡素化できることから特に有用であるが、特許文献1のようにp型半導体層を囲むようにn型半導体層を形成し、貫通電極とp型半導体層とが接触しないタイプの太陽電池にも適用できる。 The present invention is not limited to the above embodiment. The conductive paste of the present invention is particularly useful because the structure and the manufacturing method can be simplified for a solar cell in which the through-hole 7 and the p-type semiconductor layer 1a are in contact with each other and a separation groove (see FIG. 8, reference numeral 116) is unnecessary. However, the present invention can also be applied to a solar cell in which an n-type semiconductor layer is formed so as to surround a p-type semiconductor layer as in Patent Document 1 and a through electrode and a p-type semiconductor layer are not in contact with each other.
 また、本発明の導電性ペーストは、特に貫通電極形成に好適であるが、裏面電極の取出電極の形成に使用することも可能である。 The conductive paste of the present invention is particularly suitable for forming a through electrode, but can also be used for forming an extraction electrode for a back electrode.
 さらに、上記実施の形態では、半導体基板1は、p型半導体層1a上に薄層のn型半導体層1bが形成されているが、n型半導体層上に薄層のp型半導体層が形成されている場合も、同様に適用できるのはいうまでもない。 Further, in the above embodiment, the semiconductor substrate 1 has the thin n-type semiconductor layer 1b formed on the p-type semiconductor layer 1a, but the thin p-type semiconductor layer is formed on the n-type semiconductor layer. Needless to say, the same can be applied to the case where it is applied.
 次に、本発明の実施例を具体的に説明する。 Next, specific examples of the present invention will be described.
〔導電性ペーストの作製〕
 平均粒径D50が5μmの球形アトマイズAg粉、表1の成分系を有するガラス成分、及び有機ビヒクル、レオロジー調整剤としての脂肪酸アマイド及び脂肪酸(以下、有機ビヒクル及びレオロジー調整剤を総じて「有機ビヒクル等」という。)を用意した。尚、有機ビヒクルは、エチルセルロースとテキサノールとをエチルセルロース:テキサノール=1:9に配合して調製した。
[Preparation of conductive paste]
Spherical atomized Ag powder having an average particle size D 50 of 5 μm, a glass component having the component system shown in Table 1, and an organic vehicle, fatty acid amide and fatty acid as rheology modifiers (hereinafter referred to as “organic vehicle and rheology modifier collectively” Etc.)). The organic vehicle was prepared by blending ethyl cellulose and texanol in ethyl cellulose: texanol = 1: 9.
 尚、表1中、試料番号A~CのV-BaO-ZnOの組成比は、V:76.6重量%、BaO:18.5重量%、ZnO:4.9重量%となるように配合し、試料番号DのV-Fe-BaOの組成比は、V:73.0重量%、Fe:9.2重量%、BaO:17.6重量%となるように配合した。 In Table 1, the composition ratio of V 2 O 5 —BaO—ZnO of sample numbers A to C is as follows: V 2 O 5 : 76.6 wt%, BaO: 18.5 wt%, ZnO: 4.9 wt% The composition ratio of V 2 O 5 —Fe 2 O 3 —BaO of sample number D is V 2 O 5 : 73.0 wt%, Fe 2 O 3 : 9.2 wt%, BaO: 17.6 wt% was blended.
 次いで、これら原料を表1に示す配合量となるように秤量し、プラネタリーミキサーで混合した後、三本ロールミルで混練し、これにより導電性ペーストA~Jを作製した。 Next, these raw materials were weighed so as to have the blending amounts shown in Table 1, mixed with a planetary mixer, and then kneaded with a three-roll mill, thereby producing conductive pastes A to J.
 〔軟化点Tsの測定〕
 各試料に含有されるガラス成分について、TG-DTA(熱重量-示差熱分析装置)を使用して熱分析を行い、軟化点を測定した。すなわち、アルミナ製容器に試料5mgを収容し、標準試料にαアルミナを使用し、流量100mL/分で測定装置内に空気を供給しながら、該測定装置を1分間に20℃上昇するような焼成プロファイルで加熱し、温度に対する重量変化からTG曲線及びDTA曲線を作成した。そして斯かるTG曲線及びDTA曲線から各ガラス材料の軟化点を測定した。
[Measurement of softening point Ts]
The glass component contained in each sample was subjected to thermal analysis using a TG-DTA (thermogravimetric-differential thermal analyzer), and the softening point was measured. That is, 5 mg of a sample is accommodated in an alumina container, α alumina is used as a standard sample, and the measuring apparatus is heated at 20 ° C. per minute while supplying air into the measuring apparatus at a flow rate of 100 mL / min. It heated with the profile and the TG curve and the DTA curve were created from the weight change with respect to temperature. And the softening point of each glass material was measured from such TG curve and DTA curve.
〔結晶化温度Txの測定〕
 各試料に含有されるガラス成分について、軟化点と同一条件で作成したDTA曲線から各ガラス材料の結晶化温度を測定した。
[Measurement of crystallization temperature Tx]
About the glass component contained in each sample, the crystallization temperature of each glass material was measured from the DTA curve created on the same conditions as a softening point.
 表1は試料番号A~Gのペースト組成、ガラス成分種、軟化点Ts、及び結晶化温度Txを示している。 Table 1 shows the paste composition, glass component type, softening point Ts, and crystallization temperature Tx of sample numbers A to G.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 表1に示すように導電性ペーストA~Dは、Vを主成分としたV系ガラス成分を使用しており、本発明範囲内の導電性ペーストである。また、導電性ペーストE~Gは、V以外の成分系のガラス成分を使用しており、本発明範囲外の導電性ペーストである。 As shown in Table 1, the conductive pastes A to D use a V 2 O 5 glass component mainly composed of V 2 O 5 and are conductive pastes within the scope of the present invention. In addition, the conductive pastes E to G use glass components of a component system other than V 2 O 5 and are conductive pastes outside the scope of the present invention.
〔特性評価〕
 図5に示すように、p型のSi系半導体層(以下、「p-Si層」という。)からなる半導体基板12a、及びp-Si層12aの表面にn型のSi系半導体層(以下、「n-Si層」という。)を形成した半導体基板12bを用意し、これら半導体基板12a、12bの表面に所定の電極パターンを作製し、TLM(Transmission Line Model)法により接触抵抗Rcを求めた。
(Characteristic evaluation)
As shown in FIG. 5, a semiconductor substrate 12a composed of a p-type Si-based semiconductor layer (hereinafter referred to as “p-Si layer”) and an n-type Si-based semiconductor layer (hereinafter referred to as “p-Si layer”) are formed on the surface of the p-Si layer 12a. The semiconductor substrate 12b on which the “n-Si layer” is formed) is prepared, predetermined electrode patterns are formed on the surfaces of the semiconductor substrates 12a and 12b, and the contact resistance Rc is obtained by a TLM (Transmission Line Model) method. It was.
 すなわち、横Xが127mm、縦Yが127mm、厚みTが0.2mmの単結晶のp-Si層からなる半導体基板12aを用意した。また、スピンコート法を使用して前記p-Si層の表面にPOClを塗布し、その後熱処理を行ってp-Si層の表面にPを拡散させ、厚みが400μmのn-Si層を有する半導体基板12bを作製した。 That is, a semiconductor substrate 12a made of a single crystal p-Si layer having a width X of 127 mm, a length Y of 127 mm, and a thickness T of 0.2 mm was prepared. Further, POCl 3 is applied to the surface of the p-Si layer by using a spin coating method, and then heat treatment is performed to diffuse P on the surface of the p-Si layer, thereby providing an n-Si layer having a thickness of 400 μm. A semiconductor substrate 12b was produced.
 尚、p-Si層の表面にn-Si層を形成した後、酸性溶液を使用してエッチングを行い、p-Si層の端部や裏面に拡散したPやp-Si層の表面に形成されたリンケイ酸ガラスを除去した。 In addition, after forming an n-Si layer on the surface of the p-Si layer, etching is performed using an acidic solution, and formed on the surface of the P or p-Si layer diffused at the end or back surface of the p-Si layer. Removed phosphosilicate glass.
 次に、各導電性ペーストA~Gを使用して半導体基板12a、12bにスクリーン印刷を行い、半導体基板12a、12bの表面に膜厚20μmの電極パターンを作製した。 Next, screen printing was performed on the semiconductor substrates 12a and 12b using the conductive pastes A to G, and electrode patterns having a thickness of 20 μm were formed on the surfaces of the semiconductor substrates 12a and 12b.
 ここで、電極13aと電極13bとの間の距離L1は200μm、電極13bと電極13cとの間の距離L2は400μm、電極13cと電極13dとの間の距離L3は600μm、電極13dと電極13eとの間の距離L4は800μm、電極13eと電極13fとの間の距離L5は1000μmとし、電極の長さZはいずれも30mmとした。 Here, the distance L1 between the electrode 13a and the electrode 13b is 200 μm, the distance L2 between the electrode 13b and the electrode 13c is 400 μm, the distance L3 between the electrode 13c and the electrode 13d is 600 μm, and the electrode 13d and the electrode 13e. The distance L4 between the electrodes 13e and 13f was 800 μm, the distance L5 between the electrodes 13e and 13f was 1000 μm, and the electrode length Z was 30 mm.
 次いで、各試料を温度150℃に設定したオーブン中に入れて電極13a~13fを乾燥させた。 Next, each sample was placed in an oven set at a temperature of 150 ° C. to dry the electrodes 13a to 13f.
 その後、ベルト式近赤外炉(デスパッチ社製、CDF7210)を使用し、試料が入口~出口間を約1分で搬送するように搬送速度を調整し、大気雰囲気下、最高温度760℃で焼成し、n-Si層の表面に電極13a~13fが形成された試料番号1a~7a、及びp-Si層の表面に電極13a~13fが形成された試料番号1b~7bの試料を作製した。 After that, using a belt-type near-infrared furnace (Despatch, CDF7210), adjusting the transport speed so that the sample is transported from the inlet to the outlet in about 1 minute, and firing at a maximum temperature of 760 ° C. Samples 1a to 7a in which the electrodes 13a to 13f were formed on the surface of the n-Si layer and samples Nos. 1b to 7b in which the electrodes 13a to 13f were formed on the surface of the p-Si layer were prepared.
 次いで、試料番号1~7(1a~7a、1b~7b)の各試料について、TLM法を使用して接触抵抗Rcを求め、絶縁性を評価した。 Next, the contact resistance Rc was obtained for each of the samples Nos. 1 to 7 (1a to 7a, 1b to 7b) using the TLM method, and the insulating property was evaluated.
 このTLM法は、薄膜試料の接触抵抗を評価する方法として広く知られており、伝送線理論を使用し、電極と下層の半導体基板をいわゆる伝送線回路と等価と考えて接触抵抗Rcを算出する。すなわち、電極13a~13fの長さZ、n-Si層又はp-Si層のシート抵抗RSH、電極間距離L、電極間抵抗Rとの間には、数式(1)が成立する。 This TLM method is widely known as a method for evaluating the contact resistance of a thin film sample, and uses the transmission line theory to calculate the contact resistance Rc by regarding the electrode and the underlying semiconductor substrate as equivalent to a so-called transmission line circuit. . That is, Equation (1) is established among the length Z of the electrodes 13a to 13f, the sheet resistance R SH of the n-Si layer or the p-Si layer, the interelectrode distance L, and the interelectrode resistance R.
 R=(L/Z)×RSH+2Rc・・・(1)
 この数式(1)から明らかなように、電極間抵抗Rと電極間距離Lとは直線関係を有する。したがって、電極間距離Ln(n=1~5)における各抵抗Rを測定し、Lを0に外挿することによって2Rcを求め、この2Rcから接触抵抗Rcを算出することができる。
R = (L / Z) × R SH + 2Rc (1)
As is clear from the formula (1), the interelectrode resistance R and the interelectrode distance L have a linear relationship. Therefore, each resistance R at the interelectrode distance Ln (n = 1 to 5) is measured, and 2Rc is obtained by extrapolating L to 0, and the contact resistance Rc can be calculated from this 2Rc.
 そこで、本実施例では、電極間距離Lnにおける各抵抗Rを測定し、試料番号1~7の各試料について接触抵抗Rcを算出し、絶縁性を評価した。 Therefore, in this example, each resistance R at the interelectrode distance Ln was measured, and the contact resistance Rc was calculated for each of the samples Nos. 1 to 7, and the insulation was evaluated.
 尚、シート抵抗RSHは、上記の数式(1)から導き出される直線について、横軸をL、縦軸をRとしたときの傾きから算出することができ、本実施例では30Ω/cmであった。 The sheet resistance R SH can be calculated from the slope of the straight line derived from the above equation (1) with L as the horizontal axis and R as the vertical axis. In this embodiment, the sheet resistance R SH is 30 Ω / cm. It was.
 次に、上述と同様、横Xが127mm、縦Yが127mm、厚みTが0.2mmの単結晶のp型のSi系半導体基板を別途用意した。 Next, similarly to the above, a single-crystal p-type Si-based semiconductor substrate having a horizontal X of 127 mm, a vertical Y of 127 mm, and a thickness T of 0.2 mm was separately prepared.
 次いで、試料番号A~Gの導電性ペーストを使用し、半導体基板にスクリーン印刷を行い、横123mm、縦123mm、厚み20μmの塗布膜を形成した。そしてその後は上述と同様の方法・手順で焼成処理を行い、半導体基板上に貫通電極のバスバー部を模した電極を形成し、試料番号1c~7cの試料を作製した。 Next, using conductive pastes of sample numbers A to G, screen printing was performed on the semiconductor substrate to form a coating film having a width of 123 mm, a length of 123 mm, and a thickness of 20 μm. Thereafter, a baking process was performed in the same manner and procedure as described above to form an electrode simulating the bus bar portion of the through electrode on the semiconductor substrate, and samples Nos. 1c to 7c were produced.
 次に、コテ先温度を400℃に設定したはんだコテを使用し、Sn-Ag-Cuはんだめっき線(日立電線ファインテック(株)製SSA-TPS 0.16×2.0)を前記電極にはんだ付けし、前記はんだめっき線を45°の角度で引っ張って引張試験を行い、機械的強度を評価した。 Next, using a soldering iron whose tip temperature is set to 400 ° C., Sn—Ag—Cu solder plating wire (SSA-TPS 0.16 × 2.0 manufactured by Hitachi Cable Finetech Co., Ltd.) is used as the electrode. After soldering, the solder plating wire was pulled at an angle of 45 ° to conduct a tensile test, and mechanical strength was evaluated.
 表2は、試料番号1~7(1a~7a、1b~7b、1c~7c)の導電性ペースト種、n-Si層、p-Si層の各接触抵抗Rc、及び引張強度の試験結果、並びに総合評価を示している。 Table 2 shows test results of conductive paste types of sample numbers 1 to 7 (1a to 7a, 1b to 7b, 1c to 7c), contact resistance Rc of n-Si layer and p-Si layer, and tensile strength, The overall evaluation is also shown.
 ここで、n-Si層上の接触抵抗Rcは30Ω以上を良品、30Ω未満を不良品と判断し、p-Si層上の接触抵抗Rcは10000Ω以上を良品、10000Ω未満を不良品と判断した。 Here, the contact resistance Rc on the n-Si layer was determined to be 30 Ω or higher as a non-defective product, and the contact resistance Rc on the p-Si layer was determined to be 10000 Ω or higher as a non-defective product. .
 また、引張強度については、3N以上、かつ、半導体基板が破壊してしまったものを良品(○)と判断し、その他の場合、すなわち、電極と半導体基板との間が破壊するか、又ははんだ濡れ性が悪く、電極とはんだめっき線界面で剥離した場合は不良品(×)と判断した。 As for the tensile strength, 3N or more and the semiconductor substrate destroyed is judged as a non-defective product (◯), and in other cases, that is, between the electrode and the semiconductor substrate is broken, or solder When the wettability was poor and peeling occurred at the interface between the electrode and the solder plating wire, it was judged as a defective product (x).
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
 試料番号5は、十分な接触抵抗Rcを得ることはできなかった。これは導電性ペーストEに含有されるガラス成分の軟化点が540℃と高く、流動性に劣る上に、電気伝導性にも劣るためと考えられる。したがって、導電性ペーストEでは、十分な絶縁性を確保できず、漏れ電流を抑制するのは困難である。しかも、この試料番号5は、引張強度も劣り、はんだ付け性や機械的強度にも劣ることが分かった。 Sample No. 5 could not obtain a sufficient contact resistance Rc. This is probably because the softening point of the glass component contained in the conductive paste E is as high as 540 ° C., which is inferior in fluidity and inferior in electrical conductivity. Therefore, with the conductive paste E, sufficient insulation cannot be secured, and it is difficult to suppress the leakage current. Moreover, it was found that Sample No. 5 was inferior in tensile strength and inferior in solderability and mechanical strength.
 試料番号6、7も、試料番号5と同様、導電性ペーストF、Gに含有されるガラス成分の軟化点が524~580℃と高く、流動性に劣る上に、電気伝導性にも劣り、このため接触抵抗Rcも低く、十分な絶縁性を確保するのは困難である。また、この試料番号6、7も、試料番号5と同様、引張強度にも劣り、はんだ付け性や機械的強度にも劣ることが分かった。 Sample Nos. 6 and 7 also have the same softening point as 524 to 580 ° C. of the glass component contained in the conductive pastes F and G, which is inferior in fluidity and inferior in electrical conductivity, as in Sample No. 5. For this reason, the contact resistance Rc is also low, and it is difficult to ensure sufficient insulation. Moreover, it turned out that these sample numbers 6 and 7 are also inferior in tensile strength similarly to sample number 5, and inferior also in solderability and mechanical strength.
 これに対し試料番号1~4は、ガラス成分としてV系ガラス材料を含有しているので、軟化点Tsは310~430℃と低く、いずれも焼成処理(熱処理)でガラス成分が結晶化することから、電気伝導性もより一層向上し、接触抵抗Rcはn-Si層上で40Ω以上、p-Si層上で27000Ω以上と高くなった。したがって、これら導電性ペーストA~Dを貫通電極形成用に使用しても、n-Si層から貫通電極を経てp-Si層にリークする漏れ電流を抑制でき、発電効率を向上させることができると考えられる。 On the other hand, sample numbers 1 to 4 contain a V 2 O 5 glass material as a glass component, so the softening point Ts is as low as 310 to 430 ° C., and the glass component is crystallized by firing treatment (heat treatment). Therefore, the electrical conductivity was further improved, and the contact resistance Rc was as high as 40Ω or more on the n-Si layer and 27000Ω or more on the p-Si layer. Therefore, even when these conductive pastes A to D are used for forming a through electrode, leakage current leaking from the n-Si layer to the p-Si layer through the through electrode can be suppressed, and the power generation efficiency can be improved. it is conceivable that.
 また、この試料番号1~4は、引張強度も良好で優れたはんだ付け性と機械的強度が得られることが分かった。これは、導電性ペーストA~Dではいずれもガラス成分が焼成処理により結晶化しているので、結晶化後にはガラス成分の流動性が低下し、その結果、電極表面にガラスが浮き上がるのを抑制できたためと思われる。 Further, it was found that Sample Nos. 1 to 4 had good tensile strength and excellent solderability and mechanical strength. This is because, in all of the conductive pastes A to D, the glass component is crystallized by the baking treatment, so that the fluidity of the glass component is reduced after crystallization, and as a result, the glass can be prevented from floating on the electrode surface. It seems that it was because of
〔導電性ペーストの作製〕
 実施例1と同様、平均粒径D50が5μmの球形アトマイズAg粉及び有機ビヒクル等を用意し、さらに表3の組成比を有するガラス成分を用意した。尚、有機ビヒクルは、実施例1と同様、エチルセルロースとテキサノールとをエチルセルロース:テキサノール=1:9に配合して調製した。
[Preparation of conductive paste]
As in Example 1, spherical atomized Ag powder having an average particle size D 50 of 5 μm, an organic vehicle, and the like were prepared, and further glass components having the composition ratios shown in Table 3 were prepared. The organic vehicle was prepared by blending ethyl cellulose and texanol into ethyl cellulose: texanol = 1: 9 as in Example 1.
 次いで、これら原料をAg粉:80重量%、ガラス成分:10重量%、有機ビヒクル等:10重量%となるように秤量し、プラネタリーミキサーで混合した後、三本ロールミルで混練し、これにより試料番号11~16の導電性ペーストを作製した。 Next, these raw materials are weighed so that Ag powder: 80% by weight, glass component: 10% by weight, organic vehicle, etc .: 10% by weight, mixed with a planetary mixer, and then kneaded with a three-roll mill. Conductive pastes of sample numbers 11 to 16 were prepared.
 尚、試料番号11は、実施例1で使用した導電性ペーストA~Cと同一組成であり、試料番号12は、実施例1で使用した導電性ペーストDと同一の組成である。 Sample No. 11 has the same composition as the conductive pastes A to C used in Example 1, and Sample No. 12 has the same composition as the conductive paste D used in Example 1.
〔特性評価〕
 図6に示すように、まず、p型のSi系半導体基板(以下、「p-Si基板」という。)15の一方の主面にフィンガー電極及びバスバー電極が形成されるように上記導電性ペーストをスクリーン印刷して乾燥した。次いで、該p-Si基板15の他方の主面全域にAlペーストをスクリーン印刷し、乾燥させた。そしてその後、実施例1と同様、ベルト式近赤外炉を使用して焼成し、p-Si基板15の一方の主面に表面電極16を形成し、かつ該p-Si基板15の他方の主面に裏面電極17を形成し、これにより試料番号11~16の試料を作製した。
(Characteristic evaluation)
As shown in FIG. 6, first, the conductive paste is formed so that finger electrodes and bus bar electrodes are formed on one main surface of a p-type Si-based semiconductor substrate (hereinafter referred to as “p-Si substrate”) 15. The screen was printed and dried. Next, an Al paste was screen printed over the other main surface of the p-Si substrate 15 and dried. Thereafter, as in Example 1, firing is performed using a belt-type near-infrared furnace to form a surface electrode 16 on one main surface of the p-Si substrate 15, and the other of the p-Si substrate 15. A back electrode 17 was formed on the main surface, thereby preparing samples Nos. 11 to 16.
 そして、試料番号11~16の各試料について、セルテスター(NPC社製、NCT-180AA-M)を使用し、表面電極16と裏面電極17との間に-10~+10Vの電圧を印加し、電流値を測定し、電流-電圧曲線(以下、「I-V曲線」という。)を得た。 Then, for each of the samples Nos. 11 to 16, a cell tester (NPC, NCT-180AA-M) was used, and a voltage of −10 to +10 V was applied between the front electrode 16 and the rear electrode 17, The current value was measured to obtain a current-voltage curve (hereinafter referred to as “IV curve”).
 図7は、I-V曲線の一例を示す図であり、横軸が電圧V(V)、縦軸が電流I(A)である。 FIG. 7 is a diagram showing an example of an IV curve, in which the horizontal axis represents voltage V (V) and the vertical axis represents current I (A).
 図中、第1象限の曲線は、順方向バイアス、すなわち、p-Si基板15に正電圧を印加した場合の電流特性であり、p-Si基板15から表面電極16に流れる電流を示している。 In the figure, the curve in the first quadrant is a forward bias, that is, a current characteristic when a positive voltage is applied to the p-Si substrate 15, and indicates a current flowing from the p-Si substrate 15 to the surface electrode 16. .
 一方、第3象限の曲線は、逆方向バイアス、すなわち、表面電極16に正電圧を印加した場合の電流特性であり、表面電極16からp-Si基板15に流れる電流を示している。 On the other hand, the curve in the third quadrant is the reverse bias, that is, the current characteristic when a positive voltage is applied to the surface electrode 16, and shows the current flowing from the surface electrode 16 to the p-Si substrate 15.
 そして、逆方向バイアスを示す第3象限において、表面電極16からp-Si基板15への電流が流れ難い程、表面電極16(貫通電極)からp-Si基板15への漏れ電流が小さいことを表す。 In the third quadrant indicating the reverse bias, the leakage current from the surface electrode 16 (through electrode) to the p-Si substrate 15 is smaller as the current from the surface electrode 16 to the p-Si substrate 15 is less likely to flow. To express.
 したがって、逆方向バイアスを印加した場合に急激に電流が流れるまでのI-V曲線の接線Sの勾配を算出し、この勾配の逆数を求め、これを微分抵抗とした。 Therefore, when the reverse bias is applied, the slope of the tangent S of the IV curve until the current flows suddenly is calculated, the reciprocal of this slope is obtained, and this is used as the differential resistance.
 また、試料番号11~16の各試料について、実施例1と同様の方法・手順ではんだ付け性を評価した。 Further, the solderability of each sample Nos. 11 to 16 was evaluated by the same method and procedure as in Example 1.
 表3は、試料番号11~16の各試料のガラス組成、微分抵抗、及びはんだ付け性を示している。 Table 3 shows the glass composition, differential resistance, and solderability of each sample Nos. 11 to 16.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
 この表3から明らかなように、試料番号14は、ガラス成分中のVの含有量が、34.6重量%であり、主成分といわれる程、多くのVが含有されておらず、このためはんだ付け性に劣り、微分抵抗も0.49Ωと小さかった。 As is apparent from Table 3, Sample No. 14 has a V 2 O 5 content of 34.6% by weight in the glass component, and contains so much V 2 O 5 that it is said to be a main component. Therefore, the solderability was inferior, and the differential resistance was as small as 0.49Ω.
 これに対し試料番号11~13、15、及び16は、ガラス成分中のVの含有量が、50重量%以上であり、ガラス成分はVを主成分としていることから、はんだ付け性が良好で、微分抵抗も0.70Ω以上となった。 In contrast, Sample Nos. 11 to 13, 15, and 16 have a V 2 O 5 content of 50% by weight or more in the glass component, and the glass component contains V 2 O 5 as a main component. The solderability was good and the differential resistance was 0.70Ω or higher.
 特に、ガラス成分中のVの含有量が、70重量%以上の試料番号11~13は、はんだ付け性が良好な上に微分抵抗も5.45~46.42Ωとなって、漏れ電流のより一層の抑制が可能なことが分かった。 In particular, Sample Nos. 11 to 13 with a V 2 O 5 content of 70% by weight or more in the glass component have good solderability and a differential resistance of 5.45 to 46.42Ω, which is a leak. It has been found that the current can be further suppressed.
 図8は、ガラス成分中のVの含有量と微分抵抗との関係を示す図であり、横軸がVの含有量(重量%)、縦軸が微分抵抗(Ω)を示している。 FIG. 8 is a diagram showing the relationship between the content of V 2 O 5 in the glass component and the differential resistance, where the horizontal axis is the content (% by weight) of V 2 O 5 and the vertical axis is the differential resistance (Ω). Is shown.
 この図8から明らかなように、Vのガラス成分中の含有量が70重量%を超えると、微分抵抗が3Ωを超えて大きくなり、漏れ電流をより効果的に抑制できることが分かる。 As is apparent from FIG. 8, when the content of V 2 O 5 in the glass component exceeds 70% by weight, the differential resistance increases beyond 3Ω, and the leakage current can be suppressed more effectively.
〔導電性ペーストの作製〕
 リン酸系化合物として、Ag、AgPO、Zn、MnPO、及びZrWO(POを用意した。また、実施例2の試料番号11と同一の組成を有するガラス成分、及び実施例1と同様の球形アトマイズAg粉、及び有機ビヒクル等を用意した。
[Preparation of conductive paste]
As phosphoric acid compounds, Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 (PO 4 ) 2 were prepared. Moreover, the glass component which has the same composition as the sample number 11 of Example 2, the spherical atomization Ag powder similar to Example 1, an organic vehicle, etc. were prepared.
 次いで、これら原料をAg:80重量%、ガラス成分:8重量%、リン酸系化合物:2重量%:有機ビヒクル等:10重量%となるように秤量し、プラネタリーミキサーで混合した後、三本ロールミルで混練し、これにより試料番号21~25の導電性ペーストを作製した。 Next, these raw materials were weighed so that Ag: 80% by weight, glass component: 8% by weight, phosphoric acid compound: 2% by weight: organic vehicle, etc .: 10% by weight, and mixed with a planetary mixer. The conductive paste of sample numbers 21 to 25 was produced by kneading with this roll mill.
 また、比較例として、Ag:80重量%、ガラス成分:10重量%、有機ビヒクル等:10重量%となるように秤量し、プラネタリーミキサーで混合した後、三本ロールミルで混練し、これによりリン酸系化合物を含有しない試料番号26の導電性ペーストを作製した。 Further, as a comparative example, Ag: 80% by weight, glass component: 10% by weight, organic vehicle, etc .: 10% by weight are weighed, mixed with a planetary mixer, then kneaded with a three roll mill, A conductive paste of Sample No. 26 containing no phosphoric acid compound was prepared.
〔特性評価〕
 試料番号21~26の導電性ペーストを使用し、実施例1と同様の方法・手順で、p-Si層及びn-Si層を有する半導体基板の表面に所定の電極パターンを作製し、TLM法によりn-Si層及びp-Si層の各接触抵抗Rc、はんだ付け性、及び引張強度を求めた。
(Characteristic evaluation)
A predetermined electrode pattern was prepared on the surface of a semiconductor substrate having a p-Si layer and an n-Si layer by using the conductive paste of sample numbers 21 to 26 in the same manner and procedure as in Example 1, and the TLM method Thus, the contact resistance Rc, solderability, and tensile strength of the n-Si layer and the p-Si layer were determined.
 表4は、その測定結果を示している。 Table 4 shows the measurement results.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
 この表4から明らかなように試料番号21~26のいずれにおいても、良好なはんだ付け性と引張強度を得ることができた。 As is clear from Table 4, good solderability and tensile strength could be obtained in any of the sample numbers 21 to 26.
 また、接触抵抗Rcについては、n-Si層ではリン酸系化合物を含有させた試料番号21~25とリン酸系化合物を含有させなかった試料番号26とで、略同程度であったが、p-Si層ではリン酸系化合物を含有させた試料番号21~25は、リン酸系化合物を含有させなかった試料番号26に比べ、大幅に上昇しており、絶縁性が向上することが分かった。 Further, the contact resistance Rc was substantially the same in the sample numbers 21 to 25 containing the phosphate compound in the n-Si layer and in the sample number 26 not containing the phosphate compound. In the p-Si layer, the sample numbers 21 to 25 containing the phosphoric acid compound are significantly higher than the sample number 26 not containing the phosphoric acid compound, indicating that the insulation is improved. It was.
 図9は、試料番号25におけるp-Si層側半導体基板の断面をSEM(走査型電子顕微鏡)で撮像したSEM像である。 FIG. 9 is a SEM image obtained by imaging the cross section of the p-Si layer side semiconductor substrate of sample number 25 with a SEM (scanning electron microscope).
 この図9から分かるように、Ag粒子の外周表面にP濃度の高い絶縁層が形成されており、斯かる絶縁層が形成されたことにより、高い絶縁性が得られたものと思われる。 As can be seen from FIG. 9, an insulating layer having a high P concentration is formed on the outer peripheral surface of the Ag particles, and it is considered that high insulating properties are obtained by forming such an insulating layer.
〔導電性ペーストの作製〕
 アトマイズ法又は湿式還元法を使用し、結晶子径が70~125nm、平均粒径D50が1.5~5.0μmのAg粉を作製した。尚、このAg粉の平均粒径は、レーザー回折法におけるマイクロトラックを使用して測定した。
[Preparation of conductive paste]
Using an atomizing method or a wet reduction method, an Ag powder having a crystallite size of 70 to 125 nm and an average particle size D 50 of 1.5 to 5.0 μm was prepared. In addition, the average particle diameter of this Ag powder was measured using the microtrack in a laser diffraction method.
 また、実施例2の試料番号11と同一の組成を有するガラス成分、及び実施例1と同様の有機ビヒクル等を用意した。 Further, a glass component having the same composition as that of Sample No. 11 in Example 2, an organic vehicle similar to that in Example 1, and the like were prepared.
 次いで、これら原料をAg:80重量%、ガラス成分:10重量%、有機ビヒクル等:10重量%となるように秤量し、プラネタリーミキサーで混合した後、三本ロールミルで混練し、これにより試料番号31~36の導電性ペーストを作製した。 Next, these raw materials are weighed so that Ag: 80% by weight, glass component: 10% by weight, organic vehicle, etc .: 10% by weight, mixed with a planetary mixer, then kneaded with a three-roll mill, and thereby a sample Conductive pastes with numbers 31 to 36 were produced.
〔特性評価〕
 試料番号31~36の導電性ペーストを使用し、実施例1と同様の方法・手順で、p-Si層及びn-Si層を有する半導体基板の表面に所定の電極パターンを作製し、TLM法によりn-Si層及びp-Si層の各接触抵抗Rc、はんだ付け性、及び引張強度を求めた。
(Characteristic evaluation)
A predetermined electrode pattern was prepared on the surface of the semiconductor substrate having the p-Si layer and the n-Si layer by using the conductive paste of sample numbers 31 to 36 in the same manner and procedure as in Example 1, and the TLM method Thus, the contact resistance Rc, solderability, and tensile strength of the n-Si layer and the p-Si layer were determined.
 表5は、その測定結果を示している。 Table 5 shows the measurement results.
Figure JPOXMLDOC01-appb-T000005
Figure JPOXMLDOC01-appb-T000005
 この表5から明らかなように試料番号31~36のいずれにおいても、良好なはんだ付け性と引張強度を得ることができた。 As apparent from Table 5, good solderability and tensile strength could be obtained in any of the sample numbers 31 to 36.
 また、接触抵抗Rcについても、n-Si層では50~56Ωと良好な結果が得られ、さらにp-Si層でも30000~170000Ωの良好な結果が得られることが分かった。これは、Ag粉の結晶子径が70nm以上と大きいため、電極が過剰に収縮することもないことから、高い接触抵抗が得られたものと思われる。 As for the contact resistance Rc, it was found that a good result of 50 to 56Ω was obtained for the n-Si layer, and a good result of 30000 to 170000Ω was obtained for the p-Si layer. This is probably because the Ag powder has a large crystallite diameter of 70 nm or more, and the electrode does not shrink excessively, so that a high contact resistance is obtained.
 貫通電極と半導体基板との間の絶縁性が良好で高い発電効率を得ることができ、また、バスバー部のはんだ付け性や引張強度等の機械的特性にも優れたMWT構造の太陽電池を得ることができる。 A solar cell having an MWT structure in which insulation between the through electrode and the semiconductor substrate is good and high power generation efficiency can be obtained, and in addition, mechanical properties such as solderability and tensile strength of the bus bar portion are obtained. be able to.
 1 半導体基板
 1a p型半導体層
 1b n型半導体層
 6 貫通電極
 7 貫通孔
 8a 貫通導体
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a p-type semiconductor layer 1b n-type semiconductor layer 6 Through electrode 7 Through hole 8a Through conductor

Claims (10)

  1.  太陽電池の電極を形成するための導電性ペーストであって、
     導電性粉末と、ガラス成分と、有機ビヒクルとを含有し、
     かつ、前記ガラス成分は、V酸化物を主成分としたV酸化物系材料で形成されていることを特徴とする導電性ペースト。
    A conductive paste for forming a solar cell electrode,
    Containing conductive powder, glass component, and organic vehicle,
    And the said glass component is formed with the V oxide type material which has V oxide as a main component, The electrically conductive paste characterized by the above-mentioned.
  2.  前記ガラス成分中のVの含有量は、酸化物に換算し重量比率で70重量%以上であることを特徴とする請求項1記載の導電性ペースト。 2. The conductive paste according to claim 1, wherein the content of V in the glass component is 70% by weight or more in terms of weight ratio in terms of oxide.
  3.  前記ガラス成分の含有量は、5~15重量%であることを特徴とする請求項1又は請求項2記載の導電性ペースト。 3. The conductive paste according to claim 1, wherein the content of the glass component is 5 to 15% by weight.
  4.  前記ガラス成分は、熱処理で結晶化されることを特徴とする請求項1乃至請求項3のいずれかに記載の導電性ペースト。 The conductive paste according to any one of claims 1 to 3, wherein the glass component is crystallized by heat treatment.
  5.  リン酸系化合物が含有されていることを特徴とする請求項1乃至請求項4のいずれかに記載の導電性ペースト。 The conductive paste according to any one of claims 1 to 4, wherein a phosphoric acid compound is contained.
  6.  前記リン酸系化合物は、Ag、AgPO、Zn、MnPO、及びZrWO(POの群から選択された少なくとも1種を含むことを特徴とする請求項5記載の導電性ペースト The phosphoric acid compound is at least one selected from the group consisting of Ag 4 P 2 O 5 , Ag 3 PO 4 , Zn 2 P 2 O 7 , Mn 2 PO 4 , and Zr 2 WO 4 (PO 4 ) 2. The conductive paste according to claim 5, comprising:
  7.  前記導電性粉末は、結晶子径が70nm以上であることを特徴とする請求項1乃至請求項6のいずれかに記載の導電性ペースト。 The conductive paste according to any one of claims 1 to 6, wherein the conductive powder has a crystallite diameter of 70 nm or more.
  8.  前記導電性粉末は、アトマイズ法で作製されたアトマイズ粉を含むことを特徴とする請求項1乃至請求項7のいずれかに記載の導電性ペースト。 The conductive paste according to any one of claims 1 to 7, wherein the conductive powder includes atomized powder produced by an atomizing method.
  9.  前記導電性粉末が、Agを主成分としていることを特徴とする請求項1乃至請求項8のいずれかに記載の導電性ペースト。 The conductive paste according to any one of claims 1 to 8, wherein the conductive powder contains Ag as a main component.
  10.  基板に貫通孔を形成した後、請求項1乃至請求項9のいずれかに記載の導電性ペーストを前記貫通孔に充填して貫通導体を形成し、その後焼成処理を行なって前記基板に貫通電極を形成することを特徴とする貫通電極の製造方法。 After the through hole is formed in the substrate, the conductive paste according to any one of claims 1 to 9 is filled into the through hole to form a through conductor, and then a baking process is performed to form a through electrode on the substrate. Forming a through electrode.
PCT/JP2012/078975 2011-11-10 2012-11-08 Conductive paste and method for producing through electrode WO2013069727A1 (en)

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CN103594529A (en) * 2013-11-27 2014-02-19 奥特斯维能源(太仓)有限公司 MWT and passivation combined crystal silicon solar cell and manufacturing method thereof
CN104538461A (en) * 2015-01-16 2015-04-22 浙江晶科能源有限公司 MWT solar energy battery piece
WO2017204422A1 (en) * 2016-05-25 2017-11-30 알무스인터내셔널 주식회사 Solar cell and manufacturing method therefor
CN116722079A (en) * 2023-08-09 2023-09-08 浙江晶科能源有限公司 Solar cell manufacturing method, solar cell and photovoltaic module

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JPH11329072A (en) * 1998-05-13 1999-11-30 Murata Mfg Co Ltd Conductive paste and solar battery using the same
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CN103594529A (en) * 2013-11-27 2014-02-19 奥特斯维能源(太仓)有限公司 MWT and passivation combined crystal silicon solar cell and manufacturing method thereof
CN104538461A (en) * 2015-01-16 2015-04-22 浙江晶科能源有限公司 MWT solar energy battery piece
WO2017204422A1 (en) * 2016-05-25 2017-11-30 알무스인터내셔널 주식회사 Solar cell and manufacturing method therefor
CN116722079A (en) * 2023-08-09 2023-09-08 浙江晶科能源有限公司 Solar cell manufacturing method, solar cell and photovoltaic module
CN116722079B (en) * 2023-08-09 2024-05-28 浙江晶科能源有限公司 Solar cell manufacturing method, solar cell and photovoltaic module

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