WO2013052054A1

WO2013052054A1 - System and method for providing bi-directional power flow and power conditioning

Info

Publication number: WO2013052054A1
Application number: PCT/US2011/055088
Authority: WO
Inventors: John Victor VELIADIS
Original assignee: Northrop Grumman Systems Corporation
Priority date: 2011-10-06
Filing date: 2011-10-06
Publication date: 2013-04-11

Abstract

A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a system that comprises a first normally-on junction field-effect transistor (JFET) having a drain that forms a first coupling node and a first normally-off semiconductor transistor having a drain coupled to a source of the first normally-on JFET and a source coupled to a gate of the first normally-on JFET, wherein a high voltage on the first coupling node provides a negative voltage on the gate of the first normally-on JFET resulting in blocking of the high voltage and mitigating power flow through the normally-on JFET and normally-off semiconductor transistor.

Description

SYSTEM AND METHOD FOR PROVIDING BI-DIRECTIONAL POWER FLOW AND

POWER CONDITIONING

[0001] The invention was made under a contract with an agency of the United States Government, contract number W91 1 NF-06-2-0002.

BACKGROUND

[0002] Inverters/rectifiers and DC/DC converters critical for supporting high- power, high-voltage systems, such as hybrid-electric ground vehicle propulsion systems, typically operate between two high voltage busses with bi-directional power flow of up to hundreds of kilowatts. To prevent system damage during fault conditions, bi-directional fault isolation, or power conditioning, is needed. Because mechanical contactors do not provide adequate actuation times and suffer severe degradation during repeated fault isolation, a solid-state circuit breaker (SSCB) is desirable.

[0003] To provide such a SSCB, and to enable such bi-directional power flow in a semiconductor device, the device should provide symmetric current flow in forward and reverse directions and blocking of a specified voltage in forward and reverse directions. In addition, the gate-drive of the bi-directional circuit should operate at high current-gain and high bandwidth with low conduction losses, should allow for fast switching, and should have small physical size, all of which contribute to the bidirectional circuit's efficiency.

SUMMARY

[0004] In accordance with an aspect of the present invention, a system is provided for providing bi-directional power flow and power conditioning for high- voltage applications. The system comprises a first normally-on junction field-effect transistor (JFET) having a drain that forms a first coupling node and a first normally- off semiconductor transistor having a drain coupled to a source of the first normally- on JFET and a source coupled to a gate of the first normally-on JFET, wherein a high voltage on the first coupling node provides a negative voltage on the gate of the first normally-on JFET resulting in blocking of the high voltage (pinching off) and mitigating power flow through the normally-on JFET and normally-off semiconductor transistor. The system further comprises a gate drive coupled to a gate of the first normally-off semiconductor transistor, the gate drive being configured to selectively bias the first normally-off semiconductor transistor so that the system allows current to flow bi-directionally between the first coupling node and the source of the first normally-off semiconductor transistor, or so that the system blocks voltages from the first coupling node to the source of the first normally-off semiconductor transistor.

[0005] In accordance with another aspect of the invention, another system is provided for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. The system comprises a first cascode comprising a first normally-on JFET and a first normally-off semiconductor transistor. The first normally-on JFET has a drain that is a first coupling node and a source coupled to a drain of the first normally-off semiconductor transistor. The system also comprises a second cascode comprising a second normally-off semiconductor transistor and a second normally-on JFET. The second normally-off semiconductor transistor has a drain node that is coupled to a source node of the second normally- on JFET. The second normally-on JFET has a drain node that is a second coupling node, wherein sources of the first and second normally-off semiconductor transistors are shorted together at a common point S. The system also comprises a gate drive that applies a voltage bias (V_G) to both the first and second normally-off

semiconductor transistors, the gate drive being configured to selectively bias V_G so that the system allows current to flow bi-directionally between the first coupling node and the second coupling node, or so that the system blocks voltages applied to the first coupling node or the second coupling node.

[0006] In accordance with yet another aspect of the invention, a method is provided for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. The method comprises providing a first and second back- to-back connected cascode being driven by a single gate-drive. Each of the first and second cascodes having a normally-on JFET coupled to a normally-off

semiconductor transistor with the normally-off semiconductor transistors of each of the first and second cascodes sharing a common source terminal and with each of the normally-on JFETs of the first and second cascodes providing respective first and second coupling terminals. The method further comprises selectively applying a voltage bias (V_G) from the gate drive to gates of both the normally-off semiconductor transistors of the first and second cascodes. The voltage bias is below the built-in- potential of the gate-to-source pn junctions of the normally-off semiconductor transistors, and is such that current can flow bi-directionally between the first coupling node and the second coupling node.

DESCRIPTION OF THE DRAWINGS

[0007] The detailed description will refer to the following drawings, and wherein:

[0008] Figure 1 is a partial cross-sectional diagram illustrating an embodiment of a high-voltage silicon carbide vertical channel junction field effect transistor (JFET).

[0009] Figure 2 is a graph illustrating forward gate-to-source and gate-to-drain voltage bias characteristics of a SiC JFET.

[0010] Figure 3 is a graph illustrating transistor electrical characteristic curves of a normally-on SiC JFET and a normally-off SiC JFET.

[0011] Figure 4 is an embodiment of a schematic of a cascode switch and its constituent JFETs.

[0012] Figure 5 is a diagram illustrating an embodiment of a system for providing symmetric, efficient bi-directional power flow.

[0013] Figure 6 is a flowchart illustrating an embodiment of a method for providing symmetric, efficient bi-directional power flow.

DETAILED DESCRIPTION

[0014] System and methods are provided for providing bi-directional power flow and conditioning. The systems and methods provide a gate biasing and settings topology for efficient and symmetrical bidirectional power conditioning using a pair of normally-off semiconductor transistor / normally-on junction field-effect-transistor (JFET) cascode switches. Bidirectional power flow requires symmetric current flow in forward and reverse directions and blocking of a specified voltage in forward and reverse directions. Additionally, the gate-drive needs to operate at high current-gain to contribute to its efficiency. The systems and methods provide bias settings for efficient and symmetrical normally-off bidirectional power conditioning using two back-to-back connected wide-bandgap cascodes, being driven by a single gate- drive. Each cascode will include a normally-on JFET coupled to a normally-off semiconductor transistor with the normally-off semiconductor transistors of each cascode sharing a common source terminal. The normally-off semiconductor transistor provides the desired normally-off condition, while the normally-on JFET provides the desired high voltage protection. The normally-off semiconductor transistors are chosen from a list that includes JFETs, MOSFETs and BJTs.

[0015] Silicon carbide (SiC) and gallium nitride (GaN) are typically excellent materials for bi-directional power conditioning since they can block high voltages with relatively low associated conduction and switching losses. Several SiC power devices are candidates for bi-directional power conditioning, such as SiC bipolar junction transistors (BJTs), SiC metal oxide semiconductor field effect transistors (MOSFETs), lateral-channel vertical junction field-effect-transistors (LC-JFETs), and vertical-channel junction-field-effect-transistors (VJFETs).

[0016] SiC BJTs currently suffer from forward voltage degradation (which is a reliability issue) and have a relatively low current-gain that complicates and increases the size of the gate drive. Also, SiC BJT current-gain deteriorates with temperature, limiting operation to below 200 ^QC. SiC MOSFETs suffer from low mobility and reliability stemming from their native gate oxides. SiC MOSFET operation is limited to -200 ^QC due to its native gate oxide instability and its threshold-voltage-shift. SiC vertical-channel JFETs are ideal candidates for bidirectional power flow applications as they have low switching and conduction losses, are relatively easy to fabricate, and can operate at temperatures in excess of 300 °-C.

[0017] Embodiments of a system and method for providing symmetric, efficient bidirectional power flow and power conditioning are described herein. Embodiments provide a more energy efficient system for bi-directional power flow that can operate at high temperatures, such as at 300 ^QC, high frequencies, high current-gain, and has no native gate-oxide or forward-voltage degradation reliability concerns.

Embodiments may include back-to-back connected SiC based cascodes, with specified biasing settings, to provide efficient and symmetrical bi-directional power flow and power conditioning. Each SiC JFET cascode will include a normally-on JFET coupled to a normally-off semiconductor transistor with the normally-off semiconductor transistors of each cascode sharing a common source terminal.

Such embodiments provide a SSCB that overcomes problems described above. JFETs do not have native gate-oxide or forward-voltage degradation reliability concerns, have been operated in excess of 300 ^QC and can be operated at high- current gain. It is to be appreciated that the present examples will be illustrated with respect to a SSCB that employs vertical SiC JFETs. However, other types of JFETs and semiconductor transistors and other types of semiconductor material may be employed in accordance with various embodiments of the present invention.

Although certain embodiments of a system and method for providing symmetric, efficient bi-directional power flow and power conditioning discussed below utilize cascodes with normally-off JFETs for illustration purposes, a person of ordinary skill in the art will readily recognize that the system and method for providing symmetric, efficient bi-directional power flow and power conditioning is not limited to these particular cascodes, and may, in fact, utilize cascodes with other normally-off semiconductor transistors including MOSFETs and BJTs. Also, although certain embodiments of a system and method for providing symmetric, efficient bi-directional power flow and power conditioning discussed below are applied to cascodes with normally-on JFETs and normally-off JFETs having built-in potentials of about 2.7 V and normally-off JFETs blocking voltage at gate biases equal to or less than zero for illustration purposes, a person of ordinary skill in the art will readily recognize that they can be readily applied to cascodes with semiconductor transistors having built- in potentials and blocking voltage gate biases of other values without departing from the spirit of the invention.

[0018] With reference now to Figure 1 , shown is an embodiment of a SiC

JFET 100 that may be used in the back-to-back cascode configuration described above. JFET 100 includes a gate-to-drain (GD) pn junction 120, i.e., GD diode, and a gate-to-source (GS) pn junction 1 10, i.e., GS diode. JFET 100 also includes a source terminal 130, a gate terminal 140, and a drain terminal 150. Figure 1 also illustrates the various p+ (gate), n+ (source), n- drift (drift layer) and n+ (buffer and substrate) regions of JFET 100. Although JFET 100 is fabricated from silicon carbide (SiC), other materials suitable for high-voltage applications, such as gallium nitride (GaN), gallium arsenide (GaAs), and diamond can be used.

[0019] With reference now to Figure 2, shown is a graph illustrating forward GS pn junction 1 10 and GD pn junction 120 electrical characteristics of a JFET such as JFET 100. Specifically, the graph illustrates gate-current as a function of gate-to- source bias (VGS) and gate-to-drain bias (V_GD)- AS shown, for doping levels relevant to power conditioning applications such as in the embodiments described herein, the wide band-gap of SiC power devices may lead to GS pn junction and GD pn junction built-in potentials {pn junction turn-on) of about 2.7 V.

[0020] With reference again to Figure 1 , the GS pn junction 1 10 typically has a breakdown voltage of less than 100 V and may be used to control the current flow through the JFET 100. The GD pn junction 120 typically has a breakdown voltage that is primarily determined by the thickness and doping levels of the JFET 100 drift layer (n- drift), and blocks the high voltages present in power conditioning

applications. Typical JFET gate-to-drain pn junctions block from a few hundred to tens of thousands of volts.

[0021] An important requirement for efficient power JFET gate-drive operation is maintaining high current-gain voltage-control capability by biasing the gate-to-source and gate-to-drain pn junctions below their built-in potential values. If the gate voltage exceeds these values bipolar gate-current is generated, current-gain deteriorates exponentially, and significant current-handling capability may be needed of the gate drive, which may result in increased physical-size and conduction losses. Bipolar gate-current will reduce switching speed, which increases switching losses and limits switching frequency. In addition, under bipolar gate-to-drain current flow (gate-to- drain junction turned on), electron-hole pair recombinations at basal-plane- dislocations in the drift layer of the JFET may induce stacking fault formation and expansion, which may cause forward voltage degradation and eventual device failure. Accordingly, for efficient gate-drive operation the JFET's gate junctions need to be biased below their turn-on voltages. Under this gate biasing condition and for low-resistance on-state conduction, JFETs capable of blocking in excess of 1200 V are typically designed normally-on (N-ON), i.e., the JFETs block their specified voltage with a negative bias applied to their gates.

[0022] In the example illustrated in Figures 1 and 2, when the gate drive voltage V_G reaches about 2.7 V or higher, the GD and GS diodes are turned on, i.e., the built-in potential of the gate is 2.7 V. The built-in potential value of a SiC JFET may vary depending on design, layer dopings and thickness levels, manufacturing tolerances, passivation techniques etc. However, the gate-to-drain (GD) pn junction 120 and gate-to-source (GS) pn junction 1 10 must be biased below their built-in potential value, for efficient gate drive operation and device reliability. Under such circumstances, the GS and GD diodes are not turned on, very little gate current is needed, and no bipolar gate current is present.

[0023] With reference now to Figure 3, shown is a graph illustrating electrical transistor characteristic curves of high voltage normally-on SiC JFETs and high voltage normally-off SiC JFETs. The graph shows transistor curves of vertical junction recessed implanted gate JFETs blocking 1290-V normally-off (black squares), and 1290-V normally-on (gray triangles) at V_GS = -34 V. The left axis of Figure 3 shows on-state transistor characteristics versus gate-to-source bias in steps of 0.5 V. The strong gate-depletion-region overlap needed to block 1290-V normally- OFF restricts current flow and leads to saturation at low drain voltages. At V_GS = 2.5 V, the normally-ON JFET has a low specific on-state resistance of 2.6 mQ cm² and shows negligible saturation, while the N-OFF JFET has a resistance of 23 mQ cm² and saturates at V_DS = 0.3 V. Therefore, operating the 1200-V N-OFF JFET at the gate bias of 2.5 V, which ensures high current-gain, leads to prohibitively high on- state resistance. Operating the 1200-V N-OFF JFET at gate biases in excess of 2.7 V (gate-to-source pn junction is turned on) results in low current-gain and gate-drive losses and complexity. This is experimental confirmation that high voltage (+1200-V) normally-off vertical junction recessed implanted gate JFETs cannot be operated efficiently in power switching applications.

[0024] On the right axis of Fig. 3, blocking-voltage characteristics for gate-bias steps of -4 V for the N-ON and +0.5 V for the N-OFF JFETs are shown. The N-ON blocks 1290-V and 1450-V at gate biases of -34 V and -37 V, respectively. By design, the N-OFF blocks 1290 V at zero gate bias.

[0025] To implement a normally-off +1200-V JFET-based power switch, high- voltage normally-on and low-voltage normally-off JFETs are connected in a cascode configuration. This creates a normally-off power switch with control specifications similar to those of silicon MOSFETs and IGBTs. A schematic of a cascode switch 170 and its constituent JFETs is shown in Figure 4. A first terminal (T1 ) of the cascode switch 170 is coupled to a voltage supply (VSUPPLY) through a load, while a second terminal (T2) can be coupled to a secondary voltage (VSECONDARY), such as ground or another cascode switch. In the cascode switch 170 configuration, a low- voltage (LV) normally-off JFET is coupled in series with a high-voltage (HV)

normally-on JFET. The first terminal (T1 ) is coupled to a drain (D_Hv) of the HV JFET and a source (SHV) of the HV JFET is coupled to a drain (D_Lv) of the LV JFET. A source (SLV) of the LV JFET is coupled to a gate (GHV) of the HV JFET and a gate (G_Lv) of the LV JFET is employed as a control bias of the cascade switch 1 70.

When the LV JFET is biased in the on state, the HV JFET and the LV JFET operate in series, with the gate-to-source junction of the HV JFET being automatically biased at a voltage value equal to the negative of the drain-to-source voltage drop (V_Lv) across the LV JFET.

[0026] Furthermore, a high voltage, for example, due to a high voltage spike, from VSUPPLY (e.g., 5000 volts) causes a high voltage on the first terminal (T1 ). This results in a high drain-source voltage drop (e.g., 50 volts) across the LV JFET and a high negative gate-source voltage drop across the HV JFET. This high negative gate-source voltage drop (e.g., -50 volts) causes the HV JFET to pinch off, blocking any further high voltage to the second terminal (T2). Once the high voltage is detected and blocked by the HV JFET, only a negligible leakage current flows through both the HV JFET and the LV JFET. After the HV JFET is pinched-off, further increase in voltage at the drain of the cascode is supported by the HV JFET.

[0027] JFETs can conduct current in both directions and so the normally-off JFET-based cascode switch is capable of bidirectional current flow. However, the cascode switch can only block high voltage from drain (T1 ) to source as this reverse biases its gate-to-drain diodes. A high voltage at the source side of the cascode switch (T2) forward biases its gate-to-drain pn junctions and no blocking is feasible. To enable bidirectional power operation, two cascodes can be connected in series with their sources at a common point (back-to-back sources configuration) as illustrated in Figure 5.

[0028] With reference now to Figure 5, shown is a diagram illustrating an embodiment of system 200 providing symmetric, efficient bi-directional power flow and power conditioning. In system 200, two back-to-back connected wide-bandgap JFET (e.g., vertical-channel type JFET) based cascodes 21 0 and 220 are coupled together (connected with their sources in common) and driven by a single gate- drive 230. Each cascode will include a normally-on JFET coupled to a normally-off JFET with the normally-off JFETs of each cascode sharing a common source terminal S. As illustrated in Figure 5, nodes D-i , G-i , and Si are the drain, gate, and source terminals of a first high voltage (HV1 ) normally-on JFET of the first cascade 21 0, and nodes S-i , G and S are the drain, gate, and source terminals of a first low voltage (LV1 ) normally-off JFET of the first cascode 21 0. Nodes D₂, G₂, and S₂ are the drain, gate, and source terminals of a second high voltage (HV2) normally-on JFET of the second cascode 220 and nodes S₂, G and S are the drain, gate, and source terminals of a second low voltage (LV2) normally-off JFET of the second cascode 220.

[0029] A common gate drive 230 applies substantially equal bias to the gates G of both low voltage normally-off JFETs (gates of LV1 and LV2). The gate drive is referenced to node S where the sources of the two low-voltage normally off JFETs (LV1 , LV2) are shorted. As shown in Figure 5, to achieve normally-off cascode operation, the sources of the low-voltage normally-off JFETs (S) are connected to the gates of the high-voltage normally-on JFETs (G-i , G₂). Although JFETs LV1 , LV2, HV1 and HV2 have been illustrated as being fabricated from SiC, other materials suitable for high-voltage applications, such as gallium nitride (GaN), gallium arsenide (GaAs), and diamond can be used.

[0030] System 200 includes gate bias V_G settings for efficient and symmetrical bidirectional power flow and power conditioning in high voltage applications requiring from a few hundred to tens of thousands of volts. Consequently, gate drive 230 is configured to provide (a) gate biases V_G that enable efficient and symmetrical bidirectional current flow through system 200 {i.e., on-state current flow from D to D₂, and vice-versa) and (b) gate biases V_G that block high voltages applied to D or D₂, respectively. Gate drive 230 may be programmed or otherwise configured to determine when to allow power flow through HV1 , LV1 , LV2 and HV2 (i.e., when to apply gate bias (a)) and when to block voltages applied to D or D₂ (i.e., when to apply gate bias (b)). Gate drive 230 may include programmed hardware (e.g., a programmed application specific integrated chip (ASIC)) or a processor and memory that includes instructions, for execution by processor, that receive various inputs, determine when to apply (a) or (b), and control gate drive 230 to apply (a) or (b). Alternatively, gate drive 230 may be configured to apply (a) or (b) based on a control signal or other input received. One of ordinary skill in the art would understand how to configure and design gate drive 230 based on the requirements of the application in which system 200 is used. [0031 ] With continuing reference to Figure 6, the below describes the appropriate gate biases V_G (a) and (b) for system 200. As described above, for gate drive 230 to operate with low conduction losses, low switching losses, high frequency, and small physical size, the gate current it supplies to LV1 , LV2, HV1 and HV2 may need to be as small as possible. Accordingly, the GD pn junctions and GS pn junctions of LV1 , LV2, HV1 and HV2 are preferably biased below their built-in potential, e.g., -2.7 V. In addition, biasing the GD pn junctions below their built-in potential contributes to higher JFET reliability.

Symmetrical and Bi-directional On-State Current Flow

[0032] The following describes the gate bias V_G and voltage settings for efficient symmetrical and bi-directional current flow through system 200 (i.e., bias settings (a) described above). It is to be appreciated that the following examples will be illustrated with respect to cascodes 21 0 and 220 having normally-off JFETs as normally-off semiconductor transistors. It is further to be appreciated that the normally-on JFETs and normally-off JFETs have built-in potentials of about 2.7 V for illustration purposes. The gate bias V_G setting for current flow in the direction of Di to D₂ is described first.

Current flow direction D1 to D2

[0033] In the current flow direction from D1 to D2, the drain D1 of HV1 is at a higher voltage than the drain D2 of HV2. Thus, in the schematic of Fig. 5 the current flow is from D1 to D2.

JFET HV1 :

[0034] From Kirchhoff's law, the voltages across the gate-to-drain (G1 D1 ) and gate-to-source (G1 S1 ) diodes of HV1 are:

G1 D1 : VG-I DI = VG-I SI + SI DI = VGI S + ssi + VSI DI

= 0 + Vssi + Vsi D1 = Vssi + Vsi D1 ( )

V_Gis = 0 V since G1 and S are shorted

Vssi and VSI DI are always negative for D1 to D2 current flow

G1 S1 : VG-I SI = V_{G S} + V_Ssi = 0 + V_Ssi = V_Ssi (2) Vssi < 0 V for D1 to D2 current flow Thus, the diodes of HV1 are always turned off in D1 to D2 current flow.

JFET LV1 :

[0035] From Kirchhoff's law, the voltages across the gate-to-drain (GS1 ) and gate-to-source (GS) diodes of LV1 are:

GS: V_GS < 2.7 V by default biasing (3)

VGS≤ 2.7 V by default biasing and V_Ssi is always negative for D1 to D2 current flow Thus, the diodes of LV1 are always turned off in D1 to D2 current flow.

JFET LV2:

[0036] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS2) diodes of LV2 are:

GS: VQS≤ 2.7 V by default biasing (5)

GS2: VQS2 = VQS + Vss2 must be≤ 2.7 V (6)

VQS≤ 2.7 V by default biasing

Vss2 is always positive for D1 to D2 current flow

Condition (6) is not met by default and constitutes a requirement for efficient gate- drive operation.

JFET HV2:

[0037] From Kirchhoff's law, the voltages across the gate-to-drain (G2D2) and gate-to-source (G2S2) diodes of HV1 are:

G2D2: VG2D2 = VG2S2 + Vs2D2 = VG2S + VsS2 + Vs2D2

= 0 + Vss2 + Vs2D2 = Vss2 + Vs?n? must be ≤ 2.7 V (7) VG2S = 0 V since G2 and S are shorted.

Vss2 and V_S2D2 are always positive for D1 to D2 current flow. Condition (7) is not met by default and constitutes a requirement for efficient gate-drive operation. G2S2: VQ2S2 = V_G2s + V_SS2 = 0 + V_SS2 = V_SS2 must be < 2.7 V (8)

Vss2 is always positive for D1 to D2 current flow. Condition (8) is not met by default and constitutes a requirement for efficient gate-drive operation. However, condition

(8) is automatically satisfied if condition (6) or (7) is satisfied.

Thus, the D1 to D2 symmetrical current flow with efficient gate drive operation requires:

Current flow direction D2 to D1

[0038] In the current flow direction from D2 to D1 , the drain D2 of HV2 is at a higher voltage than the drain D1 of HV1 . Thus, in the schematic of Fig. 5 the current flow is from D2 to D1 .

JFET HV2:

[0039] From Kirchhoff's law, the voltages across the gate-to-drain (G2D2) and gate-to-source (G2S2) diodes of HV2 are:

G2D2: VQ2D2 = VQ2S2 + Vs2D2 = VQ2S + VsS2 + Vs2D2

= 0 + VsS2 + s2D2 = sS2 + s2D2 (9)

VQ2S = 0 V since G2 and S are shorted.

Vss2 and V_S2D2 are always negative for D2 to D1 current flow

G2S2: VQ2S2 = V_G2s + V_SS2 = 0 + V_SS2 = V_SS2 which is < 0 V (10)

From (9) and (10), we conclude that the diodes of HV2 are always turned off in D2 to D1 current flow.

JFET LV2:

[0040] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS2) diodes of LV2 are:

GS: VQS≤ 2.7 V by default biasing (1 1 ) GS2: V_Gs2 = V_GS + VSS2 (1 2)

VQS≤ 2.7 V by default biasing

Vss2 is always negative for D2 to D1 current flow

From (1 1 ) and (1 2), we conclude that the diodes of LV2 are always turned off in D2 to D1 current flow.

JFET LV1 :

[0041 ] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS1 ) diodes of LV1 are:

GS: VQS≤ 2.7 V by default biasing (1 3)

GS1 : V_Gsi = VQS + V_SSi must be < 2.7 V (14)

VQS≤ 2.7 V by default biasing

Vssi is always positive for D2 to D1 current flow

Condition (14) is not met by default and constitutes a requirement for efficient gate- drive operation.

JFET HV1 :

[0042] From Kirchhoff's law, the voltages across the gate-to-drain (G1 D1 ) and gate-to-source (G1 S1 ) diodes of HV1 are:

G1 D1 : V_Gim = V_GI S1 + si D1 = QI S + ssi + Vsi D1

= 0 + Vssi + Vsi Di = Vssi + Vsi Di must be < 2.7 V (1 5) QI S = 0 V since G1 and S are shorted.

Vssi and V_S-I DI are always positive for D2 to D1 current flow. Condition (1 5) is not met by default and constitutes a requirement for efficient gate-drive operation.

G1 S1 : V_Gisi = V_Gis + V_SSi = 0 + V_SSi = V_SSi must be < 2.7 V (1 6)

Condition (1 6) is not met by default and constitutes a requirement for efficient gate- drive operation. However, condition (16) is automatically satisfied if condition (14) or (15) is satisfied. Thus, the D2 to D1 symmetrical power flow with efficient gate drive operation

an ssi + _SI DI≤

To summarize, for bidirectional cascode current flow with a single gate drive signal and efficient low gate-drive current, the following 4 conditions must be met:

[0043] As described above, when symmetrical, bi-directional current flow is required by the application in which system 200 is utilized, gate drive 230 will supply a single gate bias V_G = V_GS that satisfies these equations. Gate drive 230 may include control circuitry or software for determining the appropriate gate bias V_G based on these equations and when to apply such gate bias V_G in order to enable symmetrical, bi-directional current flow and when not to apply such gate bias V_G. Alternatively, control circuitry or software for determining when to apply such gate bias V_G in order to enable symmetrical, bi-directional current flow and when not to apply such gate bias V_G may be external to gate drive 230 and may simply send control signal to gate drive 230 to set gate bias V_G at the appropriate level.

Furthermore, gate drive 230 may include control circuitry that senses signals (e.g. current, voltage, temperature) within the two cascodes 210 and 220, and processes these signals to apply appropriate gate bias V_G based on the equations above. In this case, the gate drive 230 only senses circuit points located between the nodes Di and D₂, and has no sensing or other connection to circuit points located outside the D-i and D₂ nodes.

[0044] The following describes the gate bias V_G settings for high-voltage power conditioning through system 200 (i.e., high-voltage blocking bias settings (b) described above). As illustrated in Figure 5, system 200 can block voltages from 0V to multiple Kilovolts (kV). In high-voltage applications, the voltages that system 200 would typically block would be in the Kilovolt range. The maximum voltage that system 200 could block would be determined by the design and specifications of each JFET in system 200 and vary depending on the materials used to fabricate the JFETs and variations in fabrication. It is to be appreciated that the following examples will be illustrated with respect to cascodes 210 and 220 having normally- off JFETs as normally-off semiconductor transistors. It is further to be appreciated that the normally-on JFETs and normally-off JFETs have built-in potentials of about 2.7 V for illustration purposes. Furthermore, in blocking-voltage mode, the applied gate bias at the gates of the normally-off semiconductor transistors is V_GS≤ 0 V for illustration purposes. The gate bias V_G setting for high-voltage blocking in the direction of D to D₂ is described first.

II. Bidirectional voltage-blocking

Voltage blocking direction D1 to D2

[0045] In blocking-voltage mode the applied gate bias is V_GS≤ 0 V. When high voltages are applied to drain D1 of JFET HV1 , the low-voltage LV1 JFET's drain-to- source blocking-voltage at V_Gs≤ 0 V provides the necessary negative gate bias to pinch off the high-voltage JFET HV1 . After the high-voltage JFET HV1 is pinched- off, further increase in voltage at D1 is supported by the JFET HV1 . This is described by the equations below:

JFET LV1 :

[0046] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS1 ) diodes of LV1 are:

GS: V_GS≤ 0 V by default biasing in blocking-voltage mode (17)

GS1 : V_Gsi = V_GS + Vssi < 0 V + V_SSi (18)

Vssi is always negative for high voltage applied to D1 . From (17) and (18), we conclude that the diodes of LV1 are always turned off in D1 to D2 high voltage application.

JFET HV1 :

[0047] From Kirchhoff's law, the voltages across the gate-to-source (G1 S1 ) and gate-to-drain (G1 D1 ) diodes of HV1 are: G1 S1 : V_G1Si = V_G1S + V_SSi = 0 + V_SSi = V_SSi (19)

G1D1: V_Gim = V_G1 S1 + siD1 = QIS + ssi + siD1

= 0 + Vssi + VSIDI = Vssi + VSIDI (20) QIS = 0 V since G1 and S are shorted

Vssi and V_S-IDI are always negative for D1 to D2 high voltage application

From (19) and (20), we conclude that the diodes of HV1 are always turned off in D1 to D2 high voltage application.

Once the cascode formed by JFETs HV1 and LV1 blocks the high voltage applied at D1 , the JFETs LV2 and HV2 experience a nano-ampere to micro-ampere leakage current flowing from S to D2; l_SD2- The small voltage drop from this leakage current is not sufficient to turn any of the LV2 and HV2 JFET diodes on.

This is described by the equations below:

JFET LV2:

[0048] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS2) diodes of LV2 are:

GS: VQS≤ 0 V by default biasing in blocking-voltage mode (21 )

GS2: V_Gs2 = V_GS + V_SS2 = V_SS2 = ISD₂ ^* Rss₂ must be < 2.7 V (22) ISD2 * Rss2 is always less than 2.7 V as the current ISD2 is in the nano or micro range

From (21) and (22), we conclude that the diodes of LV2 are always turned off in D1 to D2 high voltage application.

JFET HV2:

[0049] From Kirchhoff's law, the voltages across the gate-to-drain (G2D2) and gate-to-source (G2S2) diodes of HV2 are:

G2D2: VG2D2 = G2S2 + Vs2D2 = G2S + sS2 + s2D2

= 0 + VsS2 + Vs2D2 = VsS2 + Vs2D2 = lsD2 * RsD2 mUSt be < 2.7 V (23)

VQ2S = 0 V since G2 and S are shorted.

ISD2 * RSD2 is always less than 2.7 V as the current ISD2 is in the nano or micro range G2S2: VQ2S2 = VQ2S + Vss2 = 0 + Vss2 = Vss2 = ISD2 * Rss2 must

be < 2.7 V (24)

ISD2 * Rss2 is always less than 2.7 V as the current ISD2 is in the nano or micro range

From (23) and (24), we conclude that the diodes of HV2 are always turned off in D1 to D2 high voltage application.

From (1 7)-(24), we conclude that all JFET diodes are in the off-state in D1 to D2 high voltage application with V_GS≤ 0 V.

[0050] The gate bias V_G setting for high-voltage blocking in the direction D₂ to D (the D₂ to Di blocking-voltage mode) is demonstrated below:

Voltage blocking direction D2 to D1

[0051 ] In blocking-voltage mode the applied gate bias is V_GS≤ 0 V. When high voltages are applied to drain D2 of JFET HV2, the low-voltage LV2 JFET's drain-to- source blocking-voltage at V_Gs≤ 0 V provides the necessary negative gate bias to pinch off the high-voltage JFET HV2. After the high-voltage JFET HV2 is pinched- off, further increase in voltage at D2 is supported by the JFET HV2. This is described by the equations below:

JFET LV2:

[0052] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS2) diodes of LV2 are:

GS: V_GS≤ 0 V by default biasing in blocking-voltage mode (25)

GS2: V_GS2 = V_GS + Vss2≤ 0 V + V_SS2 (26)

Vss2 is always negative for high voltage applied to D2. From (25) and (26), we conclude that the diodes of LV2 are always turned off in D2 to D1 high voltage application. JFET HV2 :

[0053] From Kirchhoff's law, the voltages across the gate-to-source (G2S2) and gate-to-drain (G2D2) diodes of HV2 are:

G2S2 : VG2S2 = G2S + ss2 = 0 + Vss2 = ss2 (27)

G2D2 : VQ2D2 = VQ2S2 + Vs2D2 = VQ2S + VsS2 + Vs2D2

= 0 + VsS2 + s2D2 = sS2 + s2D2 (28)

VQ2S = 0 V since G2 and S are shorted

Vss2 and V_S2D2 are always negative in D2 to D1 high voltage application

From (27) and (28), we conclude that the diodes of HV2 are always turned off in D2 to D1 high voltage application.

Once the cascode formed by JFETs HV2 and LV2 blocks the high voltage applied at D2, the JFETs LV1 and HV1 experience a nano-ampere to micro-ampere leakage current flowing from S to D1 ; I_SDI- The small voltage drop from this leakage current is not sufficient to turn any of the LV1 and HV1 JFET diodes on. This is described by the equations below:

JFET LV1 :

[0054] From Kirchhoff's law, the voltages across the gate-to-source (GS) and gate-to-drain (GS1 ) diodes of LV1 are:

GS: VQS≤ 0 V by default biasing in blocking-voltage mode (29)

GS1 : VGSI = GS + ssi = ssi = ISDI * Rssi (30)

ISDI * Rssi is always less than 2.7 V as the current I_SDI is in the nano or micro range.

From (29) and (30), we conclude that the diodes of LV1 are always turned off in D2 to D1 high voltage application. JFET HV1 :

[0055] From Kirchhoff's law, the voltages across the gate-to-drain (G1 D1 ) and gate-to-source (G1 S1 ) diodes of HV1 are:

G1 D1 : V_Gim = V_G1 S1 + si D1 = QI S + ssi + si D1

= 0 + Vssi + Vsi D1 = ssi + Vsi D1 = ISDI * RSDI (31 )

VGI S = 0 V since G1 and S are shorted.

ISDI * RSDI is always less than 2.7 V as the current I_SDI is in the nano or micro range

G1 S1 : VQI SI = GI S + ssi = 0 + Vssi = ssi = ISDI * Rssi (32) ISDI * Rssi is always less than 2.7 V as the current ISDI is in the nano or micro range

From (31 ) and (32), we conclude that the diodes of HV1 are always turned off in D2 to D1 high voltage application.

From (25)-(32), we conclude that all JFET diodes are in the off-state in D2 to D1 high voltage application with V_Gs≤ 0 V.

From (1 7)-(32) we conclude that applying V_Gs≤ 0 V for high voltage blocking is sufficient to keep all diodes below their 2.7 V turn-on. No additional biasing restrictions arise from voltage blocking mode.

[0056] As described above, when a Di to D₂ blocking-voltage mode or D₂ to Di blocking-voltage mode is required by the application in which system 200 is utilized, gate drive 230 will supply a single gate bias V_G = V_Gs that satisfies the above equations. Gate drive 230 may include control circuitry or software for determining the appropriate gate bias V_G based on these equations and determining when to apply such gate bias V_G in order to enable D to D₂ or D₂ to D blocking-voltage modes and when not to apply such gate bias V_G. Alternatively, control circuitry or software for determining the appropriate gate bias V_G and when to apply such gate bias VG may be external to gate drive 230 and may simply send control signal to gate drive 230 to set gate bias V_G at the appropriate level. Furthermore, gate drive 230 may include control circuitry that senses signals (e.g. current, voltage, temperature) within the two cascodes 21 0 and 220, and processes these signals to apply appropriate gate bias V_G based on the equations above. In this case, the gate drive 230 only senses circuit points located between the nodes D and D₂, and has no sensing or other connection to circuit points located outside the D and D₂ nodes.

[0057] To summarize, for bidirectional back-to-back-cascode current/voltage flow (normally-off operation) with a common gate drive signal and efficient low gate-drive current, the following conditions must be met:

On-state current conduction :

Voltage Blocking: V_GS≤0 V

[0058] With reference to Figure 6, shown is a flowchart of an embodiment of method 300 for providing symmetric, efficient bi-directional power flow and power conditioning. The methodology 300 begins at 302 where a first and a second cascode are connected in a back-to-back configuration to provide a SSCB. Each cascode will include a normally-on JFET coupled to a normally-off semiconductor transistor with the normally-off semiconductor transistors of each cascode sharing a common source terminal (back-to-back sources configuration). Furthermore, the normally-on JFETs of each cascode will have drains that provide a first and a second coupling terminal, respectively. Furthermore, the source of the normally-off semiconductor transistor for each respective cascode is coupled to the gate of the corresponding normally-on JFET of the respective cascode, such that a high voltage on a respective coupling node results in a negative voltage across the gate to source of the respective normally-on JFET pinching off the respective normally-on JFET to block both current flow and high voltage between the first and second coupling terminals. The methodology then proceeds to 304.

[0059] At 304, the first and second coupling terminals of the SSCB are coupled into a system to protect the system from high voltages. At 306, a voltage bias is selectively applied to gates of each cascode to allow for bi-directional current flow. The voltage bias applied is below the built-in-potentials of the gate-to-drain and gate- to-source pn junctions in the JFETs of the SSCB. At 308, a high voltage on one of the first and second coupling terminals is sensed. The high voltage will be blocked due to the negative voltage applied to the gate of one of the normally-on JFETs. At 310, a voltage bias is selectively applied to gates of each cascode to block high voltages in the first and second coupling terminals. Again, the voltage bias is applied such that none of the gate-to-drain and gate-to-source pn junctions in the JFETs of the SSCB conduct.

[0060] Embodiments of system 200 may be used for a variety of applications. For example, embodiments of system 200 may be used as a solid-state circuit breaker to provide bi-directional fault isolation in a fraction of a microsecond in power electronic circuits, such as those used in hybrid vehicles. Presently used mechanical contactors may be too slow and suffer severe degradation during repeated fault isolation. Embodiments of system 200 do not suffer such degradation.

[0061] Likewise, embodiments of system 200 may also be used for Army's hybrid military ground vehicles. Additionally, embodiments of system 200 may be used by the Air-Force for their latest generation fighter aircraft 270 DC power system, and by the Navy for their high-voltage ship systems. Embodiments of system 200 may eventually be present in every hybrid vehicle and every power circuit that needs fault protection.

[0062] The bi-directional power flow enabled by embodiments of system 200 enables regeneration applications. Industrial applications can reap significant energy savings by returning otherwise wasted energy to AC mains. Examples of such industrial applications that can utilize embodiments of system 200 include rolling mills, conveyor belts, and elevators. In electric-gasoline hybrid vehicles, bidirectional power flow may be needed to power the electric motor and to receive and store regenerated energy like that from braking.

[0063] Embodiments of system 200 may also be used in photovoltaic systems interacting with the utility grid. For example, embodiments of system 200 may be used to provide bi-directional flow of solar photovoltaic power to utility AC grid and from utility AC grid to charge the photovoltaic battery bank.

[0064] Embodiments of system 200 may provide wind power transfer to the utility grid and back, such as by providing bi-directional power flow between the wind turbine generator and the utility grid. [0065] Embodiments of system 200 may also provide fuel cell bi-directional power flow. In fuel cell hybrid vehicles, the electric drive-train motor is supplied by an inverter connected to a fuel cell. In addition, traditional chemical-power batteries are employed to provide better cold start characteristics and the option to recover braking energy. Bi-directional power flow, such as that provided by embodiments of system 200 are needed to interface the chemical-power battery with the fuel cell.

[0066] In short, embodiments of system 200 enable power flow in multiple directions that saves energy and allows interface of power sources with the grid. Current silicon circuitry cannot operate at high temperatures and is less energy efficient. Back-to-back connected, SiC, other similar composition, JFETs configured as in system 200 with bias settings as described herein operate fast enough for these applications, do not degrade with faults, can operate at high temperatures and are more energy efficient than current silicon circuitry.

[0067] Although in the exemplary embodiments above, JFET based cascode 210 and 220 have been connected back-to-back with sources of the normally-off transistors coupled at a common point S, one skilled in the art will recognize that similar results can be obtained by connecting the two JFET cascodes back-to-back with drains of the normally-off transistors coupled at a common point S.

[0068] The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that many variations are possible within the spirit and scope of the invention as defined in the following claims, and their equivalents, in which all terms are to be understood in their broadest possible sense unless otherwise indicated.

Claims

What is claimed is:

1 . A system for providing bi-directional power flow and power conditioning for high-voltage applications, comprising:

a first normally-on junction field-effect transistor (JFET) having a drain that forms a first coupling node;

a first normally-off semiconductor transistor having a drain coupled to a source of the first normally-on JFET and a source coupled to a gate of the first normally-on JFET, wherein a high voltage on the first coupling node provides a negative voltage on the gate of the first normally-on JFET resulting in blocking of the high voltage and mitigating power flow through the normally-on JFET and normally- off semiconductor transistor;

a gate drive coupled to a gate of the first normally-off semiconductor transistor, the gate drive being configured to selectively apply a voltage bias V_G to the first normally-off semiconductor transistor so that the system allows current to flow bi-directionally between the first coupling node and the source of the first normally-off semiconductor transistor, or so that the system blocks voltages from the first coupling node to the source of the first normally-off semiconductor transistor.

2. The system of claim 1 , wherein the first normally-off semiconductor transistor is a normally-off JFET.

3. The system of claim 2, wherein the gate-to-drain and gate-to-source pn junctions of the first normally-off JFET and the first normally-on JFET are biased below their built-in potentials during both bi-directional current flow and voltage blocking.

4. The system of claim 2, wherein the first normally-off JFET and the first normally-on JFET are vertical-channel JFETs.

5. The system of claim 1 , wherein the first normally-off semiconductor transistor and the first normally-on JFET are fabricated from a wide-bandgap semiconductor chosen from the list comprised of silicon carbide, gallium nitride, gallium arsenide, and diamond.

6. The system of claim 1 , further comprising:

a second normally-off semiconductor transistor having a source coupled to a source of the first normally-off semiconductor transistor;

a second normally-on JFET having a source coupled to a drain of the second normally-off semiconductor transistor, a drain that forms a second coupling node and a gate coupled to the source of both the first and second normally-off semiconductor transistors, wherein a high voltage on the second coupling node provides a negative voltage on the gate of the second normally-on JFET resulting in blocking of the high voltage and mitigating power flow through the normally-on second JFET and the normally-off second semiconductor transistor; and

the gate drive further being coupled to a gate of the second normally-off semiconductor transistor and further being configured to selectively apply a voltage bias V_G to the second normally-off semiconductor transistor so that the system allows current to flow bi-directionally between the first coupling node and the second coupling node, or so that the system also blocks voltages from the second coupling node to the source of the second normally-off semiconductor transistor.

7. The system of claim 6, wherein the first normally-off semiconductor transistor and the second normally-off semiconductor transistor are normally-off JFETs.

8. The system of claim 7, wherein voltages across the gate-to-drain and gate-to- source pn junctions of the first and second normally-off JFETs and the first and second normally-on JFETs are less than or equal to their pn junction built-in potentials during both bi-directional current flow and voltage blocking.

9. The system of claim 7, wherein the first and second normally-off JFETs and the first and second normally-on JFETs are fabricated from a wide-bandgap semiconductor chosen from the list comprised of silicon carbide, gallium nitride, gallium arsenide, and diamond.

10. The system of claim 7, wherein V_G is selectively biased to allow current to flow from the first coupling node to the second coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the second normally-off JFET is less than a built-in potential of a gate-to-drain pn junction of the second normally-off JFET, and the voltage from the source to the drain of the second normally-off JFET plus the voltage from the source to the drain of the second normally-on JFET is less than a built-in potential of a gate-to-drain pn junction of the second normally-on JFET.

1 1 . The system of claim 7, wherein V_G is selectively biased to allow current to flow from the second coupling node to the first coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the first normally-off JFET is less than a built-in potential of a gate-to-drain pn junction of the first normally-off JFET, and the voltage from the source to the drain of the first normally-off JFET plus the voltage from the source to the drain of the first normally-on JFET is less than a built- in potential of a gate-to-drain pn junction of the first normally-on JFET.

12. The system of claim 6, wherein V_G is selectively biased to block voltages applied to either the first coupling node or the second coupling node by setting V_G equal to or less than zero.

13. The system of claim 6, in which the gate drive includes control circuitry configured to selectively set V_G and further includes control circuitry to sense a high voltage at the first coupling node and set V_G to further block high voltages from the first coupling node to the source of the first normally-off semiconductor transistor.

14. The system of claim 6, in which the gate drive includes control circuitry configured to selectively set V_G and further includes control circuitry to sense a high voltage at the second coupling node and set V_G to further block high voltages from the second coupling node to the source of the second normally-off semiconductor transistor.

15. A solid-state circuit breaker comprising the system of claim 6.

16. A system for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications, comprising:

a first cascode comprising:

a first normally-on junction field-effect transistor; and

a first normally-off semiconductor transistor , the first normally-on JFET having a drain that is a first coupling node and a source coupled to a drain of the first normally-off semiconductor transistor;

a second cascode comprising: a second normally-off semiconductor transistor; and

a second normally-on JFET, the second normally-off semiconductor transistor having a drain node that is coupled to a source node of the second normally-on JFET, the second normally-on JFET having a drain node that is a second coupling node, wherein sources of the first and second normally-off semiconductor transistors are shorted together at a common point S; and

a gate drive that applies a voltage bias (V_G) to both the first and second normally-off semiconductor transistors, the gate drive being configured to selectively bias V_G so that the system allows current to flow bi-directionally between the first coupling node and the second coupling node, or so that the system blocks voltages applied to the first coupling node or the second coupling node.

17. The system of claim 16, wherein the first normally-off semiconductor transistor and the second normally-off semiconductor transistor are normally-off JFETs.

18. The system of claim 17, wherein voltages across the gate-to-drain and gate- to-source pn junctions of the first and second normally-off JFETs and the first and second normally-on JFETs are less than or equal to their pn junction built-in potentials during both bi-directional current flow and voltage blocking.

19. The system of claim 17, the first normally-off JFET having a source node coupled to a gate of the first normally-on JFET, wherein a high voltage on the first coupling node provides a negative voltage on the gate of the first normally-on JFET resulting in blocking the high voltage and mitigating power flow through the first normally-on JFET and the first normally-off JFET, and the second normally-off JFET having a source node coupled to a gate of the second normally-on JFET, wherein a high voltage on the second coupling node provides a negative voltage on the gate of the second normally-on JFET resulting in blocking the high voltage and mitigating power flow through the second normally-on JFET and the second normally-off JFET.

20. The system of claim 19, in which the gate drive includes control circuitry configured to selectively set V_G and further includes control circuitry to sense a high voltage at either the first coupling node or the second coupling node and set V_G to further block high voltages from flowing between the first coupling node and the second coupling node.

21 . The system of claim 20, wherein V_G is selectively biased to allow current to flow from the first coupling node to the second coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the second normally-off JFET is less than a built-in potential of a gate-to-drain pn junction of the second normally-off JFET, and the voltage from the source to the drain of the second normally-off JFET plus the voltage from the source to the drain of the second normally-on JFET is less than a built-in potential of a gate-to-drain pn junction of the second normally-on JFET, and V_G is selectively biased to allow current to flow from the second coupling node to the first coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the first normally-off JFET is less than a built-in potential of a gate-to-drain pn junction of the first normally-off JFET, and the voltage from the source to the drain of the first normally-off JFET plus the voltage from the source to the drain of the first normally-on JFET is less than a built-in potential of a gate-to- drain pn junction of the first normally-on JFET.

22. The system of claim 21 , wherein V_G is selectively biased to block voltages applied to either the first coupling node of the second coupling node by setting V_G equal to or less than zero.

23. A method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications, comprising:

providing a first and a second back-to-back connected cascode being driven by a single gate-drive, each of the first and second cascodes having a normally-on JFET coupled to a normally-off semiconductor transistor with the normally-off semiconductor transistors of each of the first and second cascodes sharing a common source terminal and with each of the normally-on JFETs of the first and second JFET cascodes providing respective first and second coupling terminals; selectively applying a voltage bias (V_G) from the gate drive to gates of both the normally-off semiconductor transistors of the first and second cascodes, the voltage bias being below the built-in-potentials of the gate-to-drain and gate-to- source pn junctions of the normally-on JFETS of the first and second JFET cascodes, such that current can flow bi-directionally between the first coupling node and the second coupling node.

24. The method of claim 23 wherein the normally-off semiconductor transistors of the first and second cascodes are normally-off JFETs.

25. The method of claim 24, further comprising sensing a high voltage on one of the first and second coupling nodes and applying a gate voltage bias (V_G) that blocks current flow between the first and second coupling nodes.

26. The method of claim 25, wherein a source of the normally-off JFET is coupled to a gate of the normally-on JFET for each respective cascode of the first and second cascodes, such that a high voltage on the first coupling node provides a negative voltage on the gate of the normally-on JFET of the first cascode resulting in blocking the high voltage and mitigating power flow through the normally-on JFET of the first cascode and a high voltage on the second coupling node provides a negative voltage on the gate of the normally-on JFET of the second cascode resulting in blocking the high voltage and mitigating power flow through the normally-on JFET of the second cascode.

27. The method of claim 26, wherein V_G is selectively biased to allow current to flow from the first coupling node to the second coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the normally-off JFET of the second cascode is less than a built-in potential of a gate-to-drain pn junction of the normally-off JFET of the second cascode, and the voltage from the source to the drain of the normally-off JFET of the second cascode plus the voltage from the source to the drain of the normally-on JFET of the second cascode is less than a built-in potential of a gate-to-drain pn junction of the normally-on JFET of the second cascode, and V_G is selectively biased to allow current to flow from the second coupling node to the first coupling node by setting V_G, such that V_G plus the voltage from the source to the drain of the normally-off JFET of the first cascode is less than a built-in potential of a gate-to-drain pn junction of the normally-off JFET of the first cascode, and the voltage from the source to the drain of the normally-off JFET of the first cascode plus the voltage from the source to the drain of the normally-on JFET of the first cascode is less than a built-in potential of a gate-to-drain pn junction of the normally-on JFET of the first cascode.

28. The method of claim 27, wherein voltages across the gate-to-drain and gate- to-source pn junctions of the normally-off JFETs and the normally-on JFETs of the first and second cascodes are less than or equal to their pn junction built-in potentials during both bi-directional current flow and voltage blocking.