WO2013010362A1

WO2013010362A1 - Integrated circuit and method for defending against power attack

Info

Publication number: WO2013010362A1
Application number: PCT/CN2011/083060
Authority: WO
Inventors: 原义栋; 王晋雄; 马磊; 王小曼; 李娜
Original assignee: 中国电力科学研究院; 国家电网公司
Priority date: 2011-07-18
Filing date: 2011-11-28
Publication date: 2013-01-24
Also published as: BR112014001209A2; CN202189369U

Abstract

Provided are an integrated circuit and a method for defending against a power attack. The integrated circuit comprises: a power source, a power source management module (2), an algorithm module (3), a storage unit (4), control logic (5) and an attack defense module (6). The attack defense module (6) has a true random number generator (9) and a scrambling algorithm module (10). A CMOS integrated circuit is used in the scrambling algorithm module (10). The method utilizes the scrambling algorithm module (10) to process N random signals Xctrl[N:l], so as to generate N control signals Yctrl[N:l]. The integrated circuit and method enables a random consumption circuit to have a high degree of randomness, thereby desirably covering the power curve, and enhancing the security and reliability of information communication of the entire chip.

Description

Integrated circuit and method for preventing power consumption attack

Technical field

The present invention belongs to the field of information security circuits, and in particular relates to an integrated circuit and method for preventing power consumption attacks.

Background technique

In the field of modern information security technologies, hardware devices are often used to encrypt important information. However, during the normal operation, the power consumption curve of the hardware device will be stolen, and the attacker can use the obtained power consumption curve and use statistical analysis methods to guess key information such as the encryption system key. Simple Power Analysis (SPA) and Differential Power Analysis (DPA) are two fast and effective information security attacks using power attacks. They are both user personal information and the entire information network security. Caused a huge harm.

At present, the methods for defending power consumption attacks mainly include algorithm level protection and circuit level protection. The algorithm-level protection mechanism is mainly for the improvement of the algorithm. By introducing a randomly generated mask into the algorithm to hide the intermediate result, the internal signal of the chip is not related to the power consumption statistics of the encryption operation, thereby realizing the masking of the power consumption curve. The circuit-level protection mechanism mainly implements the power consumption curve for masking or disturbing the encryption operation through the circuit. The main implementation methods include standard cell libraries that are not related to power consumption, and random current consumption circuits. The basic idea of customizing the standard cell library that is not related to power consumption is to realize the constant power logic unit through full customization, so that the power consumption of the circuit is constant, which is irrelevant to the running algorithm and data, thus concealing the power consumption of the algorithm. curve. This way of implementation does not require the addition of additional auxiliary circuits, only the need to use a customized standard cell library in the circuit synthesis process Yes, but the full customization of the standard cell library is difficult. In addition to the complete customization of the circuit and layout, a lot of verification work is needed to ensure the correctness of the design. In addition, the area of the whole chip is greatly increased, so it is currently based on customization and The effect of the standard cell library with uncorrelated power consumption is not ideal; while the method of adding random current can well achieve the scrambling of the power consumption curve, the randomness of the added random current should be high enough to ensure better. The scrambling effect. Say

Therefore, the implementation of the defense against power consumption attacks in the prior art is difficult and costly. Book

Summary of the invention

In order to overcome the above drawbacks, the present invention provides a method and an integrated circuit for preventing power consumption attacks, which adopts a combination of a true random number generator and a scrambling algorithm to make the random consumption circuit have high randomness, thereby realizing the work. Covering the consumption curve to improve the security and reliability of chip information communication.

To achieve the above object, the present invention provides an integrated circuit for preventing power consumption attacks, comprising: a power supply (1), a power management module (2), an algorithm module (3), a storage unit (4), and a control logic unit (5). The improvement is that the integrated circuit includes an attack prevention module (6) for receiving a power signal VCCVVSS1 output by the power management module (2) and an instruction issued by the control logic unit (5); control logic The unit (5) is respectively connected to the algorithm module (3), the storage unit (4) and the anti-attack module (6);

The power management module (2) receives the signal sent by the power supply (1) and outputs a power supply signal VCCVVSS1 after being internally converted, and the power supply signal VCCVVSS1 is used as the internal power supply domain as the algorithm module (3), the storage unit. (4), the control logic unit (5) and the The attack prevention module (6) supplies power;

The control logic unit (5) also sends an instruction to the algorithm module (3) and receives a signal from the algorithm module (3); the algorithm module (3) is from the storage unit during operation ( Reading data in 4) and writing the result data and intermediate data into the storage unit (4); the control logic unit (5) writes to the storage unit (4) when performing an instruction operation or Read the data. Say

In a preferred technical solution provided by the present invention, the power management module (2) and the storage unit (4) are separately isolated; the algorithm module (Book 3) and the control logic unit (5) are put together , but isolated from other modules; the anti-attack module (6) is isolated from other circuits.

In a second preferred technical solution provided by the present invention, the attack prevention module (6) comprises a bias circuit (7), an on-chip oscillator (8), a true random number generator (9), and a scrambling algorithm unit (10). a voltage-current conversion unit (11) and a current source array (12); the bias circuit (7) and the voltage-current conversion unit (11), the on-chip oscillator (8), and the true random a number generator (9) is connected, the current source array (12) is connected to the scrambling algorithm unit (10), the current source array (12), the on-chip oscillator (8) and the true random number The generator (9), the scrambling algorithm unit (10) are connected, and the true random number generator (9) is connected to the scrambling algorithm unit (10).

In a third preferred technical solution provided by the present invention, the integrated circuit utilizes a guard ring to perform isolation between modules and units.

In the fourth preferred technical solution provided by the present invention, the protection ring in the attack defense module (6) is set as follows:

The bias circuit (7), the voltage-current conversion unit (11) and the current source array (12) are located The first guard ring; the on-chip oscillator (8) is located in the second guard ring; the true random number generator (9) is located in the third guard ring, and the scrambling algorithm unit (10) is located in the fourth Inside the protection ring.

In a fifth preferred technical solution provided by the present invention, the bias circuit (7) is the voltage-current conversion unit (11), the on-chip oscillator (8), and the true random number generator (9) Provide bias voltage;

The square wave signal output by the on-chip oscillator (8) provides a synchronous clock for the true random number generator (9) and the scrambling algorithm unit (10);

The output of the true random number generator (9) is an N random input signal Xctrl[N:l] as an input of the scrambling algorithm unit (10), and the N random input signals are processed by a scrambling algorithm Then get N way control signal Yctrl[N:l] _;

The voltage-current conversion unit (11) converts the voltage signal provided by the bias circuit (7) into a current bias signal as a current reference source of the current source array (12);

The current source array (12) internally includes N current sources with unequal current values, each of which is controlled by a single switch, and the N-way control signal Yctrl[N:l output by the scrambling algorithm unit (10) Switching the N current sources of the current source array (12) separately.

In a sixth preferred embodiment of the present invention, the bias circuit includes a bandgap reference source (13) and a voltage dividing circuit (14), wherein the stable DC voltage generated by the bandgap reference source (13) passes After the voltage dividing circuit (14) is processed, a reference voltage Vref is generated.

In a seventh preferred technical solution provided by the present invention, the scrambling algorithm unit (10) includes a shift out-of-order module (16), an exclusive-OR module (17), and an N-bit register X-reg[N:l] (18). ), data replacement module 1 (19), data replacement module 11 (20), and combination module (21); a block, the XOR module, and the N-bit register X_reg[N:l] are sequentially connected; the N-bit register X_reg[N:l] is respectively associated with the data replacement module 1 (19) and data The replacement module 11 (20) is connected; the data replacement module 1 (19) and the data replacement module 11 (20) are both connected to the combination module (21).

In an eighth preferred technical solution provided by the present invention, the scrambling algorithm unit uses a CMOS integrated circuit. Say

In a ninth preferred technical solution provided by the present invention, the shift out-of-order module (16) performs shift out-of-order processing on the input N-bit data; the book exclusive OR module (17) will not perform shifting out of order Processing the N-bit data and shifting the N-bit data after the out-of-order processing to perform an exclusive-OR operation; the N-bit register X_reg[N:l] (18) stores the N-bit data after the XOR operation; The permutation module 1 (19) performs a permutation operation on the upper order data stored in the N-bit register X_reg[N:l](18) to obtain new high order data; the data replacement module 11(20) pair is stored in The low-fl bit data in the N-bit register X_reg[N:l](18) performs a permutation operation to obtain new low-order data; the combination module (21) obtains new high-fl bit data and new low-practice data. Combine and output.

In a tenth preferred technical solution provided by the present invention, the data replacement module 1 (19) and the data replacement module 11 (20) respectively perform a replacement operation on the data using different permutation tables.

In a preferred solution provided by the present invention, a method for defending against power consumption attacks is provided, which is improved in that the method includes the following steps:

(1) Receiving a power supply signal VCC3/VSS1, generating three bias voltage signals;

(2) performing voltage and current conversion on the first bias voltage signal, and inputting the converted current signal into the current source array corresponding to the power signal; and the second bias voltage signal Processing generates a clock signal; performing a true random number generation process on the third way bias voltage signal and the clock signal to generate N random input signals Xctrl[N:l] _;

(3) processing the N random input signals Xctrl[N:l] and generating N control signals Yctrl[N:l], the N control signals Yctrl[N:l] respectively for the current The N-way switch of the source array is controlled to generate random current consumption.

In the second preferred embodiment of the present invention, the voltage-current conversion step is specifically:

The voltage signal is converted into an electric book flow bias signal of the current source array, and the current source array copies the reference current into N current sources respectively controlled by the N-way switches, and the N current sources are not equal to each other.

In a third preferred solution provided by the present invention, in the step 3: the N random input signal Xctrl[N:l] is a digital signal, and is represented by N-bit random input data Xctrl[N:l];

(3-1). The N-bit random input data Xctrl[N:l] is subjected to shift out-of-order processing to obtain shifting out-of-order data;

(3-2). XOR the shift out-of-order data with the N-bit random input data Xctrl[N _: l] to generate new N-bit data, which is sequentially stored in the N-bit register X_reg[N :l]

(3-3). The N-bit data in the register X_reg[N:l] is divided into two parts, wherein the high N 2 bit data is subjected to the data replacement algorithm I to obtain new high order data, and the low N 2 bit data is passed through the data. Replacement Algorithm II obtains new low N/Z bit data;

(3-4) Combine the new high/1 bit data and the new low N/2 bit data obtained by the replacement The data Yctrl[N:l] _; the data Yctrl[N:l] is a digital signal, which is represented by the N-way control signal Yctrl[N:l].

Compared with the prior art, the present invention provides an integrated circuit and method for defensive power attack, and an anti-attack module is added to an integrated circuit for preventing power consumption attacks, thereby shielding the algorithm power consumption curve and improving security features. Moreover, the method of adding an anti-attack module to the system realizes the shielding function of the algorithm power consumption line and improves the security characteristics of the system; the real random number generator is used as the control signal for changing the power consumption, and the power consumption is improved. The randomness achieves reliable shielding of the power consumption curve; the book adds a scrambling algorithm unit to the anti-attack module to implement the scrambling process on the random sequence, and further improves the reliability of the power consumption curve shielding; The layout of the integrated circuit with power consumption is reasonable, and the crosstalk of signals between modules is reduced, which ensures the integrity of the signal and the reliability of the function.

DRAWINGS

Figure 1 is a schematic diagram of an integrated circuit that protects against power consumption attacks.

Figure 2 shows the block diagram of the anti-attack module.

Figure 3 is a block diagram of the structure of the bias circuit.

FIG. 4 is a structural block diagram of a scrambling algorithm unit and a flow chart of the scrambling algorithm. Figure 5 shows the layout of an integrated circuit that protects against power consumption attacks.

detailed description

The integrated circuit for preventing power consumption attacks of the present invention is as shown in FIG. 1. The integrated circuit 1 for preventing power consumption attacks is composed of a power management module 2, an algorithm module 3, a storage unit 4, a control logic unit 5, and an attack defense module 6. The power supply VCC/VSS is an integrated circuit 1 and a power management module 2 for preventing power consumption attacks. The power supply, after being internally converted by the power management module 2, outputs a power supply signal VCC3/VSS1 that is stable and has a certain driving capability. The VCC3/VSS1 serves as an internal power domain for powering the algorithm module 3, the storage unit 4, the control logic unit 5, and the attack defense module 6 in the system. The control logic unit 5 is responsible for transmitting instructions to the algorithm module 3 and the attack defense module 6, and receiving signals from the algorithm module 3. The algorithm module 3 reads data from the storage unit 4 during operation, and writes the output result data and intermediate data into the storage unit 4; the control logic unit 5 writes to the storage unit 4 when the instruction operation is performed. The data is simultaneously read from the storage unit 4 with the required data. book

Since the power domain VCC3/VSS1 of the algorithm module is from the power management module 2, the power domain of the power management module 2 is from the system power domain VCC/VSS, so that the power consumption curve information of the algorithm module 3 is reflected to the system power domain VCC/VSS. on. The system power domain can be monitored from the outside, so that external power consumption attack technology can steal key information such as the system key. The anti-attack module 6 is added to the integrated circuit 1 for preventing power consumption attacks. The anti-attack module 6 and the algorithm module 3 share a power domain. The power-shielding technology of the anti-attack module 6 can protect the operation process of the algorithm module 3. . The block diagram of the anti-attack module 6 is shown in FIG. 2. The main modules include a bias circuit 7, an on-chip oscillator 8, a true random number generator 9, a scrambling algorithm unit 10, a voltage-current conversion unit 11, and a current source array 12. The power domain of the attack defense module 6 is VCCVVSS1, which is from the power management module 2. In the attack prevention module 6, the bias circuit 7 provides a stable bias voltage for the voltage-current conversion unit 11, the on-chip oscillator 8 and the true random number generator 9, and the on-chip oscillator 8 is an oscillation unit implemented by an on-chip integrated circuit. Its output frequency characteristics are related to its input bias voltage Off, the output square wave signal of the on-chip oscillator 8 provides a synchronous clock for the true random number generator 9 and the scrambling algorithm unit 10; the true random number generator 9 is a true random number with high randomness based on the resistance noise characteristic. The randomness of the output sequence is related to the statistical characteristics of the resistance noise. The output of the true random number generator 9 is the N random input signal Xctrl[N:l] as the input of the scrambling algorithm unit 10, the N The path control signal is processed by the scrambling algorithm to obtain an N-way control signal number Yctrl[N:l] _{; the} voltage-current conversion unit 11 functions to convert the stable voltage signal provided by the bias circuit 7 into a stable current offset. The signal is used as the current reference source of the current source array 12; the current source array 12 internally contains N current sources with unequal current values, each of which is controlled by a single switch, and the N control signals output by the scrambling algorithm unit 10 Yctrl[N:l] controls the switches of the N current sources of the current source array 12, respectively. In this way, the random number sequence generated by the true random number generator is processed by the scrambling algorithm as a control signal of the current source array, and the power consumption consumed on the power supply also exhibits a random characteristic, thereby realizing the shielding function of the power consumption curve. 3 is a block diagram showing the structure of the bias circuit 7, mainly composed of a bandgap reference source 13 and a voltage dividing circuit 14. The bandgap reference source 13 can generate a DC voltage that has little relationship with the power supply and process parameters. The relationship between the DC voltage and the temperature is determined. The DC voltage value varies very little over the entire operating temperature range of the chip, up to O. The magnitude of lmV. The stable DC voltage generated by the bandgap reference source 13 is processed by the voltage dividing circuit 14, and the reference voltage value Vref required by the subsequent modules is generated. These reference voltage values also have high stability, and parameters such as power supply, process, and temperature. The sensitivity factor is very small. 4 is a block diagram showing the structure of the scrambling algorithm unit 10. The scrambling algorithm unit 10 includes a shift out-of-order module 16, an exclusive-OR module 17, an N-bit register X_reg[N:l] 18, and a data set. a replacement module 119, a data replacement module 1120, and a combination module 21; the shift out-of-order module, the XOR module, and the N-bit register X_reg[N:l] are sequentially connected; the N-bit register X_reg[ N: 1] is respectively connected to the data replacement module 119 and the data replacement module 1120; the data replacement module 119 and the data replacement module 1120 are both connected to the combination module 21.

The shift out-of-order module 16 performs shift out-of-order processing on the input N-bit data; the XOR module 17 performs N-bit data that has not been subjected to shift out-of-order processing and N-bits after shifting out-of-order processing. Data is XORed; the N-bit book register X_reg[N: l] 18 stores N-bit data after the XOR operation; the data replacement module 119 pairs are stored in the N-bit register X_reg The high fl bit data in [N:l] 18 performs a permutation operation to obtain new high N 2 bit data; the data permutation module 1120 replaces the lower order data stored in the N bit register X_reg[N:l] 18 Operation, obtaining new low/1 bit data; the combining module 21 combines and outputs the obtained new high N 2 bit data and new low bit data. In order to ensure the function and characteristics of the whole system, it is necessary to rationally layout the layout of each module in the design implementation. Figure 5 is a layout layout of an integrated circuit 1 for protection against power consumption attacks, wherein the thick line frame represents a guard ring for isolating crosstalk on the layout. As shown in FIG. 5, the power management 2 and the storage unit 4 are separately isolated; the algorithm module 3 and the control logic unit 5 in the digital circuit are placed together with other modules; the attack prevention module 6 is isolated from other circuits, and internal It is further divided into the following four parts: a bias circuit 7, a voltage-current conversion unit 11 and a current source array; an on-chip oscillator 8; a true random number generator 9; and a scrambling algorithm unit 10. A method for defending against power consumption attacks, the method comprising the following steps: (1) After the attack prevention module 6 receives the power supply signal VCC3/VSS1, the bias circuit 7 generates a three-way bias voltage signal to be respectively transmitted to the voltage-current conversion unit 11, the on-chip oscillator. 8 and the true random number generator 9;

(2) While the clock signals generated by the on-chip oscillator 8 are input to the true random number generator 9 and the scrambling algorithm unit 10, respectively, the true random number generator 9 generates N random inputs. Signal Xctr says l[N:l] is transmitted to the scrambling algorithm unit 10;

(3) The scrambling algorithm unit 10 processes the N-way random input signal Xctrl[N:l] and generates an N-way control signal Yctrl[N:l], and the N-book control signal Yctrl[N:l The N-way switches of the current source array 12 are separately controlled to generate random current consumption. In the method, the voltage-current conversion unit 11 converts the voltage signal into a current bias signal of the current source array 12, and the current source array 12 copies the reference current into N current sources respectively controlled by the N-way switch. The N current sources are not equal to each other.

As shown in FIG. 5, in the step 3, the N random input signal Xctrl[N:l] is a digital signal, which is represented by N-bit random input data Xctrl[N:l]; (3-1). The N-bit random input data Xctrl[N:l] is subjected to shift out-of-order processing to obtain shift out-of-order data;

(3-4) Combine the new high fl bit data obtained by the replacement with the new low/1 bit data into The data Yctrl[N:l] _; the data Yctrl[N:l] is a digital signal, which is represented by the N-way control signal Yctrl[N:l]. It is to be understood that the present invention and the specific embodiments thereof are intended to clarify the practical application of the technical solutions provided by the present invention, and should not be construed as limiting the scope of the present invention. Various modifications, equivalent substitutions, or improvements can be made by those skilled in the art in light of the spirit and scope of the invention. However, these changes or modifications are within the scope of the application for approval. book

Claims

Rights request

An integrated circuit for preventing power consumption attacks, comprising: a power supply (1), a power management module (2), an algorithm module (3), a storage unit (4), and a control logic unit (5), wherein The integrated circuit includes an attack prevention module (6) for receiving a power signal VCCVVSS1 output by the power management module (2) and an instruction issued by the control logic unit (5); a control logic unit (5) and an algorithm module respectively (3) the storage unit (4) and the attack prevention module (6) are connected; the power management module (2) receives the signal sent by the power source (1) and outputs the power signal VCC3/VSS1 after internal conversion, The power signal VCC3/VSS1 serves as an internal power domain for powering the algorithm module (3), the storage unit (4), the control logic unit (5), and the attack defense module (6);

The control logic unit (5) also sends an instruction to the algorithm module (3) and receives a signal from the algorithm module (3); the algorithm module (3) is from the storage unit during operation ( Reading data in 4) and writing the result data and intermediate data into the storage unit (4); the control logic unit (5) writes to the storage unit (4) when performing an instruction operation or Read the data.

2. The integrated circuit for preventing power consumption attacks according to claim 1, wherein said power management module (2) and said storage unit (4) are separately isolated; said algorithm module (3) and The control logic unit (5) is placed together but isolated from other modules; the attack protection module (6) is isolated from other circuits.

The integrated circuit for preventing power consumption attacks according to claim 1 or 2, wherein the attack prevention module (6) comprises a bias circuit (7), an on-chip oscillator (8), and a true random number occurs. (9), a scrambling algorithm unit (10), a voltage-current conversion unit (11) and a current source array (12); the bias circuit (7) and the voltage-current conversion unit (11), Above-arc Rights request

The splicer (8) is connected to the true random number generator (9), and the current source array (12) is connected to the scrambling algorithm unit (10) and the current source array (12), and the on-chip oscillation The device (8) is connected to the true random number generator (9) and the scrambling algorithm unit (10), and the true random number generator (9) is connected to the scrambling algorithm unit (10).

4. The integrated circuit for protection against power consumption as claimed in claim 3, wherein the integrated circuit performs isolation between the module and the unit by using a guard ring.

The integrated circuit for preventing power consumption attacks according to claim 4, wherein the protection ring in the attack defense module (6) is set as follows:

The bias circuit (7), the voltage-current conversion unit (11) and the current source array (12) are located in the first protection ring; the on-chip oscillator (8) is located in the second protection ring; The number generator (9) is located within the third guard ring, and the scrambling algorithm unit (10) is located within the fourth guard ring.

The integrated circuit for preventing power consumption attack according to claim 3, wherein said bias circuit (7) is said voltage-current conversion unit (11), said on-chip oscillator (8), and The true random number generator (9) provides a bias voltage;

The square wave signal outputted by the on-chip oscillator (8) provides a homogenous clock for the true random number generator (9) and the scrambling algorithm unit (10);

The voltage-current conversion unit (11) converts the voltage signal provided by the bias circuit (7) into a current bias signal as a current reference source of the current source array (12); Rights request

7. The integrated circuit for protection against power consumption according to claim 3, wherein said bias circuit comprises a bandgap reference source (13) and a voltage dividing circuit (14), wherein said bandgap reference The stable DC voltage generated by the source (13) is processed by the voltage dividing circuit (14) to generate a reference voltage Vref.

8. The integrated circuit for preventing power consumption attacks according to claim 3, wherein said scrambling algorithm unit (10) comprises a shift out-of-order module (16), an exclusive-OR module (17), and an N-bit register. X-reg[N:l] (18), data replacement module 1 (19), data replacement module 11 (20), and combination module (21); the shift out-of-order module, the XOR module, and the N-bit registers X_reg[N:l] are sequentially connected; the N-bit registers X_reg[N:l] are respectively connected to the data replacement module 1 (19) and the data replacement module 11 (20); Module 1 (19) and the data replacement module 11 (20) are both connected to the combination module (21).

9. The integrated circuit for protection against power consumption according to claim 3, wherein said scrambling algorithm unit employs a CMOS integrated circuit.

The integrated circuit for preventing power consumption attack according to claim 8, wherein the shift out-of-order module (16) performs shift out-of-order processing on the input N-bit data; 17) performing an exclusive OR operation on the N-bit data that has not been subjected to shift out-of-order processing and the N-bit data after shifting out-of-order processing; the N-bit register X_reg[N:l](18) is exclusive-OR operation The subsequent N-bit data is stored; the data replacement module 1 (19) performs a replacement operation on the high N 2 bit data stored in the N-bit register X_reg[N: l] (18) to obtain a new high N 2 Rights request

Bit data; the data replacement module 11 (20) performs a permutation operation on the low N/2-bit data stored in the N-bit register X_reg[N:l](18) to obtain a new low N/2-bit data; The combination module (21) combines and outputs the obtained new high order data and new low order data.

11. The integrated circuit for preventing power consumption attacks according to claim 10, wherein said data replacement module 1 (19) and said data replacement module 11 (20) respectively replace data using different permutation tables. operating.

12. A method for defending against power consumption attacks, characterized in that the method comprises the following steps:

(2) performing voltage and current conversion on the first bias voltage signal, and inputting the converted current signal into the current source array corresponding to the power signal; generating a clock signal on the second bias voltage signal processing; The three-way bias voltage signal and the clock signal are subjected to true random number generation processing to generate N random input signals Xctrl[N:l] _;

(3) processing the N random input signals Xctrl[N: l] and generating N control signals Yctrl[N:l], the N control signals Yctrl[N:l] respectively for the current The N-way switch of the source array is controlled to generate random current consumption.

The method for defending against power consumption attacks according to claim 12, wherein the step of converting the voltage-current is specifically:

The voltage signal is converted into a current bias signal of the current source array, and the current source array copies the reference current into N current sources respectively controlled by N switches, the N current sources being unequal to each other. Rights request

The method for defending against power consumption attacks according to claim 12, wherein in the step 3: the N random input signals Xctrl[N:l] are digital signals, and are randomly input with N bits. The data Xctrl[N:l] indicates;

(3-2). XORing the shift out-of-order data with the N-bit random input data Xctrl[N:l] to generate new N-bit data, which is sequentially stored in the N-bit register X_reg[N :l]

(3-3). The N-bit data in the register X_reg[N:l] is divided into two parts, wherein the high-fl bit data is subjected to the data replacement algorithm I to obtain a new high N 2 bit data, and the low N 2 bit data. After the data replacement algorithm II, new low-level data is obtained;

(3-4) Combine the new high N/2 bit data and the new low N/2 bit data obtained by the replacement into data Yctrl[N:l] _; the data Yctrl[N:l] is a digital signal, and is controlled by N channels. The signal Yctrl[N:l] is indicated.