WO2012124603A1

WO2012124603A1 - Semiconductor substrate and organic el display device

Info

Publication number: WO2012124603A1
Application number: PCT/JP2012/055978
Authority: WO
Inventors: 宣孝岸
Original assignee: シャープ株式会社
Priority date: 2011-03-15
Filing date: 2012-03-08
Publication date: 2012-09-20
Also published as: TW201248845A

Abstract

In this semiconductor substrate: a plurality of subpixels (SG) are arranged such that different emission colors are adjacent in the x direction; each subpixel (SG) comprises a light-emission unit (3) and a pixel circuit (5); the pixel circuits (5) are arranged along a boundary (7) between the subpixel (SG) comprising the pixel circuit and the adjacent subpixel (SG) on one side in the x direction; and the light-emission units (3) are arranged between the pixel circuit (5) inside the subpixel (SG) comprising the light-emission unit and the pixel circuit (5) inside the subpixel (SG) adjacent on the other side in the x direction.

Description

Semiconductor substrate and organic EL display device

The present invention relates to a semiconductor substrate that can be used in an organic EL display device that performs color display.

In recent years, flat panel displays have been used in various products and fields, and further flat panel displays are required to have larger sizes, higher image quality, and lower power consumption.

Under such circumstances, an organic EL display device including an organic EL element using electroluminescence (hereinafter referred to as “EL”) of an organic material is an all-solid-state type, low voltage drive, and high-speed response. As a flat panel display excellent in self-luminous property, wide viewing angle characteristics, etc., it has attracted a great deal of attention.

The organic EL display device has a configuration in which, for example, an organic EL element electrically connected to a TFT is provided on a substrate made of a glass substrate or the like provided with a TFT (thin film transistor).

For example, in a full-color organic EL display device, generally, organic EL elements including light emitting layers of red (R), green (G), and blue (B) are arranged and formed on a substrate as sub-pixels. Color images are displayed by selectively emitting light from these organic EL elements with a desired luminance using TFTs.

Therefore, in order to manufacture an organic EL display device, it is necessary to form a light emitting layer made of an organic light emitting material that emits light of each color in a predetermined pattern for each organic EL element.

As a method for forming such a light emitting layer in a predetermined pattern, for example, a vacuum deposition method, an ink jet method, a laser transfer method and the like are known. For example, in a low molecular organic EL display (OLED), a vacuum deposition method is often used.

In the vacuum deposition method, a mask (also referred to as a shadow mask) in which openings of a predetermined pattern are formed is used, and the deposition surface of the substrate on which the mask is closely fixed is opposed to the deposition source.

Then, the vapor deposition particles (film forming material) from the vapor deposition source are vapor-deposited on the surface to be vapor-deposited through the opening of the mask, thereby forming a thin film having a predetermined pattern. Vapor deposition is performed for each color of the light emitting layer, and this is called “separate vapor deposition”.

Patent Document 1 and Patent Document 2 describe a method in which the mask is moved little by little with respect to the substrate and the light emitting layers of the respective colors are separately deposited.

In such a conventional separate vapor deposition method, a mask having the same size as the substrate is used, and the mask is fixed so as to cover the deposition surface of the substrate during vapor deposition.

Therefore, in the conventional separate vapor deposition method, as the substrate becomes larger, it is necessary to enlarge the mask accordingly.

However, when the mask is enlarged, a gap is easily generated between the substrate and the mask due to the self-weight deflection and elongation of the mask, and the size of the gap varies depending on the position of the deposition surface of the substrate.

Therefore, when the conventional separate vapor deposition method is used, it is difficult to perform high-precision patterning, and there is a problem in that the position of vapor deposition and color mixing occur.

The above color mixing problem will be described in detail with reference to FIG. FIG. 11 is a diagram for explaining a layout of components of a conventional sub-pixel. As shown in FIG. 11, the deposition surface 100 of the substrate is usually partitioned in a matrix by, for example, signal lines SL and scanning lines WS, and these partitioned areas become subpixels SG, respectively. The subpixels SG are arranged so that subpixels SG of different emission colors are adjacent to each other in one direction (hereinafter referred to as a first direction) x of the vertical direction and the horizontal direction of the matrix. In this direction (hereinafter referred to as the second direction) y, sub-pixels of the same emission color are arranged so as to be adjacent to each other.

Each sub-pixel SG includes a light emitting unit 107 and a pixel circuit 106 that drives the light emitting unit 107 to perform a light emitting operation. In the conventional subpixel SG, as shown in FIG. 11, the pixel circuit 106 is gathered and arranged in one place (for example, one end side in the second direction y) in the subpixel SG. It is formed over the entire remaining area in the sub-pixel SG. That is, the interval between the light emitting units 107 in the first direction x (that is, the interval between adjacent light emitting units 107 of different emission colors) is about the width of the signal line SL or the like (see, for example, Patent Document 3).

Japanese Patent Publication “Japanese Patent Laid-Open No. 8-227276 (published on September 3, 1996)” Japanese Patent Publication “JP 2000-188179 A (published July 4, 2000)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2008-39876 (published on Feb. 21, 2008)”

Conventionally, as described above, the interval between the light emitting units 107 in the first direction x (that is, the interval between adjacent light emitting units 107 of different emission colors) is about the width of the signal line SL or the like. Therefore, under the above-described vapor deposition method in which high-accuracy patterning cannot be performed, there is a problem that adjacent light emitting portions 107 having different light emission colors overlap and color mixing is likely to occur.

In order to solve this problem, the interval between the light emitting portions 107 in the first direction x may be widened. However, this causes a problem that the area of the light emitting portion 107 is reduced (thus, the aperture ratio is reduced).

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor substrate and an organic EL display device that can prevent color mixture of emission colors without reducing the aperture ratio. .

In order to solve the above-described problems, a semiconductor substrate of the present invention is a semiconductor substrate on which a plurality of subpixels arranged in the vertical and horizontal directions are formed, and the plurality of subpixels are arranged in the vertical direction and the horizontal direction of the arrangement. In the first direction, which is one of the directions, sub-pixels having different emission colors are arranged adjacent to each other, and each of the sub-pixels emits the light-emitting unit that emits the emission color and emits the light-emitting unit. A pixel circuit that is driven to operate, and the pixel circuit is disposed along a first boundary between the sub pixel including the pixel circuit and the adjacent sub pixel on one side in the first direction. The light emitting unit is disposed between the pixel circuit in the sub pixel including the light emitting unit and the pixel circuit in the sub pixel adjacent to the other side in the first direction. .

According to the above configuration, in the first direction, the sub-pixels (and thus the light-emitting portions) are arranged so that different light emission colors are adjacent to each other. The pixel circuit of each sub-pixel is arranged along a first boundary between the sub-pixel including the sub-pixel and the adjacent sub-pixel on one side in the first direction. The pixel circuit in the sub-pixel including the pixel circuit is disposed between the pixel circuit in the adjacent sub-pixel on the other side in the first direction. That is, the arrangement area of the pixel circuit is also used as a color mixture prevention region for preventing color mixture between adjacent light emitting parts of different light emission colors.

Therefore, since a pixel circuit is arranged between adjacent light emitting portions having different light emission colors, a sufficient interval between adjacent light emitting portions having different light emission colors can be ensured without reducing the area of the light emitting portion. Can do. Thereby, it is possible to prevent color mixing of the emission colors without reducing the aperture ratio.

As described above, the semiconductor substrate of the present invention is a semiconductor substrate on which a plurality of sub-pixels arranged in the vertical and horizontal directions are formed, and the plurality of sub-pixels are included in the vertical and horizontal directions of the arrangement. In one direction, which is one direction, sub-pixels of different emission colors are arranged adjacent to each other, and each of the sub-pixels emits the emission color and emits light from the emission unit. A pixel circuit to be driven, and the pixel circuit is disposed along a first boundary between the sub-pixel including the pixel circuit and the sub-pixel adjacent to one side in the first direction, and the light emission The unit is arranged between the pixel circuit in the sub-pixel including the pixel circuit and the pixel circuit in the sub-pixel adjacent to the other side in the first direction.

Therefore, it is possible to prevent color mixing of the emission colors without reducing the aperture ratio.

FIG. 3 is a plan view of a semiconductor substrate used in the organic EL display device according to the first embodiment when viewed from the opposite side of the support substrate. 3 is a diagram illustrating a layout of components of each sub-pixel in Embodiment 1. FIG. 3 is a diagram illustrating an example of a layout in the case where a pixel circuit includes two transistors and one capacitor in Embodiment 1. FIG. FIG. 4 is a sectional view taken along line IV-IV in FIG. 3. FIG. 4 is an equivalent circuit diagram of a subpixel in the case of FIG. 3. It is a figure explaining the formation process of the light emitting layer of a semiconductor substrate. FIG. 10 is a diagram illustrating a layout of components of each sub pixel in the second embodiment. FIG. 10 is a diagram illustrating an example of a layout in the case where a pixel circuit includes three transistors and one capacitor in Embodiment 2. FIG. 9 is an equivalent circuit diagram of a subpixel in the case of FIG. 8. FIG. 10 is a diagram for explaining a layout of components of each sub-pixel in Embodiment 3. FIG. 10 is a diagram illustrating an example of a layout in the case where a pixel circuit includes three transistors and one capacitor in Embodiment 3. It is a figure explaining the layout of the component of the conventional subpixel.

Hereinafter, embodiments of the present invention will be described in detail.

[Embodiment 1]
The embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.

FIG. 1 is a plan view of a semiconductor substrate used in the organic EL display device according to the present embodiment as viewed from the opposite side of the support substrate.

The organic EL display device 1 according to this embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 includes a support substrate 20, a pixel array unit 30 including a plurality of sub-pixels SG arranged in a matrix (that is, vertically and horizontally) on one main surface of the support substrate 20, and a pixel array The scanning line driving circuit 40 that scans each sub pixel SG of the unit 30 in units of rows, and the signal line driving circuit 50 that writes a video signal to each sub pixel SG selected by the scanning line driving circuit 40 are provided. .

The pixel array unit 30 includes a plurality of scanning lines WS arranged in a row, a plurality of signal lines SL arranged in a column, and sub areas arranged in each region partitioned by each scanning line WS and each signal line SL. It consists of pixels SG.

Each scanning line WS is connected to the scanning line driving circuit 40 and is sequentially selected by the scanning line driving circuit 40 to output a control signal from the scanning line driving circuit 40 to the sub-pixels SG in units of rows. Each signal line SL is connected to the signal line drive circuit 50, and the video signal from the signal line drive circuit 50 is written to each subpixel SG selected by the scanning line drive circuit 40.

This organic EL display device 1 is a full-color active matrix type organic EL display device, and is provided on each of the matrix regions partitioned by the scanning lines WS and the signal lines SL on the support substrate 20, respectively. Sub-pixels SGb, SGg, and SGr composed of organic EL elements of blue (B), green (G), and red (R) are disposed. In other words, each region partitioned by each scanning line WS and each signal line SL is one subpixel SG, and B, G, and R light emitting regions are formed for each subpixel SGb, SGg, and SGr. .

Here, the organic EL display device 1 is configured as a bottom emission type that emits light from the support substrate 20 side, but may be configured as a top emission type that emits light from the opposite side of the support substrate 20. Absent.

Note that “R”, “B”, and “G” described in the block of each sub-pixel SG in FIG. 1 mean that light is emitted in red, blue, and green, respectively.

Here, each sub-pixel SG emits light differently in one direction (here, horizontal direction x: first direction) of the vertical direction (that is, the column direction) and the horizontal direction (that is, the row direction) of the array. The color sub-pixels SG are arranged so as to be adjacent to each other, and the sub-pixels SG of the same emission color are arranged so as to be adjacent in the other direction (here, the vertical direction y: second direction).

In this organic EL display device 1, one pixel G is composed of three subpixels SGr, SGb, and SGg, which are a red subpixel SGr, a green subpixel SGg, and a blue subpixel SGb.

(Sub-pixel configuration)
FIG. 2 is a diagram for explaining the layout of components of the sub-pixel SG. FIG. 3 is a diagram illustrating an example of a layout in a case where a pixel circuit that is a constituent element of the sub-pixel SG includes two transistors and one capacitor. 4 is a cross-sectional view taken along the line IV-IV in FIG.

As shown in FIG. 2, each sub-pixel SG includes a light-emitting unit 3 that emits a light emission color assigned to the sub-pixel SG, and a pixel circuit 5 that drives the light-emitting unit 3 to emit light. ing.

The pixel circuit 5 of each subpixel SG is along a boundary (first boundary) 7 between the subpixel SG and the adjacent subpixel SG on one side in the horizontal direction x in which different emission colors are arranged (that is, It is arranged along the boundary 7 so as to be arranged on the boundary 7 or along the boundary 7 so as to be arranged in the vicinity of the boundary 7). Further, the pixel circuit 5 is arranged along the boundary 7 so as to extend from the vicinity of one end of the sub-pixel SG to the vicinity of the other end.

Specifically, the pixel circuit 5 includes, for example, two transistors (switching transistor T1 and driving transistor T2) and one capacitor (holding capacitor) C as shown in FIG. The transistors T1 and T2 are arranged in a line along the boundary 7. The capacitors C are formed in a long shape along the boundary 7, and are arranged in a line together with the transistors T1 and T2.

Here, as an example of the configuration of the pixel circuit 5, a case in which two transistors T1 and T2 and one storage capacitor C are provided is described as an example. However, the present invention is not limited to this example. One or three or more may be provided, or two or more capacities may be provided or may be omitted.

By the way, in an organic EL display device, the light emission efficiency is generally different depending on the light emission color. For example, green has high current efficiency and blue has low current efficiency. In this case, the aspect ratio (ratio of the channel length L to the channel width W (W / L ratio)) of the driving transistor T2 that supplies current to the light emitting unit 3 of the green subpixel SGg is small, and the light emission of the blue subpixel SGb. The aspect ratio of the driving transistor T2 that supplies current to the unit 3 must be increased.

Therefore, it is desirable to change the direction of arrangement of the drive transistor T2 in accordance with the aspect ratio. For example, the drive transistor T2 of the blue subpixel SGb whose channel width W is larger than the channel length (W> L) is preferably arranged so that the direction of the channel width W is substantially parallel to the direction of the boundary 7. On the other hand, in each of the drive transistors T2 of the red subpixel SGr and the green subpixel SGg whose channel width W is smaller than the channel length L (W <L), the channel length L direction is substantially parallel to the boundary 7 direction. It is desirable to be arranged in. Thereby, it is possible to provide a margin for the distance between the transistor T2 and the light emitting unit 3 adjacent thereto.

In the above description, only the drive transistor T2 is targeted. However, the present invention may be applied to all transistors (for example, T1 and T2) in the pixel circuit 5. That is, among the transistors T1 and T2, those having the channel length L larger than the channel width W are arranged such that the direction of the channel length L is substantially parallel to the direction of the boundary 7, while the channel width W is larger than the channel length L. The larger channel width W may be arranged so that the direction of the channel width W is substantially parallel to the direction of the boundary 7.

Here, for the blue sub-pixel SGb, the channel width W is larger than the channel length L in each of the transistors T1 and T2, and therefore the direction of the channel width W is arranged substantially parallel to the direction of the boundary 7. On the other hand, for each of the red and green subpixels SGr and SGg, the transistor T1 has a channel width W larger than the channel length L, and thus the direction of the channel width W is arranged substantially parallel to the direction of the boundary 7. Since the channel length L of the transistor T2 is larger than the channel width W, the direction of the channel length L is arranged substantially parallel to the boundary direction.

The light emitting unit 3 of each subpixel SG is disposed between the pixel circuit 5 in the subpixel SG and the pixel circuit 5 in the subpixel SG adjacent to the horizontal direction x in which different emission colors are arranged. Yes. In other words, the pixel circuit 5 is interposed between the light emitting units 3 having different emission colors adjacent to each other.

(Cross-sectional structure of semiconductor substrate)
4 is a cross-sectional view taken along the line IV-IV in FIG.

In the cross section of FIG. 4, the semiconductor substrate 10 has a transistor T <b> 2, a signal line SL, an interlayer film 13 (interlayer insulating film, planarization film), an edge cover 15 on a transparent and insulating support substrate 20 such as a glass substrate. Is formed. Although omitted in FIG. 4, the scanning line WS, the transistor T <b> 1, and the capacitor C are also formed on the support substrate 20.

On the display area 35 (see FIG. 1) of the support substrate 20, each signal line SL and each scanning line WS are provided, and for each sub-pixel SG, a transistor T1 and a transistor T2 constituting the pixel circuit 5 are provided. And a capacitor C are provided. The transistor T1, the transistor T2, and the capacitor C are disposed along the signal line SL in the vicinity of the signal line SL that defines the boundary 7. Since the configurations of the transistors T1 and T2 and the capacitor C are well known, illustration and description thereof are omitted.

The interlayer film 13 is laminated on the entire display region 35 of the support substrate 20 so as to cover the transistors T1 and T2, the capacitor C, the signal line SL, and the scanning line WS.

The first electrode 21 of the light emitting unit 3 is formed on the interlayer film 13.

The interlayer film 13 is provided with a contact hole 13a for electrically connecting the first electrode 21 to the transistor T2. Thus, the transistor T2 is electrically connected to the light emitting unit 3 through the contact hole 13a.

The edge cover 15 prevents the first electrode 21 and the second electrode 26 described later from being short-circuited when the organic EL layer 60 becomes thin or the electric field concentration occurs at the pattern end of the first electrode 21. This is an insulating layer. The edge cover 15 is formed on the interlayer film 13 so as to cover the pattern end of the first electrode 21. Note that the transistor T1, the transistor T2, and the capacitor C are disposed below the edge cover 15.

The edge cover 15 is provided with

openings

15R, 15B, and 15G for each of the sub-pixels SGr, SGb, and SGg. The

openings

15R, 15B, and 15G of the edge cover 15 serve as light emitting regions of the sub-pixels SGr, SGb, and SGg (that is, regions in plan view of the light emitting unit 3).

Here, since the organic EL display device 1 is configured as a bottom emission type, for example, the first electrode 21 is formed as a transparent electrode, and the second electrode 26 is formed as a reflective electrode. In this case, in the present invention, since the pixel circuit 5 is disposed between the light emitting units 3, light from the organic EL (light emitting unit 3) hardly enters the pixel circuit 5, and malfunction can be prevented.

In addition, when the organic EL display device 1 is configured as a top emission type, for example, the first electrode 21 is formed as a reflective electrode, and the second electrode 26 is formed as a transparent electrode. In this case, in the present invention, the pixel circuit 5 is disposed between the light emitting units 3, that is, the pixel circuit 5 is not disposed under the light emitting unit 3. The EL film thickness can be made uniform, and the current distribution can be made uniform.

Next, the light emitting unit 3 will be described.

The light emitting unit 3 is a light emitting element (here, an organic EL element) capable of high luminance light emission by low voltage direct current drive, and is configured by laminating the first electrode 21, the organic EL layer 60, and the second electrode 26 in this order. Has been.

The first electrode 21 is a layer having a function of injecting holes into the organic EL layer 60. The first electrode 21 is connected to the transistor T2 through the contact hole 13a as described above.

Between the first electrode 21 and the second electrode 26, as shown in FIG. 4, as the organic EL layer 60, from the first electrode 21 side, a hole injection layer / hole transport layer 22 and a light emitting layer 23 (23R · 23B / 23G), the electron transport layer 24, and the electron injection layer 25 are formed in this order.

Note that the stacking order is that in which the first electrode 21 is an anode and the second electrode 26 is a cathode, the first electrode 21 is a cathode, and the second electrode 26 is an anode. The stacking order of 60 is reversed.

The hole injection layer is a layer having a function of increasing the efficiency of hole injection into the

light emitting layers

23R, 23B, and 23G. The hole transport layer is a layer having a function of improving the efficiency of transporting holes to the

light emitting layers

23R, 23B, and 23G. The hole injection / hole transport layer 22 is uniformly formed on the entire display region 35 of the support substrate 20 so as to cover the first electrode 21 and the edge cover 15.

In the present embodiment, as described above, the hole injection layer / hole transport layer 22 in which the hole injection layer and the hole transport layer are integrated is provided as the hole injection layer and the hole transport layer. An example will be described. However, the present embodiment is not limited to this. The hole injection layer and the hole transport layer may be formed as independent layers.

On the hole injection layer / hole transport layer 22, the

light emitting layers

23R, 23B, and 23G correspond to the sub-pixels SGr, SGb, and SGg, respectively, so as to cover the

openings

15R, 15B, and 15G of the edge cover 15. Is formed.

The

light emitting layers

23R, 23B, and 23G are layers having a function of emitting light by recombining holes injected from the first electrode 21 side with electrons injected from the second electrode 26 side. . The

light emitting layers

23R, 23B, and 23G are each formed of a material having high light emission efficiency, such as a low molecular fluorescent dye or a metal complex.

The electron transport layer 24 is a layer having a function of increasing the electron transport efficiency from the second electrode 26 to the

light emitting layers

23R, 23B, and 23G. The electron injection layer 25 is a layer having a function of increasing the electron injection efficiency from the second electrode 26 to the

light emitting layers

23R, 23B, and 23G.

The electron transport layer 24 is supported on the light emitting layer 23R / 23B / 23G and the hole injection layer / hole transport layer 22 so as to cover the light emitting layer 23R / 23B / 23G and the hole injection layer / hole transport layer 22. It is uniformly formed over the entire display area 35 of the substrate 20. Further, the electron injection layer 25 is uniformly formed on the entire surface of the display region 35 of the support substrate 20 on the electron transport layer 24 so as to cover the electron transport layer 24.

Note that the electron transport layer 24 and the electron injection layer 25 may be formed as independent layers as described above, or may be provided integrally with each other. That is, instead of the electron transport layer 24 and the electron injection layer 25, an electron transport layer / electron injection layer may be provided.

The second electrode 26 is a layer having a function of injecting electrons into the organic EL layer 60 composed of the organic layers (

light emitting layers

23R, 23B, and 23G) as described above. The second electrode 26 is uniformly formed on the electron injection layer 25 over the entire display region of the support substrate 20 so as to cover the electron injection layer 25.

Note that organic layers other than the

light emitting layers

23R, 23B, and 23G are not essential layers as the organic EL layer 60, and may be appropriately formed according to the required characteristics of the light emitting unit 3. In addition, a carrier blocking layer can be added to the organic EL layer 60 as necessary. For example, by adding a hole blocking layer as a carrier blocking layer between the light emitting

layers

23R, 23B, and 23G and the electron transport layer 24, the holes are prevented from passing through the electron transport layer 24, and the light emission efficiency is improved. can do.

As the configuration of the light emitting unit 3, for example, layer configurations as shown in the following (1) to (8) can be adopted.
(1) First electrode / light emitting layer / second electrode (2) First electrode / hole transport layer / light emitting layer / electron transport layer / second electrode (3) First electrode / hole transport layer / light emitting layer / Hole blocking layer (carrier blocking layer) / electron transport layer / second electrode (4) first electrode / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (5 ) 1st electrode / hole injection layer / hole transport layer / light emitting layer / electron transport layer / electron injection layer / second electrode (6) 1st electrode / hole injection layer / hole transport layer / light emitting layer / positive Hole blocking layer / electron transport layer / second electrode (7) first electrode / hole injection layer / hole transport layer / light emitting layer / hole blocking layer / electron transport layer / electron injection layer / second electrode (8) 1st electrode / hole injection layer / hole transport layer / electron blocking layer (carrier blocking layer) / light emitting layer / hole blocking layer / electron transport Layer / electron injection layer / second electrode Incidentally, as described above, for example, a hole injection layer and a hole transport layer, may be integrated. Further, the electron transport layer and the electron injection layer may be integrated.

Further, the configuration of the light emitting unit 3 is not limited to the above-described exemplary layer configuration, and a desired layer configuration can be adopted according to the required characteristics of the light emitting unit 3 as described above.

In this manner, the light emitting unit 3 of each subpixel SG is connected to the pixel circuit 5 in the subpixel SG (transistor T2 in FIG. 4) and the pixel circuit 5 in the subpixel SG adjacent to the direction x in which different emission colors are arranged. (Transistor T2 in FIG. 4).

In the above description, since the transistor T1 and the capacitor C do not appear in the cross section of FIG. 4, the description of the connection relationship between the components T1 and C is omitted, but the connection relationship between the components T1 and C is as follows. FIG. 5 is an equivalent circuit diagram (FIG. 5) described later.

(Equivalent circuit of pixel array part)
FIG. 5 is an equivalent circuit diagram of the pixel array unit 30 of the semiconductor substrate 10. In FIG. 5, for convenience of drawing, an equivalent circuit is shown only for one subpixel SG, but a similar equivalent circuit is established for all subpixels.

Each sub-pixel SG includes the light emitting unit 3 and the pixel circuit 5 as described above. The pixel circuit includes two transistors T1 and T2 and one storage capacitor C.

The transistor T1 is, for example, an N channel type switching transistor configured by a thin film transistor. The transistor T2 is, for example, a P-channel driving transistor configured by a thin film transistor. In addition, the capacitor C is a storage capacitor configured by a thin film capacitor, for example. The light emitting unit 3 is handled as a two-terminal element (diode) in this equivalent circuit.

The source / drain (between main electrodes) of the transistor T1 is connected between the signal line SL and the gate (control electrode) of the transistor T2. The gate (control electrode) of the transistor T1 is connected to the scanning line WS. The source (one main electrode) of the transistor T2 is connected to the power supply line Vcc, and the drain (the other main electrode) of the transistor T2 is connected to the anode (that is, the first electrode 21) of the light emitting unit 3. The cathode of the light emitting unit 3 (that is, the second electrode 26) is grounded. The capacitor C is connected between the power supply line Vcc and the gate of the transistor T1.

With this configuration, the light emission operation of each subpixel SG is controlled as follows. That is, a control signal is supplied to each scanning line WS sequentially selected by the scanning line driving circuit 40, and an image is displayed on each signal line SL by the signal line driving circuit 50 in accordance with the selected scanning line WS. A signal is supplied.

In each of the selected subpixels SG, the control signal supplied to the scanning line WS is applied to the gate of the transistor T1, so that the transistor T1 becomes conductive. As a result, the video signal supplied to the signal line SL is written into the capacitor C through the transistor T1. Then, the drain current Ids is supplied to the light emitting unit 3 according to the video signal written in the capacitor C by the transistor T2. Thereby, the light emission part 3 light-emits with the brightness | luminance according to a video signal. In this way, the light emission operation of each sub-pixel SG is controlled.

(Semiconductor substrate manufacturing method)
Next, the manufacturing method of the semiconductor substrate 10 is demonstrated using FIG. FIG. 6 is a diagram illustrating a process for forming a light emitting layer of the semiconductor substrate 10.

First, as shown in FIG. 1, the signal line SL and the scanning line WS are formed on the display area 35 of the support substrate 20 by a known method. Since each region partitioned by the signal line SL and the scanning line WS becomes the sub pixel SG, the signal line SL and the scanning line WS become the boundary of the sub pixel SG.

Then, in a known method, as shown in FIG. 3, in each region partitioned by the signal line SL and the scanning line WS, the transistors T1 and T2 and the capacitor C constituting the pixel circuit 5 are connected in the x direction in the region. It is formed along the boundary 7 on one side (for example, the left side in FIG. 3).

Then, by a known method, as shown in FIG. 4, the signal line SL, the scanning line WS (not shown), the transistor T1 (not shown), the transistor T2, and the capacitor C ( An interlayer film 13 is formed so as to cover (not shown), and a first region is formed in a region to be the light emitting unit 3 (that is, a region other than the region in which the pixel circuit 5 is formed in the region to be the subpixel SG). The electrode 21 and the edge cover 15 are formed, and the hole injection layer / hole transport layer 22 is formed over the entire display region 35 so as to cover them.

Then, the

light emitting layers

23R, 23B, and 23G of the respective colors are formed on the support substrate 20 on which the constituent members up to the hole injection layer / hole transport layer 22 are formed in this way by using the vapor deposition apparatus 105 of FIG. Form.

First, the vapor deposition apparatus 105 will be described. The vapor deposition apparatus 105 includes, for example, a shadow mask 102 having a slit-shaped opening 102a, a nozzle 103 having a nozzle opening 103a, and a vapor deposition source 104 connected to the nozzle 103, and these are integrated. It is configured.

In the vapor deposition apparatus 105, the nozzle 103 is arranged with the nozzle opening 103a facing upward. The shadow mask 102 is disposed above the nozzle 103. Due to this arrangement relationship, the vapor deposition particles (the material of the light emitting layer 23) ejected from the nozzle opening 103a are ejected upward through the slit-shaped opening 102a of the shadow mask 102.

On the other hand, the support substrate 20 is arranged with the display region 35 (that is, the surface on which the hole injection layer / hole transport layer 22 is formed) facing downward. The support substrate 20 is arranged so that the extending direction (y direction) of the signal lines SL of the support substrate 20 and the extending direction of the opening 102a of the shadow mask 102 are substantially parallel.

In this state, as shown in FIG. 6, the support substrate 20 is scanned in the extending direction (y direction) of the signal line SL and passed above the vapor deposition apparatus 105. As a result, the light emitting layer 23 is formed on the display region 35 of the support substrate 20.

More specifically, when the red light emitting layer 23R is formed, red vapor deposition particles are ejected from the nozzle 103. Then, using the shadow mask 102 having the opening 102a only in a predetermined region corresponding to the opening 15R (that is, the region where the red light emitting unit 3 is formed) of each red sub-pixel SGr, vapor deposition by the above scanning is performed. Do. Thereby, as shown in FIG. 4, the light emitting layer 23R is formed in the opening 15R in each red sub-pixel SGr.

When the green light emitting layer 23G and the blue light emitting layer 23B are formed, the green light emitting layer 23G is formed in the opening 15G of each green subpixel SGg in the same manner as the red light emitting layer 23R. The blue light emitting layer 23B is formed in the opening 15B of each blue subpixel SGb.

Thus, as shown in FIG. 4, the

light emitting layers

23R, 23B, and 23G of the respective colors are formed in the

openings

15R, 15B, and 15G of the subpixels SGr, SGb, and SGg of the respective colors. That is, the

light emitting layers

23R, 23B, and 23G of the sub-pixels SGr, SGb, and SGg include the pixel circuit 5 (the transistor T2 in FIG. 4) of the sub-pixel SG and the pixel circuit 5 ( In FIG. 4, it is arranged between the transistor T2).

Thus, since the pixel circuit 5 is interposed between the light emitting

layers

23R, 23B, and 23G of different colors, a sufficient interval is secured. Therefore, when the

light emitting layers

23R, 23B, and 23G are formed, the positional relationship between the shadow mask 102 and the support substrate 20 is shifted, and the formation positions of the

light emitting layers

23R, 23B, and 23G of the respective colors are different from each other. Even if the

layers

23R, 23B, and 23G are shifted to the side, they are prevented from overlapping with the adjacent

light emitting layers

23R, 23B, and 23G of different colors.

Then, as shown in FIG. 4, the electron transport layer 24, the electron injection layer 25, and the Two electrodes 26 are sequentially formed. Then, the scanning line driving circuit 40 and the signal line driving circuit 50 are formed by a known method. In this way, the semiconductor substrate 10 is manufactured.

As described above, according to this embodiment, with respect to one direction (first direction) x of the vertical direction and the horizontal direction of the arrangement of the sub pixels SG, each sub pixel SG (and thus each light emitting unit 3) is The different emission colors are arranged next to each other. The pixel circuit 5 of each subpixel SG is disposed along a boundary 7 (first boundary) between the subpixel SG including the pixel circuit 5 and the adjacent subpixel SG on one side in the first direction x. Further, the light emitting unit 3 of each subpixel SG is disposed between the pixel circuit 5 in the subpixel SG including the subpixel SG and the pixel circuit 5 in the adjacent subpixel SG on the other side in the first direction x. . That is, the arrangement area of the pixel circuit 5 is also used as a color mixture prevention region for preventing color mixture between the adjacent light emitting units 3 having different emission colors.

Therefore, since the pixel circuit 5 is disposed between the adjacent light emitting units 3 having different emission colors, the interval between the adjacent light emitting units 3 having different emission colors can be achieved without reducing the area of the light emitting unit 3. Can be secured sufficiently. Thereby, it is possible to prevent color mixing of the emission colors without reducing the aperture ratio.

[Embodiment 2]
In the first embodiment, the pixel circuit 5 of each subpixel SG is formed in a straight line along the boundary 7 as shown in FIG. 2, but in this embodiment, each subpixel SG is shown in FIG. The pixel circuit 5 ′ is formed in an L shape along the

boundaries

7 and 8. Hereinafter, this embodiment will be described in detail based on FIG. 7 and FIG.

FIG. 7 is a plan view of the layout of components of each sub-pixel SG in this embodiment. FIG. 8 is an enlarged plan view of one subpixel SG.

In this embodiment, as shown in FIG. 7, the pixel circuit 5 ′ of each sub-pixel SG is formed in an L shape along the

boundaries

7 and 8. That is, the pixel circuit 5 ′ of each subpixel SG has a portion along the boundary 7 on the one side (first boundary) of the boundary 7 (first boundary) on both sides in the x direction of the subpixel SG, as in the first embodiment. 1 portion) 5a and a portion (second portion) 5b along one boundary 8 of the boundary 8 (second boundary) on both sides in the y direction of the subpixel SG. The second portion 5b can also be said to be a portion extending in the x direction.

In FIG. 7, the second portions 5b of the sub-pixels SGr, SGg, and SGb are arranged on the same side in the y direction (lower side in FIG. 7), but it is not necessary to arrange them on the same side. For example, the second portion 5b of the sub pixel SGb may be disposed on the upper side in the y direction, and the second portion 5b of each sub pixel SGg / SGr may be disposed on the lower side in the y direction.

Note that the boundary 7 is a boundary between the sub-pixels SG having different emission colors (that is, a boundary defined by the signal line SL). The boundary 8 is a boundary between the sub-pixels SG having the same emission color (that is, a boundary defined by the scanning line WS).

Specifically, the pixel circuit 5 ′ of this embodiment includes, for example, as shown in FIG. 8, three transistors (switching transistor T3, driving transistor T4, light emission control transistor T5) and one capacitor (holding capacitor) C. And. The transistors T3 to T5 are arranged in a line along the boundary 7. The capacitor C includes a portion (first capacitor portion) Ca formed along the boundary 7 and a portion (second capacitor portion) Cb formed along the boundary 7 from the first capacitor portion Ca. The first capacitor Ca is arranged in a row together with the transistors T3 to T5, and the first portion 5a of the pixel circuit 5 'is constituted by these components Ca, T3, T4, and T5. The second capacitor portion Cb constitutes the second portion 5b of the pixel circuit 5 '.

FIG. 9 is an equivalent circuit diagram of each sub-pixel SG of this embodiment. As shown in FIG. 9, each sub-pixel SG of this embodiment includes the light emitting unit 3 and the pixel circuit 5 'as described above. The pixel circuit 5 'includes three transistors T3 to T5 and one capacitor (holding capacitor) C.

In this embodiment, a control line E is added for each scanning line WS compared to the case of the first embodiment. Each control line E is connected to the scanning line driving circuit 40, and is sequentially selected together with the corresponding scanning line WS by the scanning line driving circuit 40, and the control signal from the scanning line driving circuit 40 is sub-pixel-by-row. Output to SG.

Each of the transistors T3 to T5 is composed of, for example, an N-channel transistor. The source (one main electrode) of the transistor T3 is connected to the signal line SL, and the drain (the other main electrode) of the transistor T3 is connected to the gate (control electrode) of the transistor T4. The drain (one main electrode) of the transistor T5 is connected to the power supply line Vcc, and the source (the other main electrode) of the transistor T5 is connected to the drain (one main electrode) of the transistor T4. The source (the other main electrode) of the transistor T4 is connected to the anode of the light emitting unit 3. The cathode of the light emitting unit 3 is grounded, for example. The capacitor C is connected between the gate and source of the transistor T4. The gate of the transistor T3 is connected to the scanning line WS, and the gate of the transistor T5 is connected to the control line E.

With this configuration, the light emission operation of each subpixel SG is controlled as follows. That is, a control signal is supplied to each scanning line WS and each control line E sequentially selected by the scanning line driving circuit 40, and at the same time, the signal line driving circuit 50 adjusts to the selected scanning line WS. A video signal is supplied to each signal line SL.

In each of the selected subpixels SG, the control signal supplied to the control line E is applied to the gate of the transistor T5, so that the transistor T5 becomes conductive. Further, the control signal supplied to the scanning line WS is applied to the gate of the transistor T3, so that the transistor T3 becomes conductive. Thus, the video signal supplied to the signal line SL is written into the capacitor C through the transistor T3.

In the transistor T4, the source current Ids flows according to the video signal written in the capacitor C. Thereby, the current from the power supply line Vcc sequentially conducts the transistors T5 and T4, and the current Ids corresponding to the video signal written in the capacitor C is supplied to the light emitting unit 3. Thereby, the light emission part 3 light-emits with the brightness | luminance according to a video signal. In this way, the light emission operation of each sub-pixel SG is controlled.

In this embodiment, as an example of the configuration of the pixel circuit 5 ', a case in which three transistors T3 to T5 and one capacitor C are provided is described as an example. However, the configuration is not limited to this.

In this embodiment, the three transistors T3 to T5 are arranged in a line along the boundary 7. However, the present invention is not limited to this. For example, all or part of the three transistors T3 to T5 are arranged. May be arranged along the boundary 8.

In this embodiment, one capacitor C includes the first capacitor portion Ca along the boundary 7 and the second capacitor portion Cb along the boundary 8. However, the capacitor along the boundary 7 and the boundary 8 Two capacitances may be provided, with a capacitance along

In this embodiment, the first capacitor portion Ca of the capacitor C is disposed along the boundary 7 and the second capacitor portion Cb of the capacitor is disposed along the boundary 8. However, the present invention is not limited to this. Instead, the entire capacitor C may be disposed along the boundary 8, and the entire capacitor C may be disposed along the boundary 7 as in the first embodiment.

As described above, according to this embodiment, the pixel circuit 5 ′ includes the first portion 5a along the boundary 7 (first boundary) and the second portion 5b extending from the first portion 5a in the x direction. Therefore, even when the first portion 5a alone cannot secure a sufficient placement area of the pixel circuit 5 ′, the second portion 5b makes it possible to secure a sufficient placement area of the pixel circuit 5 ′. .

In addition, since the second portion 5b of the pixel circuit 5 ′ is disposed along the boundary 8 (second boundary), the second portion 5b does not divide the light emitting unit 3 of the subpixel SG including the second portion 5b. It is possible to secure an arrangement place of the second part.

[Embodiment 3]
In the second embodiment, as shown in FIG. 7, the pixel circuit 5 ′ is formed in an L shape. That is, the second portion (that is, the portion extending in the x direction) 5 b of the pixel circuit 5 ′ is disposed on one end side in the y direction of the light emitting unit 3. In this embodiment, as shown in FIG. 10, the second portion 5 b of the pixel circuit 5 ″ divides the light emitting unit 3 in the y direction and is arranged therebetween. Hereinafter, based on FIGS. The embodiment will be described in detail.

FIG. 10 is a diagram for explaining the layout of the components of each sub-pixel SG in this embodiment. FIG. 11 is a diagram for explaining an example of a layout in the case where the pixel circuit 5 ″ according to the third embodiment includes three transistors and one capacitor.

In this embodiment, as shown in FIG. 10, the pixel circuit 5 ″ of each subpixel SG includes a portion (first portion) 5a along the boundary 7 and a portion (second portion) 5b extending in the x direction. The second portion 5b of the pixel circuit 5 ″ is divided into two light emitting portions 3 of the same subpixel SG at appropriate locations in the y direction, and the

light emitting portions

3a and 3b divided in two are divided. Are arranged along.

In FIG. 10, the second portions 5b of the sub-pixels SGr, SGg, and SGb are arranged at the same place in the y direction, but need not be arranged at the same place in the y direction. For example, the second portion 5b of the sub pixel SGb is disposed at a location above the intermediate position in the y direction, and the second portion 5b of each sub pixel SGg / SGr is disposed at a location below the intermediate position in the y direction. May be.

Specifically, the pixel circuit 5 ″ of this embodiment includes, for example, as shown in FIG. 11, three transistors (switching transistor T3, drive transistor T4, light emission control transistor T5) and one capacitor (holding capacitor) C. The transistors T3 to T5 are arranged in a line along the boundary 7.

The capacitor C includes a portion (first capacitor portion) Ca formed along the boundary 7 and a portion (second capacitor portion) Cb extending from the first capacitor portion Ca in the x direction. The first capacitor Ca is arranged in one row together with the transistors T3 to T5. These components Ca, T3, T4, and T5 constitute the first portion 5a of the pixel circuit 5 ″. The light emitting portion 3 is divided into two at appropriate positions in the y direction, and the second capacitor portion Cb. Are arranged between the light-emitting

portions

3a and 3b divided into two (that is, along the x direction). The second capacitor portion Cb constitutes the second portion 5b of the pixel circuit 5 ″. Yes.

Note that the equivalent circuit diagram of each sub-pixel SG in this embodiment is the same as the equivalent circuit diagram of the sub-pixel SG in the second embodiment.

Further, in this embodiment, as an example of the configuration of the pixel circuit 5 ″, a case where three transistors T3 to T5 and one capacitor C are provided is described as an example, but the present invention is not limited to this.

As described above, according to this embodiment, similarly to the second embodiment, the pixel circuit 5 ″ includes the first portion 5a along the boundary 7 (first boundary) and the first portion 5a in the x direction. Since the second portion 5b extending in the (first direction) is provided, the arrangement area of the pixel circuit 5 ″ can be sufficiently ensured.

Further, the second portion 5b (Cb in FIG. 11) of the pixel circuit 5 ″ divides the light emitting section 3 of the sub-pixel SG including the pixel circuit 5 ″ in the y direction (second direction), and the divided

light emitting sections

3a and 3b. Since they are arranged between the two, the wiring of the second portion 5b can be shortened.

That is, when the second portion 5b is arranged along the x direction without dividing the light emitting portion 3, the second portion 5b is placed on the end side in the y direction of the light emitting portion 3 as shown in FIG. Since it is necessary to arrange it, it is necessary to route the wiring of the second part 5b to the end of the light emitting unit 3 in the y direction. Therefore, the wiring of the second portion 5b becomes longer.

Then, like this Embodiment 3, the light emission part 3 is divided | segmented into ay direction, and the said 2nd part 5b is arrange | positioned along between the divided | segmented light emission parts 3a * 3b, The said 2nd part 5b Wiring routing can be shortened.

Further, the second portion 5b (Cb in FIG. 11) of the pixel circuit 5 ″ is arranged between the divided

light emitting portions

3a and 3b by dividing the light emitting portion 3 of the subpixel SG including the second portion 5b in the y direction. , The emission color of each sub-pixel SG adjacent along the y direction can be displayed smoothly.

That is, when the second portion 5b is arranged along the x direction without dividing the light emitting portion 3, the second portion 5b is placed on the end side in the y direction of the light emitting portion 3 as shown in FIG. In other words, it is necessary to arrange them (along the boundary 8 between each subpixel SG adjacent in the y direction).

Therefore, the boundary 8 is further widened by the arrangement area of the second portion 5b in addition to the width of the scanning line WS, so that the emission color of each sub-pixel SG adjacent along the y direction cannot be displayed smoothly. .

Therefore, as in the third embodiment, the light emitting unit 3 is divided in the y direction, and the second portion 5b is disposed between the divided

light emitting units

3a and 3b, so that the boundary 8 has a y direction. The interval between the light emitting portions 3 of the sub-pixels SG adjacent to each other can be set to about the width of the signal line SL. Further, the interval between the divided

light emitting portions

3a and 3b is also about the width of the second portion 5b, and the light emission colors of the respective

light emitting portions

3a and 3b are displayed smoothly. Therefore, the emission color of each subpixel SG adjacent along the y direction can be displayed smoothly.

[Additional Notes]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

As described above, in the semiconductor substrate according to the embodiment of the present invention, the pixel circuit includes the first portion along the first boundary and the first portion extending from the first portion to the one side in the first direction. And a second part.

According to the above configuration, the pixel circuit includes the first portion along the first boundary and the second portion extending from the first portion to the one side in the first direction. Even when the circuit layout area cannot be sufficiently secured, the pixel circuit circuit layout area can be sufficiently secured by the presence of the second portion.

Further, in the semiconductor substrate according to the embodiment of the present invention, the second portion of the pixel circuit includes the sub-pixel including the pixel circuit and the second direction which is the other of the vertical direction and the horizontal direction. It is desirable to arrange the second sub-pixel along a second boundary between adjacent sub-pixels.

According to said structure, since the 2nd part of a pixel circuit is arrange | positioned along the 2nd boundary between the sub pixel provided with it, and the sub pixel adjacent to a 2nd direction, 2nd part of a pixel circuit Can secure the arrangement location of the second portion without dividing the light emitting portion of the sub-pixel including the same.

In the semiconductor substrate according to the embodiment of the present invention, the second part of the pixel circuit is the other direction of the vertical direction and the horizontal direction of the light emitting unit of the sub-pixel including the pixel circuit. It is desirable to divide in the second direction and arrange between the divided light emitting units.

According to the above configuration, the second portion of the pixel circuit divides the light emitting portion of the sub-pixel including the second portion in the second direction, and is arranged between the divided light emitting portions. (A) Pixel circuit The wiring of the second part can be shortened, and (b) the emission color of each sub-pixel adjacent in the second direction can be displayed smoothly.

In addition, in the semiconductor substrate according to the embodiment of the present invention, it is preferable that the pixel circuit includes a capacitor disposed along the first boundary.

According to the above configuration, since the capacitor arranged along the first boundary is provided, even when the capacitor is provided, the arrangement area of the pixel circuit is formed so as to cover the entire first boundary without increasing as much as possible. be able to.

In the semiconductor substrate according to the embodiment of the present invention, it is preferable that the pixel circuit includes one or more transistors, and the one or more transistors are arranged along the first boundary.

According to the above configuration, the one or more transistors are arranged along the first boundary. Therefore, the arrangement area of the pixel circuit is formed so as to cover the entire first boundary without increasing as much as possible. Can do.

Further, in the semiconductor substrate according to the embodiment of the present invention, it is desirable that the pixel circuit includes a capacitor disposed in the second portion of the pixel circuit.

According to the above configuration, since the capacitor disposed in the second portion of the pixel circuit is provided, the above-described effects can be obtained with respect to the capacitor.

In the semiconductor substrate according to the embodiment of the present invention, at least a part of the transistors having a channel length larger than the channel width is the other of the vertical direction and the horizontal direction. It is desirable that the second direction, which is the direction, be arranged substantially in parallel.

According to the above configuration, at least a part of the transistors having a channel length larger than the channel width is disposed so that the channel length direction is substantially parallel to the second direction. It is possible to provide a margin for the distance from the light emitting unit.

In the semiconductor substrate according to the embodiment of the present invention, at least a part of the transistors whose channel width is larger than the channel length is the other of the vertical direction and the horizontal direction. It is desirable that the second direction, which is the direction, be arranged substantially parallel to the second direction.

According to the above configuration, at least a part of the transistors whose channel width is larger than the channel length is arranged so that the direction of the channel width is substantially parallel to the second direction. It is possible to provide a margin for the distance from the light emitting unit.

In the semiconductor substrate according to the embodiment of the present invention, each of the sub-pixels is disposed in each region partitioned by a plurality of scanning lines arranged in rows and a plurality of signal lines arranged in columns. The pixel circuits of the sub-pixels are preferably arranged inside the regions.

This configuration makes it clear that the boundary of the sub-pixel is defined by the scanning line and the signal line, and the scanning line and the signal line are not included in the pixel circuit of each sub-pixel.

Further, the organic EL display device according to the embodiment of the present invention is preferably an organic EL display device including the semiconductor substrate.

According to the above configuration, an organic EL display device having the effect of the semiconductor substrate can be provided.

The present invention can be suitably used for a semiconductor substrate of an organic EL display device, for example.

DESCRIPTION OF SYMBOLS 1 Organic electroluminescence display device 3 Light emission part 3a * 3b Each light emission part 5 * 5 '* 5 "Pixel circuit 5a 1st part 5b 2nd part 7 1st boundary 8 2nd boundary 10 Semiconductor substrate 20 Support substrate 30 Pixel Array part 40 Scan line drive circuit 50 Signal line drive circuit C Capacitance Ca First capacitor part Cb Second capacitor part SG / SGr / SGb / SGg Subpixel E Control line SL Signal line WS Scan line T1, T2, T3, T4, T5 transistor x first direction y second direction

Claims

A semiconductor substrate on which a plurality of sub-pixels arranged vertically and horizontally are formed,
The plurality of sub-pixels are arranged so that sub-pixels of different emission colors are adjacent to each other in a first direction which is one of a vertical direction and a horizontal direction of the arrangement,
Each of the sub-pixels is
A light emitting unit that emits the emission color;
A pixel circuit for driving the light emitting unit to emit light;
With
The pixel circuit is disposed along a first boundary between the sub pixel including the pixel circuit and the sub pixel adjacent to one side in the first direction,
The light emitting portion is disposed between the pixel circuit in the sub pixel including the light emitting portion and the pixel circuit in the sub pixel adjacent to the other side in the first direction. .
2. The pixel circuit according to claim 1, comprising: a first portion along the first boundary; and a second portion extending from the first portion to the one side in the first direction. Semiconductor substrate.
The second portion is disposed along a second boundary between the sub-pixel including the second portion and a sub-pixel adjacent to the second direction which is the other of the vertical direction and the horizontal direction. The semiconductor substrate according to claim 2.
The second portion divides the light emitting portion of the sub-pixel including the second portion into a second direction which is the other of the vertical direction and the horizontal direction, and is arranged between the divided light emitting portions. The semiconductor substrate according to claim 2.
The semiconductor substrate according to any one of claims 1 to 4, wherein the pixel circuit includes a capacitor disposed along the first boundary.
The pixel circuit includes one or more transistors,
The semiconductor substrate according to any one of claims 1 to 5, wherein the one or more transistors are arranged along the first boundary.
The semiconductor substrate according to any one of claims 2 to 4, wherein the pixel circuit includes a capacitor disposed in the second portion of the pixel circuit.
At least a part of the transistors having a channel length larger than the channel width is disposed substantially parallel to a second direction in which the channel length direction is the other of the vertical direction and the horizontal direction. The semiconductor substrate according to claim 6.
Among the transistors having a channel width larger than the channel length, at least a part of the transistors is disposed substantially parallel to a second direction in which the channel width direction is the other of the vertical direction and the horizontal direction. The semiconductor substrate according to claim 6, wherein:
Each of the sub-pixels is disposed in each region partitioned by a plurality of scanning lines arranged in rows and a plurality of signal lines arranged in columns.
The semiconductor substrate according to any one of claims 1 to 9, wherein the pixel circuit of each of the sub-pixels is disposed inside each of the regions.
An organic EL display device comprising the semiconductor substrate according to any one of claims 1 to 10.