WO2012120694A1 - Method of manufacturing wafer level package and wafer level package - Google Patents

Method of manufacturing wafer level package and wafer level package Download PDF

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Publication number
WO2012120694A1
WO2012120694A1 PCT/JP2011/056251 JP2011056251W WO2012120694A1 WO 2012120694 A1 WO2012120694 A1 WO 2012120694A1 JP 2011056251 W JP2011056251 W JP 2011056251W WO 2012120694 A1 WO2012120694 A1 WO 2012120694A1
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WO
WIPO (PCT)
Prior art keywords
wafer
groove
level package
manufacturing
wafer level
Prior art date
Application number
PCT/JP2011/056251
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French (fr)
Japanese (ja)
Inventor
彰彦 佐野
孝明 宮地
知範 積
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オムロン株式会社
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Publication of WO2012120694A1 publication Critical patent/WO2012120694A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Definitions

  • the present invention relates to a wafer level package manufacturing method and a wafer level package, and more particularly to a wafer level package manufacturing method and a wafer level package capable of reducing dicing.
  • a mold package has been mainly used as a packaging method for semiconductor devices, but in recent years, a wafer level package capable of reducing the package cost and reducing the size of the package has expanded the market share.
  • a wafer level package is completed by dicing into individual devices by dicing.
  • dicing is performed after the first wafer and the second wafer are bonded. At that time, warpage occurs due to a difference in thermal expansion coefficient between the first wafer and the second wafer or a stress unique to the wafer, so that dicing in the presence of warpage deteriorates the wafer yield and product yield. A problem occurs.
  • FIGS. 8A to 8E after the semiconductor wafer 101 and the cap wafer 103 are bonded, A half cut 104 is performed along the scribe line from the semiconductor wafer 101 or cap wafer 103 side, and the chips in the horizontal direction are partially divided.
  • the half-cut 104 is inserted in the middle of the cap wafer 103 shown in FIG. 8A to the interface between the cap wafer 103 and the bonding layer 102 shown in FIG. 8B, as shown in FIG.
  • a plurality of surface acoustic wave device patterns 202 are formed on the surface of the piezoelectric substrate 201.
  • the step of removing the protective body 204 at the portion irradiated with the laser beam 205 to form the protective body removing portion 207 and the back surface side of the piezoelectric substrate 201 are ground by the grinder 208 to thin the piezoelectric substrate 201. It comprises a process and a process of separating each device in the modified region 206.
  • the surface acoustic wave device pattern 202 is surrounded and spaced from the outer periphery when separated into individual pieces.
  • the side wall 211 is provided, the excitation space 203 is covered, and a top plate 212 is provided that is spaced from the outer periphery to the entire periphery when separated into individual pieces, and is connected to the surface acoustic wave device pattern 202 and externally provided.
  • a connection electrode 213 for extracting an electric signal is provided on the first substrate, and the entire first surface side of the piezoelectric substrate 201 is covered with a protective body 204 made of an epoxy resin. Further, in the process of separating each device in the modified region 206, the pickup sheet 220 is attached to the piezoelectric substrate 201, and the pickup sheet 220 is stretched to be separated in the modified region 206. .
  • the laser beam 205 is condensed and the modified region 206 is provided in the piezoelectric substrate 201 to be separated into pieces.
  • the protective body removing portion 207 can be formed by condensing the laser beam 205 on the epoxy resin constituting the protective body 204 serving as a cap. Further, the device can be separated at the same time during the grinding process for thinning the piezoelectric substrate 201.
  • the device chip 301 is hermetically sealed with a sealing frame 302 made of resin.
  • the cap wafer 320 is bonded to the device wafer 310 on which the sealing frame 302 is formed, and then the sealing frame 302. 302 is divided into individual pieces by dicing.
  • the device chip 301 is isolated by the sealing frame 302, even when the sealing frames 302 and 302 are diced, the occurrence of cracks due to the dicing processing is prevented from affecting the device chip 301.
  • the wafer yield and the product yield are improved.
  • a scribe line that separates a plurality of semiconductor devices formed on a semiconductor substrate 401 individually.
  • a trench 402 for use and a through-hole trench 403 for forming a through-hole wiring in the semiconductor device are formed by etching using an etching mask 404.
  • the width of the scribe line groove 402 is made smaller than the width of the through hole groove 403.
  • the through hole groove 403 is penetrated by cutting the semiconductor substrate 401 to a thickness that reaches the bottom surface of the through hole groove 403 from the back surface to form a thinned semiconductor substrate 405.
  • the back metal wiring board 406 and the metal wiring 407 are formed.
  • a sheet 408 having adhesiveness and stretchability is attached to the back surface of the thinned semiconductor substrate 405, and along the scribe line groove 402 as shown in FIG. 11 (e). Then, the thinned semiconductor substrate 405 and the backside metal wiring board 406 are cleaved at the scribe line 411 using the break device 410, and the sheet 408 is stretched and separated for each semiconductor device as shown in FIG. To do.
  • This provides a method of manufacturing a semiconductor device that increases the number of devices that can be obtained.
  • Japanese Patent Publication Japanese Unexamined Patent Application Publication No. 2009-177034 (released on August 6, 2009)” Japanese Patent Publication “Japanese Patent Laid-Open No. 2010-213144 (published on September 24, 2010)” US Patent Application Publication No. 2009/0194861 (published Aug. 6, 2009) Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 2002-198327 (released on July 12, 2002)”
  • Patent Document 2 the semiconductor device manufacturing method disclosed in Patent Document 2 is not a wafer level package. For this reason, when applied to a wafer level package in which two substrates are bonded together, both the upper and lower substrates must be modified, which increases the number of steps. Further, since the process is finally a cracking of the substrate, there is a problem that it causes a sealing failure due to a crack, a chip or the like.
  • the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a wafer level package manufacturing method and a wafer level package capable of improving the wafer yield and the product yield.
  • a method for manufacturing a wafer level package of the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane, and a second wafer that faces the first wafer.
  • a first groove for separating into at least one of the first wafer and the second wafer is formed.
  • the method includes a first groove forming step and a bonding step for bonding the first wafer and the second wafer in this order.
  • the wafer level package according to the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer, and then bonded to each device.
  • the singulated wafer level package at least one of the first wafer and the second wafer is provided with a first groove formed for singulation for each device. Yes.
  • the first groove for separating into at least one of the first wafer and the second wafer is formed in the first groove forming step. To do. Next, the first wafer and the second wafer are bonded by a bonding process.
  • the first groove for separating the individual wafer level packages is formed with the first wafer. It is formed in advance before bonding with the second wafer.
  • the first groove for separating into at least one of the first wafer and the second wafer is formed before bonding, warping is reduced by the buffering action of the first groove. It can be joined in the state.
  • the method for manufacturing a wafer level package according to the present invention includes a first groove forming step for forming a first groove for separating at least one of the first wafer and the second wafer, This is a method including a bonding step for bonding the first wafer and the second wafer in this order.
  • At least one of the first wafer and the second wafer is provided with a first groove formed for individual device separation.
  • FIGS. 4A to 4E are cross-sectional views showing an embodiment of a method for manufacturing a wafer level package according to the present invention and showing a manufacturing process of the wafer level package.
  • FIGS. It is a perspective view which shows the structure of the said wafer level package separated into pieces. It is sectional drawing which shows the structure of the said wafer level package.
  • (A)-(e) is sectional drawing which shows the manufacturing process of the modification of the manufacturing method of the said wafer level package.
  • (A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package.
  • A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package.
  • (A) It is a top view which shows the relationship between the device chip and scribe line by the manufacturing method of the wafer level package of this Embodiment, (b) is the device chip and die thin line by the manufacturing method of the conventional wafer level package It is a top view which shows a relationship.
  • (A)-(e) is sectional drawing which shows the manufacturing method of the conventional wafer level package.
  • (A)-(f) is sectional drawing which shows the manufacturing method of the conventional semiconductor device.
  • (A) is a top view which shows the manufacturing method of the other conventional wafer level package,
  • (b) is the sectional drawing.
  • (A)-(f) is sectional drawing which shows the manufacturing method of the other conventional semiconductor device. It is sectional drawing which shows the structure of the wafer level package which bonded together two other conventional semiconductor devices shown in the said FIG.
  • FIGS. 1 to 7 An embodiment of the present invention will be described with reference to FIGS. 1 to 7 as follows.
  • FIG. 2 is a perspective view showing a configuration of a wafer level package separated into pieces
  • FIG. 2 is a cross-sectional view showing a configuration of the wafer level package before being separated into pieces.
  • the wafer level package 10 of the present embodiment is formed by joining a base portion 2 on which a device chip 1 described later is mounted or formed and a cap portion 3 covering the base portion 2.
  • a through hole 5 is formed in the cap portion 3
  • the device chip 1 has a wiring formed in the through hole 5 and a wiring pattern 6 provided on the surface of the cap portion 3. It is electrically connected to an external device provided outside (not shown). Therefore, the wafer level package 10 according to the present embodiment performs signal transfer using a through silicon via (TSV).
  • TSV through silicon via
  • TSV through silicon via
  • the device chip 1 is composed of, for example, a switch contact portion.
  • the present invention is not necessarily limited to this, and any other device or chip such as an electronic circuit may be used.
  • the wafer level package 10 includes a device wafer 20 as a first wafer on which a plurality of device chips 1 are mounted or formed in a plane, and a second wafer facing the device wafer 20. After the cap wafer 30 is bonded to each other, each device is separated into individual pieces. That is, the wafer level package 10 according to the present embodiment performs all the processes up to rewiring, electrode formation, resin sealing, and singulation in the wafer process, and the size of the device chip 1 that finally cut the wafer remains as it is. It is the size of the package. Therefore, it can be said that the wafer level package is ideal from the viewpoint of miniaturization and weight reduction. As described above, the wafer level package 10 of the present embodiment is adopted in an electronic device such as a mobile phone. Any micro electro mechanical system (MEMS) structure may be used.
  • MEMS micro electro mechanical system
  • the device wafer 20 is formed by stacking silicon (Si) wafers, and an insulating film 21 is formed on each layer of wafers. A plurality of device chips 1 are mounted on the insulating film 21 formed on the surface of the upper wafer.
  • the cap wafer 30 is also made of silicon (Si), and an insulating film 31 is formed on the surface thereof.
  • the device chip 1 is electrically connected to an external device through the through hole 5, the wiring pattern 6 and the bump 7 formed in the cap wafer 30 as described above.
  • a switch movable portion 22 is provided on the lower wafer of the device wafer 20.
  • a frame-like bonding / sealing portion 4 is formed, whereby each device chip 1 is sealed by the bonding / sealing portion 4, the upper and lower device wafers 20, and the cap wafer 30.
  • the device wafer 20 and the cap wafer 30 can be bonded by a silicon (Si) -silicon (Si) bond or a silicon (Si) -silicon dioxide (SiO 2 ) bond.
  • the joining sealing part 4 as a joining material which consists of a metal, glass frit, or resin, or the other joining material which is not shown which consists of a metal, glass frit, or resin may be sufficient.
  • the device chip 1 is hermetically sealed between the device chip 1 and the bonding sealing portion 4, the device chip 1 is filled with a substance such as an inert gas or other resin even in a complete vacuum. It may be.
  • the device wafer 20 is provided with a first groove 23 formed to be separated for each device.
  • the other cap wafer 30 different from the device wafer 20 in which the first groove 23 is formed is provided with a band-shaped through-opening 32 that is formed by other than dicing after bonding. That is, the band-shaped through opening 32 is formed up to the lower surface of the cap wafer 30. For this reason, the band-shaped through opening 32 is a band-shaped through opening having no bottom in the cap wafer 30.
  • the present invention is not necessarily limited to this, and a second groove (not shown) that is a band-like opening having a bottom in the cap wafer 30 may be used.
  • the wafer level package 10 can be singulated by scribing or the like, as will be described later, even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening.
  • the first groove 23 is provided in the device wafer 20, and the band-shaped through opening 32 is provided in the cap wafer 30.
  • the present invention is not limited to this, and for example, the first groove 23 may be provided in the cap wafer 30 and the band-shaped through opening 32 may be provided in the device wafer 20.
  • FIGS. 1A to 1E are cross-sectional views showing manufacturing steps of the wafer level package 10.
  • the first groove 23 is formed on the surface of the device wafer 20 in the first groove forming step.
  • the first groove 23 is a bottomed band-shaped opening and is formed by, for example, dry etching or laser. In the case of dry etching, a dry etching mask is used.
  • the width of the first groove 23 is narrower than the disk width of a disk cutter in a dicing method that is generally used in the past to separate the first groove 23.
  • the device wafer 20 on which the first groove 23 is formed and the cap wafer 30 are bonded.
  • bonding is performed so that the first groove 23 of the device wafer 20 faces the cap wafer 30.
  • a bonding material made of metal, glass frit, or resin can be used, and bonding is performed by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding. Is also possible.
  • the back surface of the cap wafer 30 (the upper surface in FIG. 1B) is thinned by a grinder or etching not shown.
  • the through hole 5 is formed in the cap wafer 30 by, for example, dry etching.
  • the band-shaped through opening 32 is also formed by dry etching together as the second groove forming step.
  • the band-shaped through opening 32 is a band-shaped opening that penetrates the cap wafer 30 and is arranged so as to be collinear with the first groove 23 formed in the device wafer 20. Since the band-shaped through opening 32 is formed together with the through hole 5, it can be efficiently formed.
  • the formation of the band-shaped through opening 32 is performed by dry etching, for example.
  • the present invention is not limited to this, and a laser can also be used. That is, any method other than the dicing method may be used. The reason is that the cutting allowance can be made narrower than the dicing method.
  • metal through-wiring is formed in the through hole 5 of the cap wafer 30, and the wiring pattern 6 (not shown) is formed.
  • the first groove 23 is exposed, whereby the wafer level package 10 is singulated.
  • the wafer level package 10 is singulated. There are various methods for dividing the wafer level package 10 into individual pieces.
  • the device wafer 20 can be cut along the scribe line 24.
  • the wafer level package 10 can be cut along the first groove 23 by marking a line or the like with a sharp tool (not shown) as a mark and bending the mark. That is, the thickness of the wafer level package 10 is, for example, 150 ⁇ m for the cap wafer 30, 200 ⁇ m for the device wafer 20, and 60 ⁇ m between the cap wafer 30 and the device wafer 20.
  • a band-shaped through opening 32 is formed in the cap wafer 30, and the first groove 23 is formed halfway through the thickness of the device wafer 20. Therefore, in the thickness direction of the wafer level package 10, 60 ⁇ m between the cap wafer 30 and the device wafer 20 and a part of the device wafer 20 are connected. Therefore, with this thickness, the wafer level package 10 can be easily cut by a scribe method.
  • the wafer level package 10 can be separated into pieces by stretching the sheet.
  • the method of exposing the first groove 23 and dividing the wafer level package 10 into pieces is not necessarily limited to this.
  • the device wafer 20 bonded with the first groove 23 as a boundary in the device wafer 20 in which the first groove 23 is formed, and
  • the first groove 23 can be exposed at the cut surface 25 by extending the cap wafer 30 to both sides.
  • the back surface side of the first groove 23 in the device wafer 20 in which the first groove 23 is formed is ground, polished, or The first groove 23 can be exposed by forming a thinned device wafer 20a that has been thinned by etching.
  • the half groove 26 is used to expose the first groove 23.
  • the half die 26 refers to cutting from the back surface side of the first groove 23 to the first groove 23 in the device wafer 20 in which the groove is formed by a disk cutter used for dicing.
  • the device wafer 20 on which the plurality of device chips 1 are mounted or formed in the surface and the cap wafer 30 facing the device wafer 20 are bonded to each other. After that, it is separated into pieces for each device. Then, the first groove forming step for forming the first groove 23 to be separated into at least one of the device wafer 20 and the cap wafer 30 and the bonding step for bonding the device wafer 20 and the cap wafer 30 are performed. Includes in order.
  • the wafer level package 10 includes a device wafer 20 on which a plurality of device chips 1 are mounted or formed in a plane and a cap wafer 30 facing the device wafer 20, and then bonded to the device wafer 20. Each piece is separated. At least one of the device wafer 20 and the cap wafer 30 is provided with a first groove 23 that is formed to be separated into individual devices.
  • the first groove 23 for separating into at least one of the device wafer 20 and the cap wafer 30 is formed in the first groove forming step. .
  • the device wafer 20 and the cap wafer 30 are bonded by a bonding process.
  • the first groove 23 for separating the individual wafer level package 10 is formed with the device wafer 20. It is formed in advance before bonding the cap wafer 30 together.
  • the dimensional accuracy deteriorates due to the influence of warpage, and the wafer yield and the product yield deteriorate. To do.
  • the cause of this warpage is due to the difference in thermal expansion coefficient or the stress that the wafer has.
  • the stress possessed by the wafer is, for example, the stress possessed by the films formed by forming a bonding metal, an insulating film, a wiring metal, or the like on the wafer.
  • the wafer thickness and the wafer having an SOI structure (a structure having an insulating film in the middle of silicon (Si)) used for the device wafer 20 are also caused by warpage.
  • the first groove 23 for separating the device wafer 20 and the cap wafer 30 is formed in at least one of the device wafer 20 and the cap wafer 30 before bonding, the first groove 23 warps due to the buffering action. It is possible to join in a state where it is reduced.
  • the first groove 23 it is possible to form the first groove 23 to be separated into both the device wafer 20 and the cap wafer 30 before bonding.
  • the first groove 23 By forming the first groove 23 in at least the device wafer 20, even if the device wafer 20 and the cap wafer 30 are separated into individual pieces by extending to both sides after bonding, cracks and chips on the device surface are not generated. Can be prevented.
  • the depth of the first groove 23 shallow, it is possible to prevent breakage during bonding.
  • the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30 and in the bonding step.
  • the band-shaped through-opening 32 or the second groove for separating the device wafer 20 into the other cap wafer 30 or the device wafer 20 different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is formed.
  • a second groove forming step for forming other than dicing is included.
  • the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30, and the device wafer 20 and the cap in which the first groove 23 is formed.
  • the other cap wafer 30 or device wafer 20 that is different from any one of the wafers 30 is provided with a band-shaped through-opening 32 or a second groove to be separated into pieces formed after bonding other than dicing. Is preferred.
  • the second groove is a bottomed belt-like opening, and the belt-like through opening 32 is a bottomless one.
  • the wafer level package 10 can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through opening 32.
  • a method of forming the band-like through opening 32 or the second groove other than dicing there is a method of drilling by etching or laser, for example.
  • the device wafer 20 and the device wafer 20 that are different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed are separated into pieces.
  • the band-shaped through opening 32 or the second groove is formed by other than dicing.
  • the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer.
  • the dimension of the connecting portion at 30 is small.
  • the bonded device wafer 20 and cap wafer 30 are stretched to both sides, for example, with the first groove 23 and the band-shaped through opening 32 or the second groove as a boundary, etc.
  • the wafer level package 10 can be easily separated into individual pieces. For this reason, a dicing process can be made unnecessary.
  • the number of device chips 1 can be increased. That is, as shown in FIG. 7B, conventionally, since the width of the dicing line by dicing is large, the number of device chips 1 per device wafer 20 is inevitably reduced. Specifically, in the case of the conventional dicing method shown in FIG. 7B, a dicing width of 50 to 100 ⁇ m is necessary, and a chip interval of 100 to 200 ⁇ m is necessary in consideration of dicing accuracy.
  • the device chip 1 can be cut into individual pieces by cutting with a scribe line 24 narrower than the width of the dicing line. it can.
  • the width of the groove is 5 to 30 ⁇ m, and even if the accuracy of the scribe line 24 is taken into consideration, it can be realized at an interval of 20 to 50 ⁇ m.
  • the wafer level package 10 is formed on either the device wafer 20 or the cap wafer 30 formed in the first groove forming step.
  • a first groove exposing step for exposing the first groove 23 from the back surface of the first groove 23 is included.
  • the first groove 23 is exposed and the wafer level package 10 can be singulated.
  • the first groove 23 is opposed to the back surface of the first groove 23 in either the device wafer 20 or the cap wafer 30. By scribing along the position, the first groove 23 can be exposed. As a result, the first groove 23 can be exposed by a scribing method without going through a dicing process, and the wafer level package 10 can be singulated.
  • the back surface of the first groove 23 in one of the device wafer 20 and the cap wafer 30 in which the first groove 23 is formed in the first groove exposing step, the back surface of the first groove 23 in one of the device wafer 20 and the cap wafer 30 in which the first groove 23 is formed.
  • the first groove 23 can be exposed by scraping the side by grinding, polishing, or etching to form a thin wafer.
  • the first groove 23 exists up to a thickness in the middle of either the device wafer 20 or the cap wafer 30.
  • channel 23 is exposed by scraping the back surface side of the 1st groove
  • the first groove 23 can be exposed and the wafer level package 10 can be separated into pieces by a method in which the wafer is thinned by grinding, polishing, or etching without going through a dicing process.
  • first groove exposing step from the back side of first groove 23 in either one of device wafer 20 and cap wafer 30 in which first groove 23 is formed. It is possible to expose the first groove 23 by performing the half die 26 up to the first groove 23.
  • each device chip 1 mounted on the surface of the device wafer 20 is already partitioned by the first groove 23 and the cut surface of the band-shaped through opening 32 or the second groove. For this reason, even if the half dice 26 is diced from the rear surface side of the first groove 23 with a large disc width, the dicing cost does not affect the singulation of the device chip 1. Therefore, the number of device chips 1 is not reduced.
  • the first groove 23 in either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is bounded.
  • the first groove 23 can be exposed by extending the bonded device wafer 20 and cap wafer 30 to both sides.
  • the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer 30.
  • the dimension of the connecting portion in the case is small.
  • the bonded device wafer 20 and cap wafer 30 are stretched, that is, peeled off on both sides, with the first groove 23 and the band-shaped through-opening 32 or the second groove as a boundary.
  • the wafer level package 10 can be easily separated into individual pieces.
  • the first groove 23 is exposed by a method of extending the bonded device wafer 20 and cap wafer 30 to both sides with the first groove 23 as a boundary, and the wafer level package 10 is separated into individual pieces.
  • the method for manufacturing the wafer level package 10 of the present embodiment it is possible to use a bonding material made of metal, glass frit, or resin in the bonding process.
  • the device wafer 20 and the cap wafer 30 can be reliably bonded and sealed using the bonding material.
  • the device wafer 20 and the cap are bonded by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding in the bonding process.
  • the wafer 30 can be bonded.
  • the device wafer 20 and the cap wafer 30 are bonded and sealed without using a bonding material. Therefore, the cost can be reduced by not using the bonding material.
  • the first groove is formed on one of the first wafer and the second wafer.
  • a second groove forming step of forming the band-shaped through opening or the second groove other than dicing it is preferable to include a second groove forming step of forming the band-shaped through opening or the second groove other than dicing.
  • the first groove is formed in one of the first wafer and the second wafer, and the first wafer and the first wafer in which the first groove is formed
  • the other second wafer or the first wafer which is different from any one of the two wafers, is provided with a band-shaped through-opening or a second groove for separating into pieces formed after bonding other than dicing.
  • the second groove is a bottomed belt-like opening, and the belt-like through opening is a bottomless one.
  • the wafer level package can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening.
  • a method for forming the band-shaped through-opening or the second groove other than dicing for example, there is a method of drilling by etching or laser.
  • the second wafer or the first wafer which is different from one of the first wafer and the second wafer in which the first groove is formed, is separated into pieces.
  • a belt-like through-opening or a second groove is formed by other than dicing.
  • the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and the second wafer.
  • the dimension of the connecting portion of the wafer 2 is small.
  • the first wafer and the second wafer are stretched to both sides with the first groove and the belt-like through opening or the second groove as a boundary, for example.
  • the wafer level package can be easily separated. For this reason, a dicing process can be made unnecessary.
  • the first wafer formed in either the first wafer or the second wafer formed in the first groove forming step after the second groove forming step, the first wafer formed in either the first wafer or the second wafer formed in the first groove forming step.
  • a first groove exposing step for exposing the first groove from the back surface of the one groove is included.
  • the first groove can be exposed and the wafer level package can be separated.
  • the back surface of the first groove in either one of the first wafer and the second wafer extends along a position facing the first groove.
  • the scribing means cutting the wafer level package along the first groove by cutting a line or the like with a sharp tool as a mark and bending the mark.
  • the back surface side of the first groove in either one of the first wafer and the second wafer on which the first groove is formed is ground.
  • the first groove can be exposed by scraping, polishing, or etching to form a thin wafer.
  • the first groove exists up to a thickness in the middle of one of the first wafer and the second wafer.
  • channel is exposed by scraping off the back surface side of the 1st groove
  • the first groove can be exposed by a method of thinning the wafer by grinding, polishing, or etching, and the wafer level package can be singulated.
  • the first groove is formed from the back surface side of the first groove in either one of the first wafer and the second wafer.
  • the first groove can be exposed by half-dicing up to one groove.
  • the half die is a disc cutter used for dicing, which cuts from the back side of the first groove to the first groove in either one of the first wafer and the second wafer in which the groove is formed.
  • the first groove is exposed by a method of half-dicing up to the first groove, and the wafer level package can be separated.
  • each device chip mounted on the surface of the first wafer is already partitioned at the cut surface of the first groove and the band-like through opening or the second groove. For this reason, even if half dicing is performed from the back surface side of the first groove by dicing with a large disk width, the dicing cost does not affect the device chip separation. Therefore, the number of device chips is not reduced.
  • the bonding is performed using the first groove in either one of the first wafer and the second wafer on which the first groove is formed as a boundary.
  • the first groove can be exposed by stretching the first and second wafers formed on both sides.
  • the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and second wafer.
  • the dimension of the connecting portion of the wafer is small.
  • the bonded first wafer and second wafer are stretched, that is, peeled off from both sides of the first wafer and the second wafer with the first groove and the band-shaped through-opening or the second groove as a boundary.
  • the wafer level package can be easily separated into individual pieces.
  • the first groove is exposed by extending the bonded first wafer and second wafer to both sides with the first groove as a boundary, and the wafer level package is separated into pieces. can do.
  • the present invention relates to a wafer level package, MEMS (Micro Electro Electrode) applied to a semiconductor package mounted on an electronic product represented by a mobile phone, a mobile computer, a personal digital assistant (PDA), a digital still camera (DSC) and the like. It can be applied to a manufacturing method of a wafer level package such as a mechanical system) device and a wafer level package.
  • MEMS Micro Electro Electrode
  • PDA personal digital assistant
  • DSC digital still camera

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

A method of manufacturing a wafer level package according to the present invention comprises mutually joining a device wafer (20) having a plurality of device chips mounted or formed within the surface, and a cap wafer (30) opposite the device wafer (20) and thereafter singulating the joined wafer for each device. The method includes a first groove forming step of forming a first groove (23) for singulation at least in either the device wafer (20) or the cap wafer (30) and a joining step of joining the device wafer (20) and the cap wafer (30) sequentially in the order. Hereby, it is possible to provide a method of manufacturing a wafer level package and a wafer level package, which are capable of increasing the wafer yield and the product yield.

Description

ウエハレベルパッケージの製造方法、及びウエハレベルパッケージWafer level package manufacturing method and wafer level package
　本発明は、面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、デバイス毎に個片化されるウエハレベルパッケージの製造方法、及びウエハレベルパッケージに関するものであり、特に、ダイシングレス化を図り得るウエハレベルパッケージの製造方法、及びウエハレベルパッケージに関する。 In the present invention, after a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer are bonded to each other, they are separated into individual devices. The present invention relates to a wafer level package manufacturing method and a wafer level package, and more particularly to a wafer level package manufacturing method and a wafer level package capable of reducing dicing.
　半導体デバイスのパッケージ方法として、従来はモールドパッケージが主流であったが、近年はパッケージコストの削減、並びにパッケージ寸法の小型化が可能なウエハレベルパッケージがシェアを広げている。 Conventionally, a mold package has been mainly used as a packaging method for semiconductor devices, but in recent years, a wafer level package capable of reducing the package cost and reducing the size of the package has expanded the market share.
　このようなウエハレベルパッケージでは、面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、一般的にはダイシングによりデバイス毎に個片化されてウエハレベルパッケージが完成するものとなっている。 In such a wafer level package, after a first wafer on which a plurality of device chips are mounted or formed and a second wafer facing the first wafer are bonded to each other, generally, A wafer level package is completed by dicing into individual devices by dicing.
　ここで、ウエハレベルパッケージの製造においては、第１のウエハと第２のウエハとを接合した後にダイシングする。その際、第１のウエハと第２のウエハとの熱膨張係数差又はウエハ独自の有する応力によって反りが発生するので、反りが存在する状態でダイシングすると、ウエハ歩留まりや製品歩留まりが悪化する等の問題が発生する。 Here, in the manufacture of the wafer level package, dicing is performed after the first wafer and the second wafer are bonded. At that time, warpage occurs due to a difference in thermal expansion coefficient between the first wafer and the second wafer or a stress unique to the wafer, so that dicing in the presence of warpage deteriorates the wafer yield and product yield. A problem occurs.
　そこで、この問題を解決すべく、特許文献１に開示された半導体パッケージの製造方法では、図８（ａ）～（ｅ）に示すように、半導体ウエハ１０１とキャップウエハ１０３とを接合した後、半導体ウエハ１０１又はキャップウエハ１０３側からスクライブラインに沿ってハーフカット１０４し、横方向のチップ同士を部分的に分割する。ハーフカット１０４の入れ方は、例えば、図８（ａ）に示すキャップウエハ１０３の途中まで、図８（ｂ）に示すキャップウエハ１０３と接合層１０２との界面まで、図８（ｃ）に示す接合層１０２の途中まで、図８（ｄ）に示す接合層１０２と半導体ウエハ１０１との界面まで、及び図８（ｅ）に示す半導体ウエハ１０１の途中までの様式がある。これにより、カットされた基板の個片が孤島状に存在するようになるので、いずれの場合も接合基板の反り量が大幅に低減し、ウエハ歩留まりや製品歩留まりが向上するとしている。 Therefore, in order to solve this problem, in the method of manufacturing a semiconductor package disclosed in Patent Document 1, as shown in FIGS. 8A to 8E, after the semiconductor wafer 101 and the cap wafer 103 are bonded, A half cut 104 is performed along the scribe line from the semiconductor wafer 101 or cap wafer 103 side, and the chips in the horizontal direction are partially divided. For example, the half-cut 104 is inserted in the middle of the cap wafer 103 shown in FIG. 8A to the interface between the cap wafer 103 and the bonding layer 102 shown in FIG. 8B, as shown in FIG. There are formats up to the middle of the bonding layer 102, to the interface between the bonding layer 102 and the semiconductor wafer 101 shown in FIG. 8D, and to the middle of the semiconductor wafer 101 shown in FIG. 8E. Thereby, since the cut pieces of the substrate are present in the form of isolated islands, the warpage amount of the bonded substrate is greatly reduced in any case, and the wafer yield and the product yield are improved.
　また、例えば、特許文献２に開示された半導体装置の製造方法では、図９（ａ）～（ｆ）に示すように、圧電基板２０１の表面に弾性表面波デバイスパターン２０２を複数個形成する工程と、励振空間２０３を設けて保護体２０４で覆う工程と、レーザ光２０５を圧電基板２０１の内部及び保護体２０４に集光させて照射することにより圧電基板２０１の内部に改質領域２０６を形成すると共にレーザ光２０５を照射した部分の保護体２０４を除去して保護体除去部２０７を形成する工程と、圧電基板２０１の裏面側をグラインダー２０８にて研削することにより圧電基板２０１を薄板化する工程と、改質領域２０６で各デバイスに分離する工程とを備えたものからなっている。尚、励振空間２０３を設けて保護体２０４で覆う工程においては、詳細には、弾性表面波デバイスパターン２０２を囲み、かつ個片に分離した際の外周から全周に渡って間隔を設けて形成した側壁２１１を設け、励振空間２０３を覆い、同じく個片に分離した際の外周から全周に渡って間隔を設けて形成した天板２１２を設け、かつ弾性表面波デバイスパターン２０２に接続され外部に電気信号を取り出すための接続電極２１３を設け、圧電基板２０１の第１面側全体をエポキシ系樹脂からなる保護体２０４にて覆っている。また、改質領域２０６で各デバイスに分離する工程では、圧電基板２０１にピックアップシート２２０を貼り、ピックアップシート２２０を延伸することにより、改質領域２０６にて分離させることができるものとなっている。 Further, for example, in the method of manufacturing a semiconductor device disclosed in Patent Document 2, as shown in FIGS. 9A to 9F, a plurality of surface acoustic wave device patterns 202 are formed on the surface of the piezoelectric substrate 201. A step of providing an excitation space 203 and covering it with a protective body 204; and condensing and irradiating laser light 205 on the inside of the piezoelectric substrate 201 and the protective body 204 to form a modified region 206 inside the piezoelectric substrate 201. In addition, the step of removing the protective body 204 at the portion irradiated with the laser beam 205 to form the protective body removing portion 207 and the back surface side of the piezoelectric substrate 201 are ground by the grinder 208 to thin the piezoelectric substrate 201. It comprises a process and a process of separating each device in the modified region 206. In the step of providing the excitation space 203 and covering it with the protector 204, in detail, the surface acoustic wave device pattern 202 is surrounded and spaced from the outer periphery when separated into individual pieces. The side wall 211 is provided, the excitation space 203 is covered, and a top plate 212 is provided that is spaced from the outer periphery to the entire periphery when separated into individual pieces, and is connected to the surface acoustic wave device pattern 202 and externally provided. A connection electrode 213 for extracting an electric signal is provided on the first substrate, and the entire first surface side of the piezoelectric substrate 201 is covered with a protective body 204 made of an epoxy resin. Further, in the process of separating each device in the modified region 206, the pickup sheet 220 is attached to the piezoelectric substrate 201, and the pickup sheet 220 is stretched to be separated in the modified region 206. .
　すなわち、特許文献２に開示された半導体装置の製造方法では、レーザ光２０５を集光させて圧電基板２０１内に改質領域２０６を設けて個片化する。そして、同時にキャップである保護体２０４を構成するエポキシ樹脂にもレーザ光２０５を集光することによって、保護体除去部２０７を形成することができる。また、圧電基板２０１を薄くするためのグラインド工程時に、同時にデバイス分離できるものとなっている。 That is, in the method for manufacturing a semiconductor device disclosed in Patent Document 2, the laser beam 205 is condensed and the modified region 206 is provided in the piezoelectric substrate 201 to be separated into pieces. At the same time, the protective body removing portion 207 can be formed by condensing the laser beam 205 on the epoxy resin constituting the protective body 204 serving as a cap. Further, the device can be separated at the same time during the grinding process for thinning the piezoelectric substrate 201.
　この結果、従来の弾性表面波デバイスでは、小型化してもダイシングによる切り代で十分に量産性をあげることができなかったことを回避でき、ウエハ歩留まりや製品歩留まりが向上するようになっている。 As a result, in the conventional surface acoustic wave device, it is possible to avoid that the mass productivity cannot be sufficiently increased by the cutting margin by dicing even if the device is downsized, and the wafer yield and the product yield are improved.
　さらに、例えば、特許文献３に開示されたウエハレベルパッケージ３００の製造方法では、図１０（ａ）（ｂ）に示すように、デバイスチップ３０１の周りを樹脂からなる封止枠３０２にて気密封止されたデバイスを作製するためのものであり、各デバイスに個片化する場合には、封止枠３０２が形成されたデバイスウエハ３１０にキャップウエハ３２０を接合してから、封止枠３０２・３０２間をダイシング加工にて個片化するようになっている。 Furthermore, for example, in the method for manufacturing the wafer level package 300 disclosed in Patent Document 3, as shown in FIGS. 10A and 10B, the device chip 301 is hermetically sealed with a sealing frame 302 made of resin. In order to manufacture a device that has been stopped, when the device is separated into individual devices, the cap wafer 320 is bonded to the device wafer 310 on which the sealing frame 302 is formed, and then the sealing frame 302. 302 is divided into individual pieces by dicing.
　これにより、デバイスチップ３０１は封止枠３０２で隔離されているので、封止枠３０２・３０２間をダイシング加工した場合においても、ダイシング加工に伴うクラック発生がデバイスチップ３０１に影響するのを回避し、ウエハ歩留まりや製品歩留まりを向上させるものとなっている。 Thereby, since the device chip 301 is isolated by the sealing frame 302, even when the sealing frames 302 and 302 are diced, the occurrence of cracks due to the dicing processing is prevented from affecting the device chip 301. The wafer yield and the product yield are improved.
　さらに、例えば、特許文献４に開示された半導体装置の製造方法では、図１１（ａ）（ｂ）に示すように、半導体基板４０１上に形成される複数個の半導体装置を個々に隔てるスクライブライン用溝４０２と、半導体装置にスルーホール配線を施すためのスルーホール用溝４０３とをエッチングマスク４０４を用いてエッチングすることにより形成する。このとき、スクライブライン用溝４０２の幅をスルーホール用溝４０３の幅より狭くしておく。次いで、図１１（ｃ）に示すように、半導体基板４０１を裏面からスルーホール用溝４０３の底面に達する厚さまで削って薄層化半導体基板４０５とすることにより、スルーホール用溝４０３を貫通させた後、裏面金属配線板４０６及び金属配線４０７を形成する。次いで、図１１（ｄ）に示すように、薄層化半導体基板４０５の裏面に粘着性及び延伸性を有するシート４０８を貼付け、図１１（ｅ）に示すように、スクライブライン用溝４０２に沿って薄層化半導体基板４０５と裏面金属配線板４０６とをブレイク装置４１０を用いてスクライブライン４１１にて劈開し、図１１（ｆ）に示すように、シート４０８を延伸して半導体装置毎に分離する。 Further, for example, in the method of manufacturing a semiconductor device disclosed in Patent Document 4, as shown in FIGS. 11A and 11B, a scribe line that separates a plurality of semiconductor devices formed on a semiconductor substrate 401 individually. A trench 402 for use and a through-hole trench 403 for forming a through-hole wiring in the semiconductor device are formed by etching using an etching mask 404. At this time, the width of the scribe line groove 402 is made smaller than the width of the through hole groove 403. Next, as shown in FIG. 11C, the through hole groove 403 is penetrated by cutting the semiconductor substrate 401 to a thickness that reaches the bottom surface of the through hole groove 403 from the back surface to form a thinned semiconductor substrate 405. After that, the back metal wiring board 406 and the metal wiring 407 are formed. Next, as shown in FIG. 11 (d), a sheet 408 having adhesiveness and stretchability is attached to the back surface of the thinned semiconductor substrate 405, and along the scribe line groove 402 as shown in FIG. 11 (e). Then, the thinned semiconductor substrate 405 and the backside metal wiring board 406 are cleaved at the scribe line 411 using the break device 410, and the sheet 408 is stretched and separated for each semiconductor device as shown in FIG. To do.
　これにより、デバイスの取れ数を増加させる半導体装置の製造方法を提供するものとなっている。 This provides a method of manufacturing a semiconductor device that increases the number of devices that can be obtained.
日本国公開特許公報「特開２００９－１７７０３４号公報（２００９年８月６日公開）」Japanese Patent Publication “Japanese Unexamined Patent Application Publication No. 2009-177034 (released on August 6, 2009)” 日本国公開特許公報「特開２０１０－２１３１４４号公報（２０１０年９月２４日公開）」Japanese Patent Publication “Japanese Patent Laid-Open No. 2010-213144 (published on September 24, 2010)” 米国特許出願公開第２００９／０１９４８６１号明細書（２００９年８月６日公開）US Patent Application Publication No. 2009/0194861 (published Aug. 6, 2009) 日本国公開特許公報「特開２００２－１９８３２７号公報（２００２年７月１２日公開）」Japanese Patent Publication “Japanese Laid-Open Patent Publication No. 2002-198327 (released on July 12, 2002)”
　しかしながら、上記従来のウエハレベルパッケージの製造方法、及びウエハレベルパッケージでは、以下の問題点を有している。 However, the above conventional wafer level package manufacturing method and wafer level package have the following problems.
　まず、特許文献１に開示された半導体パッケージの製造方法では、半導体ウエハ１０１とキャップウエハ１０３とを接合した後、細くて深い溝を、一方向のみから２枚の基板に渡って形成するのは、処理時間が長くなるので生産性が悪いことや接合部付近の異種材料や空間の影響によって加工し難い等の課題がある。また、ダイシングでは、ダイシング代が必要となり、デバイスの取り数が減少するという問題点を有している。 First, in the semiconductor package manufacturing method disclosed in Patent Document 1, after joining the semiconductor wafer 101 and the cap wafer 103, a narrow and deep groove is formed across only two substrates from only one direction. However, since the processing time becomes long, there are problems such as poor productivity and difficulty in processing due to the influence of different materials and spaces near the joint. Further, dicing has a problem that a dicing cost is required and the number of devices is reduced.
　また、特許文献２に開示された半導体装置の製造方法は、ウエハレベルパッケージではない。このため、２枚の基板を貼り合わせるウエハレベルパッケージに適用する場合には、上下の基板とも改質しなければならず、工数が増えるという問題点を有している。さらに、最終的には基板を割る工程となっているので、クラック、欠け等により封止不良の原因となるという問題点を有している。 Also, the semiconductor device manufacturing method disclosed in Patent Document 2 is not a wafer level package. For this reason, when applied to a wafer level package in which two substrates are bonded together, both the upper and lower substrates must be modified, which increases the number of steps. Further, since the process is finally a cracking of the substrate, there is a problem that it causes a sealing failure due to a crack, a chip or the like.
　さらに、特許文献３に開示されたウエハレベルパッケージ３００の製造方法では、ダイシングにて個片化するため、ダイシング代が必要となる。したがって、その点で、ウエハ歩留まりや製品歩留まりの向上が十分でないという問題点を有している。 Furthermore, in the manufacturing method of the wafer level package 300 disclosed in Patent Document 3, dicing is required because dicing into individual pieces. Therefore, in this respect, there is a problem that improvement in wafer yield and product yield is not sufficient.
　また、特許文献４に開示された半導体装置の製造方法をウエハレベルパッケージの製造方法に適用する場合には、図１２に示すように、図１１（ｃ）に示す薄層化半導体基板４０５・４０５をそれぞれ貼り合わせることになる。しかし、その場合、接合時の荷重により溝が深い場合にはブレイクが起き易くなるという問題点を有している。また、貼りあわせた後に、表面の薄層化半導体基板４０５と裏面の薄層化半導体基板４０５との２回のブレイクが必要となり、工数が増加する。 When the semiconductor device manufacturing method disclosed in Patent Document 4 is applied to a wafer level package manufacturing method, as shown in FIG. 12, the thinned semiconductor substrates 405 and 405 shown in FIG. Will be pasted together. However, in this case, there is a problem that breakage is likely to occur when the groove is deep due to the load at the time of joining. Further, after bonding, two breaks are required for the thin semiconductor substrate 405 on the front surface and the thin semiconductor substrate 405 on the back surface, which increases the number of steps.
　本発明は、上記従来の問題点に鑑みなされたものであって、その目的は、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージの製造方法、及びウエハレベルパッケージを提供することにある。 The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a wafer level package manufacturing method and a wafer level package capable of improving the wafer yield and the product yield.
　本発明のウエハレベルパッケージの製造方法は、上記課題を解決するために、面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、デバイス毎に個片化されるウエハレベルパッケージの製造方法において、上記第１のウエハと第２のウエハとの少なくとも一方に個片化するための第１溝を形成する第１溝形成工程と、上記第１のウエハと第２のウエハとを接合する接合工程とをこの順に含んでいることを特徴としている。 In order to solve the above problems, a method for manufacturing a wafer level package of the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane, and a second wafer that faces the first wafer. In the method of manufacturing a wafer level package in which each device is separated after being bonded to each other, a first groove for separating into at least one of the first wafer and the second wafer is formed. The method includes a first groove forming step and a bonding step for bonding the first wafer and the second wafer in this order.
　本発明のウエハレベルパッケージは、面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、デバイス毎に個片化されたウエハレベルパッケージにおいて、上記第１のウエハと第２のウエハとの少なくとも一方には、デバイス毎に個片化するために形成された第１溝が設けられていることを特徴としている。 The wafer level package according to the present invention includes a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer, and then bonded to each device. In the singulated wafer level package, at least one of the first wafer and the second wafer is provided with a first groove formed for singulation for each device. Yes.
　上記の発明によれば、ウエハレベルパッケージを製造する場合には、第１溝形成工程にて、第１のウエハと第２のウエハとの少なくとも一方に個片化するための第１溝を形成する。次いで、接合工程により、第１のウエハと第２のウエハとを接合する。 According to the above invention, when manufacturing a wafer level package, the first groove for separating into at least one of the first wafer and the second wafer is formed in the first groove forming step. To do. Next, the first wafer and the second wafer are bonded by a bonding process.
　この結果、第１のウエハと第２のウエハとを貼り合わせることにより封止されるウエハレベルパッケージを作製する工程において、個々のウエハレベルパッケージを切り離すための第１溝が、第１のウエハと第２のウエハとを貼り合わせる前に予め形成されている。 As a result, in the step of manufacturing a wafer level package to be sealed by bonding the first wafer and the second wafer, the first groove for separating the individual wafer level packages is formed with the first wafer. It is formed in advance before bonding with the second wafer.
　すなわち、第１溝が存在しない状態で第１のウエハと第２のウエハとを接合したものをダイシングする場合には、反りの影響を受けて、寸法精度が悪くなり、ウエハ歩留まり及び製品歩留まりが悪化する。 That is, when dicing a bonded first wafer and second wafer in the absence of the first groove, the dimensional accuracy deteriorates due to the influence of warpage, and the wafer yield and product yield are increased. Getting worse.
　この点、本発明では、接合前に第１のウエハと第２のウエハとの少なくとも一方に個片化するための第１溝が形成されているので、第１溝の緩衝作用により反りを軽減した状態で接合することができる。 In this regard, in the present invention, since the first groove for separating into at least one of the first wafer and the second wafer is formed before bonding, warping is reduced by the buffering action of the first groove. It can be joined in the state.
　したがって、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージの製造方法、及びウエハレベルパッケージを提供することができる。 Therefore, it is possible to provide a wafer level package manufacturing method and a wafer level package that can improve the wafer yield and the product yield.
　本発明のウエハレベルパッケージの製造方法は、以上のように、第１のウエハと第２のウエハとの少なくとも一方に個片化するための第１溝を形成する第１溝形成工程と、上記第１のウエハと第２のウエハとを接合する接合工程とをこの順に含んでいる方法である。 As described above, the method for manufacturing a wafer level package according to the present invention includes a first groove forming step for forming a first groove for separating at least one of the first wafer and the second wafer, This is a method including a bonding step for bonding the first wafer and the second wafer in this order.
　本発明のウエハレベルパッケージは、第１のウエハと第２のウエハとの少なくとも一方には、デバイス毎に個片化するために形成された第１溝が設けられているものである。 In the wafer level package of the present invention, at least one of the first wafer and the second wafer is provided with a first groove formed for individual device separation.
　それゆえ、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージの製造方法、及びウエハレベルパッケージを提供するという効果を奏する。 Therefore, it is possible to provide a method for manufacturing a wafer level package capable of improving the wafer yield and the product yield, and to provide the wafer level package.
（ａ）～（ｅ）は、本発明におけるウエハレベルパッケージの製造方法の実施の一形態を示すものであって、ウエハレベルパッケージの製造工程を示す断面図である。FIGS. 4A to 4E are cross-sectional views showing an embodiment of a method for manufacturing a wafer level package according to the present invention and showing a manufacturing process of the wafer level package. FIGS. 個片化された上記ウエハレベルパッケージの構成を示す斜視図である。It is a perspective view which shows the structure of the said wafer level package separated into pieces. 上記ウエハレベルパッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the said wafer level package. （ａ）～（ｅ）は、上記ウエハレベルパッケージの製造方法の変形例の製造工程を示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing process of the modification of the manufacturing method of the said wafer level package. （ａ）～（ｅ）は、上記ウエハレベルパッケージの製造方法の他の変形例の製造工程を示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package. （ａ）～（ｅ）は、上記ウエハレベルパッケージの製造方法の他の変形例の製造工程を示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing process of the other modification of the manufacturing method of the said wafer level package. （ａ）本実施の形態のウエハレベルパッケージの製造方法によるデバイスチップとスクライブラインとの関係を示す平面図であり、（ｂ）は従来のウエハレベルパッケージの製造方法によるデバイスチップとダイシンブラインとの関係を示す平面図である。(A) It is a top view which shows the relationship between the device chip and scribe line by the manufacturing method of the wafer level package of this Embodiment, (b) is the device chip and die thin line by the manufacturing method of the conventional wafer level package It is a top view which shows a relationship. （ａ）～（ｅ）は、従来のウエハレベルパッケージの製造方法を示す断面図である。(A)-(e) is sectional drawing which shows the manufacturing method of the conventional wafer level package. （ａ）～（ｆ）は、従来の半導体装置の製造方法を示す断面図である。(A)-(f) is sectional drawing which shows the manufacturing method of the conventional semiconductor device. （ａ）は、従来の他のウエハレベルパッケージの製造方法を示す平面図であり、（ｂ）はその断面図である。(A) is a top view which shows the manufacturing method of the other conventional wafer level package, (b) is the sectional drawing. （ａ）～（ｆ）は、従来の他の半導体装置の製造方法を示す断面図である。(A)-(f) is sectional drawing which shows the manufacturing method of the other conventional semiconductor device. 上記図１１に示す従来の他の半導体装置を２枚貼り合わせたウエハレベルパッケージの構成を示す断面図である。It is sectional drawing which shows the structure of the wafer level package which bonded together two other conventional semiconductor devices shown in the said FIG.
　本発明の一実施形態について図１～図７に基づいて説明すれば、以下のとおりである。 An embodiment of the present invention will be described with reference to FIGS. 1 to 7 as follows.
　本実施の形態のウエハレベルパッケージの構成について、図２及び図３に基づいて説明する。図２は個片化されたウエハレベルパッケージの構成を示す斜視図であり、図２は個片化される前のウエハレベルパッケージの構成を示す断面図である。 The configuration of the wafer level package according to the present embodiment will be described with reference to FIGS. FIG. 2 is a perspective view showing a configuration of a wafer level package separated into pieces, and FIG. 2 is a cross-sectional view showing a configuration of the wafer level package before being separated into pieces.
　本実施の形態のウエハレベルパッケージ１０は、図２に示すように、後述するデバイスチップ１を搭載又は形成した基部２と、その上を覆うキャップ部３とを接合したものからなっている。上記ウエハレベルパッケージ１０は、例えば、キャップ部３にスルーホール５が形成されており、デバイスチップ１が、スルーホール５に形成された配線、及びキャップ部３の表面に設けられた配線パターン６を介して図示しない外部に設けられた外部機器に電気的に接続されるようになっている。したがって、本実施の形態のウエハレベルパッケージ１０は、シリコン貫通電極（ＴＳＶ：Through-Silicon via）により、信号の受け渡しを行うものとなっている。尚、本実施の形態では、このように、シリコン貫通電極（ＴＳＶ：Through-Silicon via）を採用していることが好ましいが、本発明においては必ずしもこれに限らない。 As shown in FIG. 2, the wafer level package 10 of the present embodiment is formed by joining a base portion 2 on which a device chip 1 described later is mounted or formed and a cap portion 3 covering the base portion 2. In the wafer level package 10, for example, a through hole 5 is formed in the cap portion 3, and the device chip 1 has a wiring formed in the through hole 5 and a wiring pattern 6 provided on the surface of the cap portion 3. It is electrically connected to an external device provided outside (not shown). Therefore, the wafer level package 10 according to the present embodiment performs signal transfer using a through silicon via (TSV). In the present embodiment, it is preferable to employ a through silicon via (TSV) as described above. However, the present invention is not limited to this.
　また、本実施の形態のウエハレベルパッケージ１０では、デバイスチップ１は、例えば、スイッチ接点部からなっている。しかし、本発明においては必ずしもこれに限らず、他のデバイス又は電子回路等のチップであればよい。 Further, in the wafer level package 10 of the present embodiment, the device chip 1 is composed of, for example, a switch contact portion. However, the present invention is not necessarily limited to this, and any other device or chip such as an electronic circuit may be used.
　上記ウエハレベルパッケージ１０は、図３に示すように、面内に複数のデバイスチップ１が搭載又は形成された第１のウエハとしてのデバイスウエハ２０と該デバイスウエハ２０に対向する第２のウエハとしてのキャップウエハ３０とが互いに接合された後、デバイス毎に個片化されるものからなっている。すなわち、本実施の形態のウエハレベルパッケージ１０は、ウエハプロセスにて再配線や電極形成、樹脂封止及び個片化までを全て行い、最終的にウエハを切断したデバイスチップ１の大きさがそのままパッケージの大きさとなるものである。このため、ウエハレベルパッケージは、小型化及び軽量化の観点からも理想的であるといえ、このように、本実施の形態のウエハレベルパッケージ１０は、例えば、携帯電話等の電子機器に採用されるマイクロエレクトロメカニカルシステム（ＭＥＭＳ）構造であればよい。 As shown in FIG. 3, the wafer level package 10 includes a device wafer 20 as a first wafer on which a plurality of device chips 1 are mounted or formed in a plane, and a second wafer facing the device wafer 20. After the cap wafer 30 is bonded to each other, each device is separated into individual pieces. That is, the wafer level package 10 according to the present embodiment performs all the processes up to rewiring, electrode formation, resin sealing, and singulation in the wafer process, and the size of the device chip 1 that finally cut the wafer remains as it is. It is the size of the package. Therefore, it can be said that the wafer level package is ideal from the viewpoint of miniaturization and weight reduction. As described above, the wafer level package 10 of the present embodiment is adopted in an electronic device such as a mobile phone. Any micro electro mechanical system (MEMS) structure may be used.
　上記デバイスウエハ２０はシリコン（Ｓｉ）からなるウエハが積層されたものからなっており、各層のウエハには絶縁膜２１が形成されている。そして、上側のウエハの表面に形成された絶縁膜２１の上には、複数のデバイスチップ１が搭載されている。また、キャップウエハ３０もシリコン（Ｓｉ）からなっており、その表面には絶縁膜３１が形成されている。そして、上記デバイスチップ１は、前述したように、キャップウエハ３０に形成されたスルーホール５、配線パターン６及びバンプ７を介して外部機器に電気的に接続されるようになっている。また、デバイスウエハ２０における下層のウエハには、スイッチ可動部２２が設けられている。 The device wafer 20 is formed by stacking silicon (Si) wafers, and an insulating film 21 is formed on each layer of wafers. A plurality of device chips 1 are mounted on the insulating film 21 formed on the surface of the upper wafer. The cap wafer 30 is also made of silicon (Si), and an insulating film 31 is formed on the surface thereof. The device chip 1 is electrically connected to an external device through the through hole 5, the wiring pattern 6 and the bump 7 formed in the cap wafer 30 as described above. In addition, a switch movable portion 22 is provided on the lower wafer of the device wafer 20.
　上記デバイスチップ１の周りには枠状の接合封止部４が形成されており、これによって、各デバイスチップ１は接合封止部４及び上下のデバイスウエハ２０及びキャップウエハ３０によって、封止されている。また、デバイスウエハ２０とキャップウエハ３０とは、シリコン（Ｓｉ）－シリコン（Ｓｉ）接合又はシリコン（Ｓｉ）－二酸化シリコン（ＳｉＯ２ ）接合にて接合することが可能である。また、金属、ガラスフリット又は樹脂からなる接合材としての接合封止部４、又は金属、ガラスフリット又は樹脂からなる図示しない他の接合材であってもよい。 Around the device chip 1, a frame-like bonding / sealing portion 4 is formed, whereby each device chip 1 is sealed by the bonding / sealing portion 4, the upper and lower device wafers 20, and the cap wafer 30. ing. The device wafer 20 and the cap wafer 30 can be bonded by a silicon (Si) -silicon (Si) bond or a silicon (Si) -silicon dioxide (SiO 2 ) bond. Moreover, the joining sealing part 4 as a joining material which consists of a metal, glass frit, or resin, or the other joining material which is not shown which consists of a metal, glass frit, or resin may be sufficient.
　上記デバイスチップ１と接合封止部４との間は、デバイスチップ１が気密封止されるものであれば、完全な真空であっても、不活性気体又は他の樹脂等の物質に満たされたものであってもよい。 As long as the device chip 1 is hermetically sealed between the device chip 1 and the bonding sealing portion 4, the device chip 1 is filled with a substance such as an inert gas or other resin even in a complete vacuum. It may be.
　ここで、本実施の形態のウエハレベルパッケージ１０には、例えば、デバイスウエハ２０には、デバイス毎に個片化するために形成された第１溝２３が設けられている。また、第１溝２３が形成されたデバイスウエハ２０とは異なる他方のキャップウエハ３０には、接合後にダイシング以外で形成された個片化するための帯状貫通開口３２が設けられている。すなわち、帯状貫通開口３２は、キャップウエハ３０の下面まで形成されている。このため、帯状貫通開口３２は、キャップウエハ３０において底のない帯状貫通開口となっている。尚、本発明においては、必ずしもこれに限らず、キャップウエハ３０において底が存在する帯状開口である図示しない第２溝であってもよい。これにより、必ずしも帯状貫通開口でなくても、有底帯状開口である第２溝とすることによっても、後述するように、スクライブ等によってウエハレベルパッケージ１０を個片化することが可能である。 Here, in the wafer level package 10 of the present embodiment, for example, the device wafer 20 is provided with a first groove 23 formed to be separated for each device. Further, the other cap wafer 30 different from the device wafer 20 in which the first groove 23 is formed is provided with a band-shaped through-opening 32 that is formed by other than dicing after bonding. That is, the band-shaped through opening 32 is formed up to the lower surface of the cap wafer 30. For this reason, the band-shaped through opening 32 is a band-shaped through opening having no bottom in the cap wafer 30. In the present invention, the present invention is not necessarily limited to this, and a second groove (not shown) that is a band-like opening having a bottom in the cap wafer 30 may be used. As a result, the wafer level package 10 can be singulated by scribing or the like, as will be described later, even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening.
　また、本実施の形態では、第１溝２３はデバイスウエハ２０に設けられると共に、帯状貫通開口３２はキャップウエハ３０に設けられている。しかしながら、本発明においては、必ずしもこれに限らず、例えば、第１溝２３がキャップウエハ３０に設けられると共に、帯状貫通開口３２がデバイスウエハ２０に設けられたものであってもよい。 In the present embodiment, the first groove 23 is provided in the device wafer 20, and the band-shaped through opening 32 is provided in the cap wafer 30. However, the present invention is not limited to this, and for example, the first groove 23 may be provided in the cap wafer 30 and the band-shaped through opening 32 may be provided in the device wafer 20.
　次に、上記構成のウエハレベルパッケージ１０の製造方法について、図１（ａ）～（ｅ）に基づいて、以下に説明する。図１（ａ）～（ｅ）は、ウエハレベルパッケージ１０の製造工程を示す断面図である。 Next, a method for manufacturing the wafer level package 10 having the above configuration will be described below with reference to FIGS. 1 (a) to 1 (e). FIGS. 1A to 1E are cross-sectional views showing manufacturing steps of the wafer level package 10.
　本実施の形態では、図１（ａ）に示すように、最初に、第１溝形成工程において、デバイスウエハ２０の表面に第１溝２３を形成しておく。この第１溝２３は、有底の帯状開口であり、例えば、ドライエッチング又はレーザにより形成する。ドライエッチングの場合には、ドライエッチングマスクが使用される。この第１溝２３の幅は、個片化するために従来一般的に使用されているダイシング法におけるディスクカッターのディスク幅よりも狭いものとなっている。 In the present embodiment, as shown in FIG. 1A, first, the first groove 23 is formed on the surface of the device wafer 20 in the first groove forming step. The first groove 23 is a bottomed band-shaped opening and is formed by, for example, dry etching or laser. In the case of dry etching, a dry etching mask is used. The width of the first groove 23 is narrower than the disk width of a disk cutter in a dicing method that is generally used in the past to separate the first groove 23.
　そして、接合工程において、第１溝２３が形成されたデバイスウエハ２０とキャップウエハ３０とを接合する。この接合においては、デバイスウエハ２０の第１溝２３がキャップウエハ３０に対向するように接合する。接合方法は、金属、ガラスフリット又は樹脂からなる接合材を使用することができると共に、シリコン（Ｓｉ）－シリコン（Ｓｉ）接合又はシリコン（Ｓｉ）－二酸化シリコン（ＳｉＯ２ ）接合にて接合することも可能である。 In the bonding step, the device wafer 20 on which the first groove 23 is formed and the cap wafer 30 are bonded. In this bonding, bonding is performed so that the first groove 23 of the device wafer 20 faces the cap wafer 30. As a bonding method, a bonding material made of metal, glass frit, or resin can be used, and bonding is performed by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding. Is also possible.
　次に、図１（ｂ）に示すように、キャップウエハ３０の裏面（図１（ｂ）においては上面）を図示しないグラインダー又はエッチングにて薄ウエハ化する。 Next, as shown in FIG. 1B, the back surface of the cap wafer 30 (the upper surface in FIG. 1B) is thinned by a grinder or etching not shown.
　次に、図１（ｃ）に示すように、キャップウエハ３０に例えばドライエッチングにてスルーホール５を形成する。このとき、本実施の形態では、第２溝形成工程として帯状貫通開口３２も一緒にドライエッチングにて形成する。この帯状貫通開口３２は、キャップウエハ３０を貫通する帯状開口であり、デバイスウエハ２０に形成された第１溝２３と同一直線上となるように配されている。この帯状貫通開口３２は、スルーホール５と一緒に形成されるので、効率よく形成することができる。尚、帯状貫通開口３２の形成は、例えばドライエッチングにて行っているが、必ずしもこれに限らず、レーザを使用することも可能である。すなわち、ダイシング法以外の方法であればよい。その理由は、ダイシング法よりも切り代を狭くできるからである。 Next, as shown in FIG. 1C, the through hole 5 is formed in the cap wafer 30 by, for example, dry etching. At this time, in the present embodiment, the band-shaped through opening 32 is also formed by dry etching together as the second groove forming step. The band-shaped through opening 32 is a band-shaped opening that penetrates the cap wafer 30 and is arranged so as to be collinear with the first groove 23 formed in the device wafer 20. Since the band-shaped through opening 32 is formed together with the through hole 5, it can be efficiently formed. The formation of the band-shaped through opening 32 is performed by dry etching, for example. However, the present invention is not limited to this, and a laser can also be used. That is, any method other than the dicing method may be used. The reason is that the cutting allowance can be made narrower than the dicing method.
　次いで、図１（ｄ）に示すように、キャップウエハ３０のスルーホール５に、金属貫通配線を形成し、図示しない前記配線パターン６を形成する。 Next, as shown in FIG. 1D, metal through-wiring is formed in the through hole 5 of the cap wafer 30, and the wiring pattern 6 (not shown) is formed.
　次いで、図１（ｅ）に示すように、第１溝露出工程において、第１溝２３を露出させ、これによって、ウエハレベルパッケージ１０を個片化する。このウエハレベルパッケージ１０を個片化する方法は、各種存在する。 Next, as shown in FIG. 1E, in the first groove exposing step, the first groove 23 is exposed, whereby the wafer level package 10 is singulated. There are various methods for dividing the wafer level package 10 into individual pieces.
　例えば、図１（ｅ）に示すように、デバイスウエハ２０における第１溝２３の裏面から該第１溝２３の対向位置に沿ってスクライブすることにより、スクライブライン２４にて、切断することができる。スクライブに際しては、目印として図示しない尖った器具で線等を刻み付け、折曲等することによって第１溝２３に沿ってウエハレベルパッケージ１０を切断することができる。すなわち、ウエハレベルパッケージ１０の厚さは、例えば、キャップウエハ３０が例えば１５０μｍ、デバイスウエハ２０が２００μｍ、キャップウエハ３０とデバイスウエハ２０との間が６０μｍである。そして、キャップウエハ３０には帯状貫通開口３２が形成されており、かつデバイスウエハ２０の厚さの途中まで第１溝２３が形成されている。したがって、ウエハレベルパッケージ１０の厚さ方向において、連結されているのは、キャップウエハ３０とデバイスウエハ２０との間の６０μｍと、デバイスウエハ２０の一部である。したがって、この厚さであればスクライブ法により、容易にウエハレベルパッケージ１０を切断することができる。 For example, as shown in FIG. 1E, by scribing from the back surface of the first groove 23 in the device wafer 20 along the opposing position of the first groove 23, the device wafer 20 can be cut along the scribe line 24. . At the time of scribing, the wafer level package 10 can be cut along the first groove 23 by marking a line or the like with a sharp tool (not shown) as a mark and bending the mark. That is, the thickness of the wafer level package 10 is, for example, 150 μm for the cap wafer 30, 200 μm for the device wafer 20, and 60 μm between the cap wafer 30 and the device wafer 20. A band-shaped through opening 32 is formed in the cap wafer 30, and the first groove 23 is formed halfway through the thickness of the device wafer 20. Therefore, in the thickness direction of the wafer level package 10, 60 μm between the cap wafer 30 and the device wafer 20 and a part of the device wafer 20 are connected. Therefore, with this thickness, the wafer level package 10 can be easily cut by a scribe method.
　この場合、デバイスウエハ２０の裏面には、図示しないシートが貼られているので、このシートを延伸することにより、ウエハレベルパッケージ１０を個片化させることができる。 In this case, since a sheet (not shown) is pasted on the back surface of the device wafer 20, the wafer level package 10 can be separated into pieces by stretching the sheet.
　尚、第１溝露出工程において、第１溝２３を露出させ、ウエハレベルパッケージ１０を個片化する方法は、必ずしもこれに限らない。 In the first groove exposing step, the method of exposing the first groove 23 and dividing the wafer level package 10 into pieces is not necessarily limited to this.
　例えば、図４（ａ）～（ｅ）に示すように、第１溝露出工程において、第１溝２３が形成されたデバイスウエハ２０における第１溝２３を境界として該接合されたデバイスウエハ２０及びキャップウエハ３０を両側へ延伸させることにより、切断面２５にて第１溝２３を露出させることが可能である。 For example, as shown in FIGS. 4A to 4E, in the first groove exposing step, the device wafer 20 bonded with the first groove 23 as a boundary in the device wafer 20 in which the first groove 23 is formed, and The first groove 23 can be exposed at the cut surface 25 by extending the cap wafer 30 to both sides.
　また、例えば、図５（ａ）～（ｅ）に示すように、第１溝露出工程において、第１溝２３が形成されたデバイスウエハ２０における第１溝２３の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化した薄化デバイスウエハ２０ａとすることにより、第１溝２３を露出させることができる。 Further, for example, as shown in FIGS. 5A to 5E, in the first groove exposing step, the back surface side of the first groove 23 in the device wafer 20 in which the first groove 23 is formed is ground, polished, or The first groove 23 can be exposed by forming a thinned device wafer 20a that has been thinned by etching.
　さらに、例えば、図６（ａ）～（ｅ）に示すように、第１溝露出工程において、第１溝２３が形成されたデバイスウエハ２０における第１溝２３の裏面側から第１溝２３までをハーフダイス２６することにより、第１溝２３を露出させることができる。尚、ハーフダイス２６とは、ダイシングに用いるディスクカッターにて、溝が形成されたデバイスウエハ２０における第１溝２３の裏面側から第１溝２３までを切断することをいう。 Further, for example, as shown in FIGS. 6A to 6E, from the back surface side of the first groove 23 to the first groove 23 in the device wafer 20 in which the first groove 23 is formed in the first groove exposing step. The half groove 26 is used to expose the first groove 23. Note that the half die 26 refers to cutting from the back surface side of the first groove 23 to the first groove 23 in the device wafer 20 in which the groove is formed by a disk cutter used for dicing.
　このように、本実施の形態のウエハレベルパッケージ１０の製造方法は、面内に複数のデバイスチップ１が搭載又は形成されたデバイスウエハ２０と該デバイスウエハ２０に対向するキャップウエハ３０とが互いに接合された後、デバイス毎に個片化される。そして、デバイスウエハ２０とキャップウエハ３０との少なくとも一方に個片化するための第１溝２３を形成する第１溝形成工程と、デバイスウエハ２０とキャップウエハ３０とを接合する接合工程とをこの順に含んでいる。 As described above, in the method of manufacturing the wafer level package 10 according to the present embodiment, the device wafer 20 on which the plurality of device chips 1 are mounted or formed in the surface and the cap wafer 30 facing the device wafer 20 are bonded to each other. After that, it is separated into pieces for each device. Then, the first groove forming step for forming the first groove 23 to be separated into at least one of the device wafer 20 and the cap wafer 30 and the bonding step for bonding the device wafer 20 and the cap wafer 30 are performed. Includes in order.
　また、本実施の形態のウエハレベルパッケージ１０は、面内に複数のデバイスチップ１が搭載又は形成されたデバイスウエハ２０と該デバイスウエハ２０に対向するキャップウエハ３０とが互いに接合された後、デバイス毎に個片化されている。そして、デバイスウエハ２０とキャップウエハ３０との少なくとも一方には、デバイス毎に個片化するために形成された第１溝２３が設けられている。 In addition, the wafer level package 10 according to the present embodiment includes a device wafer 20 on which a plurality of device chips 1 are mounted or formed in a plane and a cap wafer 30 facing the device wafer 20, and then bonded to the device wafer 20. Each piece is separated. At least one of the device wafer 20 and the cap wafer 30 is provided with a first groove 23 that is formed to be separated into individual devices.
　上記構成によれば、ウエハレベルパッケージ１０を製造する場合には、第１溝形成工程にて、デバイスウエハ２０とキャップウエハ３０との少なくとも一方に個片化するための第１溝２３を形成する。次いで、接合工程により、デバイスウエハ２０とキャップウエハ３０とを接合する。 According to the above configuration, when the wafer level package 10 is manufactured, the first groove 23 for separating into at least one of the device wafer 20 and the cap wafer 30 is formed in the first groove forming step. . Next, the device wafer 20 and the cap wafer 30 are bonded by a bonding process.
　この結果、デバイスウエハ２０とキャップウエハ３０とを貼り合わせることにより封止されるウエハレベルパッケージ１０を作製する工程において、個々のウエハレベルパッケージ１０を切り離すための第１溝２３が、デバイスウエハ２０とキャップウエハ３０とを貼り合わせる前に予め形成されている。 As a result, in the process of manufacturing the wafer level package 10 to be sealed by bonding the device wafer 20 and the cap wafer 30, the first groove 23 for separating the individual wafer level package 10 is formed with the device wafer 20. It is formed in advance before bonding the cap wafer 30 together.
　すなわち、第１溝２３が存在しない状態でデバイスウエハ２０とキャップウエハ３０とを接合したものをダイシングする場合には、反りの影響を受けて、寸法精度が悪くなり、ウエハ歩留まり及び製品歩留まりが悪化する。この反りが発生する要因は、熱膨張係数差又はウエハが有する応力による。ウエハが有する応力とは、具体的には、例えば、接合用のメタルや絶縁膜、配線のメタル等をウエハ上に形成していることによって生じるそれらの膜が持つ応力のことである。また、ウエハの厚みや、デバイスウエハ２０に用いられているＳＯＩ構造（シリコン（Ｓｉ）の中間に絶縁膜を持つ構造）のウエハも反りに起因する要素となる。接合用のメタルや絶縁膜、配線のメタル等をウエハに形成する際、それらの膜にそれぞれ内部応力が保持されており、それらの膜毎に保持される内部応力も異なっている。そのため、層間での応力差により、反りが発生する。 That is, in the case where the device wafer 20 and the cap wafer 30 bonded together without the first groove 23 are diced, the dimensional accuracy deteriorates due to the influence of warpage, and the wafer yield and the product yield deteriorate. To do. The cause of this warpage is due to the difference in thermal expansion coefficient or the stress that the wafer has. Specifically, the stress possessed by the wafer is, for example, the stress possessed by the films formed by forming a bonding metal, an insulating film, a wiring metal, or the like on the wafer. In addition, the wafer thickness and the wafer having an SOI structure (a structure having an insulating film in the middle of silicon (Si)) used for the device wafer 20 are also caused by warpage. When a bonding metal, an insulating film, a wiring metal, or the like is formed on a wafer, internal stresses are held in these films, and the internal stress held for each film is also different. For this reason, warping occurs due to the stress difference between the layers.
　この点、本実施の形態では、接合前にデバイスウエハ２０とキャップウエハ３０との少なくとも一方に個片化するための第１溝２３が形成されているので、第１溝２３の緩衝作用により反りを軽減した状態で接合することができる。 In this respect, in the present embodiment, since the first groove 23 for separating the device wafer 20 and the cap wafer 30 is formed in at least one of the device wafer 20 and the cap wafer 30 before bonding, the first groove 23 warps due to the buffering action. It is possible to join in a state where it is reduced.
　尚、本実施の形態において、例えば、接合前にデバイスウエハ２０とキャップウエハ３０との両方に個片化するための第１溝２３を形成しておくことが可能である。この場合、
少なくともデバイスウエハ２０に第１溝２３を形成しておくことによって、接合後にデバイスウエハ２０及びキャップウエハ３０を両側に延伸すること等により個片化しても、デバイス面へのクラックや欠けの発生を防止することができる。また、第１溝２３の深さを浅くしておくことによって、接合時のブレイクも防止できる。 In the present embodiment, for example, it is possible to form the first groove 23 to be separated into both the device wafer 20 and the cap wafer 30 before bonding. in this case,
By forming the first groove 23 in at least the device wafer 20, even if the device wafer 20 and the cap wafer 30 are separated into individual pieces by extending to both sides after bonding, cracks and chips on the device surface are not generated. Can be prevented. Moreover, by making the depth of the first groove 23 shallow, it is possible to prevent breakage during bonding.
　したがって、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージ１０の製造方法、及びウエハレベルパッケージ１０を提供することができる。 Therefore, it is possible to provide a method for manufacturing the wafer level package 10 and the wafer level package 10 that can improve the wafer yield and the product yield.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、第１溝形成工程では、第１溝２３はデバイスウエハ２０とキャップウエハ３０とのいずれか一方に形成されていると共に、接合工程の後、第１溝２３を形成したデバイスウエハ２０とキャップウエハ３０とのいずれか一方とは異なる他方のキャップウエハ３０又はデバイスウエハ２０にも個片化するための帯状貫通開口３２又は第２溝をダイシング以外で形成する第２溝形成工程を含んでいる。 Further, in the method for manufacturing the wafer level package 10 of the present embodiment, in the first groove forming step, the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30 and in the bonding step. After that, the band-shaped through-opening 32 or the second groove for separating the device wafer 20 into the other cap wafer 30 or the device wafer 20 different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is formed. A second groove forming step for forming other than dicing is included.
　さらに、本実施の形態のウエハレベルパッケージ１０は、第１溝２３はデバイスウエハ２０とキャップウエハ３０とのいずれか一方に形成されていると共に、第１溝２３が形成されたデバイスウエハ２０とキャップウエハ３０とのいずれか一方とは異なる他方のキャップウエハ３０又はデバイスウエハ２０には、接合後にダイシング以外で形成された個片化するための帯状貫通開口３２又は第２溝が設けられていることが好ましい。尚、第２溝は有底帯状開口であり、帯状貫通開口３２は、無底のものをいう。また、必ずしも帯状貫通開口３２でなくても、有底帯状開口である第２溝とすることによっても、スクライブ等によってウエハレベルパッケージ１０を個片化することは可能である。さらに、ダイシング以外での帯状貫通開口３２又は第２溝の形成方法としては、例えば、エッチング又はレーザにて穿孔する方法がある。 Furthermore, in the wafer level package 10 of the present embodiment, the first groove 23 is formed in one of the device wafer 20 and the cap wafer 30, and the device wafer 20 and the cap in which the first groove 23 is formed. The other cap wafer 30 or device wafer 20 that is different from any one of the wafers 30 is provided with a band-shaped through-opening 32 or a second groove to be separated into pieces formed after bonding other than dicing. Is preferred. The second groove is a bottomed belt-like opening, and the belt-like through opening 32 is a bottomless one. In addition, the wafer level package 10 can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through opening 32. Further, as a method of forming the band-like through opening 32 or the second groove other than dicing, there is a method of drilling by etching or laser, for example.
　これにより、第２溝形成工程にて、第１溝２３を形成したデバイスウエハ２０とキャップウエハ３０とのいずれか一方とは異なる他方のキャップウエハ３０又はデバイスウエハ２０にも個片化するための帯状貫通開口３２又は第２溝をダイシング以外で形成する。 Accordingly, in the second groove forming step, the device wafer 20 and the device wafer 20 that are different from either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed are separated into pieces. The band-shaped through opening 32 or the second groove is formed by other than dicing.
　この結果、接合されたデバイスウエハ２０及びキャップウエハ３０においては、第１溝２３及び帯状貫通開口３２又は第２溝が同一線上に存在しており、これによって、接合されたデバイスウエハ２０及びキャップウエハ３０における連結部分の寸法は小さいものとなっている。これにより、接合されたデバイスウエハ２０及びキャップウエハ３０を、例えば、第１溝２３及び帯状貫通開口３２又は第２溝を境界として該デバイスウエハ２０及びキャップウエハ３０を両側に延伸すること等により、容易に、ウエハレベルパッケージ１０を個片化することができる。このため、ダイシングプロセスを不要とすることができる。 As a result, in the bonded device wafer 20 and cap wafer 30, the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer. The dimension of the connecting portion at 30 is small. Thereby, the bonded device wafer 20 and cap wafer 30 are stretched to both sides, for example, with the first groove 23 and the band-shaped through opening 32 or the second groove as a boundary, etc. The wafer level package 10 can be easily separated into individual pieces. For this reason, a dicing process can be made unnecessary.
　この結果、ダイシングプロセスに伴うダイシング代が不要となるので、デバイスチップ１の取り数を増加することができる。すなわち、図７（ｂ）に示すように、従来では、ダイシングによるダイシングラインの幅が大きかったので、必然的に、デバイスウエハ２０の一枚当たりのデバイスチップ１の取れ数が少なくなっていた。具体的には、図７（ｂ）に示す従来のダイシング方式の場合、ダイシング幅が５０～１００μｍ必要であり、さらにダイシング精度を考慮して１００～２００μｍのチップ間隔が必要であった。 As a result, since the dicing cost associated with the dicing process is not required, the number of device chips 1 can be increased. That is, as shown in FIG. 7B, conventionally, since the width of the dicing line by dicing is large, the number of device chips 1 per device wafer 20 is inevitably reduced. Specifically, in the case of the conventional dicing method shown in FIG. 7B, a dicing width of 50 to 100 μm is necessary, and a chip interval of 100 to 200 μm is necessary in consideration of dicing accuracy.
　この点、本実施の形態では図７（ａ）に示すように、ダイシングラインの幅よりも狭いスクライブライン２４にて切断して個片化できるので、デバイスチップ１の取り数を増加することができる。具体的には、図７（ａ）に示すダイシングレスの場合、溝の幅は５～３０μｍであり、スクライブライン２４の精度を考慮しても２０～５０μｍの間隔で実現可能である。 In this respect, in the present embodiment, as shown in FIG. 7A, the device chip 1 can be cut into individual pieces by cutting with a scribe line 24 narrower than the width of the dicing line. it can. Specifically, in the case of dicingless shown in FIG. 7A, the width of the groove is 5 to 30 μm, and even if the accuracy of the scribe line 24 is taken into consideration, it can be realized at an interval of 20 to 50 μm.
　また、ダイシング時のダイシング近傍域へのひび割れ、つまりチッピングによる封止不良を削減することができる。 Also, cracks in the vicinity of the dicing during dicing, that is, sealing failure due to chipping can be reduced.
　したがって、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージ１０の製造方法、及びウエハレベルパッケージ１０を提供することができる。 Therefore, it is possible to provide a method for manufacturing the wafer level package 10 and the wafer level package 10 that can improve the wafer yield and the product yield.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、第２溝形成工程の後、第１溝形成工程にて形成されたデバイスウエハ２０とキャップウエハ３０とのいずれか一方に形成された第１溝２３の裏面から、該第１溝２３を露出するための第１溝露出工程を含んでいる。 In the method for manufacturing the wafer level package 10 according to the present embodiment, after the second groove forming step, the wafer level package 10 is formed on either the device wafer 20 or the cap wafer 30 formed in the first groove forming step. A first groove exposing step for exposing the first groove 23 from the back surface of the first groove 23 is included.
　これにより、第１溝露出工程にて、第１溝２３を露出して、ウエハレベルパッケージ１０を個片化することができる。 Thereby, in the first groove exposing step, the first groove 23 is exposed and the wafer level package 10 can be singulated.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、第１溝露出工程では、デバイスウエハ２０とキャップウエハ３０とのいずれか一方における第１溝２３の裏面から該第１溝２３の対向位置に沿ってスクライブすることにより、第１溝２３を露出させることが可能である。これにより、ダイシングプロセスを経ることなく、スクライブの方法にて第１溝２３を露出させ、ウエハレベルパッケージ１０を個片化することができる。 In the method for manufacturing the wafer level package 10 of the present embodiment, in the first groove exposing step, the first groove 23 is opposed to the back surface of the first groove 23 in either the device wafer 20 or the cap wafer 30. By scribing along the position, the first groove 23 can be exposed. As a result, the first groove 23 can be exposed by a scribing method without going through a dicing process, and the wafer level package 10 can be singulated.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、第１溝露出工程では、第１溝２３が形成されたデバイスウエハ２０とキャップウエハ３０とのいずれか一方における第１溝２３の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化することにより、第１溝２３を露出させることが可能である。 In the method for manufacturing the wafer level package 10 of the present embodiment, in the first groove exposing step, the back surface of the first groove 23 in one of the device wafer 20 and the cap wafer 30 in which the first groove 23 is formed. The first groove 23 can be exposed by scraping the side by grinding, polishing, or etching to form a thin wafer.
　すなわち、第１溝２３はデバイスウエハ２０とキャップウエハ３０とのいずれか一方における途中の厚さまで存在している。このため、デバイスウエハ２０又はキャップウエハ３０における第１溝２３の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化することにより、第１溝２３が露出する。これにより、ダイシングプロセスを経ることなく、研削、研磨、又はエッチングにて削り取って薄ウエハ化する方法にて第１溝２３を露出させ、ウエハレベルパッケージ１０を個片化することができる。 That is, the first groove 23 exists up to a thickness in the middle of either the device wafer 20 or the cap wafer 30. For this reason, the 1st groove | channel 23 is exposed by scraping the back surface side of the 1st groove | channel 23 in the device wafer 20 or the cap wafer 30 by grinding, grinding | polishing, or etching, and making it a thin wafer. As a result, the first groove 23 can be exposed and the wafer level package 10 can be separated into pieces by a method in which the wafer is thinned by grinding, polishing, or etching without going through a dicing process.
　本実施の形態のウエハレベルパッケージ１０の製造方法では、第１溝露出工程では、第１溝２３が形成されたデバイスウエハ２０とキャップウエハ３０とのいずれか一方における第１溝２３の裏面側から第１溝２３までをハーフダイス２６することにより、第１溝２３を露出させることが可能である。 In the manufacturing method of wafer level package 10 of the present embodiment, in the first groove exposing step, from the back side of first groove 23 in either one of device wafer 20 and cap wafer 30 in which first groove 23 is formed. It is possible to expose the first groove 23 by performing the half die 26 up to the first groove 23.
　これにより、ダイシングプロセスを経ることなく、第１溝２３までをハーフダイス２６する方法にて第１溝２３を露出させ、ウエハレベルパッケージ１０を個片化することができる。また、本実施の形態においては、デバイスウエハ２０の表面に搭載された各デバイスチップ１は、第１溝２３、及び帯状貫通開口３２又は第２溝の切断面にて既に区画化されている。このため、第１溝２３の裏面側からディスク幅の大きいダイシングにてハーフダイス２６しても、ダイシング代がデバイスチップ１の個片化に影響することがない。したがって、デバイスチップ１の取り数が減少することはない。 Thereby, without passing through the dicing process, the first groove 23 is exposed by the method of half-die 26 up to the first groove 23, and the wafer level package 10 can be singulated. In the present embodiment, each device chip 1 mounted on the surface of the device wafer 20 is already partitioned by the first groove 23 and the cut surface of the band-shaped through opening 32 or the second groove. For this reason, even if the half dice 26 is diced from the rear surface side of the first groove 23 with a large disc width, the dicing cost does not affect the singulation of the device chip 1. Therefore, the number of device chips 1 is not reduced.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、第１溝露出工程では、第１溝２３が形成されたデバイスウエハ２０とキャップウエハ３０とのいずれか一方における第１溝２３を境界として該接合されたデバイスウエハ２０及びキャップウエハ３０を両側へ延伸させることにより、第１溝２３を露出させることが可能である。 In the method for manufacturing the wafer level package 10 of the present embodiment, in the first groove exposing step, the first groove 23 in either the device wafer 20 or the cap wafer 30 in which the first groove 23 is formed is bounded. The first groove 23 can be exposed by extending the bonded device wafer 20 and cap wafer 30 to both sides.
　すなわち、接合されたデバイスウエハ２０及びキャップウエハ３０においては、第１溝２３及び帯状貫通開口３２又は第２溝が同一線上に存在しており、これによって、接合されたデバイスウエハ２０及びキャップウエハ３０おける連結部分の寸法は小さいものとなっている。 That is, in the bonded device wafer 20 and cap wafer 30, the first groove 23 and the band-shaped through opening 32 or the second groove exist on the same line, and thereby the bonded device wafer 20 and cap wafer 30. The dimension of the connecting portion in the case is small.
　この結果、接合されたデバイスウエハ２０及びキャップウエハ３０を、第１溝２３及び帯状貫通開口３２又は第２溝を境界として該デバイスウエハ２０及びキャップウエハ３０を両側に延伸、つまり引き剥がすこと等により、容易に、ウエハレベルパッケージ１０を個片化することができる。 As a result, the bonded device wafer 20 and cap wafer 30 are stretched, that is, peeled off on both sides, with the first groove 23 and the band-shaped through-opening 32 or the second groove as a boundary. The wafer level package 10 can be easily separated into individual pieces.
　したがって、ダイシングプロセスを経ることなく、第１溝２３を境界として該接合されたデバイスウエハ２０及びキャップウエハ３０を両側へ延伸させる方法にて第１溝２３を露出させ、ウエハレベルパッケージ１０を個片化することができる。 Therefore, without passing through the dicing process, the first groove 23 is exposed by a method of extending the bonded device wafer 20 and cap wafer 30 to both sides with the first groove 23 as a boundary, and the wafer level package 10 is separated into individual pieces. Can be
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、接合工程では、金属、ガラスフリット又は樹脂からなる接合材を使用することが可能である。 Further, in the method for manufacturing the wafer level package 10 of the present embodiment, it is possible to use a bonding material made of metal, glass frit, or resin in the bonding process.
　これにより、接合材を用いて、デバイスウエハ２０とキャップウエハ３０とを確実に接合及び封止することができる。 Thereby, the device wafer 20 and the cap wafer 30 can be reliably bonded and sealed using the bonding material.
　また、本実施の形態のウエハレベルパッケージ１０の製造方法では、接合工程では、シリコン（Ｓｉ）－シリコン（Ｓｉ）接合又はシリコン（Ｓｉ）－二酸化シリコン（ＳｉＯ２ ）接合にてデバイスウエハ２０とキャップウエハ３０とを接合することが可能である。 In the method of manufacturing the wafer level package 10 of the present embodiment, the device wafer 20 and the cap are bonded by silicon (Si) -silicon (Si) bonding or silicon (Si) -silicon dioxide (SiO 2 ) bonding in the bonding process. The wafer 30 can be bonded.
　これにより、接合材を使用しないで、デバイスウエハ２０とキャップウエハ３０とを接合及び封止する。したがって、接合材を用いないことによるコストの低減を図ることができる。 Thereby, the device wafer 20 and the cap wafer 30 are bonded and sealed without using a bonding material. Therefore, the cost can be reduced by not using the bonding material.
　以上のように、本発明のウエハレベルパッケージの製造方法では、前記第１溝形成工程では、前記第１溝は前記第１のウエハと第２のウエハとのいずれか一方に形成されていると共に、前記接合工程の後、前記第１溝を形成した前記第１のウエハと第２のウエハとのいずれか一方とは異なる他方の第２のウエハ又は第１のウエハにも個片化するための帯状貫通開口又は第２溝をダイシング以外で形成する第２溝形成工程を含んでいることが好ましい。 As described above, in the method of manufacturing a wafer level package according to the present invention, in the first groove forming step, the first groove is formed on one of the first wafer and the second wafer. In order to separate the first wafer and the second wafer different from either the first wafer or the second wafer formed with the first groove after the bonding step. It is preferable to include a second groove forming step of forming the band-shaped through opening or the second groove other than dicing.
　本発明のウエハレベルパッケージでは、前記第１溝は前記第１のウエハと第２のウエハとのいずれか一方に形成されていると共に、上記第１溝が形成された前記第１のウエハと第２のウエハとのいずれか一方とは異なる他方の第２のウエハ又は第１のウエハには、接合後にダイシング以外で形成された個片化するための帯状貫通開口又は第２溝が設けられていることが好ましい。尚、第２溝は有底帯状開口であり、帯状貫通開口は、無底のものをいう。また、必ずしも帯状貫通開口でなくても、有底帯状開口である第２溝とすることによっても、スクライブ等によってウエハレベルパッケージを個片化することは可能である。さらに、ダイシング以外での帯状貫通開口又は第２溝の形成方法としては、例えば、エッチング又はレーザにて穿孔する方法がある。 In the wafer level package of the present invention, the first groove is formed in one of the first wafer and the second wafer, and the first wafer and the first wafer in which the first groove is formed The other second wafer or the first wafer, which is different from any one of the two wafers, is provided with a band-shaped through-opening or a second groove for separating into pieces formed after bonding other than dicing. Preferably it is. The second groove is a bottomed belt-like opening, and the belt-like through opening is a bottomless one. In addition, the wafer level package can be separated into pieces by scribing or the like even if the second groove is a bottomed belt-like opening, not necessarily the belt-like through-opening. Further, as a method for forming the band-shaped through-opening or the second groove other than dicing, for example, there is a method of drilling by etching or laser.
　これにより、第２溝形成工程にて、第１溝を形成した第１のウエハと第２のウエハとのいずれか一方とは異なる他方の第２のウエハ又は第１のウエハにも個片化するための帯状貫通開口又は第２溝をダイシング以外で形成する。 Thereby, in the second groove forming step, the second wafer or the first wafer, which is different from one of the first wafer and the second wafer in which the first groove is formed, is separated into pieces. A belt-like through-opening or a second groove is formed by other than dicing.
　この結果、接合された第１のウエハ及び第２のウエハにおいては、第１溝及び帯状貫通開口又は第２溝が同一線上に存在しており、これによって、接合された第１のウエハ及び第２のウエハにおける連結部分の寸法は小さいものとなっている。これにより、接合された第１のウエハ及び第２のウエハを、例えば、第１溝及び帯状貫通開口又は第２溝を境界として該第１のウエハ及び第２のウエハを両側に延伸すること等により、容易に、ウエハレベルパッケージを個片化することができる。このため、ダイシングプロセスを不要とすることができる。 As a result, in the bonded first wafer and the second wafer, the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and the second wafer. The dimension of the connecting portion of the wafer 2 is small. Thereby, for example, the first wafer and the second wafer are stretched to both sides with the first groove and the belt-like through opening or the second groove as a boundary, for example. Thus, the wafer level package can be easily separated. For this reason, a dicing process can be made unnecessary.
　この結果、ダイシングプロセスに伴うダイシング代が不要となるので、デバイスチップの取り数を増加することができる。また、ダイシング時のダイシング近傍域へのひび割れ、つまりチッピングによる封止不良を削減することができる。 As a result, since the dicing cost associated with the dicing process is not required, the number of device chips can be increased. In addition, cracks in the vicinity of the dicing during dicing, that is, sealing failure due to chipping can be reduced.
　したがって、ウエハ歩留まり及び製品歩留まりを向上し得るウエハレベルパッケージの製造方法、及びウエハレベルパッケージを提供することができる。 Therefore, it is possible to provide a wafer level package manufacturing method and a wafer level package that can improve the wafer yield and the product yield.
　本発明のウエハレベルパッケージの製造方法では、前記第２溝形成工程の後、前記第１溝形成工程にて形成された第１のウエハと第２のウエハとのいずれか一方に形成された第１溝の裏面から、該第１溝を露出するための第１溝露出工程を含んでいる。 In the method for manufacturing a wafer level package according to the present invention, after the second groove forming step, the first wafer formed in either the first wafer or the second wafer formed in the first groove forming step. A first groove exposing step for exposing the first groove from the back surface of the one groove is included.
　これにより、第１溝露出工程にて、第１溝を露出して、ウエハレベルパッケージを個片化することができる。 Thus, in the first groove exposing step, the first groove can be exposed and the wafer level package can be separated.
　本発明のウエハレベルパッケージの製造方法では、前記第１溝露出工程では、前記第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面から該第１溝の対向位置に沿ってスクライブすることにより、第１溝を露出させることが可能である。尚、スクライブとは、目印として尖った器具で線等を刻み付け、折曲等することによって第１溝に沿ってウエハレベルパッケージを切断することをいう。 In the method for manufacturing a wafer level package according to the present invention, in the first groove exposing step, the back surface of the first groove in either one of the first wafer and the second wafer extends along a position facing the first groove. By scribing, the first groove can be exposed. The scribing means cutting the wafer level package along the first groove by cutting a line or the like with a sharp tool as a mark and bending the mark.
　これにより、ダイシングプロセスを経ることなく、スクライブの方法にて第１溝を露出させ、ウエハレベルパッケージを個片化することができる。 This makes it possible to separate the wafer level package by exposing the first groove by a scribing method without going through a dicing process.
　本発明のウエハレベルパッケージの製造方法では、前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化することにより、第１溝を露出させることが可能である。 In the method for manufacturing a wafer level package of the present invention, in the first groove exposing step, the back surface side of the first groove in either one of the first wafer and the second wafer on which the first groove is formed is ground. The first groove can be exposed by scraping, polishing, or etching to form a thin wafer.
　すなわち、第１溝は第１のウエハと第２のウエハとのいずれか一方における途中の厚さまで存在している。このため、第１のウエハ又は第２のウエハにおける第１溝の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化することにより、第１溝が露出する。 That is, the first groove exists up to a thickness in the middle of one of the first wafer and the second wafer. For this reason, the 1st groove | channel is exposed by scraping off the back surface side of the 1st groove | channel in a 1st wafer or a 2nd wafer by grinding, grinding | polishing, or etching, and making it a thin wafer.
　これにより、ダイシングプロセスを経ることなく、研削、研磨、又はエッチングにて削り取って薄ウエハ化する方法にて第１溝を露出させ、ウエハレベルパッケージを個片化することができる。 Thereby, without passing through the dicing process, the first groove can be exposed by a method of thinning the wafer by grinding, polishing, or etching, and the wafer level package can be singulated.
　本発明のウエハレベルパッケージの製造方法では、前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面側から第１溝までをハーフダイスすることにより、第１溝を露出させることが可能である。尚、ハーフダイスとは、ダイシングに用いるディスクカッターにて、溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面側から第１溝までを切断することをいう。 In the wafer level package manufacturing method of the present invention, in the first groove exposing step, the first groove is formed from the back surface side of the first groove in either one of the first wafer and the second wafer. The first groove can be exposed by half-dicing up to one groove. The half die is a disc cutter used for dicing, which cuts from the back side of the first groove to the first groove in either one of the first wafer and the second wafer in which the groove is formed. Say.
　これにより、ダイシングプロセスを経ることなく、第１溝までをハーフダイスする方法にて第１溝を露出させ、ウエハレベルパッケージを個片化することができる。また、本発明においては、第１のウエハの表面に搭載された各デバイスチップは、第１溝、及び帯状貫通開口又は第２溝の切断面にて既に区画化されている。このため、第１溝の裏面側からディスク幅の大きいダイシングにてハーフダイスしても、ダイシング代がデバイスチップの個片化に影響することがない。したがって、デバイスチップの取り数が減少することはない。 Thereby, without passing through the dicing process, the first groove is exposed by a method of half-dicing up to the first groove, and the wafer level package can be separated. In the present invention, each device chip mounted on the surface of the first wafer is already partitioned at the cut surface of the first groove and the band-like through opening or the second groove. For this reason, even if half dicing is performed from the back surface side of the first groove by dicing with a large disk width, the dicing cost does not affect the device chip separation. Therefore, the number of device chips is not reduced.
　本発明のウエハレベルパッケージの製造方法では、前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝を境界として該接合された第１のウエハ及び第２のウエハを両側へ延伸させることにより、第１溝を露出させることが可能である。 In the method for manufacturing a wafer level package according to the present invention, in the first groove exposing step, the bonding is performed using the first groove in either one of the first wafer and the second wafer on which the first groove is formed as a boundary. The first groove can be exposed by stretching the first and second wafers formed on both sides.
　すなわち、接合された第１のウエハ及び第２のウエハにおいては、第１溝及び帯状貫通開口又は第２溝が同一線上に存在しており、これによって、接合された第１のウエハ及び第２のウエハにおける連結部分の寸法は小さいものとなっている。 That is, in the bonded first wafer and the second wafer, the first groove and the band-shaped through-opening or the second groove exist on the same line, and thereby the bonded first wafer and second wafer. The dimension of the connecting portion of the wafer is small.
　この結果、接合された第１のウエハ及び第２のウエハを、第１溝及び帯状貫通開口又は第２溝を境界として該第１のウエハ及び第２のウエハを両側に延伸、つまり引き剥がすこと等により、容易に、ウエハレベルパッケージを個片化することができる。 As a result, the bonded first wafer and second wafer are stretched, that is, peeled off from both sides of the first wafer and the second wafer with the first groove and the band-shaped through-opening or the second groove as a boundary. Thus, the wafer level package can be easily separated into individual pieces.
　したがって、ダイシングプロセスを経ることなく、第１溝を境界として該接合された第１のウエハ及び第２のウエハを両側へ延伸させる方法にて第１溝を露出させ、ウエハレベルパッケージを個片化することができる。 Therefore, without passing through the dicing process, the first groove is exposed by extending the bonded first wafer and second wafer to both sides with the first groove as a boundary, and the wafer level package is separated into pieces. can do.
　尚、本発明は、上記の実施の形態に限定されるものではなく、本発明の範囲内で種々の変更が可能であり、本実施形態にそれぞれ開示された技術的手段を適宜組み合わせて得られる実施形態についても本発明の技術的範囲に含まれる。 Note that the present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the present invention. The present invention can be obtained by appropriately combining the technical means disclosed in the present embodiment. Embodiments are also included in the technical scope of the present invention.
　本発明は、携帯電話、モバイルコンピュータ、パーソナル携帯情報機器（ＰＤＡ）、デジタルスチルカメラ（ＤＳＣ）等に代表されるエレクトニクス製品に搭載される半導体パッケージに適用されるウエハレベルパッケージ、ＭＥＭＳ（Micro Electro Mechanical Systems）デバイス等のウエハレベルパッケージの製造方法、及びウエハレベルパッケージに適用することができる。 The present invention relates to a wafer level package, MEMS (Micro Electro Electrode) applied to a semiconductor package mounted on an electronic product represented by a mobile phone, a mobile computer, a personal digital assistant (PDA), a digital still camera (DSC) and the like. It can be applied to a manufacturing method of a wafer level package such as a mechanical system) device and a wafer level package.
　１　　　デバイスチップ
　２　　　基部
　３　　　キャップ部
　４　　　接合封止部（接合材）
　５　　　スルーホール
　６　　　配線パターン
１０　　　ウエハレベルパッケージ
２０　　　デバイスウエハ（第１のウエハ）
２０ａ　　薄化デバイスウエハ（第１のウエハ）
２３　　　第１溝
２４　　　スクライブライン
２５　　　切断面
２６　　　ハーフダイス
３０　　　キャップウエハ（第２のウエハ）
３２　　　帯状貫通開口 DESCRIPTION OF SYMBOLS 1 Device chip 2 Base 3 Cap part 4 Joining sealing part (joining material)
5 Through-hole 6 Wiring pattern 10 Wafer level package 20 Device wafer (first wafer)
20a Thinned device wafer (first wafer)
23 First groove 24 Scribe line 25 Cut surface 26 Half die 30 Cap wafer (second wafer)
32 Band-shaped through-opening

Claims (9)

  1. 　面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、デバイス毎に個片化されるウエハレベルパッケージの製造方法において、
    　上記第１のウエハと第２のウエハとの少なくとも一方に個片化するための第１溝を形成する第１溝形成工程と、
    　上記第１のウエハと第２のウエハとを接合する接合工程とをこの順に含んでいることを特徴とするウエハレベルパッケージの製造方法。     A wafer level package in which a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer are bonded to each other and then separated into individual devices. In the manufacturing method,
    A first groove forming step for forming a first groove to be separated into at least one of the first wafer and the second wafer;
    A method for producing a wafer level package, comprising: a joining step for joining the first wafer and the second wafer in this order.
  2. 　前記第１溝形成工程では、前記第１溝は前記第１のウエハと第２のウエハとのいずれか一方に形成されていると共に、
    　前記接合工程の後、
    　前記第１溝を形成した前記第１のウエハと第２のウエハとのいずれか一方とは異なる他方の第２のウエハ又は第１のウエハにも個片化するための帯状貫通開口又は第２溝をダイシング以外で形成する第２溝形成工程を含んでいることを特徴とする請求項１記載のウエハレベルパッケージの製造方法。     In the first groove forming step, the first groove is formed on one of the first wafer and the second wafer,
    After the joining step,
    A band-shaped through-opening or second for separating the second wafer different from either the first wafer or the second wafer in which the first groove is formed or the first wafer. 2. The method of manufacturing a wafer level package according to claim 1, further comprising a second groove forming step of forming the groove by means other than dicing.
  3. 　前記第２溝形成工程の後、前記第１溝形成工程にて形成された第１のウエハと第２のウエハとのいずれか一方に形成された第１溝の裏面から、該第１溝を露出するための第１溝露出工程を含んでいることを特徴とする請求項２記載のウエハレベルパッケージの製造方法。 After the second groove forming step, the first groove is formed from the back surface of the first groove formed in one of the first wafer and the second wafer formed in the first groove forming step. 3. The method of manufacturing a wafer level package according to claim 2, further comprising a first groove exposing step for exposing.
  4. 　前記第１溝露出工程では、前記第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面から該第１溝の対向位置に沿ってスクライブすることにより、第１溝を露出させることを特徴とする請求項３記載のウエハレベルパッケージの製造方法。 In the first groove exposing step, the first groove is exposed by scribing along the opposing position of the first groove from the back surface of the first groove in one of the first wafer and the second wafer. 4. The method of manufacturing a wafer level package according to claim 3, wherein:
  5. 　前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面側を研削、研磨、又はエッチングにて削り取って薄ウエハ化することにより、第１溝を露出させることを特徴とする請求項３記載のウエハレベルパッケージの製造方法。 In the first groove exposing step, a thin wafer is formed by grinding, polishing, or etching the back side of the first groove in either one of the first wafer and the second wafer in which the first groove is formed. 4. The method of manufacturing a wafer level package according to claim 3, wherein the first groove is exposed by forming the first groove.
  6. 　前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝の裏面側から第１溝までをハーフダイスすることにより、第１溝を露出させることを特徴とする請求項３記載のウエハレベルパッケージの製造方法。 In the first groove exposing step, by half-dicing from the back surface side of the first groove to the first groove in either one of the first wafer and the second wafer in which the first groove is formed, 4. The method of manufacturing a wafer level package according to claim 3, wherein one groove is exposed.
  7. 　前記第１溝露出工程では、前記第１溝が形成された第１のウエハと第２のウエハとのいずれか一方における第１溝を境界として該接合された第１のウエハ及び第２のウエハを両側へ延伸させることにより、第１溝を露出させることを特徴とする請求項３記載のウエハレベルパッケージの製造方法。 In the first groove exposing step, the first wafer and the second wafer bonded together with the first groove in either one of the first wafer and the second wafer formed with the first groove as a boundary. 4. The method of manufacturing a wafer level package according to claim 3, wherein the first groove is exposed by extending the film to both sides.
  8. 　面内に複数のデバイスチップが搭載又は形成された第１のウエハと該第１のウエハに対向する第２のウエハとが互いに接合された後、デバイス毎に個片化されたウエハレベルパッケージにおいて、
    　上記第１のウエハと第２のウエハとの少なくとも一方には、デバイス毎に個片化するために形成された第１溝が設けられていることを特徴とするウエハレベルパッケージ。     In a wafer level package in which a first wafer on which a plurality of device chips are mounted or formed in a plane and a second wafer facing the first wafer are bonded to each other and then separated into individual devices. ,
    A wafer level package, wherein at least one of the first wafer and the second wafer is provided with a first groove formed for individual device separation.
  9. 　前記第１溝は前記第１のウエハと第２のウエハとのいずれか一方に形成されていると共に、
    　上記第１溝が形成された前記第１のウエハと第２のウエハとのいずれか一方とは異なる他方の第２のウエハ又は第１のウエハには、接合後にダイシング以外で形成された個片化するための帯状貫通開口又は第２溝が設けられていることを特徴とする請求項８記載のウエハレベルパッケージ。     The first groove is formed in one of the first wafer and the second wafer,
    On the other second wafer or the first wafer different from any one of the first wafer and the second wafer in which the first groove is formed, an individual piece formed after bonding other than dicing 9. The wafer level package according to claim 8, further comprising a band-shaped through-opening or a second groove for forming the same.
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