WO2012050034A1 - Method for manufacturing display device, and display device - Google Patents

Method for manufacturing display device, and display device Download PDF

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Publication number
WO2012050034A1
WO2012050034A1 PCT/JP2011/073045 JP2011073045W WO2012050034A1 WO 2012050034 A1 WO2012050034 A1 WO 2012050034A1 JP 2011073045 W JP2011073045 W JP 2011073045W WO 2012050034 A1 WO2012050034 A1 WO 2012050034A1
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WIPO (PCT)
Prior art keywords
connection
voltage
connection element
active matrix
matrix substrate
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PCT/JP2011/073045
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French (fr)
Japanese (ja)
Inventor
善光 田島
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シャープ株式会社
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Publication of WO2012050034A1 publication Critical patent/WO2012050034A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • the present invention relates to a method of manufacturing a display device having an electrostatic protection function and a display device having an electrostatic protection function.
  • the liquid crystal panel has a structure in which a liquid crystal substance is sandwiched between two glass substrates.
  • a thin film transistor hereinafter referred to as TFT
  • a pixel electrode and the like are formed on one glass substrate, and a counter electrode is formed on the other glass substrate.
  • TFT thin film transistor
  • the former is called an active matrix substrate, and the latter is called a counter substrate.
  • a method for preventing electrostatic breakdown in the manufacturing process a method of providing a protective wiring (also called a short ring) on the outer periphery of the active matrix substrate and commonly connecting the external terminals of the active matrix substrate to the protective wiring is used. .
  • a protective wiring also called a short ring
  • the active matrix substrate provided with the protective wiring even if charging occurs, the charge is immediately distributed to other external terminals without being localized. Thereby, it is possible to prevent a large potential difference from occurring between the external terminals and to prevent electrostatic breakdown.
  • Patent Document 1 describes an electrically programmable antifuse (see FIG. 16).
  • a PN junction 92 is formed on a silicon substrate 91, and a diffusion barrier 93 made of titanium nitride (TiN) or the like and a metal layer 94 made of aluminum or the like are disposed thereon.
  • TiN titanium nitride
  • a metal layer 94 made of aluminum or the like are disposed thereon.
  • a voltage pulse is applied to this laminate from a programmable voltage pulse source 95, a current flows through the PN junction 92, Joule heat is generated, and the metal of the metal layer 94 penetrates into the PN junction 92 and the diffusion barrier 93. . Thereby, the resistance of the PN junction 92 can be reduced.
  • the same ITO (Indium ⁇ ⁇ Tin Oxide) film as that for forming a pixel electrode may be used.
  • this method has a problem in that after the pixel electrode is formed, an independent signal cannot be input to the external terminal, and thus the electrical inspection of the active matrix substrate cannot be performed.
  • Patent Document 1 a method using an antifuse described in Patent Document 1 can be considered when connecting the external terminal and the protective wiring.
  • a voltage pulse is applied to the laminate, a high-density current of about 1 ⁇ 10 5 A / cm 2 flows through the PN junction 92, and intense Joule heat is generated. appear.
  • invades high heat
  • an object of the present invention is to provide a manufacturing method of a display device in which an external terminal on an active matrix substrate and a protective wiring are connected with a small calorific value, and a display device manufactured by this method.
  • a first aspect of the present invention is a method of manufacturing a display device having an electrostatic protection function, A plurality of connection elements are formed by overlapping the first conductor portion connected to the protective wiring, the semiconductor portion, and the second conductor portion connected to each external terminal at a plurality of locations on the active matrix substrate. Forming, and By applying a voltage for connection between the first and second conductor parts in a state where the connecting element is pressed and pressed against one conductor part of the connection element and the connection element is compressed and distorted, A connection step of irreversibly changing the connection element from the non-conductive state to the conductive state.
  • the method Prior to the connecting step, the method further includes a step of inspecting the active matrix substrate by applying an inspection voltage to the second conductor portion.
  • a needle used when applying the inspection voltage is used as the voltage applying needle.
  • the method Prior to the connecting step, the method further includes a step of correcting the active matrix substrate based on an inspection result.
  • connection step in the first aspect of the present invention, the connection voltage is sequentially applied to the plurality of connection elements.
  • a sixth aspect of the present invention is the fifth aspect of the present invention, In the connection step, when the current flowing through the connection element exceeds a threshold value, the connection element to which the connection voltage is applied is switched.
  • connection step in the first aspect of the present invention, the connection voltage is applied in parallel to the plurality of connection elements.
  • a temperature sensitive element having a positive temperature characteristic is provided on a path of a current flowing through the connecting element.
  • a ninth aspect of the present invention is a display device having an electrostatic protection function, An active matrix substrate; A counter substrate, The active matrix substrate is A pixel region including a plurality of thin film transistors and a plurality of pixel electrodes; A plurality of external terminals provided for external connection; Protective wiring commonly connected to the external terminals; A plurality of connection elements provided between the external terminal and the protective wiring, The connection element includes a first conductor portion connected to the protective wiring, a semiconductor portion, and a needle for applying a voltage to one conductor portion of a stacked portion formed by a second conductor portion connected to the external terminal.
  • connection element (laminated portion) is formed using the first conductor portion, the semiconductor portion, and the second conductor portion between the protective wiring and the external terminal, and the connection voltage Is applied irreversibly to connect the plurality of external terminals to the protective wiring in common, thereby preventing electrostatic breakdown of the display device.
  • the connection voltage Is applied irreversibly to connect the plurality of external terminals to the protective wiring in common, thereby preventing electrostatic breakdown of the display device.
  • the connection voltage Is applied irreversibly to connect the plurality of external terminals to the protective wiring in common, thereby preventing electrostatic breakdown of the display device.
  • the connection voltage Is applied irreversibly to connect the plurality of external terminals to the protective wiring in common, thereby preventing electrostatic breakdown of the display device.
  • the active matrix substrate can be inspected by inputting an independent signal to the external terminals even in the state having the protective wiring.
  • Such a connection element can be formed by a normal manufacturing process of the active matrix substrate.
  • connection voltage to the connection element in a compressed and distorted state
  • current and heat generated when the connection element is conducted can be smoothed.
  • pixel defects can be detected and corrected without adding a new film formation process and a wiring process (hereinafter abbreviated as wiring process) in which a predetermined pattern is exposed / etched using a photomask. And the yield of the substrate can be improved.
  • the protective wiring is provided by applying the inspection voltage to the second conductor portion. Even in the state, the active matrix substrate can be inspected by inputting an independent signal to the external terminal.
  • connection element it is possible to perform a process of conducting the connection element following the inspection of the active matrix substrate while the needle is applied to the second conductor portion.
  • the yield of the display device can be improved by correcting the active matrix substrate based on the inspection result.
  • the external terminals and the protective wiring can be reliably connected by sequentially applying the connection voltages to the plurality of connection elements.
  • connection element when the current flowing through the connection element exceeds a threshold value, an excessive current is passed through each external terminal and the protective wiring by switching the connection element to which the connection voltage is applied. Can be securely connected without any problems.
  • a plurality of external terminals and protective wiring can be connected in a short time by applying a connection voltage in parallel to a plurality of connection elements.
  • connection element by providing a temperature-sensitive element on the path of the current flowing through the connection element, conduction in one connection element causes delay in conduction of other connection elements. Can be suppressed.
  • FIG. 4 is a partially enlarged view of FIG. 3. It is a figure which shows the state before the connection process of the active matrix substrate shown in FIG. It is a figure which shows the state after the connection process of the active matrix substrate shown in FIG. It is a figure which shows the manufacturing process of the liquid crystal panel which concerns on 1st Embodiment. It is a figure which shows the other manufacturing process of the liquid crystal panel which concerns on 1st Embodiment.
  • FIG. 1 is a diagram showing a configuration of an active matrix substrate included in a liquid crystal panel according to the first embodiment of the present invention.
  • An active matrix substrate 1 shown in FIG. 1 includes a pixel region 2, a scanning signal line driving circuit 3, a plurality of external terminals 4, a protective wiring 5, and a plurality of connection elements 10.
  • the active matrix substrate 1 has a high electrostatic protection function when the plurality of external terminals 4 are brought into conduction with each other through the protective wiring 5.
  • m and n are natural numbers other than 1
  • i is a natural number of m or less
  • j is a natural number of n or less.
  • the pixel area 2 includes m scanning signal lines G1 to Gm, n data signal lines S1 to Sn, and (m ⁇ n) pixel circuits Pij arranged in a matrix.
  • the scanning signal lines G1 to Gm are arranged in parallel to each other, and the data signal lines S1 to Sn are arranged in parallel to each other so as to be orthogonal to the scanning signal lines G1 to Gm.
  • the pixel circuit Pij includes a TFT 6 connected to these two signal lines in the vicinity of the intersection of the scanning signal line Gi and the data signal line Sj, and a pixel electrode 7. According to the matrix permutation example shown in FIG. , I-th from the top and j-th position from the left.
  • the gate terminal, the source terminal, and the drain terminal of the TFT 6 are respectively connected to the scanning signal line Gi, the data signal line Sj, and the pixel electrode 7 without unnecessarily intersecting with other wirings.
  • the pixel region 2 includes a plurality of TFTs 6 and a plurality of pixel electrodes 7 that are two-dimensionally arranged.
  • the scanning signal line driving circuit 3 is a driving circuit for the scanning signal lines G1 to Gm, and is formed on the active matrix substrate 1.
  • the drive circuits for the data signal lines S1 to Sn are provided outside the active matrix substrate 1.
  • An external terminal 4 is provided at one end of the data signal lines S1 to Sn in order to apply a voltage corresponding to the video signal to the data signal lines S1 to Sn from the outside.
  • an external terminal 4 connected to the scanning signal line driving circuit 3 is provided in order to give a control signal to the scanning signal line driving circuit 3 from the outside.
  • the external terminal 4 is provided for external connection.
  • the protective wiring 5 is a wiring for electrostatic protection and is provided on the outer peripheral portion of the active matrix substrate 1.
  • One connection element 10 is provided between the external terminal 4 and the protective wiring 5.
  • the external terminal 4 is commonly connected to the protective wiring 5 via the connection element 10.
  • the protective wiring 5 is provided along one side of the active matrix substrate 1, but the protective wiring 5 may be provided along two or more sides of the active matrix substrate 1.
  • FIG. 2 is a cross-sectional view of the liquid crystal panel according to the present embodiment.
  • a liquid crystal panel 100 shown in FIG. 2 includes an active matrix substrate 1, a counter substrate 101, and a liquid crystal substance 102. As described above, the TFT 6 and the pixel electrode 7 are formed on the active matrix substrate 1. On the other hand, a counter electrode 103 is formed on the counter substrate 101.
  • the liquid crystal panel 100 is formed by disposing the active matrix substrate 1 and the counter substrate 101 so as to face each other, and filling and sealing the liquid crystal material 102 between them (a seal used for sealing is not shown).
  • the protective wiring 5 and the connection element 10 formed on the active matrix substrate 1 are removed in a process of dividing the mother substrate into a plurality of liquid crystal panels (hereinafter referred to as a cutting process). Specifically, the portion above line A-A ′ shown in FIG. 1 (the portion on the right side of line B-B ′ in FIG. 3 described later) is removed in the cutting step.
  • the liquid crystal panel according to this embodiment is characterized by a connection element 10 that connects the external terminal 4 and the protective wiring 5.
  • the connection element 10 is formed by overlapping the first conductor part, the semiconductor part, and the second conductor part.
  • the connection element 10 is in a non-conductive state in the initial state.
  • the connection element 10 is irreversibly changed from a non-conduction state to a conduction state by applying a predetermined voltage (hereinafter referred to as a connection voltage) under conditions described later.
  • a connection voltage a predetermined voltage
  • FIG. 3 is a diagram showing a connection process of the liquid crystal panel according to the present embodiment.
  • FIG. 4 is an enlarged view of a part of FIG.
  • the connection element forming step the first conductor portion 11, the semiconductor portion 12, and the second conductor portion 13, for example, are formed at a plurality of locations on the active matrix substrate 1, thereby forming the connection element 10.
  • the first conductor portion 11 is formed using a conductor material in the same process as the scanning signal lines G1 to Gm (that is, film formation by W / Ta continuous sputtering, wiring process).
  • the semiconductor portion 12 is formed using a material mainly composed of silicon oxide in the same process as the gate oxide film of the TFT 6.
  • the second conductor portion 13 has the same process as the data signal lines S1 to Sn (that is, a film forming and wiring process by continuous sputtering of Ti / Al / TiN) and the same process as the pixel electrode 7 (that is, an alternating current of ITO). Film formation by sputtering, wiring process).
  • the first conductor portion 11 is connected to the protective wiring 5 (not shown) via the wiring 15, and the second conductor portion 13 is connected to the external terminal 4 via the wiring 14. Since the semiconductor part 12 having an insulating layer is interposed between the first conductor part 11 and the second conductor part 13, the connection element 10 is in a non-conductive state before the connection process.
  • a power supply circuit 21 that outputs a connection voltage is used.
  • Voltage supply needles 22 and 23 are connected to the power supply circuit 21.
  • One needle 23 is applied to the protective wiring 5 (or the wiring 15 connected to the protective wiring 5).
  • the other needle 22 is pressed against the second conductor portion 13 in the uppermost layer of the connection element 10.
  • the power supply circuit 21 applies a connection voltage to the connection element 10 in a compressed and distorted state. Thereby, the semiconductor part 12 is destroyed and the connection element 10 is irreversibly changed from the non-conductive state to the conductive state.
  • connection step the voltage application needle 22 is pressed against the second conductor 13 and the connection element 10 is compressed and distorted so that the connection is made between the first conductor 11 and the second conductor 13.
  • the connection element 10 is irreversibly changed from the non-conductive state to the conductive state.
  • FIG. 5A is a diagram showing a state of the active matrix substrate 1 before the connection process.
  • FIG. 5B is a diagram illustrating a state of the active matrix substrate 1 after the connection process.
  • the connection element 10 Prior to the connection step (FIG. 5A), since the connection element 10 is in a non-conductive state, the external terminals 4 are electrically disconnected from each other by a high resistance. Therefore, by applying an inspection voltage to the second conductor portion 13 of the connection element 10, an independent signal is input to the external terminal 4 to perform an electrical inspection of the active matrix substrate 1 even when the protective wiring 5 is provided. be able to.
  • an inspection voltage may be applied to the external terminal 4 or the wiring 14.
  • connection step since the connection element 10 is in a conductive state, all the external terminals 4 are commonly connected to the protective wiring 5. Therefore, even when charging occurs in the active matrix substrate 1, the electric charge is dispersed to the plurality of external terminals 4, so that a large potential difference does not occur between the external terminals 4. Therefore, after the connecting step, electrostatic breakdown of the active matrix substrate 1 can be prevented.
  • FIG. 6 is a diagram showing a manufacturing process of the liquid crystal panel according to the present embodiment.
  • the scanning signal lines G1 to Gm, the gate electrode of the TFT 6, and the like are formed on the active matrix substrate 1.
  • the pixel electrode 7 and the like are formed using an ITO film.
  • the connection element 10 is formed in the TFT formation step S1 and the pixel formation step S2.
  • a plurality of non-conductive connection elements 10 are formed on the active matrix substrate 1 when the pixel formation step S2 is completed.
  • an electrical inspection of the active matrix substrate 1 is first performed, and then a process for making the connection element 10 conductive is performed.
  • a needle is applied to the second conductor portion 13 and an inspection voltage is applied to the second conductor portion 13.
  • the connection element 10 is made conductive, the needle used for applying the inspection voltage is used as the voltage application needle 22.
  • a process of bonding the active matrix substrate 1 and the counter substrate 101 is performed.
  • the liquid crystal process S5 a process of filling and sealing the liquid crystal substance 102 between the active matrix substrate 1 and the counter substrate 101 is performed.
  • the cutting step S6 a process of cutting the mother substrate and dividing it into a plurality of liquid crystal panels 100 is performed.
  • the mounting step S7 a process of attaching a polarizing plate (not shown) to the liquid crystal panel 100 is performed.
  • FIG. 7 is a diagram showing another manufacturing process of the liquid crystal panel according to the present embodiment.
  • an inspection / correction / connection process S13 is performed instead of the inspection / connection process S3.
  • the inspection / correction / connection process S13 after the electrical inspection of the active matrix substrate 1, a process of correcting the active matrix substrate 1 is performed, and after checking the success / failure of the correction, the connection element 10 is made conductive. Processing is performed. Thereby, the yield of the liquid crystal panel 100 can be improved.
  • FIG. 8A and 8B are diagrams showing a manufacturing process of a conventional liquid crystal panel.
  • the active matrix substrate cannot be electrically inspected after the pixel electrode is formed. Therefore, whether the pixel electrode is formed after the electrical inspection of the active matrix substrate (FIG. 8A), or whether the external terminal and the protective wiring are connected by forming a film and wiring for connection after the pixel inspection ( 8B).
  • the former method has a problem that defects generated in the pixel formation process cannot be detected and corrected, and the latter method has a new process (connection wiring formation process in FIG. 8B) for connecting the external terminal and the protective wiring. ) Need to be added.
  • connection element 10 can be formed by a normal manufacturing process of the active matrix substrate 1. Therefore, according to the manufacturing process of the liquid crystal panel according to the present embodiment, it is possible to connect the external terminal and the protective wiring without adding a new process, and to detect and correct a defect generated in the pixel forming process. .
  • connection step the voltage application needle 22 is pressed against the second conductor portion 13 to compress and distort the connection element 10 between the first conductor portion 11 and the second conductor portion 13. Apply connection voltage to.
  • EPROM Electrically Programmable Read Only Memory
  • the operating voltage of an FPGA Field Programmable Gate Array: Field Programmable Gate Array
  • FPGA Field Programmable Gate Array
  • FIG. 9 is a diagram showing the relationship between the gate oxide film thickness and the gate breakdown voltage. As shown in FIG. 9, for example, in order to achieve a breakdown voltage of 20 V or more with only the gate oxide film, the gate oxide film thickness needs to be 30 nm or more.
  • the semiconductor part 12 of the connection element 10 is formed in the same process as the gate oxide film of the TFT 6, the thickness of the semiconductor part 12 is the same as the gate oxide film thickness of the TFT 6. For this reason, when the connection voltage is applied to the connection element 10 without being pressed by the voltage application needle 22, after the breakdown voltage is exceeded, the connection element 10 is subjected to intense Joule heat irregularly. There is a danger that a high-density current that is generated suddenly flows and the connecting element 10 is burnt.
  • connection step according to the present embodiment the first conductor portion 11 and the second conductor portion 13 are pressed in a state where the voltage application needle 22 is pressed against the second conductor portion 13 to compress and distort the connection element 10.
  • a connection voltage is applied between the two.
  • the current locally flows in a portion of the connection element 10 pressed by the voltage application needle 22. Therefore, compared with the case where the needle 22 for applying voltage is not pressed, energization starts from a low voltage state and the energization region can be controlled, so that the current flowing through the entire connection element 10 becomes gentler.
  • connection element 10 the heat generated locally in the connection element 10 is smoothly dissipated to the peripheral region, and the wiring is not easily cut by scorching due to sudden overheating. Therefore, by applying a connection voltage to the connection element 10 in a compressed and distorted state, current and heat generated when the connection element 10 is conducted can be smoothed.
  • the manufacturing method of the liquid crystal panel according to the present embodiment includes the first conductor portion 11 connected to the protective wiring 5, the semiconductor portion 12, and each external part at a plurality of locations on the active matrix substrate 1.
  • a step of forming a plurality of connection elements 10 and a voltage application to one conductor portion (second conductor portion 13) of the connection element 10 are performed.
  • the connecting element 10 is made conductive from the non-conductive state.
  • a connection step for irreversibly changing the state Prior to the connection step, the active matrix substrate 1 is inspected by applying an inspection voltage to the second conductor portion 13.
  • the plurality of external terminals 4 can be commonly connected to the protective wiring 5, and electrostatic breakdown of the liquid crystal panel 100 can be prevented. Further, since the external terminals 4 are electrically separated from each other by a high resistance before the connection process, the active matrix substrate 1 is inspected by inputting an independent signal to the external terminals 4 even when the protective wiring 5 is provided. be able to.
  • the connection element 10 can be formed by a normal manufacturing process of the active matrix substrate 1. In addition, by applying a connection voltage to the connection element 10 in a compressed and distorted state, current and heat generated when the connection element 10 is conducted can be smoothed.
  • connection step the inspection matrix used when applying the inspection voltage is used as the voltage application needle 22, so that the active matrix substrate 1 remains in a state where the needle is applied to the second conductor portion 13. Subsequent to the inspection, a process for making the connection element 10 conductive can be performed. Further, the yield of the liquid crystal panel 100 can be improved by correcting the active matrix substrate 1 based on the inspection result before the connection step.
  • FIG. 10 is a diagram showing a connection process of the liquid crystal panel according to the second embodiment of the present invention.
  • the plurality of connection elements 10 are sequentially conducted using the power supply circuit 21, the plurality of switches 24, and the plurality of current sensors (not shown).
  • the switch 24 and the current sensor are provided in series on the path of the current flowing through the connection element 10.
  • the current sensor detects a current flowing through the connection element 10.
  • connection elements 10a to 10d are conducted in the connection process.
  • the switches provided on the path of the current flowing through the connection elements 10a to 10d are referred to as switches 24a to 24d. Further, in order to facilitate understanding of the drawings, in FIG. 10 and FIG.
  • FIG. 11 is a diagram illustrating changes in voltages Va to Vd applied to the connection elements 10a to 10d and currents Ia to Id flowing through the connection elements 10a to 10d.
  • the switch 24a switch corresponding to the connection element 10a
  • the power supply circuit 21 increases the voltage Va (voltage applied to the connection element 10a) at a predetermined speed.
  • the power supply circuit 21 slows the rate of increase of the voltage Va.
  • the second threshold value Ith2 Ith2> Ith1
  • the connection element 10a is stably in a conductive state. Therefore, the power supply circuit 21 controls the voltage Va to zero, and the switch 24a is turned off. Note that, after the current Ia exceeds the first threshold value Ith1, the power supply circuit 21 may keep the voltage Va constant.
  • the power supply circuit 21 controls the voltage Vb applied to the connection element 10b by the same method. Furthermore, the power supply circuit 21 controls the voltage Vc applied to the connection element 10c and the voltage Vd applied to the connection element 10d by the same method. As described above, in the connection process according to the present embodiment, when the current flowing through the connection element 10 exceeds the threshold, the connection element 10 to which the connection voltage is applied is switched using the power supply circuit 21 and the switches 24a to 24d.
  • an electrical inspection of the active matrix substrate 1 is performed by applying an inspection voltage to the second conductor portion 13 before the connection step.
  • the needle used when applying the inspection voltage may be used as the voltage application needle 22.
  • a process for correcting the active matrix substrate 1 may be performed before the connection step.
  • connection voltage is sequentially applied to the plurality of connection elements 10 in the connection step, whereby each external terminal 4 and the protective wiring 5 Can be securely connected. Further, in the connection process, when the current flowing through the connection element 10 exceeds the threshold value, the connection element 10 to which the connection voltage is applied is switched, so that an excessive current does not flow through each external terminal 4 and the protective wiring 5. It can be securely connected.
  • FIG. 12 is a diagram showing a connection process of the liquid crystal panel according to the third embodiment of the present invention.
  • the plurality of connection elements 10 are conducted in parallel using the power supply circuit 21 and the plurality of thermistors 25.
  • the thermistor 25 is a kind of temperature sensitive element, and is provided on a path of current flowing through the connection element 10.
  • a PTC (Positive Temperature Coefficient) thermistor having a positive temperature characteristic (a characteristic in which a resistance value increases as the temperature increases) is used.
  • FIG. 13 is a characteristic diagram showing several examples of characteristics indicating resistance change with temperature of the PTC thermistor.
  • the horizontal axis indicates the temperature
  • the vertical axis indicates the resistance ratio with a resistance value of 1 at 25 ° C. as a logarithmic value.
  • the resistance value of the PTC thermistor increases rapidly when the temperature rises to some extent. For example, when the temperature changes from 25 ° C. to 100 ° C., the resistance of the PTC thermistor becomes 1000 times or more.
  • the PTC thermistor is used as a switch for preventing overheating.
  • the thermistor 25 when a large current flows through the previously connected connection element 10, the temperature of the corresponding thermistor 25 rises due to Joule heat. When the temperature of the thermistor 25 increases to some extent, the resistance of the thermistor 25 increases rapidly. Thereby, the electric current which flows into the connection element 10 which conduct
  • connection elements 10a to 10d are conducted in the connection process.
  • the thermistors provided on the path of the current flowing through the connection elements 10a to 10d are referred to as thermistors 25a to 25d.
  • FIG. 14 is a diagram illustrating changes in voltages Va and Vb applied to the connection elements 10a and 10b and currents Ia and Ib flowing through the connection elements 10a and 10b.
  • the connection element 10a is first conducted among the four connection elements 10a to 10d.
  • the connection element 10a becomes conductive at time t1
  • a large current flows through the connection element 10a.
  • the voltage Vb voltage applied to the connection element 10b decreases.
  • FIG. 15 is an equivalent circuit diagram when the connection elements 10a to 10d are conducted in parallel.
  • Ra to Rd indicate the resistances of the connection elements 10a to 10d
  • Za to Zd indicate the resistances of the thermistors 25a to 25d.
  • the thermistor temperature is low, Ra >> Za, Rb >> Zb, Rc >> Zc, Rd >> Zd, and the circuit resistance is ⁇ (Ra) ⁇ 1 + (Rb) ⁇ . 1 + (Rc) becomes -1 + (Rd) -1 ⁇ -1 .
  • the connection element 10a is first turned on, the resistance Ra decreases rapidly, and Ra ⁇ Za.
  • the circuit resistance is ⁇ (Za) ⁇ 1 + (Rb) ⁇ 1 + (Rc) ⁇ 1 + (Rd) ⁇ 1 ⁇ ⁇ 1 .
  • connection element 10a Thereafter, a large current flows through the connection element 10a and the thermistor 25a, so that most of the energy supplied from the output power supply to the entire circuit is consumed around the connection element 10a, resulting in a voltage drop due to exceeding the power supply capability.
  • the voltage applied to the connection elements 10b to 10d also decreases.
  • the resistance Za increases exponentially as the temperature of the thermistor 25a increases to some extent due to the temperature rise due to Joule heat.
  • connection element 10b when the connection element 10b is turned on, the resistance Rb rapidly decreases, and Rb ⁇ Zb.
  • the circuit resistance is ⁇ (Za) ⁇ 1 + (Zb) ⁇ 1 + (Rc) ⁇ 1 + (Rd) ⁇ 1 ⁇ ⁇ 1 .
  • a large current flows through the connection element 10b and the thermistor 25b, a voltage drop occurs in the entire circuit, and the voltage applied to the connection elements 10c and 10d also decreases.
  • the temperature of the thermistor 25b rises due to Joule heat and increases to some extent, the resistance Zb rapidly increases.
  • connection element 10b After a while after the connection element 10b becomes conductive, the voltage of the entire circuit is recovered, and the voltage applied to the connection elements 10c and 10d is also recovered. Even when the connection elements 10c and 10d are turned on, the resistance of the circuit shown in FIG. 15 changes similarly.
  • the resistance of the thermistor 25 at room temperature is about 1 k ⁇ . If the resistance at room temperature is about 1 k ⁇ , the resistance at high temperature is several M ⁇ , so that the voltage of the entire circuit can be sufficiently recovered.
  • an electrical inspection of the active matrix substrate 1 is performed by applying an inspection voltage to the second conductor portion 13 before the connection step.
  • the needle used when applying the inspection voltage may be used as the voltage application needle 22.
  • a process for correcting the active matrix substrate 1 may be performed before the connection step.
  • connection voltage is applied in parallel to the plurality of connection elements 10 in the connection step, thereby connecting the plurality of external terminals 4 to the protective wiring. 5 can be realized within a short time. Further, in the connection process, by providing the thermistor 25 having a positive temperature characteristic on the path of the current flowing through the connection element 10, conduction in one connection element 10 is a factor, and conduction in other connection elements 10 is delayed. This can be suppressed.
  • the active matrix substrate 1 includes the scanning signal line driving circuit 3.
  • the active matrix substrate of the present invention may not include the scanning signal line driving circuit, and other control circuits (for example, all or part of the data signal line driver circuit) may be provided.
  • the active matrix substrate 1 includes only one protective wiring 5, the active matrix substrate of the present invention may include two or more protective wirings.
  • the method for manufacturing a display device according to the present invention has a feature that an external terminal and a protective wiring can be connected with a small amount of wiring, and can be used, for example, for manufacturing an active matrix substrate such as a liquid crystal panel.
  • the display device of the present invention can be used for an active matrix substrate such as a liquid crystal panel, for example.

Abstract

A plurality of connection elements (10) are formed by forming and laminating first conductor parts (11) that are connected to a protective wiring line (5), semiconductor parts (12), and second conductor parts (13) that are connected to respective external terminals (4) in a plurality of positions on an active matrix substrate. In a connection step, a needle (22) for voltage application is pressed against each second conductor part (13) so that each connection element (10) is held in a compressed and strained state, and a voltage for connection is applied between each first conductor part (11) and each second conductor part (13), so that the connection element (10) is irreversibly changed from an electrically disconnected state to an electrically connected state. Consequently, the external terminals on the active matrix substrate and the protective wiring line can be connected with a small calorific power.

Description

表示装置の製造方法および表示装置Display device manufacturing method and display device
　本発明は、静電気保護機能を有する表示装置の製造方法、および、静電気保護機能を有する表示装置に関する。 The present invention relates to a method of manufacturing a display device having an electrostatic protection function and a display device having an electrostatic protection function.
　液晶パネルは、２枚のガラス基板の間に液晶物質を挟み込んだ構造を有する。一方のガラス基板には薄膜トランジスタ（Thin Film Transistor：以下、ＴＦＴと略称する）や画素電極などが形成され、他方のガラス基板には対向電極が形成される。以下、前者をアクティブマトリクス基板、後者を対向基板という。 The liquid crystal panel has a structure in which a liquid crystal substance is sandwiched between two glass substrates. A thin film transistor (hereinafter referred to as TFT), a pixel electrode, and the like are formed on one glass substrate, and a counter electrode is formed on the other glass substrate. Hereinafter, the former is called an active matrix substrate, and the latter is called a counter substrate.
　液晶パネルでは、数百Ｖ以上の帯電が生じた後に、何らかの原因で一気に電荷が放出されると、パネルが表示不良となる程のＴＦＴ破壊が発生する。このような静電気による破壊は、アクティブマトリクス基板の製造工程でも起こり得る。そこで、製造工程における静電気破壊を防止する方法として、アクティブマトリクス基板の外周部分に保護配線（ショートリングとも呼ばれる）を設け、アクティブマトリクス基板の外部端子を保護配線に共通接続する方法が用いられている。保護配線を設けたアクティブマトリクス基板では、帯電が生じたとしても、電荷は局在することなく直ちに他の外部端子に分散する。これにより、外部端子間に大きな電位差が生じることを防止し、静電気破壊を防止することができる。 In a liquid crystal panel, if a charge of several hundred volts or more is generated and then an electric charge is released at a stroke for some reason, TFT destruction occurs to the extent that the panel becomes defective in display. Such breakdown due to static electricity can also occur in the manufacturing process of the active matrix substrate. Therefore, as a method for preventing electrostatic breakdown in the manufacturing process, a method of providing a protective wiring (also called a short ring) on the outer periphery of the active matrix substrate and commonly connecting the external terminals of the active matrix substrate to the protective wiring is used. . In the active matrix substrate provided with the protective wiring, even if charging occurs, the charge is immediately distributed to other external terminals without being localized. Thereby, it is possible to prevent a large potential difference from occurring between the external terminals and to prevent electrostatic breakdown.
　本願発明に関連して、特許文献１には、電気的にプログラミング可能なアンチヒューズが記載されている（図１６を参照）。図１６に示すように、シリコン基板９１上にＰ－Ｎ接合９２を形成し、その上に窒化チタン（ＴｉＮ）などによる拡散障壁９３とアルミニウムなどによる金属層９４とを配置する。この積層体にプログラマブル電圧パルスソース９５から電圧パルスを印加すると、Ｐ－Ｎ接合９２に電流が流れてジュール熱が発生し、Ｐ－Ｎ接合９２と拡散障壁９３に金属層９４の金属が侵入する。これにより、Ｐ－Ｎ接合９２の抵抗を低下させることができる。 In connection with the present invention, Patent Document 1 describes an electrically programmable antifuse (see FIG. 16). As shown in FIG. 16, a PN junction 92 is formed on a silicon substrate 91, and a diffusion barrier 93 made of titanium nitride (TiN) or the like and a metal layer 94 made of aluminum or the like are disposed thereon. When a voltage pulse is applied to this laminate from a programmable voltage pulse source 95, a current flows through the PN junction 92, Joule heat is generated, and the metal of the metal layer 94 penetrates into the PN junction 92 and the diffusion barrier 93. . Thereby, the resistance of the PN junction 92 can be reduced.
日本国特開平６－２９３９６号公報Japanese Unexamined Patent Publication No. 6-29396
　液晶表示装置の製造方法として、外部端子と保護配線を接続するときに、画素電極を形成するときと同じＩＴＯ（Indium Tin Oxide）膜が使用されることがある。しかしながら、この方法には、画素電極を形成した後では、外部端子に独立した信号を入力できないので、アクティブマトリクス基板の電気的検査を行うことができないという問題がある。 As a manufacturing method of a liquid crystal display device, when connecting an external terminal and a protective wiring, the same ITO (Indium す る Tin Oxide) film as that for forming a pixel electrode may be used. However, this method has a problem in that after the pixel electrode is formed, an independent signal cannot be input to the external terminal, and thus the electrical inspection of the active matrix substrate cannot be performed.
　そこで、外部端子と保護配線を接続するときに、特許文献１に記載されたアンチヒューズを用いる方法が考えられる。しかしながら、特許文献１に記載された方法では、積層体に電圧パルスを印加したときに、Ｐ－Ｎ接合９２に１×１０5 Ａ／ｃｍ2 程度の高密度の電流が流れ、激しいジュール熱が発生する。このため、金属層９４の金属が侵入したときに、接続部位に高熱が加わり、接続部位が焼けてしまう可能性がある。 Therefore, a method using an antifuse described in Patent Document 1 can be considered when connecting the external terminal and the protective wiring. However, in the method described in Patent Document 1, when a voltage pulse is applied to the laminate, a high-density current of about 1 × 10 5 A / cm 2 flows through the PN junction 92, and intense Joule heat is generated. appear. For this reason, when the metal of the metal layer 94 penetrate | invades, high heat | fever is added to a connection part and a connection part may burn.
　それ故に、本発明は、アクティブマトリクス基板上の外部端子と保護配線を少ない発熱量で接続する表示装置の製造方法、および、この方法で製造された表示装置を提供することを目的とする。 Therefore, an object of the present invention is to provide a manufacturing method of a display device in which an external terminal on an active matrix substrate and a protective wiring are connected with a small calorific value, and a display device manufactured by this method.
　本発明の第１の局面は、静電気保護機能を有する表示装置の製造方法であって、
　アクティブマトリクス基板上の複数の箇所に、保護配線に接続された第１導体部、半導体部、および、各外部端子に接続された第２導体部を重ねて形成することにより、複数の接続素子を形成する工程と、
　前記接続素子の一方の導体部に電圧印加用の針を押し当て、前記接続素子を圧縮して歪ませた状態で前記第１および第２導体部間に接続用電圧を印加することにより、前記接続素子を非導通状態から導通状態に不可逆的に変化させる接続工程とを備える。 A first aspect of the present invention is a method of manufacturing a display device having an electrostatic protection function,
A plurality of connection elements are formed by overlapping the first conductor portion connected to the protective wiring, the semiconductor portion, and the second conductor portion connected to each external terminal at a plurality of locations on the active matrix substrate. Forming, and
By applying a voltage for connection between the first and second conductor parts in a state where the connecting element is pressed and pressed against one conductor part of the connection element and the connection element is compressed and distorted, A connection step of irreversibly changing the connection element from the non-conductive state to the conductive state.
　本発明の第２の局面は、本発明の第１の局面において、
　前記接続工程より前に、前記第２導体部に検査用電圧を印加して前記アクティブマトリクス基板を検査する工程をさらに備える。 According to a second aspect of the present invention, in the first aspect of the present invention,
Prior to the connecting step, the method further includes a step of inspecting the active matrix substrate by applying an inspection voltage to the second conductor portion.
　本発明の第３の局面は、本発明の第２の局面において、
　前記接続工程では、前記検査用電圧を印加するときに用いた針を前記電圧印加用の針として用いることを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
In the connecting step, a needle used when applying the inspection voltage is used as the voltage applying needle.
　本発明の第４の局面は、本発明の第２の局面において、
　前記接続工程より前に、検査結果に基づき前記アクティブマトリクス基板を修正する工程をさらに備える。 According to a fourth aspect of the present invention, in the second aspect of the present invention,
Prior to the connecting step, the method further includes a step of correcting the active matrix substrate based on an inspection result.
　本発明の第５の局面は、本発明の第１の局面において、
　前記接続工程では、前記複数の接続素子に対して前記接続用電圧を順次に印加することを特徴とする。 According to a fifth aspect of the present invention, in the first aspect of the present invention,
In the connection step, the connection voltage is sequentially applied to the plurality of connection elements.
　本発明の第６の局面は、本発明の第５の局面において、
　前記接続工程では、前記接続素子を流れる電流が閾値を超えたときに、前記接続用電圧を印加する接続素子を切り替えることを特徴とする。 A sixth aspect of the present invention is the fifth aspect of the present invention,
In the connection step, when the current flowing through the connection element exceeds a threshold value, the connection element to which the connection voltage is applied is switched.
　本発明の第７の局面は、本発明の第１の局面において、
　前記接続工程では、前記複数の接続素子に対して前記接続用電圧を並列に印加することを特徴とする。 According to a seventh aspect of the present invention, in the first aspect of the present invention,
In the connection step, the connection voltage is applied in parallel to the plurality of connection elements.
　本発明の第８の局面は、本発明の第７の局面において、
　前記接続工程では、前記接続素子を流れる電流の経路上に正温度特性を有する感温素子を設けることを特徴とする。 According to an eighth aspect of the present invention, in the seventh aspect of the present invention,
In the connecting step, a temperature sensitive element having a positive temperature characteristic is provided on a path of a current flowing through the connecting element.
　本発明の第９の局面は、静電気保護機能を有する表示装置であって、
　アクティブマトリクス基板と、
　対向基板とを備え、
　前記アクティブマトリクス基板は、
　　複数の薄膜トランジスタおよび複数の画素電極を含む画素領域と、
　　外部接続用に設けられた複数の外部端子と、
　　前記外部端子に共通接続された保護配線と、
　　前記外部端子および前記保護配線の間に設けられた複数の接続素子とを含み、
　前記接続素子は、前記保護配線に接続された第１導体部、半導体部、および、前記外部端子に接続された第２導体部で形成された積層部の一方の導体部に電圧印加用の針を押し当て、前記積層部を圧縮して歪ませた状態で前記第１および第２導体部間に接続用電圧を印加することにより、前記積層部を非導通状態から導通状態に不可逆的に変化させたものであることを特徴とする。 A ninth aspect of the present invention is a display device having an electrostatic protection function,
An active matrix substrate;
A counter substrate,
The active matrix substrate is
A pixel region including a plurality of thin film transistors and a plurality of pixel electrodes;
A plurality of external terminals provided for external connection;
Protective wiring commonly connected to the external terminals;
A plurality of connection elements provided between the external terminal and the protective wiring,
The connection element includes a first conductor portion connected to the protective wiring, a semiconductor portion, and a needle for applying a voltage to one conductor portion of a stacked portion formed by a second conductor portion connected to the external terminal. Is applied, and a voltage for connection is applied between the first and second conductor parts in a state where the laminated part is compressed and distorted, thereby irreversibly changing the laminated part from a non-conductive state to a conductive state. It is characterized by the above.
　本発明の第１または第９の局面によれば、保護配線と外部端子の間に第１導体部、半導体部および第２導体部を用いて接続素子（積層部）を形成し、接続用電圧を印加して接続素子を不可逆的に導通させることにより、複数の外部端子を保護配線に共通接続し、表示装置の静電気破壊を防止することができる。また、接続工程より前では外部端子は互いに高抵抗によって電気的に切り離されているので、保護配線を有する状態でも外部端子に独立した信号を入力してアクティブマトリクス基板の検査を行うことができる。このような接続素子は、アクティブマトリクス基板の通常の製造工程で形成することができる。また、圧縮して歪ませた状態の接続素子に接続用電圧を印加することにより、接続素子を導通させるときの電流や発熱を平滑化することができる。これらの方法により、新たな膜形成と、フォトマスクを用いて所定パターンを露光／エッチングする配線化（以下、配線化と略称する）の製造工程を追加することなく、画素欠陥の検出と修正を可能とし、基板の歩留まりを向上させることができる。 According to the first or ninth aspect of the present invention, the connection element (laminated portion) is formed using the first conductor portion, the semiconductor portion, and the second conductor portion between the protective wiring and the external terminal, and the connection voltage Is applied irreversibly to connect the plurality of external terminals to the protective wiring in common, thereby preventing electrostatic breakdown of the display device. Further, since the external terminals are electrically separated from each other by a high resistance before the connection step, the active matrix substrate can be inspected by inputting an independent signal to the external terminals even in the state having the protective wiring. Such a connection element can be formed by a normal manufacturing process of the active matrix substrate. In addition, by applying a connection voltage to the connection element in a compressed and distorted state, current and heat generated when the connection element is conducted can be smoothed. With these methods, pixel defects can be detected and corrected without adding a new film formation process and a wiring process (hereinafter abbreviated as wiring process) in which a predetermined pattern is exposed / etched using a photomask. And the yield of the substrate can be improved.
　本発明の第２の局面によれば、接続工程より前では外部端子は互いに高抵抗によって電気的に切り離されているので、第２導体部に検査用電圧を印加することにより、保護配線を有する状態でも外部端子に独立した信号を入力してアクティブマトリクス基板の検査を行うことができる。 According to the second aspect of the present invention, since the external terminals are electrically separated from each other by a high resistance before the connection step, the protective wiring is provided by applying the inspection voltage to the second conductor portion. Even in the state, the active matrix substrate can be inspected by inputting an independent signal to the external terminal.
　本発明の第３の局面によれば、第２導体部に針を当てた状態のままで、アクティブマトリクス基板の検査に続いて、接続素子を導通させる処理を行うことができる。 According to the third aspect of the present invention, it is possible to perform a process of conducting the connection element following the inspection of the active matrix substrate while the needle is applied to the second conductor portion.
　本発明の第４の局面によれば、検査結果に基づきアクティブマトリクス基板を修正することにより、表示装置の歩留まりを向上させることができる。 According to the fourth aspect of the present invention, the yield of the display device can be improved by correcting the active matrix substrate based on the inspection result.
　本発明の第５の局面によれば、複数の接続素子に対して接続用電圧を順次に印加することにより、各外部端子と保護配線を確実に接続することができる。 According to the fifth aspect of the present invention, the external terminals and the protective wiring can be reliably connected by sequentially applying the connection voltages to the plurality of connection elements.
　本発明の第６の局面によれば、接続素子を流れる電流が閾値を超えたときに、接続用電圧を印加する接続素子を切り替えることにより、各外部端子と保護配線とを過剰な電流を流すことなく確実に接続することができる。 According to the sixth aspect of the present invention, when the current flowing through the connection element exceeds a threshold value, an excessive current is passed through each external terminal and the protective wiring by switching the connection element to which the connection voltage is applied. Can be securely connected without any problems.
　本発明の第７の局面によれば、複数の接続素子に対して接続用電圧を並列に印加することにより、複数の外部端子と保護配線を短時間で接続することができる。 According to the seventh aspect of the present invention, a plurality of external terminals and protective wiring can be connected in a short time by applying a connection voltage in parallel to a plurality of connection elements.
　本発明の第８の局面によれば、接続素子を流れる電流の経路上に感温素子を設けることにより、ある接続素子での導通が要因となって他の接続素子の導通が遅延することを抑制することができる。 According to the eighth aspect of the present invention, by providing a temperature-sensitive element on the path of the current flowing through the connection element, conduction in one connection element causes delay in conduction of other connection elements. Can be suppressed.
本発明の第１の実施形態に係る液晶パネルに含まれるアクティブマトリクス基板の構成を示す図である。It is a figure which shows the structure of the active matrix substrate contained in the liquid crystal panel which concerns on the 1st Embodiment of this invention. 図１に示すアクティブマトリクス基板を含む液晶パネルの断面図である。It is sectional drawing of the liquid crystal panel containing the active matrix substrate shown in FIG. 第１の実施形態に係る液晶パネルの接続工程を示す図である。It is a figure which shows the connection process of the liquid crystal panel which concerns on 1st Embodiment. 図３の一部の拡大図である。FIG. 4 is a partially enlarged view of FIG. 3. 図１に示すアクティブマトリクス基板の接続工程の前の状態を示す図である。It is a figure which shows the state before the connection process of the active matrix substrate shown in FIG. 図１に示すアクティブマトリクス基板の接続工程の後の状態を示す図である。It is a figure which shows the state after the connection process of the active matrix substrate shown in FIG. 第１の実施形態に係る液晶パネルの製造工程を示す図である。It is a figure which shows the manufacturing process of the liquid crystal panel which concerns on 1st Embodiment. 第１の実施形態に係る液晶パネルの他の製造工程を示す図である。It is a figure which shows the other manufacturing process of the liquid crystal panel which concerns on 1st Embodiment. 従来の液晶パネルの製造工程を示す図である。It is a figure which shows the manufacturing process of the conventional liquid crystal panel. 従来の液晶パネルの製造工程を示す図である。It is a figure which shows the manufacturing process of the conventional liquid crystal panel. ゲート酸化膜厚とゲート破壊電圧の関係を示す図である。It is a figure which shows the relationship between a gate oxide film thickness and a gate breakdown voltage. 本発明の第２の実施形態に係る液晶パネルの接続工程を示す図である。It is a figure which shows the connection process of the liquid crystal panel which concerns on the 2nd Embodiment of this invention. 第２の実施形態に係る接続工程における、接続素子に印加される電圧と接続素子を流れる電流の変化を示す図である。It is a figure which shows the change of the voltage applied to a connection element, and the electric current which flows through a connection element in the connection process which concerns on 2nd Embodiment. 本発明の第３の実施形態に係る液晶パネルの接続工程を示す図である。It is a figure which shows the connection process of the liquid crystal panel which concerns on the 3rd Embodiment of this invention. ＰＴＣサーミスタの特性の例を示す特性図である。It is a characteristic view which shows the example of the characteristic of a PTC thermistor. 第３の実施形態に係る接続工程における、接続素子に印加される電圧と接続素子を流れる電流の変化を示す図である。It is a figure which shows the change of the voltage applied to a connection element, and the electric current which flows through a connection element in the connection process which concerns on 3rd Embodiment. 第３の実施形態に係る接続工程において接続素子を並列に導通させるときの等価回路図である。It is an equivalent circuit diagram when connecting elements in parallel in the connecting step according to the third embodiment. 従来のアンチヒューズを示す図である。It is a figure which shows the conventional antifuse.
　（第１の実施形態）
　図１は、本発明の第１の実施形態に係る液晶パネルに含まれるアクティブマトリクス基板の構成を示す図である。図１に示すアクティブマトリクス基板１は、画素領域２、走査信号線駆動回路３、複数の外部端子４、保護配線５、および、複数の接続素子１０を備えている。アクティブマトリクス基板１は、保護配線５を介して複数の外部端子４が互いに導通状態となることで、高い静電気保護機能を有する。以下、ｍおよびｎは１ではない自然数、ｉはｍ以下の自然数、ｊはｎ以下の自然数である。 (First embodiment)
FIG. 1 is a diagram showing a configuration of an active matrix substrate included in a liquid crystal panel according to the first embodiment of the present invention. An active matrix substrate 1 shown in FIG. 1 includes a pixel region 2, a scanning signal line driving circuit 3, a plurality of external terminals 4, a protective wiring 5, and a plurality of connection elements 10. The active matrix substrate 1 has a high electrostatic protection function when the plurality of external terminals 4 are brought into conduction with each other through the protective wiring 5. Hereinafter, m and n are natural numbers other than 1, i is a natural number of m or less, and j is a natural number of n or less.
　画素領域２は、ｍ本の走査信号線Ｇ１～Ｇｍ、ｎ本のデータ信号線Ｓ１～Ｓｎ、および、（ｍ×ｎ）個のマトリクス配列された画素回路Ｐｉｊを含んでいる。走査信号線Ｇ１～Ｇｍは互いに平行に配置され、データ信号線Ｓ１～Ｓｎは走査信号線Ｇ１～Ｇｍと直交するように互いに平行に配置される。画素回路Ｐｉｊは、走査信号線Ｇｉとデータ信号線Ｓｊの交点近傍でこれら２本の信号線に接続されたＴＦＴ６と、画素電極７とを含み、図１に示すマトリクスの順列の例に従えば、上からｉ番目、左からｊ番目の位置に配置される。ＴＦＴ６のゲート端子、ソース端子およびドレイン端子は、それぞれ、走査信号線Ｇｉ、データ信号線Ｓｊおよび画素電極７に、他の配線と不必要に交差することなく接続される。このように画素領域２は、２次元状に配置された複数のＴＦＴ６と複数の画素電極７を含んでいる。 The pixel area 2 includes m scanning signal lines G1 to Gm, n data signal lines S1 to Sn, and (m × n) pixel circuits Pij arranged in a matrix. The scanning signal lines G1 to Gm are arranged in parallel to each other, and the data signal lines S1 to Sn are arranged in parallel to each other so as to be orthogonal to the scanning signal lines G1 to Gm. The pixel circuit Pij includes a TFT 6 connected to these two signal lines in the vicinity of the intersection of the scanning signal line Gi and the data signal line Sj, and a pixel electrode 7. According to the matrix permutation example shown in FIG. , I-th from the top and j-th position from the left. The gate terminal, the source terminal, and the drain terminal of the TFT 6 are respectively connected to the scanning signal line Gi, the data signal line Sj, and the pixel electrode 7 without unnecessarily intersecting with other wirings. As described above, the pixel region 2 includes a plurality of TFTs 6 and a plurality of pixel electrodes 7 that are two-dimensionally arranged.
　走査信号線駆動回路３は、走査信号線Ｇ１～Ｇｍの駆動回路であり、アクティブマトリクス基板１上に形成される。データ信号線Ｓ１～Ｓｎの駆動回路は、アクティブマトリクス基板１の外部に設けられる。外部からデータ信号線Ｓ１～Ｓｎに映像信号に応じた電圧を与えるために、データ信号線Ｓ１～Ｓｎの一端には外部端子４が設けられる。また、外部から走査信号線駆動回路３に制御信号を与えるために、走査信号線駆動回路３に接続した外部端子４が設けられる。このように外部端子４は、外部接続用に設けられる。 The scanning signal line driving circuit 3 is a driving circuit for the scanning signal lines G1 to Gm, and is formed on the active matrix substrate 1. The drive circuits for the data signal lines S1 to Sn are provided outside the active matrix substrate 1. An external terminal 4 is provided at one end of the data signal lines S1 to Sn in order to apply a voltage corresponding to the video signal to the data signal lines S1 to Sn from the outside. In addition, an external terminal 4 connected to the scanning signal line driving circuit 3 is provided in order to give a control signal to the scanning signal line driving circuit 3 from the outside. Thus, the external terminal 4 is provided for external connection.
　保護配線５は、静電気保護用の配線であり、アクティブマトリクス基板１の外周部分に設けられる。外部端子４と保護配線５の間には、接続素子１０が１個ずつ設けられる。外部端子４は、接続素子１０を介して保護配線５に共通接続される。なお、図１では保護配線５はアクティブマトリクス基板１の１辺に沿って設けられているが、保護配線５をアクティブマトリクス基板１の２箇所以上の辺に沿って設けてもよい。 The protective wiring 5 is a wiring for electrostatic protection and is provided on the outer peripheral portion of the active matrix substrate 1. One connection element 10 is provided between the external terminal 4 and the protective wiring 5. The external terminal 4 is commonly connected to the protective wiring 5 via the connection element 10. In FIG. 1, the protective wiring 5 is provided along one side of the active matrix substrate 1, but the protective wiring 5 may be provided along two or more sides of the active matrix substrate 1.
　図２は、本実施形態に係る液晶パネルの断面図である。図２に示す液晶パネル１００は、アクティブマトリクス基板１、対向基板１０１、および、液晶物質１０２を備えている。上述したように、アクティブマトリクス基板１にはＴＦＴ６や画素電極７などが形成される。一方、対向基板１０１には対向電極１０３が形成される。液晶パネル１００は、アクティブマトリクス基板１と対向基板１０１を対向させて配置し、両者の間に液晶物質１０２を充填、密封（密封に用いるシールは図示せず）することにより形成される。 FIG. 2 is a cross-sectional view of the liquid crystal panel according to the present embodiment. A liquid crystal panel 100 shown in FIG. 2 includes an active matrix substrate 1, a counter substrate 101, and a liquid crystal substance 102. As described above, the TFT 6 and the pixel electrode 7 are formed on the active matrix substrate 1. On the other hand, a counter electrode 103 is formed on the counter substrate 101. The liquid crystal panel 100 is formed by disposing the active matrix substrate 1 and the counter substrate 101 so as to face each other, and filling and sealing the liquid crystal material 102 between them (a seal used for sealing is not shown).
　アクティブマトリクス基板１上に形成される保護配線５と接続素子１０は、マザー基板を切断して複数の液晶パネルに分割する工程（以下、切断工程という）で除去される。具体的には、図１に示す線Ａ－Ａ’より上の部分（後述する図３では、線Ｂ－Ｂ’より右の部分）は、切断工程で除去される。 The protective wiring 5 and the connection element 10 formed on the active matrix substrate 1 are removed in a process of dividing the mother substrate into a plurality of liquid crystal panels (hereinafter referred to as a cutting process). Specifically, the portion above line A-A ′ shown in FIG. 1 (the portion on the right side of line B-B ′ in FIG. 3 described later) is removed in the cutting step.
　本実施形態に係る液晶パネルは、外部端子４と保護配線５を接続する接続素子１０に特徴がある。接続素子１０は、第１導体部と半導体部と第２導体部を重ねて形成することにより形成される。接続素子１０は、初期状態では非導通状態にある。接続素子１０は、後述する条件下で所定の電圧（以下、接続用電圧という）を印加することにより、非導通状態から導通状態に不可逆的に変化する。以下、接続素子１０を形成する工程を接続素子形成工程といい、接続素子１０を導通させる工程を接続工程という。 The liquid crystal panel according to this embodiment is characterized by a connection element 10 that connects the external terminal 4 and the protective wiring 5. The connection element 10 is formed by overlapping the first conductor part, the semiconductor part, and the second conductor part. The connection element 10 is in a non-conductive state in the initial state. The connection element 10 is irreversibly changed from a non-conduction state to a conduction state by applying a predetermined voltage (hereinafter referred to as a connection voltage) under conditions described later. Hereinafter, the process of forming the connection element 10 is referred to as a connection element formation process, and the process of making the connection element 10 conductive is referred to as a connection process.
　図３は、本実施形態に係る液晶パネルの接続工程を示す図である。図４は、図３の一部の拡大図である。接続素子形成工程では、アクティブマトリクス基板１上の複数の箇所に、第１導体部１１と半導体部１２と例えば第２導体部１３とが重ねて形成され、これにより接続素子１０が形成される。第１導体部１１は、走査信号線Ｇ１～Ｇｍと同じ工程（すなわち、Ｗ／Ｔａの連続スパッタによる成膜、配線化工程）で導体材料を用いて形成される。半導体部１２は、ＴＦＴ６のゲート酸化膜と同じ工程でシリコン酸化物を主成分とする材料を用いて形成される。第２導体部１３は、データ信号線Ｓ１～Ｓｎと同じ工程（すなわち、Ｔｉ／Ａｌ／ＴｉＮの連続スパッタによる成膜、配線化工程）、および、画素電極７と同じ工程（すなわち、ＩＴＯの交流スパッタによる成膜、配線化工程）で形成される。第１導体部１１は配線１５を介して保護配線５（図示せず）に接続され、第２導体部１３は配線１４を介して外部端子４に接続される。第１導体部１１と第２導体部１３の間には絶縁層を有する半導体部１２が介在しているので、接続工程より前では接続素子１０は非導通状態にある。 FIG. 3 is a diagram showing a connection process of the liquid crystal panel according to the present embodiment. FIG. 4 is an enlarged view of a part of FIG. In the connection element forming step, the first conductor portion 11, the semiconductor portion 12, and the second conductor portion 13, for example, are formed at a plurality of locations on the active matrix substrate 1, thereby forming the connection element 10. The first conductor portion 11 is formed using a conductor material in the same process as the scanning signal lines G1 to Gm (that is, film formation by W / Ta continuous sputtering, wiring process). The semiconductor portion 12 is formed using a material mainly composed of silicon oxide in the same process as the gate oxide film of the TFT 6. The second conductor portion 13 has the same process as the data signal lines S1 to Sn (that is, a film forming and wiring process by continuous sputtering of Ti / Al / TiN) and the same process as the pixel electrode 7 (that is, an alternating current of ITO). Film formation by sputtering, wiring process). The first conductor portion 11 is connected to the protective wiring 5 (not shown) via the wiring 15, and the second conductor portion 13 is connected to the external terminal 4 via the wiring 14. Since the semiconductor part 12 having an insulating layer is interposed between the first conductor part 11 and the second conductor part 13, the connection element 10 is in a non-conductive state before the connection process.
　接続工程では、接続用電圧を出力する電源回路２１が使用される。電源回路２１には、電圧印加用の針２２、２３が接続される。一方の針２３は、保護配線５（または、保護配線５に接続された配線１５）に当てられる。他方の針２２は、接続素子１０の最上層にある第２導体部１３に押し当てられる。第２導体部１３に針２２を押し当てると、接続素子１０（特に、半導体部１２）は圧縮され、歪みが内在した状態となる。電源回路２１は、圧縮して歪ませた状態の接続素子１０に接続用電圧を印加する。これにより、半導体部１２は破壊され、接続素子１０は非導通状態から導通状態に不可逆的に変化する。このように接続工程では、第２導体部１３に電圧印加用の針２２を押し当て、接続素子１０を圧縮して歪ませた状態で第１導体部１１と第２導体部１３の間に接続用電圧を印加することにより、接続素子１０を非導通状態から導通状態に不可逆的に変化させる。 In the connection process, a power supply circuit 21 that outputs a connection voltage is used. Voltage supply needles 22 and 23 are connected to the power supply circuit 21. One needle 23 is applied to the protective wiring 5 (or the wiring 15 connected to the protective wiring 5). The other needle 22 is pressed against the second conductor portion 13 in the uppermost layer of the connection element 10. When the needle 22 is pressed against the second conductor portion 13, the connection element 10 (particularly, the semiconductor portion 12) is compressed and is in a state in which distortion is inherent. The power supply circuit 21 applies a connection voltage to the connection element 10 in a compressed and distorted state. Thereby, the semiconductor part 12 is destroyed and the connection element 10 is irreversibly changed from the non-conductive state to the conductive state. In this way, in the connection step, the voltage application needle 22 is pressed against the second conductor 13 and the connection element 10 is compressed and distorted so that the connection is made between the first conductor 11 and the second conductor 13. By applying the application voltage, the connection element 10 is irreversibly changed from the non-conductive state to the conductive state.
　図５Ａは、接続工程の前のアクティブマトリクス基板１の状態を示す図である。図５Ｂは、接続工程の後のアクティブマトリクス基板１の状態を示す図である。接続工程の前（図５Ａ）では、接続素子１０は非導通状態にあるので、外部端子４は互いに高抵抗によって電気的に切り離された状態にある。したがって、接続素子１０の第２導体部１３に検査用電圧を印加することにより、保護配線５を有する状態でも、外部端子４に独立した信号を入力してアクティブマトリクス基板１の電気的検査を行うことができる。なお、アクティブマトリクス基板１の電気的検査を行うときには、検査用電圧を外部端子４や配線１４に印加してもよい。 FIG. 5A is a diagram showing a state of the active matrix substrate 1 before the connection process. FIG. 5B is a diagram illustrating a state of the active matrix substrate 1 after the connection process. Prior to the connection step (FIG. 5A), since the connection element 10 is in a non-conductive state, the external terminals 4 are electrically disconnected from each other by a high resistance. Therefore, by applying an inspection voltage to the second conductor portion 13 of the connection element 10, an independent signal is input to the external terminal 4 to perform an electrical inspection of the active matrix substrate 1 even when the protective wiring 5 is provided. be able to. When performing an electrical inspection of the active matrix substrate 1, an inspection voltage may be applied to the external terminal 4 or the wiring 14.
　接続工程の後（図５Ｂ）では、接続素子１０は導通状態にあるので、すべての外部端子４は保護配線５に共通接続される。したがって、アクティブマトリクス基板１で帯電が生じたときでも、電荷は複数の外部端子４に分散するので、外部端子４の間に大きな電位差が生じない。よって、接続工程の後では、アクティブマトリクス基板１の静電気破壊を防止することができる。 After the connection step (FIG. 5B), since the connection element 10 is in a conductive state, all the external terminals 4 are commonly connected to the protective wiring 5. Therefore, even when charging occurs in the active matrix substrate 1, the electric charge is dispersed to the plurality of external terminals 4, so that a large potential difference does not occur between the external terminals 4. Therefore, after the connecting step, electrostatic breakdown of the active matrix substrate 1 can be prevented.
　図６は、本実施形態に係る液晶パネルの製造工程を示す図である。ＴＦＴ形成工程Ｓ１では、アクティブマトリクス基板１上に、走査信号線Ｇ１～ＧｍやＴＦＴ６のゲート電極などが形成される。画素形成工程Ｓ２では、ＩＴＯ膜を用いて画素電極７などが形成される。接続素子１０は、ＴＦＴ形成工程Ｓ１と画素形成工程Ｓ２で形成される。画素形成工程Ｓ２が終了した段階で、アクティブマトリクス基板１上には非導通状態の接続素子１０が複数個形成されている。 FIG. 6 is a diagram showing a manufacturing process of the liquid crystal panel according to the present embodiment. In the TFT formation step S1, the scanning signal lines G1 to Gm, the gate electrode of the TFT 6, and the like are formed on the active matrix substrate 1. In the pixel forming step S2, the pixel electrode 7 and the like are formed using an ITO film. The connection element 10 is formed in the TFT formation step S1 and the pixel formation step S2. A plurality of non-conductive connection elements 10 are formed on the active matrix substrate 1 when the pixel formation step S2 is completed.
　検査／接続工程Ｓ３では、まずアクティブマトリクス基板１の電気的検査が行われ、続いて接続素子１０を導通させる処理が行われる。アクティブマトリクス基板１の電気的検査を行うときには、第２導体部１３に針を当て、第２導体部１３に検査用電圧を印加する。接続素子１０を導通させるときには、検査用電圧を印加するときに用いた針を電圧印加用の針２２として用いる。これにより、第２導体部１３に針を当てた状態のままで、アクティブマトリクス基板１の検査に続いて、接続素子１０を導通させる処理を行うことができる。 In the inspection / connection step S3, an electrical inspection of the active matrix substrate 1 is first performed, and then a process for making the connection element 10 conductive is performed. When an electrical inspection of the active matrix substrate 1 is performed, a needle is applied to the second conductor portion 13 and an inspection voltage is applied to the second conductor portion 13. When the connection element 10 is made conductive, the needle used for applying the inspection voltage is used as the voltage application needle 22. Thereby, the process which makes the connection element 10 conduct | electrically_connected can be performed following the test | inspection of the active-matrix board | substrate 1 with the state which applied the needle | hook to the 2nd conductor part 13. FIG.
　貼り合わせ工程Ｓ４では、アクティブマトリクス基板１と対向基板１０１を貼り合わる処理が行われる。液晶工程Ｓ５では、アクティブマトリクス基板１と対向基板１０１の間に液晶物質１０２を充填、密封する処理が行われる。切断工程Ｓ６では、マザー基板を切断して複数の液晶パネル１００に分割する処理が行われる。実装工程Ｓ７では、液晶パネル１００に偏光板（図示せず）を貼り付ける処理などが行われる。 In the bonding step S4, a process of bonding the active matrix substrate 1 and the counter substrate 101 is performed. In the liquid crystal process S5, a process of filling and sealing the liquid crystal substance 102 between the active matrix substrate 1 and the counter substrate 101 is performed. In the cutting step S6, a process of cutting the mother substrate and dividing it into a plurality of liquid crystal panels 100 is performed. In the mounting step S7, a process of attaching a polarizing plate (not shown) to the liquid crystal panel 100 is performed.
　図７は、本実施形態に係る液晶パネルの他の製造工程を示す図である。図７に示す製造工程では、検査／接続工程Ｓ３に代えて、検査／修正／接続工程Ｓ１３が行われる。検査／修正／接続工程Ｓ１３では、アクティブマトリクス基板１の電気的検査に続いて、アクティブマトリクス基板１を修正する処理が行われ、修正の成功／不成功を検査した後に、接続素子１０を導通させる処理が行われる。これにより、液晶パネル１００の歩留まりを向上させることができる。 FIG. 7 is a diagram showing another manufacturing process of the liquid crystal panel according to the present embodiment. In the manufacturing process shown in FIG. 7, an inspection / correction / connection process S13 is performed instead of the inspection / connection process S3. In the inspection / correction / connection process S13, after the electrical inspection of the active matrix substrate 1, a process of correcting the active matrix substrate 1 is performed, and after checking the success / failure of the correction, the connection element 10 is made conductive. Processing is performed. Thereby, the yield of the liquid crystal panel 100 can be improved.
　図８Ａおよび図８Ｂは、従来の液晶パネルの製造工程を示す図である。従来の液晶パネルの製造工程においてＩＴＯ膜を用いて外部端子と保護配線を接続する場合、画素電極を形成した後ではアクティブマトリクス基板の電気的検査を行うことができない。このため、アクティブマトリクス基板の電気的検査を行った後に画素電極を形成するか（図８Ａ）、画素検査後に、接続用に成膜、配線化することで外部端子と保護配線を接続するか（図８Ｂ）のいずれかになる。しかしながら、前者の方法には画素形成工程で発生した欠陥を検出、修正できないという問題があり、後者の方法には外部端子と保護配線を接続するために新たな工程（図８Ｂの接続配線形成工程）を追加する必要があるという問題がある。 8A and 8B are diagrams showing a manufacturing process of a conventional liquid crystal panel. When the external terminal and the protective wiring are connected using an ITO film in the conventional manufacturing process of the liquid crystal panel, the active matrix substrate cannot be electrically inspected after the pixel electrode is formed. Therefore, whether the pixel electrode is formed after the electrical inspection of the active matrix substrate (FIG. 8A), or whether the external terminal and the protective wiring are connected by forming a film and wiring for connection after the pixel inspection ( 8B). However, the former method has a problem that defects generated in the pixel formation process cannot be detected and corrected, and the latter method has a new process (connection wiring formation process in FIG. 8B) for connecting the external terminal and the protective wiring. ) Need to be added.
　これに対して、本実施形態に係る液晶パネルの製造工程（図６および図７）では、アクティブマトリクス基板１の電気的検査と接続素子１０を導通させる処理とを同一工程内で続けて行うことができる。また、接続素子１０は、アクティブマトリクス基板１の通常の製造工程で形成することができる。したがって、本実施形態に係る液晶パネルの製造工程によれば、新な工程を追加することなく外部端子と保護配線を接続し、かつ、画素形成工程で発生した欠陥を検出、修正することができる。 On the other hand, in the manufacturing process of the liquid crystal panel according to the present embodiment (FIGS. 6 and 7), the electrical inspection of the active matrix substrate 1 and the process of conducting the connection element 10 are continuously performed in the same process. Can do. Further, the connection element 10 can be formed by a normal manufacturing process of the active matrix substrate 1. Therefore, according to the manufacturing process of the liquid crystal panel according to the present embodiment, it is possible to connect the external terminal and the protective wiring without adding a new process, and to detect and correct a defect generated in the pixel forming process. .
　上述したように、接続工程では、第２導体部１３に電圧印加用の針２２を押し当て、接続素子１０を圧縮して歪ませた状態で第１導体部１１と第２導体部１３の間に接続用電圧を印加する。以下、この点について、不可逆的に書き込み可能なＲＯＭ（ＥＰＲＯＭ：Electrically Programmable Read Only Memory）を例に挙げて説明する。ＥＰＲＯＭの一種であるＦＰＧＡ（Field Programmable Gate Array ：フィールドプログラマブルゲートアレイ）の動作電圧は０Ｖ～＋５Ｖ程度であり、ＦＰＧＡのアンチヒューズ（電気的に接続する）には約１０Ｖの電圧が使用される。一方、画素領域２に含まれるＴＦＴ６には、動作時に－５Ｖ～＋１０Ｖ程度の駆動電圧が印加される。このため、＋１０Ｖ程度の電圧を印加してもＴＦＴ６が破壊しないように、ＴＦＴ６のゲート酸化膜を厚くする必要がある。図９は、ゲート酸化膜厚とゲート破壊電圧の関係を示す図である。図９に示すように、例えば、ゲート酸化膜だけで２０Ｖ以上の耐圧を実現するためには、ゲート酸化膜厚を３０ｎｍ以上にする必要がある。 As described above, in the connection step, the voltage application needle 22 is pressed against the second conductor portion 13 to compress and distort the connection element 10 between the first conductor portion 11 and the second conductor portion 13. Apply connection voltage to. Hereinafter, this point will be described by taking an irreversibly writable ROM (EPROM: Electrically Programmable Read Only Memory) as an example. The operating voltage of an FPGA (Field Programmable Gate Array: Field Programmable Gate Array), which is a kind of EPROM, is about 0V to + 5V, and a voltage of about 10V is used for the antifuse (electrically connected) of the FPGA. On the other hand, a driving voltage of about −5 V to +10 V is applied to the TFT 6 included in the pixel region 2 during operation. For this reason, it is necessary to make the gate oxide film of the TFT 6 thick so that the TFT 6 is not broken even when a voltage of about + 10V is applied. FIG. 9 is a diagram showing the relationship between the gate oxide film thickness and the gate breakdown voltage. As shown in FIG. 9, for example, in order to achieve a breakdown voltage of 20 V or more with only the gate oxide film, the gate oxide film thickness needs to be 30 nm or more.
　接続素子１０の半導体部１２はＴＦＴ６のゲート酸化膜と同じ工程で形成されるので、半導体部１２の厚さはＴＦＴ６のゲート酸化膜厚と同じになる。このため、電圧印加用の針２２で押圧することなく接続素子１０に接続用電圧を印加した場合、ブレークダウン電圧を超えた状態となった後に、不定期的に接続素子１０に激しいジュール熱が発生するほどの高密度の電流が突然流れて、接続素子１０が焼けるという危険性が生じる。 Since the semiconductor part 12 of the connection element 10 is formed in the same process as the gate oxide film of the TFT 6, the thickness of the semiconductor part 12 is the same as the gate oxide film thickness of the TFT 6. For this reason, when the connection voltage is applied to the connection element 10 without being pressed by the voltage application needle 22, after the breakdown voltage is exceeded, the connection element 10 is subjected to intense Joule heat irregularly. There is a danger that a high-density current that is generated suddenly flows and the connecting element 10 is burnt.
　そこで、本実施形態に係る接続工程では、第２導体部１３に電圧印加用の針２２を押し当て、接続素子１０を圧縮して歪ませた状態で第１導体部１１と第２導体部１３の間に接続用電圧を印加する。このため、本実施形態に係る接続工程では、電流は接続素子１０のうちで電圧印加用の針２２で押圧された部分に局所的に流れる。したがって、電圧印加用の針２２で押圧しない場合と比べて、低い電圧状態から通電が始まり、通電領域も制御できるので、接続素子１０の全体に流れる電流はより穏やかとなる。また、接続素子１０で局所的に生じた発熱は周辺領域に円滑に散逸し、急激な過熱による焼け焦げでの配線の切断が起こりにくくなる。よって、圧縮して歪ませた状態の接続素子１０に接続用電圧を印加することにより、接続素子１０を導通させるときの電流や発熱を平滑化することができる。 Therefore, in the connection step according to the present embodiment, the first conductor portion 11 and the second conductor portion 13 are pressed in a state where the voltage application needle 22 is pressed against the second conductor portion 13 to compress and distort the connection element 10. A connection voltage is applied between the two. For this reason, in the connection process according to the present embodiment, the current locally flows in a portion of the connection element 10 pressed by the voltage application needle 22. Therefore, compared with the case where the needle 22 for applying voltage is not pressed, energization starts from a low voltage state and the energization region can be controlled, so that the current flowing through the entire connection element 10 becomes gentler. Further, the heat generated locally in the connection element 10 is smoothly dissipated to the peripheral region, and the wiring is not easily cut by scorching due to sudden overheating. Therefore, by applying a connection voltage to the connection element 10 in a compressed and distorted state, current and heat generated when the connection element 10 is conducted can be smoothed.
　以上に示すように、本実施形態に係る液晶パネルの製造方法は、アクティブマトリクス基板１上の複数の箇所に、保護配線５に接続された第１導体部１１、半導体部１２、および、各外部端子４に接続された第２導体部１３を重ねて形成することにより、複数の接続素子１０を形成する工程と、接続素子１０の一方の導体部（第２導体部１３）に電圧印加用の針２２を押し当て、接続素子１０を圧縮して歪ませた状態で第１導体部１１と第２導体部１３の間に接続用電圧を印加することにより、接続素子１０を非導通状態から導通状態に不可逆的に変化させる接続工程とを備えている。接続工程より前に、第２導体部１３に検査用電圧を印加してアクティブマトリクス基板１を検査する。 As described above, the manufacturing method of the liquid crystal panel according to the present embodiment includes the first conductor portion 11 connected to the protective wiring 5, the semiconductor portion 12, and each external part at a plurality of locations on the active matrix substrate 1. By forming the second conductor portion 13 connected to the terminal 4 in an overlapping manner, a step of forming a plurality of connection elements 10 and a voltage application to one conductor portion (second conductor portion 13) of the connection element 10 are performed. By applying a connecting voltage between the first conductor portion 11 and the second conductor portion 13 in a state where the needle 22 is pressed and the connecting element 10 is compressed and distorted, the connecting element 10 is made conductive from the non-conductive state. And a connection step for irreversibly changing the state. Prior to the connection step, the active matrix substrate 1 is inspected by applying an inspection voltage to the second conductor portion 13.
　したがって、本実施形態に係る液晶パネルの製造方法によれば、複数の外部端子４を保護配線５に共通接続し、液晶パネル１００の静電気破壊を防止することができる。また、接続工程より前では外部端子４は互いに高抵抗によって電気的に切り離されているので、保護配線５を有する状態でも外部端子４に独立した信号を入力してアクティブマトリクス基板１の検査を行うことができる。接続素子１０は、アクティブマトリクス基板１の通常の製造工程で形成することができる。また、圧縮して歪ませた状態の接続素子１０に接続用電圧を印加することにより、接続素子１０を導通させるときの電流や発熱を平滑化することができる。 Therefore, according to the manufacturing method of the liquid crystal panel according to the present embodiment, the plurality of external terminals 4 can be commonly connected to the protective wiring 5, and electrostatic breakdown of the liquid crystal panel 100 can be prevented. Further, since the external terminals 4 are electrically separated from each other by a high resistance before the connection process, the active matrix substrate 1 is inspected by inputting an independent signal to the external terminals 4 even when the protective wiring 5 is provided. be able to. The connection element 10 can be formed by a normal manufacturing process of the active matrix substrate 1. In addition, by applying a connection voltage to the connection element 10 in a compressed and distorted state, current and heat generated when the connection element 10 is conducted can be smoothed.
　また、接続工程では検査用電圧を印加するときに用いた検査用の針を電圧印加用の針２２として用いることにより、第２導体部１３に針を当てた状態のままで、アクティブマトリクス基板１の検査に続いて、接続素子１０を導通させる処理を行うことができる。また、接続工程より前に検査結果に基づきアクティブマトリクス基板１を修正することにより、液晶パネル１００の歩留まりを向上させることができる。 In the connection step, the inspection matrix used when applying the inspection voltage is used as the voltage application needle 22, so that the active matrix substrate 1 remains in a state where the needle is applied to the second conductor portion 13. Subsequent to the inspection, a process for making the connection element 10 conductive can be performed. Further, the yield of the liquid crystal panel 100 can be improved by correcting the active matrix substrate 1 based on the inspection result before the connection step.
　（第２の実施形態）
　図１０は、本発明の第２の実施形態に係る液晶パネルの接続工程を示す図である。図１０に示すように、本実施形態に係る接続工程では、電源回路２１、複数のスイッチ２４、および、複数の電流センサ（図示せず）を用いて、複数の接続素子１０を順次に導通させる。スイッチ２４と電流センサは、接続素子１０を流れる電流の経路上に直列に設けられる。電流センサは、接続素子１０に流れる電流を検知する。 (Second Embodiment)
FIG. 10 is a diagram showing a connection process of the liquid crystal panel according to the second embodiment of the present invention. As shown in FIG. 10, in the connection process according to the present embodiment, the plurality of connection elements 10 are sequentially conducted using the power supply circuit 21, the plurality of switches 24, and the plurality of current sensors (not shown). . The switch 24 and the current sensor are provided in series on the path of the current flowing through the connection element 10. The current sensor detects a current flowing through the connection element 10.
　以下、接続工程において４個の接続素子１０ａ～１０ｄを導通させる場合について説明する。接続素子１０ａ～１０ｄを流れる電流の経路上に設けられたスイッチをスイッチ２４ａ～２４ｄという。また、図面の理解を容易にするために、図１０および後述する図１２では、電源回路２１に文字Ｅを記して複数の円で表す。 Hereinafter, a case where the four connection elements 10a to 10d are conducted in the connection process will be described. The switches provided on the path of the current flowing through the connection elements 10a to 10d are referred to as switches 24a to 24d. Further, in order to facilitate understanding of the drawings, in FIG. 10 and FIG.
　図１１は、接続素子１０ａ～１０ｄに印加される電圧Ｖａ～Ｖｄと接続素子１０ａ～１０ｄを流れる電流Ｉａ～Ｉｄの変化を示す図である。まず、スイッチ２４ａ（接続素子１０ａに対応したスイッチ）が導通状態になり、電源回路２１は電圧Ｖａ（接続素子１０ａに印加される電圧）を所定の速度で上昇させる。電流Ｉａ（接続素子１０ａを流れる電流）が第１閾値Ｉｔｈ１を超えると、電源回路２１は電圧Ｖａの上昇速度を遅くする。電流Ｉａが第２閾値Ｉｔｈ２（Ｉｔｈ２＞Ｉｔｈ１）を超えると、接続素子１０ａは安定的に導通状態になる。そこで、電源回路２１は電圧Ｖａをゼロに制御し、スイッチ２４ａは非導通状態になる。なお、電流Ｉａが第１閾値Ｉｔｈ１を超えた以降、電源回路２１は電圧Ｖａを一定にしてもよい。 FIG. 11 is a diagram illustrating changes in voltages Va to Vd applied to the connection elements 10a to 10d and currents Ia to Id flowing through the connection elements 10a to 10d. First, the switch 24a (switch corresponding to the connection element 10a) is turned on, and the power supply circuit 21 increases the voltage Va (voltage applied to the connection element 10a) at a predetermined speed. When the current Ia (current flowing through the connection element 10a) exceeds the first threshold value Ith1, the power supply circuit 21 slows the rate of increase of the voltage Va. When the current Ia exceeds the second threshold value Ith2 (Ith2> Ith1), the connection element 10a is stably in a conductive state. Therefore, the power supply circuit 21 controls the voltage Va to zero, and the switch 24a is turned off. Note that, after the current Ia exceeds the first threshold value Ith1, the power supply circuit 21 may keep the voltage Va constant.
　次に、電源回路２１は、接続素子１０ｂに印加される電圧Ｖｂを同じ方法で制御する。さらに、電源回路２１は、接続素子１０ｃに印加される電圧Ｖｃ、および、接続素子１０ｄに印加される電圧Ｖｄを同じ方法で制御する。このように本実施形態に係る接続工程では、電源回路２１とスイッチ２４ａ～２４ｄを用いて、接続素子１０を流れる電流が閾値を超えたときに、接続用電圧を印加する接続素子１０を切り替える。 Next, the power supply circuit 21 controls the voltage Vb applied to the connection element 10b by the same method. Furthermore, the power supply circuit 21 controls the voltage Vc applied to the connection element 10c and the voltage Vd applied to the connection element 10d by the same method. As described above, in the connection process according to the present embodiment, when the current flowing through the connection element 10 exceeds the threshold, the connection element 10 to which the connection voltage is applied is switched using the power supply circuit 21 and the switches 24a to 24d.
　第１の実施形態と同様に本実施形態でも、接続工程の前には、第２導体部１３に検査用電圧を印加して、アクティブマトリクス基板１の電気的検査が行われる。接続工程では、検査用電圧を印加するときに用いた針を電圧印加用の針２２として用いてもよい。これにより、第２導体部１３に針を当てた状態のままで、複数の接続素子１０に対して接続用電圧を順次に印加することができる。また、第１の実施形態と同様に本実施形態でも、接続工程の前に、アクティブマトリクス基板１を修正する処理を行ってもよい。 Similarly to the first embodiment, in this embodiment, an electrical inspection of the active matrix substrate 1 is performed by applying an inspection voltage to the second conductor portion 13 before the connection step. In the connection step, the needle used when applying the inspection voltage may be used as the voltage application needle 22. Thereby, it is possible to sequentially apply connection voltages to the plurality of connection elements 10 while the needle is applied to the second conductor portion 13. Further, in the present embodiment as well as the first embodiment, a process for correcting the active matrix substrate 1 may be performed before the connection step.
　以上に示すように、本実施形態に係る液晶パネルの製造方法によれば、接続工程において複数の接続素子１０に対して接続用電圧を順次に印加することにより、各外部端子４と保護配線５を確実に接続することができる。また、接続工程では接続素子１０を流れる電流が閾値を超えたときに、接続用電圧を印加する接続素子１０を切り替えることにより、各外部端子４と保護配線５とを過剰な電流を流すことなく確実に接続することができる。 As described above, according to the manufacturing method of the liquid crystal panel according to the present embodiment, the connection voltage is sequentially applied to the plurality of connection elements 10 in the connection step, whereby each external terminal 4 and the protective wiring 5 Can be securely connected. Further, in the connection process, when the current flowing through the connection element 10 exceeds the threshold value, the connection element 10 to which the connection voltage is applied is switched, so that an excessive current does not flow through each external terminal 4 and the protective wiring 5. It can be securely connected.
　（第３の実施形態）
　図１２は、本発明の第３の実施形態に係る液晶パネルの接続工程を示す図である。図１２に示すように、本実施形態に係る接続工程では、電源回路２１と複数のサーミスタ２５を用いて複数の接続素子１０を並列に導通させる。サーミスタ２５は、感温素子の一種であり、接続素子１０を流れる電流の経路上に設けられる。サーミスタ２５には、正温度特性（温度が高くなると抵抗値が大きくなる特性）を有するＰＴＣ（Positive Temperature Coefficient）サーミスタを使用する。 (Third embodiment)
FIG. 12 is a diagram showing a connection process of the liquid crystal panel according to the third embodiment of the present invention. As shown in FIG. 12, in the connection process according to the present embodiment, the plurality of connection elements 10 are conducted in parallel using the power supply circuit 21 and the plurality of thermistors 25. The thermistor 25 is a kind of temperature sensitive element, and is provided on a path of current flowing through the connection element 10. As the thermistor 25, a PTC (Positive Temperature Coefficient) thermistor having a positive temperature characteristic (a characteristic in which a resistance value increases as the temperature increases) is used.
　図１３は、ＰＴＣサーミスタの温度による抵抗変化を示す特性の例を数例示す特性図である。図１３において、横軸は温度を示し、縦軸は２５℃のときの抵抗値を１とした抵抗比を対数値で示す。図１３に示すように、ＰＴＣサーミスタの抵抗値は、温度がある程度高くなると急激に大きくなる。例えば、温度が２５℃から１００℃に変化すると、ＰＴＣサーミスタの抵抗は１０００倍以上になる。ＰＴＣサーミスタは、過熱防止用のスイッチとして使用される。 FIG. 13 is a characteristic diagram showing several examples of characteristics indicating resistance change with temperature of the PTC thermistor. In FIG. 13, the horizontal axis indicates the temperature, and the vertical axis indicates the resistance ratio with a resistance value of 1 at 25 ° C. as a logarithmic value. As shown in FIG. 13, the resistance value of the PTC thermistor increases rapidly when the temperature rises to some extent. For example, when the temperature changes from 25 ° C. to 100 ° C., the resistance of the PTC thermistor becomes 1000 times or more. The PTC thermistor is used as a switch for preventing overheating.
　以下、サーミスタ２５を設けることによる効果を説明する。複数の接続素子１０に対して並列に接続用電圧を印加するときに、各接続素子１０に実際に接続用電圧が印加され始めるタイミングには差異がある。また、接続素子１０の形状や特性にも差異がある。このため、接続素子１０が導通するタイミングには微小な差異が生じる。このため、サーミスタ２５を設けない場合には、先に導通した接続素子１０に大きな電流が流れて、回路全体に流れる電流の大半が先に導通した接続素子１０に集中してしまうために、他の接続素子１０の導通が不充分な状態となるという問題が生じる。 Hereinafter, the effect of providing the thermistor 25 will be described. There is a difference in the timing at which the connection voltage is actually applied to each connection element 10 when the connection voltage is applied in parallel to the plurality of connection elements 10. There are also differences in the shape and characteristics of the connecting element 10. For this reason, a minute difference occurs in the timing at which the connection element 10 becomes conductive. For this reason, when the thermistor 25 is not provided, a large current flows through the connection element 10 that has been previously conducted, and most of the current that flows through the entire circuit is concentrated on the connection element 10 that has been previously conducted. There arises a problem that the conduction of the connecting element 10 becomes insufficient.
　これに対して、サーミスタ２５を設けた場合には、先に導通した接続素子１０に大きな電流が流れると、対応したサーミスタ２５の温度がジュール熱によって上昇する。サーミスタ２５の温度がある程度高くなると、サーミスタ２５の抵抗が急激に大きくなる。これにより、先に導通した接続素子１０に流れる電流を抑制し、回路全体に流れる電流の均整を保つことができる。したがって、他の接続素子１０の導通の不均一性を防止することができる。 On the other hand, in the case where the thermistor 25 is provided, when a large current flows through the previously connected connection element 10, the temperature of the corresponding thermistor 25 rises due to Joule heat. When the temperature of the thermistor 25 increases to some extent, the resistance of the thermistor 25 increases rapidly. Thereby, the electric current which flows into the connection element 10 which conduct | electrically_connected previously can be suppressed, and the balance of the electric current which flows into the whole circuit can be maintained. Therefore, the non-uniformity of conduction of other connection elements 10 can be prevented.
　以下、接続工程において４個の接続素子１０ａ～１０ｄを導通させる場合について説明する。接続素子１０ａ～１０ｄを流れる電流の経路上に設けられたサーミスタをサーミスタ２５ａ～２５ｄという。 Hereinafter, a case where the four connection elements 10a to 10d are conducted in the connection process will be described. The thermistors provided on the path of the current flowing through the connection elements 10a to 10d are referred to as thermistors 25a to 25d.
　図１４は、接続素子１０ａ、１０ｂに印加される電圧Ｖａ、Ｖｂと接続素子１０ａ、１０ｂを流れる電流Ｉａ、Ｉｂの変化を示す図である。以下、４個の接続素子１０ａ～１０ｄのうちで、接続素子１０ａが最初に導通した場合について説明する。時刻ｔ１において接続素子１０ａが導通すると、接続素子１０ａに大きな電流が流れる。このため、回路全体の電圧降下が発生し、電圧Ｖｂ（接続素子１０ｂに印加される電圧）は低下する。その後、サーミスタ２５ａ（接続素子１０ａに対応したサーミスタ）の温度がジュール熱によって上昇し、サーミスタ２５ａの温度がある程度高くなると、サーミスタ２５ａの抵抗が急激に大きくなる。これ以降、接続素子１０ａには電流は流れなくなるので、電圧Ｖｂは時刻ｔ２において元のレベルに戻る。したがって、接続素子１０ｂに印加される電圧Ｖｂを維持し、接続素子１０ｂの導通が遅れることを防止することができる。同様に、接続素子１０ｃ、１０ｄの導通が遅れることも防止することができる。 FIG. 14 is a diagram illustrating changes in voltages Va and Vb applied to the connection elements 10a and 10b and currents Ia and Ib flowing through the connection elements 10a and 10b. Hereinafter, the case where the connection element 10a is first conducted among the four connection elements 10a to 10d will be described. When the connection element 10a becomes conductive at time t1, a large current flows through the connection element 10a. For this reason, a voltage drop of the entire circuit occurs, and the voltage Vb (voltage applied to the connection element 10b) decreases. Thereafter, when the temperature of the thermistor 25a (thermistor corresponding to the connection element 10a) rises due to Joule heat and the temperature of the thermistor 25a rises to some extent, the resistance of the thermistor 25a suddenly increases. Thereafter, no current flows through the connection element 10a, so that the voltage Vb returns to the original level at time t2. Therefore, it is possible to maintain the voltage Vb applied to the connection element 10b and to prevent the conduction of the connection element 10b from being delayed. Similarly, it is possible to prevent the conduction of the connection elements 10c and 10d from being delayed.
　図１５は、接続素子１０ａ～１０ｄを並列に導通させるときの等価回路図である。図１５において、Ｒａ～Ｒｄは接続素子１０ａ～１０ｄの抵抗を示し、Ｚａ～Ｚｄはサーミスタ２５ａ～２５ｄの抵抗を示す。以下、接続工程における図１５に示す回路の抵抗の変化を説明する。 FIG. 15 is an equivalent circuit diagram when the connection elements 10a to 10d are conducted in parallel. In FIG. 15, Ra to Rd indicate the resistances of the connection elements 10a to 10d, and Za to Zd indicate the resistances of the thermistors 25a to 25d. Hereinafter, a change in resistance of the circuit shown in FIG. 15 in the connection process will be described.
　接続工程の前段階では、サーミスタの温度は低く、Ｒａ＞＞Ｚａ、Ｒｂ＞＞Ｚｂ、Ｒｃ＞＞Ｚｃ、Ｒｄ＞＞Ｚｄの状態となり、回路抵抗は｛（Ｒａ）-1＋（Ｒｂ）-1＋（Ｒｃ）-1＋（Ｒｄ）-1｝-1となる。最初に接続素子１０ａが導通すると、抵抗Ｒａが急激に小さくなり、Ｒａ＜＜Ｚａとなる。このとき回路抵抗は、｛（Ｚａ）-1＋（Ｒｂ）-1＋（Ｒｃ）-1＋（Ｒｄ）-1｝-1となる。これ以降、接続素子１０ａとサーミスタ２５ａに大きな電流が流れるので、出力電源から回路全体に供給されるエネルギーの大半が接続素子１０ａのまわりで消費され、電源の供給能力を上回ることで電圧降下が発生し、接続素子１０ｂ～１０ｄに印加される電圧も低下する。その後、サーミスタ２５ａの温度がジュール熱による温度上昇によってある程度高くなるに従って、抵抗Ｚａが指数関数的に増大する。接続素子１０ａが導通してからしばらくすると、回路全体の電圧が回復し、接続素子１０ｂ～１０ｄに印加される電圧も回復する。 In the previous stage of the connection process, the thermistor temperature is low, Ra >> Za, Rb >> Zb, Rc >> Zc, Rd >> Zd, and the circuit resistance is {(Ra) −1 + (Rb) −. 1 + (Rc) becomes -1 + (Rd) -1} -1 . When the connection element 10a is first turned on, the resistance Ra decreases rapidly, and Ra << Za. At this time, the circuit resistance is {(Za) −1 + (Rb) −1 + (Rc) −1 + (Rd) −1 } −1 . Thereafter, a large current flows through the connection element 10a and the thermistor 25a, so that most of the energy supplied from the output power supply to the entire circuit is consumed around the connection element 10a, resulting in a voltage drop due to exceeding the power supply capability. In addition, the voltage applied to the connection elements 10b to 10d also decreases. Thereafter, the resistance Za increases exponentially as the temperature of the thermistor 25a increases to some extent due to the temperature rise due to Joule heat. After a while after the connection element 10a becomes conductive, the voltage of the entire circuit is recovered, and the voltages applied to the connection elements 10b to 10d are also recovered.
　次に接続素子１０ｂが導通すると、抵抗Ｒｂが急激に小さくなり、Ｒｂ＜＜Ｚｂとなる。このとき回路抵抗は、｛（Ｚａ）-1＋（Ｚｂ）-1＋（Ｒｃ）-1＋（Ｒｄ）-1｝-1となる。これ以降、接続素子１０ｂとサーミスタ２５ｂに大きな電流が流れるので、回路全体の電圧降下が発生し、接続素子１０ｃ、１０ｄに印加される電圧も低下する。その後、サーミスタ２５ｂの温度がジュール熱によって上昇しある程度高くなると、抵抗Ｚｂが急激に大きくなる。接続素子１０ｂが導通してからしばらくすると、回路全体の電圧が回復し、接続素子１０ｃ、１０ｄに印加される電圧も回復する。接続素子１０ｃ、１０ｄが導通したときにも、図１５に示す回路の抵抗は同様に変化する。 Next, when the connection element 10b is turned on, the resistance Rb rapidly decreases, and Rb << Zb. At this time, the circuit resistance is {(Za) −1 + (Zb) −1 + (Rc) −1 + (Rd) −1 } −1 . Thereafter, since a large current flows through the connection element 10b and the thermistor 25b, a voltage drop occurs in the entire circuit, and the voltage applied to the connection elements 10c and 10d also decreases. Thereafter, when the temperature of the thermistor 25b rises due to Joule heat and increases to some extent, the resistance Zb rapidly increases. After a while after the connection element 10b becomes conductive, the voltage of the entire circuit is recovered, and the voltage applied to the connection elements 10c and 10d is also recovered. Even when the connection elements 10c and 10d are turned on, the resistance of the circuit shown in FIG. 15 changes similarly.
　本実施形態に係る接続工程では、サーミスタ２５の室温時の抵抗を好適に選択する必要がある。その理由とする処は、室温時（サーミスタの低抵抗条件時）の抵抗を低くに設定しすぎると、高温時（サーミスタの高抵抗化条件時）に十分に高い抵抗値が得られず、回路全体の電圧を十分に回復させることができず、室温時の抵抗を高く設定しすぎると、接続素子１０を導通させるために十分な電流を維持することができず、接続素子１０を導通状態に変化させることができないからである。接続用電圧には５Ｖ～１０Ｖ程度の電圧を用いることが好ましく、接続工程では接続素子１０に数ｍＡ程度の電流を流すことが好ましい。したがって、サーミスタ２５の室温時の抵抗は１ｋΩ程度となる。室温時の抵抗が約１ｋΩであれば、高温時の抵抗は数ＭΩとなるので、回路全体の電圧を十分に回復させることができる。 In the connection process according to the present embodiment, it is necessary to suitably select the resistance of the thermistor 25 at room temperature. The reason is that if the resistance at room temperature (when the resistance of the thermistor is low) is set too low, a sufficiently high resistance value cannot be obtained at high temperatures (when the resistance of the thermistor is high). If the overall voltage cannot be sufficiently recovered and the resistance at room temperature is set too high, a sufficient current cannot be maintained to make the connection element 10 conductive, and the connection element 10 is made conductive. This is because it cannot be changed. It is preferable to use a voltage of about 5 V to 10 V as the connection voltage, and it is preferable to pass a current of about several mA through the connection element 10 in the connection step. Therefore, the resistance of the thermistor 25 at room temperature is about 1 kΩ. If the resistance at room temperature is about 1 kΩ, the resistance at high temperature is several MΩ, so that the voltage of the entire circuit can be sufficiently recovered.
　第１の実施形態と同様に本実施形態でも、接続工程の前には、第２導体部１３に検査用電圧を印加して、アクティブマトリクス基板１の電気的検査が行われる。接続工程では、検査用電圧を印加するときに用いた針を電圧印加用の針２２として用いてもよい。これにより、第２導体部１３に針を当てた状態のままで、複数の接続素子１０に対して接続用電圧を並列に印加することができる。また、第１の実施形態と同様に本実施形態でも、接続工程の前に、アクティブマトリクス基板１を修正する処理を行ってもよい。 Similarly to the first embodiment, in this embodiment, an electrical inspection of the active matrix substrate 1 is performed by applying an inspection voltage to the second conductor portion 13 before the connection step. In the connection step, the needle used when applying the inspection voltage may be used as the voltage application needle 22. Thereby, it is possible to apply the connection voltage in parallel to the plurality of connection elements 10 while the needle is applied to the second conductor portion 13. Further, in the present embodiment as well as the first embodiment, a process for correcting the active matrix substrate 1 may be performed before the connection step.
　以上に示すように、本実施形態に係る液晶パネルの製造方法によれば、接続工程において複数の接続素子１０に対して接続用電圧を並列に印加することで、複数の外部端子４を保護配線５とを接続させるのに短時間の内に実現することができる。また、接続工程では、接続素子１０を流れる電流の経路上に正温度特性を有するサーミスタ２５を設けることで、ある接続素子１０での導通が要因となって他の接続素子１０の導通が遅延することを抑制することができる。 As described above, according to the method for manufacturing the liquid crystal panel according to the present embodiment, the connection voltage is applied in parallel to the plurality of connection elements 10 in the connection step, thereby connecting the plurality of external terminals 4 to the protective wiring. 5 can be realized within a short time. Further, in the connection process, by providing the thermistor 25 having a positive temperature characteristic on the path of the current flowing through the connection element 10, conduction in one connection element 10 is a factor, and conduction in other connection elements 10 is delayed. This can be suppressed.
　なお、以上の説明では、アクティブマトリクス基板１は走査信号線駆動回路３を備えることとしたが、本発明のアクティブマトリクス基板は走査信号線駆動回路を備えていなくてもよく、他の制御回路（例えば、データ信号線駆動回路）の全部または一部を備えていてもよい。また、アクティブマトリクス基板１は保護配線５を１本だけ備えることとしたが、本発明のアクティブマトリクス基板は保護配線を２本以上備えていてもよい。 In the above description, the active matrix substrate 1 includes the scanning signal line driving circuit 3. However, the active matrix substrate of the present invention may not include the scanning signal line driving circuit, and other control circuits ( For example, all or part of the data signal line driver circuit) may be provided. Further, although the active matrix substrate 1 includes only one protective wiring 5, the active matrix substrate of the present invention may include two or more protective wirings.
　本発明の表示装置の製造方法は、外部端子と保護配線を少ない配線量で接続できるという特徴を有するので、例えば、液晶パネルなどのアクティブマトリクス基板の製造に利用することができる。本発明の表示装置は、例えば、液晶パネルなどのアクティブマトリクス基板に利用することができる。 The method for manufacturing a display device according to the present invention has a feature that an external terminal and a protective wiring can be connected with a small amount of wiring, and can be used, for example, for manufacturing an active matrix substrate such as a liquid crystal panel. The display device of the present invention can be used for an active matrix substrate such as a liquid crystal panel, for example.
　１…アクティブマトリクス基板
　２…画素領域
　３…走査信号線駆動回路
　４…外部端子
　５…保護配線
　６…ＴＦＴ
　７…画素電極
　１０…接続素子
　１１…第１導体部
　１２…半導体部
　１３…第２導体部
　１４、１５…配線
　２１…電源回路
　２２、２３…針
　２４…スイッチ
　２５…サーミスタ
　１００…液晶パネル
　１０１…対向基板
　１０２…液晶物質
　１０３…対向電極 DESCRIPTION OF SYMBOLS 1 ... Active matrix substrate 2 ... Pixel area 3 ... Scanning signal line drive circuit 4 ... External terminal 5 ... Protection wiring 6 ... TFT
DESCRIPTION OF SYMBOLS 7 ... Pixel electrode 10 ... Connection element 11 ... 1st conductor part 12 ... Semiconductor part 13 ... 2nd conductor part 14, 15 ... Wiring 21 ... Power supply circuit 22, 23 ... Needle 24 ... Switch 25 ... Thermistor 100 ... Liquid crystal panel 101 ... Counter substrate 102 ... Liquid crystal substance 103 ... Counter electrode

Claims (9)

  1. 　静電気保護機能を有する表示装置の製造方法であって、
    　アクティブマトリクス基板上の複数の箇所に、保護配線に接続された第１導体部、半導体部、および、各外部端子に接続された第２導体部を重ねて形成することにより、複数の接続素子を形成する工程と、
    　前記接続素子の一方の導体部に電圧印加用の針を押し当て、前記接続素子を圧縮して歪ませた状態で前記第１および第２導体部間に接続用電圧を印加することにより、前記接続素子を非導通状態から導通状態に不可逆的に変化させる接続工程とを備えた、表示装置の製造方法。     A method of manufacturing a display device having an electrostatic protection function,
    A plurality of connection elements are formed by overlapping the first conductor portion connected to the protective wiring, the semiconductor portion, and the second conductor portion connected to each external terminal at a plurality of locations on the active matrix substrate. Forming, and
    By applying a voltage for connection between the first and second conductor parts in a state where the connecting element is pressed and pressed against one conductor part of the connection element and the connection element is compressed and distorted, And a connecting step of irreversibly changing the connection element from the non-conductive state to the conductive state.
  2. 　前記接続工程より前に、前記第２導体部に検査用電圧を印加して前記アクティブマトリクス基板を検査する工程をさらに備えた、請求項１に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 1, further comprising a step of inspecting the active matrix substrate by applying an inspection voltage to the second conductor portion before the connection step.
  3. 　前記接続工程では、前記検査用電圧を印加するときに用いた針を前記電圧印加用の針として用いることを特徴とする、請求項２に記載の表示装置の製造方法。 3. The method for manufacturing a display device according to claim 2, wherein, in the connection step, a needle used when applying the inspection voltage is used as the voltage application needle.
  4. 　前記接続工程より前に、検査結果に基づき前記アクティブマトリクス基板を修正する工程をさらに備えた、請求項２に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 2, further comprising a step of correcting the active matrix substrate based on an inspection result prior to the connecting step.
  5. 　前記接続工程では、前記複数の接続素子に対して前記接続用電圧を順次に印加することを特徴とする、請求項１に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 1, wherein, in the connection step, the connection voltages are sequentially applied to the plurality of connection elements.
  6. 　前記接続工程では、前記接続素子を流れる電流が閾値を超えたときに、前記接続用電圧を印加する接続素子を切り替えることを特徴とする、請求項５に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 5, wherein, in the connection step, the connection element to which the connection voltage is applied is switched when a current flowing through the connection element exceeds a threshold value.
  7. 　前記接続工程では、前記複数の接続素子に対して前記接続用電圧を並列に印加することを特徴とする、請求項１に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 1, wherein, in the connection step, the connection voltage is applied in parallel to the plurality of connection elements.
  8. 　前記接続工程では、前記接続素子を流れる電流の経路上に正温度特性を有する感温素子を設けることを特徴とする、請求項７に記載の表示装置の製造方法。 The method for manufacturing a display device according to claim 7, wherein, in the connection step, a temperature sensitive element having a positive temperature characteristic is provided on a path of a current flowing through the connection element.
  9. 　静電気保護機能を有する表示装置であって、
    　アクティブマトリクス基板と、
    　対向基板とを備え、
    　前記アクティブマトリクス基板は、
    　　複数の薄膜トランジスタおよび複数の画素電極を含む画素領域と、
    　　外部接続用に設けられた複数の外部端子と、
    　　前記外部端子に共通接続された保護配線と、
    　　前記外部端子および前記保護配線の間に設けられた複数の接続素子とを含み、
    　前記接続素子は、前記保護配線に接続された第１導体部、半導体部、および、前記外部端子に接続された第２導体部で形成された積層部の一方の導体部に電圧印加用の針を押し当て、前記積層部を圧縮して歪ませた状態で前記第１および第２導体部間に接続用電圧を印加することにより、前記積層部を非導通状態から導通状態に不可逆的に変化させたものであることを特徴とする、表示装置。     A display device having an electrostatic protection function,
    An active matrix substrate;
    A counter substrate,
    The active matrix substrate is
    A pixel region including a plurality of thin film transistors and a plurality of pixel electrodes;
    A plurality of external terminals provided for external connection;
    Protective wiring commonly connected to the external terminals;
    A plurality of connection elements provided between the external terminal and the protective wiring,
    The connection element includes a first conductor portion connected to the protective wiring, a semiconductor portion, and a needle for applying a voltage to one conductor portion of a stacked portion formed by a second conductor portion connected to the external terminal. Is applied, and a voltage for connection is applied between the first and second conductor parts in a state where the laminated part is compressed and distorted, thereby irreversibly changing the laminated part from a non-conductive state to a conductive state. A display device characterized by being made.
PCT/JP2011/073045 2010-10-13 2011-10-06 Method for manufacturing display device, and display device WO2012050034A1 (en)

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JPH06317810A (en) * 1993-05-07 1994-11-15 Mitsubishi Electric Corp Matrix wiring board
JPH11142888A (en) * 1997-11-14 1999-05-28 Sharp Corp Liquid crystal display device and its inspection method
JP2006040916A (en) * 2004-07-22 2006-02-09 Seiko Epson Corp Semiconductor device and its manufacturing method

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