WO2012046329A1 - Semiconductor device and method of production thereof - Google Patents

Semiconductor device and method of production thereof Download PDF

Info

Publication number
WO2012046329A1
WO2012046329A1 PCT/JP2010/067673 JP2010067673W WO2012046329A1 WO 2012046329 A1 WO2012046329 A1 WO 2012046329A1 JP 2010067673 W JP2010067673 W JP 2010067673W WO 2012046329 A1 WO2012046329 A1 WO 2012046329A1
Authority
WO
WIPO (PCT)
Prior art keywords
type region
region
semiconductor device
type
forming
Prior art date
Application number
PCT/JP2010/067673
Other languages
French (fr)
Japanese (ja)
Inventor
克矢 小田
島　明生
広行 吉元
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP2012537530A priority Critical patent/JP5618430B2/en
Priority to PCT/JP2010/067673 priority patent/WO2012046329A1/en
Publication of WO2012046329A1 publication Critical patent/WO2012046329A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0895—Tunnel injectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof comprising IGBT (I nsulated G ate B ipolar T ransistor).
  • Non-Patent Document 1 A conventional IGBT having a hole (hole) injection region on the back surface is described in Non-Patent Document 1, for example.
  • a high-concentration p-type doping layer and a high-concentration n-type doping layer are provided on the back surface to form a high-concentration pn junction, thereby generating a tunnel current.
  • the resistance of the low-concentration n-type layer is reduced by conductivity modulation, and the current of the IGBT is increased.
  • FIG. 5 shows a cross-sectional structure of an intrinsic part of a conventional IGBT having a hole supply layer on the back surface as described above.
  • a p-type emitter 102, a gate insulating film 104, a gate 105, a gate sidewall insulating film 106, a gate electrode 111, and a high-concentration n-type region 103 are formed on the surface of the low-concentration n-type single crystal silicon substrate 101.
  • a tunnel junction in which the high concentration p-type layer 108 and the high concentration n-type layer 109 are in contact with each other is formed.
  • Reference numeral 107 denotes an n-type buffer layer.
  • the IGBT increases the applied voltage and the hole injection exponentially increases, so that the rise of the on-current is poor.
  • the electrode 112 connected to the high-concentration n-type layer 109 is positive.
  • a band-to-band tunnel is generated between the valence band of the high-concentration p-type layer 108 and the conduction band of the high-concentration n-type layer 109, so that current flows and the rise of on-current is expected to be improved. It was done.
  • FIG. 6A shows voltage-current characteristics. From this figure, it was found that although the rise of the on-current was improved, there was a problem that the characteristics varied and a stable IGBT operation could not be obtained.
  • An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can obtain stable operation even when a hole supply structure using a tunnel current is used.
  • a first n-type region, a first p-type region provided on a first region of the first n-type region, and the first p-type region are provided.
  • a second n-type region provided on the type region apart from the first n-type region, a gate insulating film provided on the p-type region, and a gate provided on the gate insulating film An electrode; a second p-type region formed on a second region different from the first region of the first n-type region; and a third n-type provided on the second p-type region.
  • a tunnel junction is formed between the second p-type region and the third n-type region, and the second p-type region and the third n-type region are connected to different electrodes, respectively.
  • a second step of forming an n-type region, a third step of forming a gate insulating film on the p-type region, a fourth step of forming a gate electrode on the gate insulating film, and the first n A fifth step of forming a second p-type region on a second region different from the first region of the mold region, and a third n-type region on the second p-type region to form the second region.
  • a method for manufacturing a semiconductor device comprising:
  • the tunnel current is reduced. It is possible to provide a semiconductor device and a method for manufacturing the same that can reduce fluctuations caused by a voltage drop when flowing and have a hole supply structure that uses a tunnel current, even when the semiconductor device has a stable operation.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. It is a schematic sectional drawing of the semiconductor device which concerns on the 2nd Example of this invention. It is the bird's-eye view seen from the back side of the semiconductor device concerning the 3rd example of the present invention. It is a schematic sectional drawing of the conventional semiconductor device. It is a voltage-current characteristic view of a conventional semiconductor device. It is a voltage-current characteristic view of the semiconductor device according to the first embodiment of the present invention.
  • the tunnel current is greatly influenced by the carrier concentration and the film thickness of the high-concentration p-type layer 108, it has been found that the characteristics greatly vary due to the non-uniformity of the high-concentration p-type layer.
  • the present invention was born based on the above new findings.
  • an emitter region and a gate region are formed on the surface side of a low concentration n-type silicon substrate, and a hole supply region having a collector region and a high concentration pn junction is formed on the back side of the substrate.
  • An electrode different from the collector electrode is formed and connected to the hole supply region.
  • the energy difference of the high-concentration pn junction can be controlled by voltage, and the on-resistance is reduced by increasing the hole current.
  • the hole current of the IGBT can be controlled, and the operation of parasitic elements such as thyristors and bipolar transistors can be suppressed.
  • FIG. 1 is a cross-sectional structure diagram of the intrinsic part of the semiconductor device according to this embodiment.
  • 2A to 2C are cross-sectional structural views illustrating the manufacturing method of the present embodiment in the order of steps.
  • a p-type emitter 2 and a gate 5 provided on the surface side of a semiconductor substrate (here, a low-concentration n-type Si substrate) 1 are formed in the same manner as a conventional IGBT.
  • Reference numeral 3 denotes an n-type region
  • reference numeral 4 denotes a gate insulating film
  • reference numeral 6 denotes a gate sidewall insulating film
  • reference numeral 13 denotes an emitter electrode
  • reference numeral 14 denotes a gate electrode.
  • a structure in which a channel is formed on the surface of the substrate 1 is shown here as an example, a buried gate structure in which a groove is formed by etching a part of the substrate 1 and a gate insulating film is formed on the sidewall of the groove. good.
  • the thickness of the substrate is reduced to 200 microns or less by polishing from the back surface in order to reduce the switching time of the IGBT (FIG. 2A).
  • the surface of the substrate 1 is protected by a protective film when the back surface of the substrate 1 is polished.
  • a high-concentration pn junction is formed on the back surface of the substrate.
  • substrate cleaning is performed to remove in advance contaminants and natural oxide films on the substrate surface. For example, by washing a substrate with a heated mixture of ammonia, hydrogen peroxide, and water, particles adhering to the substrate surface can be removed in addition to contamination by heavy metals and organic substances on the substrate surface.
  • the oxide film formed on the substrate surface during the cleaning with the mixed solution of ammonia, hydrogen peroxide, and water is removed with a hydrofluoric acid aqueous solution, and immediately after that, the silicon substrate surface is cleaned with hydrogen atoms. It will be covered.
  • the cleaned substrate 1 is placed in the load lock chamber of the epitaxial apparatus, and evacuation of the load lock chamber is started.
  • the silicon substrate 1 is transferred to the first growth chamber where p-type doping is performed via the transfer chamber.
  • the transfer chamber and the first growth chamber be in a high vacuum state or an ultrahigh vacuum state.
  • the pressure is about 1 ⁇ 10 ⁇ 5 Pa or less. Is preferred.
  • the transfer of the silicon substrate 1 is started after the pressure in the load lock chamber becomes about 1 ⁇ 10 ⁇ 5 Pa or less. Even if the surface of the silicon substrate 1 is subjected to hydrogen termination, it is not possible to completely prevent the formation of an oxide film on the surface and the attachment of contaminants during transportation. Therefore, the surface of the silicon substrate 1 is cleaned before epitaxial growth. As a cleaning method, for example, by heating the silicon substrate 1 in a vacuum, the natural oxide film on the substrate surface can be removed by the reaction of the formula (1).
  • the substrate surface can also be cleaned by heating the silicon substrate 1 with clean hydrogen supplied into the first growth chamber.
  • the cleaning by heating in a vacuum described above, when the substrate temperature is about 500 ° C. or higher, hydrogen that has terminated the substrate surface is desorbed, and the silicon atoms exposed on the substrate surface are exposed to the atmosphere in the growth chamber. The contained moisture and oxygen react to reoxidize the substrate surface. Then, the oxide film is reduced again, thereby increasing the unevenness of the substrate surface as well as cleaning, thereby deteriorating the uniformity and crystallinity of the subsequent epitaxial growth.
  • hydrogen gas is first supplied to the first growth chamber.
  • the substrate temperature be lower than 500 ° C. from which hydrogen is desorbed.
  • the flow rate of hydrogen gas is preferably 10 ml / min or more so that the gas can be supplied with good controllability, and 100 liters / min or less is preferable in order to safely treat the exhausted gas.
  • the lower limit of the partial pressure of hydrogen gas in the first growth chamber is set to 10 Pa so that the gas is uniformly supplied to the substrate surface, and the upper limit may be set to atmospheric pressure in order to maintain the safety of the apparatus.
  • the silicon substrate is heated to the cleaning temperature.
  • any mechanism or structure may be used as long as there is no contamination of the silicon substrate during heating or an extreme temperature difference in the substrate.
  • induction heating that heats a work coil by applying a high frequency, heating by a resistance heater, etc. can be applied.
  • a heating method using radiation from a lamp is used as a method that enables temperature control in a short time. Can do. This heating method is not limited to cleaning, and the same applies to heating during the growth of a single crystal described later.
  • the cleaning temperature should be 600 ° C. or more as a temperature at which the cleaning effect can be obtained.
  • the cleaning temperature needs to be 900 ° C. or lower in order to reduce the influence on the surface structure formed before the epitaxial growth. Further, the removal efficiency of the natural oxide film and the contaminants on the substrate surface varies depending on the cleaning temperature, and the higher the temperature, the shorter the effect. Therefore, it is desirable to perform heating under conditions that do not perform heat treatment more than necessary.
  • the cleaning temperature is 700 ° C., the cleaning effect is small, and therefore the cleaning time needs to be 30 minutes.
  • the cleaning time When the cleaning time is 900 ° C., the cleaning time may be 2 minutes or more.
  • the cleaning temperature is desirably about 800 ° C. or less, and the cleaning time at this time is 10 ° C. Just minutes.
  • cleaning using atomic hydrogen can be performed as a method that enables the cleaning temperature to be lowered.
  • this method by irradiating the surface of the substrate with active hydrogen atoms, it is possible to cause an oxygen reduction reaction without raising the substrate temperature, and a cleaning effect can be obtained even at room temperature.
  • atomic hydrogen generation methods hydrogen molecules are thermally dissociated by irradiating hydrogen gas to a filament such as tungsten heated to a high temperature, or hydrogen molecules are electrically generated by generating plasma in hydrogen gas. Can be dissociated, and atomic hydrogen can be generated by irradiation with ultraviolet rays.
  • the cleaning temperature may be 650 ° C.
  • the natural oxide film on the surface can be removed by a chemical reaction that does not require heating.
  • the oxide film is removed by an etching reaction, so that the surface can be cleaned at room temperature.
  • the substrate temperature is lowered to a temperature at which epitaxial growth is performed, and a time for stabilizing the substrate temperature at the temperature at which epitaxial growth is performed is provided.
  • the temperature stabilization step it is desirable to continue supplying hydrogen gas to keep the cleaned silicon substrate surface clean.
  • hydrogen gas has the effect of cooling the substrate surface. If the conditions are the same, the substrate surface temperature changes according to the gas flow rate. Therefore, even if the temperature is stable in a state where hydrogen gas having a flow rate greatly different from the total flow rate of the gas used for epitaxial growth is supplied, the substrate temperature greatly fluctuates due to the change in the gas flow rate when epitaxial growth is started. .
  • the hydrogen flow rate that is substantially the same as the total flow rate of the gas used for epitaxial growth.
  • the flow rate of hydrogen gas is adjusted while lowering the substrate temperature, and when the substrate temperature reaches the epitaxial growth temperature, It is preferable that the flow rate be equal to the flow rate of the growth gas. In this case, since the epitaxial growth can be started at the same time as the substrate temperature is lowered, the throughput can be greatly improved.
  • the source gas used here a compound composed of a group 4 element such as silicon or germanium and hydrogen, chlorine, fluorine, or the like can be used. Examples include monosilane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), silicon trichloride (SiHCl 3 ), silicon tetrachloride (SiCl 4 ), etc. The usage is the same. In this embodiment, a method for forming the high-concentration p-type layer 8 made of single crystal silicon will be described as an example.
  • a germanium raw material is used.
  • Monogermane (GeH 4 ) or digermane (Ge 2 H 6 ) may be added as a gas, and in order to form a multilayer film composed of single crystal silicon, germanium, and carbon into which carbon is introduced, monomethyl is used as a carbon source gas.
  • Silane (CH 3 SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), trimethylsilane ((CH 3 ) 3 SiH), or the like may be added.
  • the p-type doping gas a compound composed of a Group 3 element and hydrogen, chlorine, fluorine, or the like can be used, and examples thereof include diborane (B 2 H 6 ).
  • the concentration of the high-concentration p-type layer 8 needs to be 5 ⁇ 10 19 cm ⁇ 3 or more, and the upper limit is 1 ⁇ 10 21 cm ⁇ as a concentration capable of maintaining electrical characteristics as a semiconductor. 3 is sufficient.
  • the film thickness is preferably about 10 nm or less through which a tunnel current flows. However, the film thickness that allows the current generated by the tunnel effect to diffuse and flow into the emitter region may be 50 nm or less. In order to thin the high-concentration p-type region with good controllability, it is desirable to reduce the epitaxial growth rate.
  • a source gas such as disilane or monosilane that can reduce the growth temperature and the growth pressure
  • the temperature range is 500 ° C. or higher at which the source gas begins to thermally decompose, and the upper limit is maintained at a good surface morphology 650. It is suitable if it is below °C.
  • the growth pressure is preferably 0.1 Pa or higher, which is determined by the reaction at the surface, and the upper limit is preferably atmospheric pressure or lower in order to ensure the safety of the epitaxial growth apparatus.
  • the substrate is taken out from the epitaxial growth apparatus, an insulating film such as an oxide film is deposited, and the insulating film 10 is partially formed using photolithography and etching.
  • the high-concentration p-type layer 8 is very thin, about 10 nm or less, and the etching of the insulating film 10 is performed by wet etching with a hydrofluoric acid aqueous solution or a buffered hydrofluoric acid aqueous solution so that etching damage does not occur. This is preferable.
  • the substrate is again set in the epitaxial growth apparatus, and then the same substrate surface cleaning process as that before the growth of the high-concentration p-type layer 8 is performed.
  • the heat treatment during cleaning be performed at a lower temperature in order to prevent the p-type dopant from diffusing and changing the profile.
  • the temperature may be 600 ° C. or higher at which a cleaning effect is obtained, and 850 ° C. or lower in order to prevent profile fluctuation due to p-type dopant diffusion.
  • the high-concentration n-type single crystal layer 9 is grown by heating the substrate to the epitaxial growth temperature and introducing a growth gas and an n-type doping gas.
  • the high-concentration n-type layer 9 needs to be selectively epitaxially grown only in a portion other than the insulating film 10, it is preferable to use a silicon oxide film having a high selectivity as the material of the insulating film 10.
  • Si 2 H 6 when disilane (Si 2 H 6 ) is used as a silicon source gas, Si 2 H 6 + 2SiO 2 ⁇ 4SiO ⁇ + 3H 2 ⁇ (2)
  • dichlorosilane (SiH 2 Cl 2 ) when dichlorosilane (SiH 2 Cl 2 ) is used as a source gas, SiH 2 Cl 2 + SiO 2 ⁇ 2SiO ⁇ + 2HCl ⁇ (4)
  • germanium (GeH 4 ) which is a germanium source gas.
  • the reduction reaction for germane is GeH 4 + SiO 2 ⁇ SiO ⁇ + GeO ⁇ + 2H 2 ⁇ (5) It becomes.
  • the above reduction reaction is a part of a large number of reactions, and there are also other reduction reactions between radical molecules in which the source gas is decomposed to a high energy state and an oxide film.
  • etching due to the reduction reaction and deposition caused by decomposition of the source gas proceed simultaneously, and the magnitude relationship between etching and deposition changes depending on the growth temperature and pressure.
  • chlorine gas (Cl) or Etching of the silicon layer itself is performed by adding a halogen-based gas such as hydrogen chloride gas (HCl).
  • the reaction includes Si + 2Cl 2 ⁇ SiCl 4 ⁇ (6) Si + 2HCl ⁇ SiH 2 Cl 2 ⁇ (7) There is something like this.
  • the temperature range for performing epitaxial growth is 500 ° C. or more at which the selectivity between the silicon oxide film and the silicon nitride film and single crystal silicon can be obtained satisfactorily, and the upper limit is the range of 800 ° C. or less with good surface morphology.
  • the growth pressure may be 0.1 Pa or higher, where the growth rate is determined by the reaction at the surface, and the upper limit may be 100 Pa or lower at which the reaction in the gas phase begins to occur.
  • the doping concentration can be controlled by the flow rate of the doping gas. For example, in the case of doping with P (phosphorus), in order to perform doping of 1 ⁇ 10 20 cm ⁇ 3 , it may be set to 0.01 ml / min (FIG. 2B). .
  • the n-type buffer layer 7 may be formed by epitaxial growth or ion implantation.
  • the high concentration p-type layer 8 can be formed after the rear surface of the substrate 1 is cleaned and before epitaxial growth.
  • the ion implantation is performed after removing the damaged layer by polishing the back surface of the substrate 1. Thereafter, cleaning of the back surface of the substrate and epitaxial growth of the high concentration p-type layer 8 are performed.
  • an electrode is formed in each region.
  • the film thickness is as thin as about 10 nm or less. Therefore, when an electrode material is deposited and silicide is formed, metal atoms diffuse to the low-concentration n-type layer and are short-circuited. Therefore, it is preferable to additionally grow a high concentration p-type layer on the high concentration p-type layer 8 before electrode formation. Thereafter, an electrode material such as nickel is deposited and annealed to form silicide, thereby forming electrodes 11 and 12 having low contact resistance. (Fig.
  • the electrodes 13 and 14 are formed on the p-type emitter 2 and the gate 5, respectively, on the front surface side, thereby completing the IGBT having the hole supply layer on the back surface.
  • Figure 1 As described above, the structure in which the emitter and gate are formed on the front side of the substrate and the collector and hole supply region are formed on the back side has been described. After forming the emitter and gate on the front side, the emitter and gate are protected by an insulating film. In addition, the collector layer and the hole supply region can be formed in another region on the surface side.
  • FIG. 6B shows the voltage-current characteristics of the IBGT according to this example. 6A and 6B showing the conventional characteristics, it can be seen that the characteristics of the IGBT according to the present embodiment are remarkably stable as compared with the conventional IGBT in a state where the rising of the on-current is improved. .
  • the output current density greatly varies with respect to the voltage (FIG. 6A).
  • a tunnel junction of a very thin high-concentration p-type layer and high-concentration n-type layer with a thickness of about 10 nm or less can be formed with good controllability, and an electrode can be connected to each of the collector region and the hole supply region.
  • IGBT characteristic variations can be greatly reduced (FIG. 6B).
  • the hole current of the IGBT can be controlled, and the operation of parasitic elements such as thyristors and bipolar transistors can be suppressed.
  • the IGBT according to the present invention can achieve both reduction in on-resistance and high-speed operation.
  • a semiconductor device that can achieve stable operation by forming an electrode for controlling the voltage in the hole supply region, even if it has a hole supply structure using a tunnel current, and its manufacture A method can be provided.
  • the energy difference of the high-concentration pn junction can be controlled by voltage, and the on-resistance is reduced by increasing the hole current. It is possible to reduce fluctuations due to voltage drop when a tunnel current flows and characteristic fluctuations caused by variations in carrier concentration and film thickness of the high-concentration p-type layer.
  • Example 1 The difference between this example and Example 1 is in the method of forming the high-concentration p-type layer and the high-concentration n-type layer.
  • a high concentration is formed on the back surface of the substrate (low-concentration n-type Si region) 1 by ion implantation.
  • a tunnel junction is formed by forming a doping profile.
  • FIG. 3 shows a schematic cross-sectional structure of the semiconductor device (IGBT) according to the present embodiment.
  • the surface structure of the substrate (low-concentration n-type Si region) 1 is formed with a p-type emitter 2, a gate insulating film 4, a gate 5, etc., as in Example 1, and ion implantation is performed with the back surface of the substrate 1 exposed. .
  • Reference numeral 15 denotes an n-type buffer layer.
  • the energy is 2 keV and the dose is 1 ⁇ 10 14 cm ⁇ 2 , so that B has a peak concentration of 3 ⁇ 10 20 cm ⁇ 3 at about 15 nm from the implantation surface.
  • a high-concentration p-type layer 16 having a profile can be realized.
  • the insulating film 10 is formed in a region separating the collector and the hole supply layer, and an n-type impurity is ion-implanted while the collector region (high-concentration p-type region) 18 is masked to form a tunnel junction.
  • the acceleration energy is 10 keV
  • the dose is 2 ⁇ 10 14 cm ⁇ 2
  • the peak is about 3 ⁇ 10 20 cm ⁇ 3 at about 10 nm from the surface.
  • a high-concentration n-type region 17 having the following profile is obtained.
  • the p-type ion implantation region (collector region) 18 is added to the contact portion with the electrode 12 in order to form the electrode 12 in the collector region 18, it is possible to prevent a short circuit failure when silicidized.
  • the doping profile of the surface structure will change. Therefore, annealing using a CO 2 laser or the like is performed, so that the vicinity of the laser irradiation is obtained. Only after activation, almost the same doping profile as after ion implantation can be realized.
  • a high-concentration pn junction can be formed by ion implantation on the back surface of the IGBT, making it possible to manufacture the IGBT more simply than epitaxial growth, and improving throughput and reducing costs.
  • FIG. 4 is a bird's-eye view of the cross section of the IGBT obtained by dividing the electrode and the back surface of the substrate (low-concentration n-type Si region) 1 according to this embodiment.
  • the characteristics of the IGBT are greatly affected by fluctuations in the hole current, and thus it is necessary to reduce variations in the tunnel current.
  • the high-concentration p-type layer 8 is very thin, about 10 nm or less, and the carrier concentration is as high as 1 ⁇ 10 20 cm ⁇ 3 or more, the entire IGBT having a size of 1 mm square or more is uniform. It is difficult to secure the sex.
  • an insulating film 19 for separating the high-concentration p-type layer 8 formed on the back surface into a plurality of regions is provided, an electrode 12 is connected to the high-concentration p-type layer 8 in each region, and an optimum voltage is applied A tunnel current with uniform characteristics can be obtained.
  • This embodiment can provide the same effects as those of the first embodiment. Further, the characteristics of the IGBT applied to the power supply control module of 1 mm square or more can be made uniform, and the turn-on / turn-off characteristics due to the characteristic variation are improved, so that the high-frequency characteristics can be improved.
  • a first n-type region A first p-type region provided on a first region of the first n-type region; A second n-type region provided on the first p-type region and separated from the first n-type region; A gate insulating film provided on the p-type region; A gate electrode provided on the gate insulating film; A second p-type region formed on a second region different from the first region of the first n-type region; A third n-type region provided on the second p-type region; A tunnel junction is formed between the second p-type region and the third n-type region, and the second p-type region and the third n-type region are respectively connected to different electrodes.
  • a semiconductor device (2) The above description (1), wherein the first region and the second region of the first n-type region are provided on opposite surfaces of the first n-type region. Semiconductor device. (3) The above (1) or (2), wherein the first region and the second region of the first n-type region are provided on the same surface of the first n-type region. ) Semiconductor device. (4) The semiconductor device according to any one of (1) to (3), wherein the second p-type region includes at least one of silicon and germanium. (5) The semiconductor device according to any one of (1) to (4), wherein the second p-type region is separated into a plurality by an insulating film.
  • a semiconductor device comprising a plurality of the semiconductor devices according to any one of (1) to (8).
  • (10) a first step of forming a first p-type region on the first region of the first n-type region; A second step of forming a second n-type region on the first p-type region apart from the first n-type region; A third step of forming a gate insulating film on the p-type region; A fourth step of forming a gate electrode on the gate insulating film; A fifth step of forming a second p-type region on a second region different from the first region of the first n-type region; A fifth step of forming a third n-type region on the second p-type region to form a tunnel junction between the second p-type region and the third n-type region; A method of manufacturing a semiconductor device, comprising: a sixth step of connecting different electrodes to the second p-type region and the third n-type region, respectively.
  • the fourth step includes a step of cleaning a surface of the first n-type region and a step of forming the second p-type region by epitaxial growth.
  • Semiconductor device manufacturing method (12) The method of manufacturing a semiconductor device according to (11), wherein the cleaning step includes a step of heating while supplying hydrogen to the surface of the first n-type region. (13) The flow rate of the hydrogen gas immediately before the step of forming the second p-type region by epitaxial growth is set to be the same as the total flow rate of the gas used for the epitaxial growth. 12) A method for producing a semiconductor device according to item 12). (14) The method for manufacturing a semiconductor device according to (11), wherein the cleaning step uses atomic hydrogen.
  • the fourth step includes a step of forming the second p-type region using ion implantation, The method of manufacturing a semiconductor device according to (10), wherein the fifth step includes a step of forming the third n-type region using ion implantation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

In order to provide a semiconductor device and a method of production thereof that yields stable operation even if the device has a hole supplying structure using a tunnel current, the semiconductor device has an emitter (2) and an emitter electrode (13), a gate insulating film (4), a gate (5) and a gate electrode (14) that are formed on an obverse side of a substrate (1), and a high-density p-type layer (8), a high-density n-type layer (9) and a tunnel junction configured therebetween, that are formed on a reverse side of the substrate (1), wherein different electrodes (11,12) that are connected respectively to the high-density p-type layer (8) and the high-density n-type layer (9) are formed. Accordingly, fluctuation due to a drop in voltage when the tunnel current flows is reduced, and stable operation is made possible.

Description

半導体装置およびその製造方法Semiconductor device and manufacturing method thereof
　本発明は、ＩＧＢＴ（Insulated Gate Bipolar Transistor）を含む半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof comprising IGBT (I nsulated G ate B ipolar T ransistor).
　従来の裏面にホール（正孔）注入領域を有するＩＧＢＴは、例えば非特許文献１に記載されている。基板の表面側に通常のＩＧＢＴを形成した後、裏面に高濃度ｐ型ドーピング層と高濃度ｎ型ドーピング層を設け、高濃度ｐｎ接合を形成することでトンネル電流を発生させる。この際、トンネル電流の中の正孔が低濃度ｎ型ドリフト層に拡散することから、伝導度変調により低濃度ｎ型層の抵抗が低減し、ＩＧＢＴの電流が増大する。 A conventional IGBT having a hole (hole) injection region on the back surface is described in Non-Patent Document 1, for example. After forming a normal IGBT on the front surface side of the substrate, a high-concentration p-type doping layer and a high-concentration n-type doping layer are provided on the back surface to form a high-concentration pn junction, thereby generating a tunnel current. At this time, since holes in the tunnel current diffuse into the low-concentration n-type drift layer, the resistance of the low-concentration n-type layer is reduced by conductivity modulation, and the current of the IGBT is increased.
　前述した裏面にホール供給層を有する従来のＩＧＢＴの、真性部分における断面構造を図５に示す。低濃度ｎ型単結晶シリコン基板１０１の表面にｐ型エミッタ１０２、ゲート絶縁膜１０４、ゲート１０５、ゲート側壁絶縁膜１０６、ゲート電極１１１、高濃度ｎ型領域１０３が形成されており、裏面には高濃度ｐ型層１０８と高濃度ｎ型層１０９が接したトンネル接合が形成されている。符号１０７はｎ型バッファ層を示す。一般的にＩＧＢＴは印加電圧を高めるとともにホール注入が指数関数的に増加するためオン電流の立上りが悪いが、非特許文献１においては、高濃度ｎ型層１０９に接続された電極１１２に正の電圧を印加すると、高濃度ｐ型層１０８の価電子帯と高濃度ｎ型層１０９の伝導帯の間でバンド間トンネルが発生し、電流が流れ、オン電流の立上りが改善されることが期待された。そこで、この構造のＩＧＢＴを試作して特性を評価した。図６Ａに電圧電流特性を示す。この図から、オン電流の立上りは改善されるものの、特性がばらつき、安定したＩＧＢＴの動作が得られないという問題のあることが分かった。 FIG. 5 shows a cross-sectional structure of an intrinsic part of a conventional IGBT having a hole supply layer on the back surface as described above. A p-type emitter 102, a gate insulating film 104, a gate 105, a gate sidewall insulating film 106, a gate electrode 111, and a high-concentration n-type region 103 are formed on the surface of the low-concentration n-type single crystal silicon substrate 101. A tunnel junction in which the high concentration p-type layer 108 and the high concentration n-type layer 109 are in contact with each other is formed. Reference numeral 107 denotes an n-type buffer layer. In general, the IGBT increases the applied voltage and the hole injection exponentially increases, so that the rise of the on-current is poor. However, in Non-Patent Document 1, the electrode 112 connected to the high-concentration n-type layer 109 is positive. When a voltage is applied, a band-to-band tunnel is generated between the valence band of the high-concentration p-type layer 108 and the conduction band of the high-concentration n-type layer 109, so that current flows and the rise of on-current is expected to be improved. It was done. Thus, an IGBT having this structure was prototyped and the characteristics were evaluated. FIG. 6A shows voltage-current characteristics. From this figure, it was found that although the rise of the on-current was improved, there was a problem that the characteristics varied and a stable IGBT operation could not be obtained.
　本発明の目的は、トンネル電流を用いたホール供給構造を有する場合であっても、安定した動作が得られる半導体装置やその製造方法を提供することにある。 An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can obtain stable operation even when a hole supply structure using a tunnel current is used.
　前述した課題を解決するための一実施形態として、第１のｎ型領域と、前記第１のｎ型領域の第１領域上に設けられた第１のｐ型領域と、前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて設けられた第２のｎ型領域と、前記ｐ型領域上に設けられたゲート絶縁膜と、前記ゲート絶縁膜上に設けられたゲート電極と、前記第１のｎ型領域の前記第１領域とは異なる第２領域上に形成された第２のｐ型領域と、前記第２のｐ型領域上に設けられた第３のｎ型領域を有し、前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合が形成され、前記第２のｐ型領域と前記第３のｎ型領域が異なる電極にそれぞれ接続されていることを特徴とする半導体装置とする。 As an embodiment for solving the above-described problem, a first n-type region, a first p-type region provided on a first region of the first n-type region, and the first p-type region are provided. A second n-type region provided on the type region apart from the first n-type region, a gate insulating film provided on the p-type region, and a gate provided on the gate insulating film An electrode; a second p-type region formed on a second region different from the first region of the first n-type region; and a third n-type provided on the second p-type region. A tunnel junction is formed between the second p-type region and the third n-type region, and the second p-type region and the third n-type region are connected to different electrodes, respectively. Thus, a semiconductor device is provided.
　また、第１のｎ型領域の第１領域上に第１のｐ型領域を形成する第１工程と、前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて第２のｎ型領域を形成する第２工程と、前記ｐ型領域上にゲート絶縁膜を形成する第３工程と、前記ゲート絶縁膜上にゲート電極を形成する第４工程と、前記第１のｎ型領域の前記第１領域とは異なる第２領域上に第２のｐ型領域を形成する第５工程と、前記第２のｐ型領域上に第３のｎ型領域を形成して前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合を形成する第５工程と、前記第２のｐ型領域と前記第３のｎ型領域にそれぞれ異なる電極を接続する第６工程とを有することを特徴とする半導体装置の製造方法とする。 A first step of forming a first p-type region on the first region of the first n-type region; and a second step spaced apart from the first n-type region on the first p-type region. A second step of forming an n-type region, a third step of forming a gate insulating film on the p-type region, a fourth step of forming a gate electrode on the gate insulating film, and the first n A fifth step of forming a second p-type region on a second region different from the first region of the mold region, and a third n-type region on the second p-type region to form the second region. A fifth step of forming a tunnel junction between the second p-type region and the third n-type region, and a sixth step of connecting different electrodes to the second p-type region and the third n-type region, respectively. A method for manufacturing a semiconductor device, comprising:
　本発明によれば、第２のｐ型領域（高濃度ｐ型層）と第３のｎ型領域（高濃度ｎ型層）にそれぞれ接続される異なった電極を形成することにより、トンネル電流が流れたときの電圧降下による変動等が低減され、トンネル電流を用いたホール供給構造を有する場合であっても、安定した動作が得られる半導体装置やその製造方法を提供することができる。 According to the present invention, by forming different electrodes respectively connected to the second p-type region (high-concentration p-type layer) and the third n-type region (high-concentration n-type layer), the tunnel current is reduced. It is possible to provide a semiconductor device and a method for manufacturing the same that can reduce fluctuations caused by a voltage drop when flowing and have a hole supply structure that uses a tunnel current, even when the semiconductor device has a stable operation.
本発明の第１の実施例に係る半導体装置の概略断面図である。1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 本発明の第１の実施例に係る半導体装置の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. 本発明の第１の実施例に係る半導体装置の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. 本発明の第１の実施例に係る半導体装置の製造方法を工程順に示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Example of this invention in process order. 本発明の第２の実施例に係る半導体装置の概略断面図である。It is a schematic sectional drawing of the semiconductor device which concerns on the 2nd Example of this invention. 本発明の第３の実施例に係る半導体装置の裏面側から見た鳥瞰図である。It is the bird's-eye view seen from the back side of the semiconductor device concerning the 3rd example of the present invention. 従来の半導体装置の概略断面図である。It is a schematic sectional drawing of the conventional semiconductor device. 従来の半導体装置の電圧電流特性図である。It is a voltage-current characteristic view of a conventional semiconductor device. 本願発明の第１の実施例に係る半導体装置の電圧電流特性図である。It is a voltage-current characteristic view of the semiconductor device according to the first embodiment of the present invention.
　トンネル電流を用いたホール供給構造を有するＩＧＢＴにおいて、動作が安定しない理由を検討した。本ＩＧＢＴでは、高濃度ｐｎ接合に直接電圧を印加しているのは電極１１２のみであり、高濃度ｐ型層１０８の電位は表面のエミッタ電極１１０から低濃度ｎ型層（基板）１０１、ｎ型バッファ層１０７を介して与えられている。そのため、発生した電流による電圧降下の影響で電位が定まらず、高濃度ｐｎ接合のエネルギー差が変動することが、安定動作しない原因であることが分かった。  
　また、トンネル電流は高濃度ｐ型層１０８のキャリア濃度や膜厚によって大きく影響を受けるため、高濃度ｐ型層の不均一性によって、特性が大きく変動することが分かった。
　本発明は上記新たな知見に基づいて生まれたものである。 The reason why the operation of the IGBT having the hole supply structure using the tunnel current is not stable was examined. In this IGBT, only the electrode 112 applies a voltage directly to the high-concentration pn junction, and the potential of the high-concentration p-type layer 108 is changed from the emitter electrode 110 on the surface to the low-concentration n-type layer (substrate) 101, n. It is given through the type buffer layer 107. For this reason, it was found that the potential is not determined due to the voltage drop due to the generated current and the energy difference of the high-concentration pn junction fluctuates, which is the cause of the unstable operation.
In addition, since the tunnel current is greatly influenced by the carrier concentration and the film thickness of the high-concentration p-type layer 108, it has been found that the characteristics greatly vary due to the non-uniformity of the high-concentration p-type layer.
The present invention was born based on the above new findings.
　本発明に係るＩＧＢＴの好適な実施の形態は、低濃度ｎ型シリコン基板の表面側にエミッタ領域とゲート領域を形成し、基板の裏面側にコレクタ領域と高濃度ｐｎ接合を有するホール供給領域を形成し、コレクタ電極とは異なる電極をホール供給領域に接続したものである。 In a preferred embodiment of the IGBT according to the present invention, an emitter region and a gate region are formed on the surface side of a low concentration n-type silicon substrate, and a hole supply region having a collector region and a high concentration pn junction is formed on the back side of the substrate. An electrode different from the collector electrode is formed and connected to the hole supply region.
　このようにコレクタ領域とホール供給領域にそれぞれ電極を接続することで、高濃度ｐｎ接合のエネルギー差を電圧によって制御することが可能となり、正孔電流を増大させることでオン抵抗を低減した上に、トンネル電流が流れたときの電圧降下による変動や高濃度ｐ型層のキャリア濃度や膜厚のばらつきに起因した特性変動を低減することが可能となる。 By connecting the electrodes to the collector region and the hole supply region in this way, the energy difference of the high-concentration pn junction can be controlled by voltage, and the on-resistance is reduced by increasing the hole current. Thus, it is possible to reduce the fluctuation due to the voltage drop when the tunnel current flows and the characteristic fluctuation due to the carrier concentration and film thickness variation of the high-concentration p-type layer.
　さらに高濃度ｐｎ接合のエネルギー障壁を変化させることにより、ＩＧＢＴの正孔電流を制御することが可能となり、サイリスタやバイポーラトランジスタなどの寄生素子の動作を抑制することができる。 Furthermore, by changing the energy barrier of the high-concentration pn junction, the hole current of the IGBT can be controlled, and the operation of parasitic elements such as thyristors and bipolar transistors can be suppressed.
　また、ＩＧＢＴのオフ動作時に残留した正孔を電極から引き出すことができるため、ターンオフ特性が良好になる。従って、本発明に係るＩＧＢＴは、オン抵抗の低減と高速動作の両立が可能となる。  
　次に、本発明に係る半導体装置とその製造方法について実施例により、以下詳細に説明する。
＜実施例１＞
　本発明の第1の実施例について、図１、図２Ａ～図２Ｃ、図６Ａ、図６Ｂを用いて説明する。図１は、本実施例係る半導体装置の真性部分の断面構造図である。図２Ａ～図２Ｃは、本実施例の製造方法を工程順に示した断面構造図である。 In addition, since the holes remaining during the IGBT off operation can be extracted from the electrode, the turn-off characteristics are improved. Therefore, the IGBT according to the present invention can achieve both reduction in on-resistance and high-speed operation.
Next, the semiconductor device and the manufacturing method thereof according to the present invention will be described in detail with reference to examples.
<Example 1>
A first embodiment of the present invention will be described with reference to FIGS. 1, 2A to 2C, 6A, and 6B. FIG. 1 is a cross-sectional structure diagram of the intrinsic part of the semiconductor device according to this embodiment. 2A to 2C are cross-sectional structural views illustrating the manufacturing method of the present embodiment in the order of steps.
　半導体基板（ここでは低濃度ｎ型Ｓｉ基板を使用）１の表面側に設けられたｐ型エミッタ２およびゲート５は従来のＩＧＢＴと同様に形成する。符号３はｎ型領域、符号４はゲート絶縁膜、符号６はゲート側壁絶縁膜、符号１３はエミッタ電極、符号１４はゲート電極を示す。ここでは基板１表面にチャネルを形成する構造を例に示しているが、基板１の一部をエッチングして溝を形成し、溝の側壁にゲート絶縁膜を形成する埋め込みゲート構造であっても良い。表面構造を形成した後、ＩＧＢＴのスイッチング時間を低減するため、裏面から研磨することで基板の厚さを２００ミクロン以下に薄くする（図２Ａ）。なお、図示していないが、基板１裏面の研磨を行なう際は、基板１表面は保護膜で保護されている。 A p-type emitter 2 and a gate 5 provided on the surface side of a semiconductor substrate (here, a low-concentration n-type Si substrate) 1 are formed in the same manner as a conventional IGBT. Reference numeral 3 denotes an n-type region, reference numeral 4 denotes a gate insulating film, reference numeral 6 denotes a gate sidewall insulating film, reference numeral 13 denotes an emitter electrode, and reference numeral 14 denotes a gate electrode. Although a structure in which a channel is formed on the surface of the substrate 1 is shown here as an example, a buried gate structure in which a groove is formed by etching a part of the substrate 1 and a gate insulating film is formed on the sidewall of the groove. good. After the surface structure is formed, the thickness of the substrate is reduced to 200 microns or less by polishing from the back surface in order to reduce the switching time of the IGBT (FIG. 2A). Although not shown, the surface of the substrate 1 is protected by a protective film when the back surface of the substrate 1 is polished.
　次に、基板裏面研磨後のダメージ層を除去した後、基板裏面に高濃度ｐｎ接合を形成する。まず始めに、基板洗浄をおこない、基板表面の汚染物や自然酸化膜をあらかじめ除去する。例えば、アンモニア、過酸化水素、水の混合液を加熱したもので基板を洗浄することにより、基板表面の重金属や有機物による汚染に加え、基板表面に付着したパーティクルを除去することができる。次いで、アンモニア、過酸化水素、水の混合液による洗浄中に基板表面に形成された酸化膜をフッ酸水溶液によって除去し、その直後に純水で洗浄することにより、シリコン基板表面は水素原子で覆われた状態となる。この状態では、基板の最表面に存在するシリコン原子は水素と結合しているため、基板洗浄を行ってから成長を開始するまでの間に表面に自然酸化膜が形成されにくくなる。この洗浄による基板表面の水素終端処理に加え、さらに表面に自然酸化膜が形成されるのを防ぐためには、基板の洗浄を行った後、基板表面が再び酸化されたり汚染物が付着するのを防ぐため、シリコン基板を清浄な窒素中にて搬送すれば好適である。以下の実施例に関しても、エピタキシャル成長前に行う基板の洗浄と搬送方法に関しては同様である。 Next, after removing the damaged layer after polishing the back surface of the substrate, a high-concentration pn junction is formed on the back surface of the substrate. First, substrate cleaning is performed to remove in advance contaminants and natural oxide films on the substrate surface. For example, by washing a substrate with a heated mixture of ammonia, hydrogen peroxide, and water, particles adhering to the substrate surface can be removed in addition to contamination by heavy metals and organic substances on the substrate surface. Next, the oxide film formed on the substrate surface during the cleaning with the mixed solution of ammonia, hydrogen peroxide, and water is removed with a hydrofluoric acid aqueous solution, and immediately after that, the silicon substrate surface is cleaned with hydrogen atoms. It will be covered. In this state, since silicon atoms present on the outermost surface of the substrate are bonded to hydrogen, it is difficult to form a natural oxide film on the surface between the substrate cleaning and the start of growth. In addition to the hydrogen termination treatment of the substrate surface by this cleaning, in order to prevent the formation of a natural oxide film on the surface, the substrate surface is again oxidized or contaminated with contaminants after the substrate is cleaned. In order to prevent this, it is preferable to transport the silicon substrate in clean nitrogen. The same is true for the following embodiments with respect to the substrate cleaning and transfer method performed before epitaxial growth.
　次いで、洗浄を行った基板１をエピタキシャル装置のロードロック室内に設置し、ロードロック室の真空排気を開始する。ロードロック室の真空排気が完了した後、シリコン基板１を、搬送室を経由してｐ型ドープを行う第1の成長室に搬送する。基板表面に汚染物が付着するのを防ぐため、搬送室及び第1の成長室は高真空状態もしくは超高真空状態であることが望ましく、例えば圧力が１×１０－５Ｐａ程度以下であると好適である。後に述べるｎ型ドープを行う第２の成長室に関しても、真空度に関しては同様である。また、これらの成長室内で形成した単結晶層中に酸素や炭素が取り込まれることによる結晶欠陥の発生を防ぐため、搬送室や第１の成長室および第２の成長室に酸素や水分、または有機系の汚染物を含んだガスの混入を防ぐ必要がある。このことから、シリコン基板１の搬送を開始するのはロードロック室の圧力が１×１０―５Ｐａ程度以下になってから行うことが望ましい。シリコン基板１表面を水素終端処理しても、搬送中における表面の酸化膜形成や汚染物の付着を完全に防ぐことはできないため、エピタキシャル成長前にシリコン基板１表面のクリーニングを行う。クリーニング方法としては、例えば真空中でシリコン基板１を加熱することによって基板表面の自然酸化膜を式(１)の反応によって除去することが可能となる。 Next, the cleaned substrate 1 is placed in the load lock chamber of the epitaxial apparatus, and evacuation of the load lock chamber is started. After the evacuation of the load lock chamber is completed, the silicon substrate 1 is transferred to the first growth chamber where p-type doping is performed via the transfer chamber. In order to prevent contaminants from adhering to the substrate surface, it is desirable that the transfer chamber and the first growth chamber be in a high vacuum state or an ultrahigh vacuum state. For example, the pressure is about 1 × 10 −5 Pa or less. Is preferred. The same applies to the second growth chamber which performs n-type doping, which will be described later, with respect to the degree of vacuum. In order to prevent generation of crystal defects due to oxygen and carbon being taken into the single crystal layer formed in these growth chambers, oxygen, moisture, or in the transfer chamber, the first growth chamber, and the second growth chamber It is necessary to prevent gas containing organic contaminants from entering. For this reason, it is desirable that the transfer of the silicon substrate 1 is started after the pressure in the load lock chamber becomes about 1 × 10 −5 Pa or less. Even if the surface of the silicon substrate 1 is subjected to hydrogen termination, it is not possible to completely prevent the formation of an oxide film on the surface and the attachment of contaminants during transportation. Therefore, the surface of the silicon substrate 1 is cleaned before epitaxial growth. As a cleaning method, for example, by heating the silicon substrate 1 in a vacuum, the natural oxide film on the substrate surface can be removed by the reaction of the formula (1).
　　Ｓｉ＋ＳｉＯ２→２ＳｉＯ↑　　　　　　　　　　　　　（１）
　または、第１の成長室内に清浄な水素を供給した状態でシリコン基板１を加熱することによっても基板表面のクリーニングを行うことが可能である。前に述べた真空中での加熱によるクリーニングでは、基板温度が５００℃程度以上になると基板表面を終端していた水素は脱離し、基板表面のむき出しになったシリコン原子と成長室内の雰囲気中に含まれる水分や酸素が反応し、基板表面が再酸化されてしまう。そして、この酸化膜が再び還元されることにより、クリーニングと共に基板表面の凹凸が増大し、その後行うエピタキシャル成長の均一性や結晶性を悪化させるという問題がある。また、同時に成長室内の雰囲気中に含まれる炭酸ガスや有機系のガスが表面に付着することから、炭素汚染によるエピタキシャル成長層の結晶性の悪化も発生する。一方、水素を基板表面に供給した状態でシリコン基板を加熱した場合、５００℃以上の温度で水素が基板表面から脱離してしまっても、常に清浄な水素ガスが供給されているため、基板表面のシリコンと水素が結合と脱離を繰り返す。その結果、表面のシリコンは再酸化されにくくなり、クリーニング中に表面の凹凸が発生することもなく、清浄な表面状態を得ることが可能となる。 Si + SiO 2 → 2SiO ↑ (1)
Alternatively, the substrate surface can also be cleaned by heating the silicon substrate 1 with clean hydrogen supplied into the first growth chamber. In the cleaning by heating in a vacuum described above, when the substrate temperature is about 500 ° C. or higher, hydrogen that has terminated the substrate surface is desorbed, and the silicon atoms exposed on the substrate surface are exposed to the atmosphere in the growth chamber. The contained moisture and oxygen react to reoxidize the substrate surface. Then, the oxide film is reduced again, thereby increasing the unevenness of the substrate surface as well as cleaning, thereby deteriorating the uniformity and crystallinity of the subsequent epitaxial growth. At the same time, since the carbon dioxide gas and organic gas contained in the atmosphere in the growth chamber adhere to the surface, the crystallinity of the epitaxial growth layer is also deteriorated due to carbon contamination. On the other hand, when a silicon substrate is heated with hydrogen supplied to the substrate surface, clean hydrogen gas is always supplied even if hydrogen desorbs from the substrate surface at a temperature of 500 ° C. or higher. Silicon and hydrogen repeatedly bond and desorb. As a result, the surface silicon is less likely to be reoxidized, and surface irregularities are not generated during cleaning, and a clean surface state can be obtained.
　水素雰囲気中でクリーニングを行うため、まず始めに第１の成長室に水素ガスを供給する。このとき、水素ガスを供給する前に基板表面から水素が脱離するのを防ぐため、基板温度を水素の脱離する５００℃より低くすれば好適である。また、水素ガスの流量は制御性良くガスが供給できるように１０ｍｌ／ｍｉｎ以上とし、排気されたガスを安全に処理するためには１００ l／ｍｉｎ以下とすれば好適である。このとき、第１の成長室内の水素ガスの分圧の下限は、基板表面に均一にガスが供給されるように１０Ｐａとし、上限は装置の安全性を保つために大気圧とすればよい。水素ガスが供給された後、シリコン基板をクリーニング温度まで加熱する。このときの加熱方法としては、加熱に際してのシリコン基板への汚染や基板内での極端な温度の違いなどがなければ、どのような機構や構造でも良い。例えばワークコイルに高周波を印加して加熱する誘導加熱や、抵抗ヒータによる加熱などが適用できるほか、特に短時間での温度制御が可能な方法として、ランプからの輻射を利用した加熱方法を用いることができる。この加熱方法はクリーニングに限らず、後述する単結晶の成長に際しての加熱に関しても同様である。 In order to perform cleaning in a hydrogen atmosphere, hydrogen gas is first supplied to the first growth chamber. At this time, in order to prevent hydrogen from desorbing from the substrate surface before supplying the hydrogen gas, it is preferable that the substrate temperature be lower than 500 ° C. from which hydrogen is desorbed. The flow rate of hydrogen gas is preferably 10 ml / min or more so that the gas can be supplied with good controllability, and 100 liters / min or less is preferable in order to safely treat the exhausted gas. At this time, the lower limit of the partial pressure of hydrogen gas in the first growth chamber is set to 10 Pa so that the gas is uniformly supplied to the substrate surface, and the upper limit may be set to atmospheric pressure in order to maintain the safety of the apparatus. After the hydrogen gas is supplied, the silicon substrate is heated to the cleaning temperature. As a heating method at this time, any mechanism or structure may be used as long as there is no contamination of the silicon substrate during heating or an extreme temperature difference in the substrate. For example, induction heating that heats a work coil by applying a high frequency, heating by a resistance heater, etc. can be applied. In addition, as a method that enables temperature control in a short time, a heating method using radiation from a lamp is used. Can do. This heating method is not limited to cleaning, and the same applies to heating during the growth of a single crystal described later.
　クリーニング温度までシリコン基板を加熱した後、所定の時間基板を加熱することにより表面の自然酸化膜や汚染物が除去できるが、例えばクリーニング温度は、クリーニングの効果が得られる温度として６００℃以上であれば良く、エピタキシャル成長の前に形成されている表面構造へ与える影響を低減するため、クリーニング温度は９００℃以下にする必要がある。また、基板表面の自然酸化膜や汚染物質の除去効率はクリーニング温度によって変化し、温度が高いほど短時間で効果が得られるため、必要以上に熱処理を行わない条件で加熱を行うことが望ましい。クリーニング温度が７００℃の場合、クリーニングの効果が小さいため、クリーニング時間を３０分とする必要があるのに対し、クリーニング時間を９００℃とした場合、クリーニング時間は２分以上であればよい。表面構造への影響として、例えば基板中のドーパントの拡散による特性変動を考えると、ドーパントの拡散を押さえるためには、クリーニング温度を約８００℃以下とする事が望ましく、この時のクリーニング時間は１０分とすればよい。 After heating the silicon substrate to the cleaning temperature and then heating the substrate for a predetermined time, the natural oxide film and contaminants on the surface can be removed. For example, the cleaning temperature should be 600 ° C. or more as a temperature at which the cleaning effect can be obtained. The cleaning temperature needs to be 900 ° C. or lower in order to reduce the influence on the surface structure formed before the epitaxial growth. Further, the removal efficiency of the natural oxide film and the contaminants on the substrate surface varies depending on the cleaning temperature, and the higher the temperature, the shorter the effect. Therefore, it is desirable to perform heating under conditions that do not perform heat treatment more than necessary. When the cleaning temperature is 700 ° C., the cleaning effect is small, and therefore the cleaning time needs to be 30 minutes. When the cleaning time is 900 ° C., the cleaning time may be 2 minutes or more. Considering, for example, the characteristic variation due to the diffusion of the dopant in the substrate as an influence on the surface structure, in order to suppress the diffusion of the dopant, the cleaning temperature is desirably about 800 ° C. or less, and the cleaning time at this time is 10 ° C. Just minutes.
　また、クリーニング温度の低温化を可能とする方法として、原子状水素を用いたクリーニングを行うこともできる。この方法では、基板表面に活性な水素原子を照射することにより、基板温度を上げなくても酸素の還元反応を生じさせることが可能となり、室温においてもクリーニング効果は得られる。原子状水素の発生方法としては、高温に加熱したタングステンなどのフィラメントに水素ガスを照射することにより熱的に水素分子を解離させる方法や、水素ガス中でプラズマを発生させて電気的に水素分子を解離させる方法や、紫外線などの照射による原子状水素の発生などが可能である。但しこの場合、フィラメントやプラズマを発生する電極周辺からの金属汚染の発生や、プラズマによる石英部品などからの汚染物の発生などに十分注意をする必要がある。各方法とも、水素原子を大量に発生させるのは非常に困難であるため、水素ガスの中で、ある割合の分子を原子状態に解離させて基板表面に照射することにより、低温化が可能となる。例えば、クリーニング時間を１０分以内とするためには、クリーニング温度を６５０℃とすればよい。 Also, cleaning using atomic hydrogen can be performed as a method that enables the cleaning temperature to be lowered. In this method, by irradiating the surface of the substrate with active hydrogen atoms, it is possible to cause an oxygen reduction reaction without raising the substrate temperature, and a cleaning effect can be obtained even at room temperature. As atomic hydrogen generation methods, hydrogen molecules are thermally dissociated by irradiating hydrogen gas to a filament such as tungsten heated to a high temperature, or hydrogen molecules are electrically generated by generating plasma in hydrogen gas. Can be dissociated, and atomic hydrogen can be generated by irradiation with ultraviolet rays. However, in this case, it is necessary to pay sufficient attention to the occurrence of metal contamination from the periphery of the electrode that generates the filament and plasma, and the generation of contaminants from quartz parts due to the plasma. In each method, it is very difficult to generate a large amount of hydrogen atoms, so it is possible to lower the temperature by dissociating a certain proportion of molecules into an atomic state in the hydrogen gas and irradiating the substrate surface. Become. For example, in order to make the cleaning time within 10 minutes, the cleaning temperature may be 650 ° C.
　更に、加熱を必要としない化学反応によって表面の自然酸化膜を除去することもできる。たとえばＨＦガスを供給することにより、酸化膜がエッチング反応によって除去されるため、室温で表面のクリーニングが可能となる。 Furthermore, the natural oxide film on the surface can be removed by a chemical reaction that does not require heating. For example, by supplying HF gas, the oxide film is removed by an etching reaction, so that the surface can be cleaned at room temperature.
　以上、エピタキシャル成長前のクリーニングについて説明を行ったが、クリーニング方法に関しては他の実施例に関しても同様である。 The cleaning before the epitaxial growth has been described above, but the cleaning method is the same for the other embodiments.
　クリーニングが終了した後、エピタキシャル成長を行う温度まで基板温度を下げ、エピタキシャル成長を行う温度で基板温度を安定させる時間を設ける。温度の安定化を行うステップでは、クリーニング後のシリコン基板表面を清浄な状態に保つために水素ガスを供給し続けることが望ましいが、水素ガスは基板表面を冷却する効果を持っているため、加熱条件が同じであればガスの流量に応じて基板表面温度が変化してしまう。従って、エピタキシャル成長で用いるガスの総流量と大きく異なる流量の水素ガスを供給した状態で温度が安定していても、エピタキシャル成長を開始した時点でガスの流量が変わることにより基板温度が大きく変動してしまう。この現象を防ぐため、基板温度の安定化を行うステップにおいては、その水素流量をエピタキシャル成長で用いるガスの総流量とほぼ同じ値を用いることが望ましい。また、必ずしも基板温度がエピタキシャル成長温度まで下がってから温度安定化を行うステップを設ける必要はなく、基板温度を下げながら水素ガスの流量を調整し、基板温度がエピタキシャル成長温度になった時点で水素ガスの流量が成長ガスの流量と等しくなっていれば好適であり、この場合、基板温度を下げたと同時にエピタキシャル成長を開始できるため、スループットを大幅に向上することができる。 After cleaning is completed, the substrate temperature is lowered to a temperature at which epitaxial growth is performed, and a time for stabilizing the substrate temperature at the temperature at which epitaxial growth is performed is provided. In the temperature stabilization step, it is desirable to continue supplying hydrogen gas to keep the cleaned silicon substrate surface clean. However, since hydrogen gas has the effect of cooling the substrate surface, If the conditions are the same, the substrate surface temperature changes according to the gas flow rate. Therefore, even if the temperature is stable in a state where hydrogen gas having a flow rate greatly different from the total flow rate of the gas used for epitaxial growth is supplied, the substrate temperature greatly fluctuates due to the change in the gas flow rate when epitaxial growth is started. . In order to prevent this phenomenon, in the step of stabilizing the substrate temperature, it is desirable to use the hydrogen flow rate that is substantially the same as the total flow rate of the gas used for epitaxial growth. In addition, it is not always necessary to provide a step of stabilizing the temperature after the substrate temperature has decreased to the epitaxial growth temperature. The flow rate of hydrogen gas is adjusted while lowering the substrate temperature, and when the substrate temperature reaches the epitaxial growth temperature, It is preferable that the flow rate be equal to the flow rate of the growth gas. In this case, since the epitaxial growth can be started at the same time as the substrate temperature is lowered, the throughput can be greatly improved.
　次いで、エピタキシャル層の原料ガスとｐ型ドーピングガスを供給することによって高濃度ｐ型層８のエピタキシャル成長を開始する。ここで使用する原料ガスとしてはシリコン、ゲルマニウム等の４族元素と水素、塩素、フッ素などからなる化合物を用いることができる。例えば、モノシラン（ＳｉＨ４）、ジシラン（Ｓｉ２Ｈ６）、ジクロルシラン（ＳｉＨ２Ｃｌ２）、三塩化シリコン（ＳｉＨＣｌ３）、四塩化シリコン（ＳｉＣｌ４）などが挙げられるが、このほかのガスに関しても使用方法は同様である。本実施例では、単結晶シリコンからなる高濃度ｐ型層８の形成方法を例に挙げて説明を行うが、４族元素のゲルマニウムを導入した単結晶シリコン・ゲルマニウムを形成するにはゲルマニウムの原料ガスとしてモノゲルマン（ＧｅＨ４）やジゲルマン（Ｇｅ２Ｈ６）を添加すればよく、炭素を導入した単結晶シリコン・ゲルマニウム・カーボンからなる多層膜を形成するには、炭素の原料ガスとして、モノメチルシラン（ＣＨ３ＳｉＨ３）、ジメチルシラン（（ＣＨ３）２ＳｉＨ２）、トリメチルシラン（（ＣＨ３）３ＳｉＨ）等を添加すればよい。また、ｐ型ドーピングガスとしては、３族元素と水素、塩素、フッ素などからなる化合物を用いることができ、例えば、ジボラン（Ｂ２Ｈ６）などが挙げられる。 Next, epitaxial growth of the high-concentration p-type layer 8 is started by supplying the source gas for the epitaxial layer and the p-type doping gas. As the source gas used here, a compound composed of a group 4 element such as silicon or germanium and hydrogen, chlorine, fluorine, or the like can be used. Examples include monosilane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), silicon trichloride (SiHCl 3 ), silicon tetrachloride (SiCl 4 ), etc. The usage is the same. In this embodiment, a method for forming the high-concentration p-type layer 8 made of single crystal silicon will be described as an example. To form single crystal silicon / germanium into which a group 4 element germanium is introduced, a germanium raw material is used. Monogermane (GeH 4 ) or digermane (Ge 2 H 6 ) may be added as a gas, and in order to form a multilayer film composed of single crystal silicon, germanium, and carbon into which carbon is introduced, monomethyl is used as a carbon source gas. Silane (CH 3 SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), trimethylsilane ((CH 3 ) 3 SiH), or the like may be added. As the p-type doping gas, a compound composed of a Group 3 element and hydrogen, chlorine, fluorine, or the like can be used, and examples thereof include diborane (B 2 H 6 ).
　トンネル電流を発生させるためには、高濃度ｐ型層８の濃度を５×１０１９ｃｍ―３以上にする必要があり、上限は半導体としての電気特性を維持できる濃度として１×１０21ｃｍ―３であれば良い。また、膜厚はトンネル電流が流れる約１０ｎｍ以下であれば好適だが、トンネル効果によって発生した電流がエミッタ領域へ拡散して流れることができる膜厚として５０ｎｍ以下であれば良い。高濃度ｐ型領域を制御性良く薄くするためには、エピタキシャル成長速度を下げるのが望ましい。そのため、成長温度と成長圧力が下げられるジシランやモノシラン等の原料ガスを用い、温度範囲としては、原料ガスが熱的に分解を始める５００℃以上で、上限は良好な表面モフォロジーが保たれる６５０℃以下であれば好適である。この温度範囲で、成長圧力は成長速度が表面での反応で律速される０．１Ｐａ以上で、上限はエピタキシャル成長装置の安全性を確保するために大気圧以下であれば好適である。 In order to generate a tunnel current, the concentration of the high-concentration p-type layer 8 needs to be 5 × 10 19 cm −3 or more, and the upper limit is 1 × 10 21 cm − as a concentration capable of maintaining electrical characteristics as a semiconductor. 3 is sufficient. The film thickness is preferably about 10 nm or less through which a tunnel current flows. However, the film thickness that allows the current generated by the tunnel effect to diffuse and flow into the emitter region may be 50 nm or less. In order to thin the high-concentration p-type region with good controllability, it is desirable to reduce the epitaxial growth rate. For this reason, a source gas such as disilane or monosilane that can reduce the growth temperature and the growth pressure is used, and the temperature range is 500 ° C. or higher at which the source gas begins to thermally decompose, and the upper limit is maintained at a good surface morphology 650. It is suitable if it is below ℃. In this temperature range, the growth pressure is preferably 0.1 Pa or higher, which is determined by the reaction at the surface, and the upper limit is preferably atmospheric pressure or lower in order to ensure the safety of the epitaxial growth apparatus.
　高濃度ｐ型層８を形成した後、基板をエピタキシャル成長装置から取り出し、酸化膜などの絶縁膜を堆積し、フォトリソグラフィーとエッチングを用いて絶縁膜１０を部分的に形成する。この際、高濃度ｐ型層８は約１０ｎｍ程度以下と非常に薄いことと、エッチングによるダメージが生じないように、絶縁膜１０のエッチングはフッ酸水溶液やバッファードフッ酸水溶液などによるウェットエッチングとすれば好適である。 After the high-concentration p-type layer 8 is formed, the substrate is taken out from the epitaxial growth apparatus, an insulating film such as an oxide film is deposited, and the insulating film 10 is partially formed using photolithography and etching. At this time, the high-concentration p-type layer 8 is very thin, about 10 nm or less, and the etching of the insulating film 10 is performed by wet etching with a hydrofluoric acid aqueous solution or a buffered hydrofluoric acid aqueous solution so that etching damage does not occur. This is preferable.
　高濃度ｎ型層９を形成するため、再びエピタキシャル成長装置に基板を設置した後、高濃度ｐ型層８の成長前と同様の基板表面のクリーニング処理を行う。ただし、すでに高濃度ｐ型層８が形成されているため、ｐ型のドーパントが拡散してプロファイルが変化することを防ぐため、クリーニング時の熱処理はより低温で実施することが望ましい。例えば、水素雰囲気中で加熱することでクリーニングを行う場合、クリーニングの効果が得られる６００℃以上で、ｐ型ドーパントの拡散によるプロファイルの変動を防ぐために８５０℃以下とすればよい。 In order to form the high-concentration n-type layer 9, the substrate is again set in the epitaxial growth apparatus, and then the same substrate surface cleaning process as that before the growth of the high-concentration p-type layer 8 is performed. However, since the high-concentration p-type layer 8 has already been formed, it is desirable that the heat treatment during cleaning be performed at a lower temperature in order to prevent the p-type dopant from diffusing and changing the profile. For example, when cleaning is performed by heating in a hydrogen atmosphere, the temperature may be 600 ° C. or higher at which a cleaning effect is obtained, and 850 ° C. or lower in order to prevent profile fluctuation due to p-type dopant diffusion.
　クリーニング処理の後、基板をエピタキシャル成長温度まで加熱し、成長ガス及びｎ型ドーピングガスを導入することにより、高濃度ｎ型単結晶層９を成長する。ここで、高濃度ｎ型層９は絶縁膜１０以外の部分のみに選択的にエピタキシャル成長する必要があるため、絶縁膜１０の材料としては、選択性の大きいシリコン酸化膜にすれば好適である。シリコン酸化膜１０の開口部に単結晶シリコンを選択エピタキシャル成長により形成すると、シリコン酸化膜上では、シリコンの原料ガスと表面分子が反応して以下のような反応が生じる。 After the cleaning process, the high-concentration n-type single crystal layer 9 is grown by heating the substrate to the epitaxial growth temperature and introducing a growth gas and an n-type doping gas. Here, since the high-concentration n-type layer 9 needs to be selectively epitaxially grown only in a portion other than the insulating film 10, it is preferable to use a silicon oxide film having a high selectivity as the material of the insulating film 10. When single crystal silicon is formed in the opening of the silicon oxide film 10 by selective epitaxial growth, the following reaction occurs on the silicon oxide film due to the reaction between the silicon source gas and the surface molecules.
　例えば、シリコンの原料ガスとしてジシラン（Ｓｉ２Ｈ６）を用いたとき、  
　　Ｓｉ２Ｈ６　＋　２ＳｉＯ２　→　４ＳｉＯ↑　＋　３Ｈ２↑　　　（２）  
　また、シリコンの原料ガスとしてモノシラン（ＳｉＨ４）を用いたとき、  
　　ＳｉＨ４　＋　ＳｉＯ２　→　２ＳｉＯ↑　＋　２Ｈ２↑　　  　　（３）  
　さらに、ジクロルシラン（ＳｉＨ２Ｃｌ２）を原料ガスとして用いると、  
　　ＳｉＨ２Ｃｌ２　＋　ＳｉＯ２　→　２ＳｉＯ↑　＋　２ＨＣｌ↑　（４）  
といった還元反応が生じる。また、ゲルマニウムの原料ガスであるゲルマン（ＧｅＨ４）についても同様である。ゲルマンに関しての還元反応は、  
　　ＧｅＨ４　＋　ＳｉＯ２　→　ＳｉＯ↑　＋　ＧｅＯ↑　＋　２Ｈ２↑ （５）  
となる。 For example, when disilane (Si 2 H 6 ) is used as a silicon source gas,
Si 2 H 6 + 2SiO 2 → 4SiO ↑ + 3H 2 ↑ (2)
When monosilane (SiH 4 ) is used as the silicon source gas,
SiH 4 + SiO 2 → 2SiO ↑ + 2H 2 ↑ (3)
Further, when dichlorosilane (SiH 2 Cl 2 ) is used as a source gas,
SiH 2 Cl 2 + SiO 2 → 2SiO ↑ + 2HCl ↑ (4)
A reduction reaction occurs. The same applies to germanium (GeH 4 ), which is a germanium source gas. The reduction reaction for germane is
GeH 4 + SiO 2 → SiO ↑ + GeO ↑ + 2H 2 ↑ (5)
It becomes.
　上記の還元反応は数多くの反応のうちの一部であり、この他にも原料ガスが分解してエネルギーが高い状態になったラジカル分子と酸化膜との還元反応なども存在する。その結果、酸化膜上では上記還元反応によるエッチングと原料ガスが分解して生じる堆積とが同時に進行しており、成長温度及び圧力に依存してエッチングと堆積の大小関係が変化する。上記の還元反応だけでは選択性を保持できる膜厚に限界があるため、比較的厚い単結晶シリコンまたは単結晶シリコン・ゲルマニウム層を選択エピタキシャル成長する場合、原料ガスに加えて、塩素ガス（Ｃｌ）や塩化水素ガス（ＨＣｌ）といったハロゲン系のガスを添加して、シリコン層自体のエッチングを行う。 The above reduction reaction is a part of a large number of reactions, and there are also other reduction reactions between radical molecules in which the source gas is decomposed to a high energy state and an oxide film. As a result, on the oxide film, etching due to the reduction reaction and deposition caused by decomposition of the source gas proceed simultaneously, and the magnitude relationship between etching and deposition changes depending on the growth temperature and pressure. Since there is a limit to the film thickness that can maintain selectivity only by the above reduction reaction, in the case of selective epitaxial growth of a relatively thick single crystal silicon or single crystal silicon / germanium layer, in addition to the source gas, chlorine gas (Cl) or Etching of the silicon layer itself is performed by adding a halogen-based gas such as hydrogen chloride gas (HCl).
　その反応には、  
　　Ｓｉ　＋　２Ｃｌ２　→　ＳｉＣｌ４↑　　　　　　　　 　　　（６）  
　　Ｓｉ　＋　２ＨＣｌ　→　ＳｉＨ２Ｃｌ２↑　　　　　　 　　　（７）  
といったものがある。 The reaction includes
Si + 2Cl 2 → SiCl 4 ↑ (6)
Si + 2HCl → SiH 2 Cl 2 ↑ (7)
There is something like this.
　以上の反応が同時に進行する結果、選択性が維持されている状態では、シリコン酸化膜上にシリコンは堆積しない。エピタキシャル成長を行う温度範囲は、シリコン酸化膜およびシリコン窒化膜と単結晶シリコンとの選択性が良好に得られる５００℃以上で、上限は表面モフォロジーが良好な８００℃以下の範囲である。この温度範囲で、成長圧力は成長速度が表面での反応で律速される０．１Ｐａ以上で、上限は気相中での反応が起こり始める１００Ｐａ以下であればよい。以下の実施例においても、単結晶シリコンの選択エピタキシャル成長条件に関しては同様である。ドーピング濃度は、ドーピングガスの流量によって制御でき、例えばＰ（リン）をドーピングする場合、１×１０２０ｃｍ－３のドーピングを行うためには、０．０１ｍｌ／ｍｉｎとすればよい（図２Ｂ）。 As a result of the above reactions proceeding simultaneously, silicon is not deposited on the silicon oxide film in a state where selectivity is maintained. The temperature range for performing epitaxial growth is 500 ° C. or more at which the selectivity between the silicon oxide film and the silicon nitride film and single crystal silicon can be obtained satisfactorily, and the upper limit is the range of 800 ° C. or less with good surface morphology. In this temperature range, the growth pressure may be 0.1 Pa or higher, where the growth rate is determined by the reaction at the surface, and the upper limit may be 100 Pa or lower at which the reaction in the gas phase begins to occur. The same applies to the conditions for selective epitaxial growth of single crystal silicon in the following examples. The doping concentration can be controlled by the flow rate of the doping gas. For example, in the case of doping with P (phosphorus), in order to perform doping of 1 × 10 20 cm −3 , it may be set to 0.01 ml / min (FIG. 2B). .
　なお、ｎ型バッファ層７はエピタキシャル成長で形成しても、イオン打ち込みで形成してもよい。エピタキシャル成長で形成する場合には、基板１の裏面のクリーニング後、高濃度ｐ型層８をエピタキシャル成長する前に形成することができる。イオン打ち込みで形成する場合には、基板１の裏面の研磨によるダメージ層を除去した後、イオン打ち込みを行なう。その後、基板裏面のクリーニング、高濃度ｐ型層８のエピタキシャル成長を行なう。 The n-type buffer layer 7 may be formed by epitaxial growth or ion implantation. In the case of forming by epitaxial growth, the high concentration p-type layer 8 can be formed after the rear surface of the substrate 1 is cleaned and before epitaxial growth. In the case of forming by ion implantation, the ion implantation is performed after removing the damaged layer by polishing the back surface of the substrate 1. Thereafter, cleaning of the back surface of the substrate and epitaxial growth of the high concentration p-type layer 8 are performed.
　次いで、各領域に電極を形成する。高濃度ｐ型層８に電極を形成する場合、膜厚が約１０ｎｍ程度以下と非常に薄いため、電極材料を堆積してシリサイドを形成すると、金属原子が低濃度ｎ型層まで拡散してショートする可能性があるため、高濃度ｐ型層８の上に電極形成前に高濃度ｐ型層を追加で成長すれば好適である。その後、ニッケル等の電極材料を堆積し、アニールを行うことでシリサイドを形成し、接触抵抗の少ない電極１１、１２を形成する。（図２Ｃ）
　最後に表面側にもｐ型エミッタ２とゲート５にそれぞれ電極１３、１４を形成することで裏面にホール供給層を有するＩＧＢＴが完成する。（図１）
　以上、基板の表面側にエミッタとゲートを形成し、裏面側にコレクタとホール供給領域を形成した構造について説明したが、表面側にエミッタとゲートを形成した後、エミッタとゲートを絶縁膜により保護し、表面側の別の領域にコレクタ層とホール供給領域を形成することもできる。 Next, an electrode is formed in each region. When an electrode is formed on the high-concentration p-type layer 8, the film thickness is as thin as about 10 nm or less. Therefore, when an electrode material is deposited and silicide is formed, metal atoms diffuse to the low-concentration n-type layer and are short-circuited. Therefore, it is preferable to additionally grow a high concentration p-type layer on the high concentration p-type layer 8 before electrode formation. Thereafter, an electrode material such as nickel is deposited and annealed to form silicide, thereby forming electrodes 11 and 12 having low contact resistance. (Fig. 2C)
Finally, the electrodes 13 and 14 are formed on the p-type emitter 2 and the gate 5, respectively, on the front surface side, thereby completing the IGBT having the hole supply layer on the back surface. (Figure 1)
As described above, the structure in which the emitter and gate are formed on the front side of the substrate and the collector and hole supply region are formed on the back side has been described. After forming the emitter and gate on the front side, the emitter and gate are protected by an insulating film. In addition, the collector layer and the hole supply region can be formed in another region on the surface side.
　本実施例に係るＩＢＧＴの電圧電流特性を図６Ｂに示す。従来の特性を示す図６Ａと図６Ｂとの比較から、オン電流の立上りは改善された状態で、従来のＩＧＢＴに比べて本実施例に係るＩＧＢＴの特性が格段に安定していることが分かる。 FIG. 6B shows the voltage-current characteristics of the IBGT according to this example. 6A and 6B showing the conventional characteristics, it can be seen that the characteristics of the IGBT according to the present embodiment are remarkably stable as compared with the conventional IGBT in a state where the rising of the on-current is improved. .
　本実施例により、従来の裏面にトンネル電流を用いたホール供給層を形成したＩＧＢＴにおいて電圧に対して出力の電流密度が大きくばらついていたものを（図６Ａ）、ＩＧＢＴの裏面に高濃度で厚さが約１０ｎｍ以下と非常に薄い高濃度ｐ型層と高濃度ｎ型層のトンネル接合を制御性良く形成し、コレクタ領域とホール供給領域のそれぞれに電極を接続することが可能となることから、ＩＧＢＴの特性ばらつきを大幅に低減することができる（図６Ｂ）。また、高濃度ｐｎ接合のエネルギー障壁を変化させることにより、ＩＧＢＴの正孔電流を制御することが可能となり、サイリスタやバイポーラトランジスタなどの寄生素子の動作を抑制することができる。さらに、ＩＧＢＴのオフ動作時に残留した正孔を電極から引き出すことができるため、ターンオフ特性が良好になる。従って、本発明に係るＩＧＢＴは、オン抵抗の低減と高速動作の両立が可能となる。 According to the present embodiment, in the conventional IGBT in which the hole supply layer using the tunnel current is formed on the back surface, the output current density greatly varies with respect to the voltage (FIG. 6A). A tunnel junction of a very thin high-concentration p-type layer and high-concentration n-type layer with a thickness of about 10 nm or less can be formed with good controllability, and an electrode can be connected to each of the collector region and the hole supply region. , IGBT characteristic variations can be greatly reduced (FIG. 6B). Further, by changing the energy barrier of the high-concentration pn junction, the hole current of the IGBT can be controlled, and the operation of parasitic elements such as thyristors and bipolar transistors can be suppressed. Furthermore, since the holes remaining during the IGBT off operation can be extracted from the electrode, the turn-off characteristics are improved. Therefore, the IGBT according to the present invention can achieve both reduction in on-resistance and high-speed operation.
　以上、本実施例によれば、トンネル電流を用いたホール供給構造を有する場合であっても、ホール供給領域の電圧を制御する電極を形成することにより安定した動作が得られる半導体装置やその製造方法を提供することができる。特に、コレクタ領域とホール供給領域にそれぞれ電極を接続することで、高濃度ｐｎ接合のエネルギー差を電圧によって制御することが可能となり、正孔電流を増大させることでオン抵抗を低減した上に、トンネル電流が流れたときの電圧降下による変動や高濃度ｐ型層のキャリア濃度や膜厚のばらつきに起因した特性変動を低減することが可能となる。
＜実施例２＞
　第２の実施例について図３を用いて説明する。なお、実施例１に記載され本実施例に未記載の事項は特段の事情がない限り本実施例にも適用することができる。 As described above, according to the present embodiment, a semiconductor device that can achieve stable operation by forming an electrode for controlling the voltage in the hole supply region, even if it has a hole supply structure using a tunnel current, and its manufacture A method can be provided. In particular, by connecting electrodes to the collector region and the hole supply region, respectively, the energy difference of the high-concentration pn junction can be controlled by voltage, and the on-resistance is reduced by increasing the hole current. It is possible to reduce fluctuations due to voltage drop when a tunnel current flows and characteristic fluctuations caused by variations in carrier concentration and film thickness of the high-concentration p-type layer.
<Example 2>
A second embodiment will be described with reference to FIG. Note that the matters described in the first embodiment and not described in the present embodiment can be applied to the present embodiment as long as there is no special circumstances.
　本実施例と実施例１との違いは高濃度ｐ型層及び高濃度ｎ型層の形成方法にあり、本実施例ではイオン打ち込みにより基板（低濃度ｎ型Ｓｉ領域）１の裏面に高濃度ドーピングプロファイルを形成することでトンネル接合を形成する。図３は本実施例に係る半導体装置（ＩＧＢＴ）の概略断面構造を示す。基板（低濃度ｎ型Ｓｉ領域）１の表面構造は実施例１と同様にｐ型エミッタ２、ゲート絶縁膜４、ゲート５等を形成し、基板１の裏面が露出した状態でイオン打ち込みを行う。実施例1と同一の符号は同一の構成を示す。符号１５はｎ型バッファ層を示す。ｐ型ドーピングとしてＢＦ２を用いた場合、エネルギーを２ｋｅＶでドーズ量を１×１０１４ｃｍ―２とすることで、打ち込み表面から約１５ｎｍに３×１０２０ｃｍ―３のピーク濃度をもったＢプロファイルを有する高濃度ｐ型層１６が実現できる。ここでコレクタとホール供給層を分離する領域に絶縁膜１０を形成し、コレクタ領域（高濃度ｐ型領域）１８をマスクした状態でｎ型不純物をイオン打ち込みすることにより、トンネル接合を形成する。ｎ型ドーピングとしてＡｓのイオン打ち込みを用いた場合、加速エネルギーを１０ｋｅＶとして、ドーズ量を２×１０１４ｃｍ―２とすることで、表面から約１０ｎｍに３×１０２０ｃｍ―３のピークを持ったプロファイルを有する高濃度ｎ型領域１７が得られる。また、コレクタ領域１８に電極１２を形成するために、電極１２との接触部分にｐ型のイオン打ち込み領域（コレクタ領域）１８を追加すればシリサイド化したときのショート不良を防ぐことができる。イオン打ち込み後、基板１全体を加熱して不純物の活性化を行うと、表面構造のドーピングプロファイルが変化してしまうため、ＣＯ２レーザー等を用いたアニールを行うことで、レーザーが照射された近傍のみを活性化することができ、活性化後でもイオン打ち込み後とほぼ同じドーピングプロファイルを実現できる。 The difference between this example and Example 1 is in the method of forming the high-concentration p-type layer and the high-concentration n-type layer. In this example, a high concentration is formed on the back surface of the substrate (low-concentration n-type Si region) 1 by ion implantation. A tunnel junction is formed by forming a doping profile. FIG. 3 shows a schematic cross-sectional structure of the semiconductor device (IGBT) according to the present embodiment. The surface structure of the substrate (low-concentration n-type Si region) 1 is formed with a p-type emitter 2, a gate insulating film 4, a gate 5, etc., as in Example 1, and ion implantation is performed with the back surface of the substrate 1 exposed. . The same reference numerals as those in the first embodiment indicate the same configuration. Reference numeral 15 denotes an n-type buffer layer. When BF 2 is used as the p-type doping, the energy is 2 keV and the dose is 1 × 10 14 cm −2 , so that B has a peak concentration of 3 × 10 20 cm −3 at about 15 nm from the implantation surface. A high-concentration p-type layer 16 having a profile can be realized. Here, the insulating film 10 is formed in a region separating the collector and the hole supply layer, and an n-type impurity is ion-implanted while the collector region (high-concentration p-type region) 18 is masked to form a tunnel junction. When As ion implantation is used as n-type doping, the acceleration energy is 10 keV, the dose is 2 × 10 14 cm −2, and the peak is about 3 × 10 20 cm −3 at about 10 nm from the surface. A high-concentration n-type region 17 having the following profile is obtained. Further, if the p-type ion implantation region (collector region) 18 is added to the contact portion with the electrode 12 in order to form the electrode 12 in the collector region 18, it is possible to prevent a short circuit failure when silicidized. After the ion implantation, if the entire substrate 1 is heated to activate the impurities, the doping profile of the surface structure will change. Therefore, annealing using a CO 2 laser or the like is performed, so that the vicinity of the laser irradiation is obtained. Only after activation, almost the same doping profile as after ion implantation can be realized.
　本実施例により、実施例1と同様の効果が得られる。また、ＩＧＢＴの裏面に高濃度ｐｎ接合をイオン打ち込みで形成することが可能となり、エピタキシャル成長よりも簡便にＩＧＢＴを作製することができ、スループットの向上と低コスト化が可能となる。
＜実施例３＞
　第３の実施例について図４を用いて説明する。なお、実施例１又は２に記載され本実施例に未記載の事項は特段の事情がない限り本実施例にも適用することができる。 According to the present embodiment, the same effect as in the first embodiment can be obtained. In addition, a high-concentration pn junction can be formed by ion implantation on the back surface of the IGBT, making it possible to manufacture the IGBT more simply than epitaxial growth, and improving throughput and reducing costs.
<Example 3>
A third embodiment will be described with reference to FIG. Note that matters described in the first or second embodiment but not described in the present embodiment can also be applied to the present embodiment unless there are special circumstances.
　本実施例では、実施例１のＩＧＢＴを実際の電源制御用モジュールに適用する際の特性安定性を図るため、ホール供給領域とコレクタ領域を複数設け、それぞれに対してトンネル電流を制御する構造を示す。図４は本実施例を示す電極を分割したＩＧＢＴの断面および基板（低濃度ｎ型Ｓｉ領域）１の裏面からの鳥瞰図である。 In this embodiment, a plurality of hole supply regions and collector regions are provided, and a tunnel current is controlled for each of them in order to achieve characteristic stability when the IGBT of Embodiment 1 is applied to an actual power supply control module. Show. FIG. 4 is a bird's-eye view of the cross section of the IGBT obtained by dividing the electrode and the back surface of the substrate (low-concentration n-type Si region) 1 according to this embodiment.
　トンネル電流で発生した正孔(ホール)電流を用いてＩＧＢＴの特性を制御する場合、正孔電流の変動によってＩＧＢＴの特性が大きく影響を受けるため、トンネル電流のばらつきを低減する必要がある。しかし、高濃度ｐ型層８が約１０ｎｍ程度以下と非常に薄く、キャリア濃度も１×１０２０ｃｍ―３以上と非常に高濃度であるため、１ミリメートル角以上の大きさとなるＩＧＢＴ全体で均一性を確保するのは困難である。そのため、裏面に形成する高濃度ｐ型層８を複数の領域に分離する絶縁膜１９を設け、それぞれの領域における高濃度ｐ型層８に電極１２を接続し、最適な電圧を印加することで特性のそろったトンネル電流を得ることができる。 When controlling the characteristics of the IGBT using a hole current generated by the tunnel current, the characteristics of the IGBT are greatly affected by fluctuations in the hole current, and thus it is necessary to reduce variations in the tunnel current. However, since the high-concentration p-type layer 8 is very thin, about 10 nm or less, and the carrier concentration is as high as 1 × 10 20 cm −3 or more, the entire IGBT having a size of 1 mm square or more is uniform. It is difficult to secure the sex. Therefore, an insulating film 19 for separating the high-concentration p-type layer 8 formed on the back surface into a plurality of regions is provided, an electrode 12 is connected to the high-concentration p-type layer 8 in each region, and an optimum voltage is applied A tunnel current with uniform characteristics can be obtained.
　本実施例により、実施例１と同様の効果を得ることができる。また、１ミリメートル角以上の電源制御用モジュールに適用したＩＧＢＴの特性を均一化することが可能となり、特性ばらつきに起因したターンオン・ターンオフ特性が向上するため、高周波特性が向上できる。 This embodiment can provide the same effects as those of the first embodiment. Further, the characteristics of the IGBT applied to the power supply control module of 1 mm square or more can be made uniform, and the turn-on / turn-off characteristics due to the characteristic variation are improved, so that the high-frequency characteristics can be improved.
　以上、本発明の好適な実施例について説明したが、本発明は前記実施例に限定されることなく、本発明の精神を逸脱しない範囲内において種々の設計変更をなし得ることは勿論である。例えば、実施例中ではｐ型単結晶シリコン、ｐ型単結晶シリコン・ゲルマニウム層およびｎ型単結晶シリコン層からなる多層膜の場合について説明したが、単結晶シリコン・ゲルマニウム・カーボン層等を用いてよいことは言うまでもない。 The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. For example, in the embodiments, the case of a multilayer film composed of p-type single crystal silicon, a p-type single crystal silicon / germanium layer, and an n-type single crystal silicon layer has been described, but a single crystal silicon / germanium / carbon layer or the like is used. Needless to say, it is good.
　以上、本願発明を詳細に説明したが、以下に主な発明の形態を列挙する。
（１）　第１のｎ型領域と、
  前記第１のｎ型領域の第１領域上に設けられた第１のｐ型領域と、
  前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて設けられた第２のｎ型領域と、
  前記ｐ型領域上に設けられたゲート絶縁膜と、
  前記ゲート絶縁膜上に設けられたゲート電極と、
  前記第１のｎ型領域の前記第１領域とは異なる第２領域上に形成された第２のｐ型領域と、
  前記第２のｐ型領域上に設けられた第３のｎ型領域を有し、
  前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合が形成され、前記第２のｐ型領域と前記第３のｎ型領域が異なる電極にそれぞれ接続されていることを特徴とする半導体装置。  
（２）　前記第１のｎ型領域の前記第１領域と前記第２領域とは、前記第１のｎ型領域の互いに反対の面に設けられていることを特徴とする上記（１）記載の半導体装置。  
（３）　前記第１のｎ型領域の前記第１領域と前記第２領域とは、前記第１のｎ型領域の同じ面に設けられていることを特徴とする上記（１）又は（２）に記載の半導体装置。  
（４）　前記第２のｐ型領域がシリコンおよびゲルマニウムの少なくとも一方を含むことを特徴とする上記（１）乃至（３）のいずれか一に記載の半導体装置。  
（５）　前記第２のｐ型領域は、絶縁膜により複数に分離されていることを特徴とする上記（１）乃至（４）のいずれか一に記載の半導体装置。  
（６）　前記第１のｐ型領域と前記第２のｐ型領域の距離が２００ミクロン以下であることを特徴とする上記（１）乃至（５）のいずれか一に記載の半導体装置。  
（７）　前記第２のｐ型領域のキャリア濃度が５×１０１９ｃｍ―３以上、１×１０２１ｃｍ―３以下であることを特徴とする上記（１）乃至（６）のいずれか一に記載の半導体装置。  
（８）　前記第２のｐ型領域の厚さが５０ｎｍ以下であることを特徴とする上記（１）乃至（７）のいずれか一に記載の半導体装置。  
（９）　上記（１）乃至（８）のいずれか一に記載の半導体装置を複数個含むことを特徴とする電源制御用モジュール。  
（１０）　第１のｎ型領域の第１領域上に第１のｐ型領域を形成する第１工程と、
  前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて第２のｎ型領域を形成する第２工程と、
  前記ｐ型領域上にゲート絶縁膜を形成する第３工程と、
  前記ゲート絶縁膜上にゲート電極を形成する第４工程と、
  前記第１のｎ型領域の前記第１領域とは異なる第２領域上に第２のｐ型領域を形成する第５工程と、
  前記第２のｐ型領域上に第３のｎ型領域を形成して前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合を形成する第５工程と、
  前記第２のｐ型領域と前記第３のｎ型領域にそれぞれ異なる電極を接続する第６工程とを有することを特徴とする半導体装置の製造方法。  
（１１）　前記第４工程は、前記第１のｎ型領域の表面をクリーニングする工程と、前記第２のｐ型領域をエピタキシャル成長により形成する工程とを含むことを特徴とする上記（１０）記載の半導体装置の製造方法。  
（１２）　前記クリーニングする工程は、前記第１のｎ型領域の表面へ水素を供給しながら加熱する工程を含むことを特徴とする上記（１１）記載の半導体装置の製造方法。  
（１３）　前記第２のｐ型領域をエピタキシャル成長により形成する工程の直前における前記水素ガスの流量は、前記エピタキシャル成長で用いるガスの総流量と同じとなるように設定されることを特徴とする上記（１２）記載の半導体装置の製造方法。  
（１４）　前記クリーニングする工程は、原子状水素を用いることを特徴とする上記（１１）記載の半導体装置の製造方法。  
（１５）　前記第５工程は、前記第３のｎ型領域を選択的にエピタキシャル成長する工程を含むことを特徴とする上記（１０）乃至（１４）のいずれか一に記載の半導体装置の製造方法。  
（１６）　前記第２のｐ型領域と前記電極との間には、第３のｐ型領域が形成されることを特徴とする上記（１０）乃至（１５）のいずれか一に記載の半導体装置の製造方法。  
（１７）　前記第４工程は、イオン打ち込みを用いて前記第２のｐ型領域を形成する工程を含み、
  前記第５工程は、イオン打ち込みを用いて前記第３のｎ型領域を形成する工程を含むことを特徴とする上記（１０）記載の半導体装置の製造方法。 Although the present invention has been described in detail above, the main invention modes are listed below.
(1) a first n-type region;
A first p-type region provided on a first region of the first n-type region;
A second n-type region provided on the first p-type region and separated from the first n-type region;
A gate insulating film provided on the p-type region;
A gate electrode provided on the gate insulating film;
A second p-type region formed on a second region different from the first region of the first n-type region;
A third n-type region provided on the second p-type region;
A tunnel junction is formed between the second p-type region and the third n-type region, and the second p-type region and the third n-type region are respectively connected to different electrodes. A semiconductor device.
(2) The above description (1), wherein the first region and the second region of the first n-type region are provided on opposite surfaces of the first n-type region. Semiconductor device.
(3) The above (1) or (2), wherein the first region and the second region of the first n-type region are provided on the same surface of the first n-type region. ) Semiconductor device.
(4) The semiconductor device according to any one of (1) to (3), wherein the second p-type region includes at least one of silicon and germanium.
(5) The semiconductor device according to any one of (1) to (4), wherein the second p-type region is separated into a plurality by an insulating film.
(6) The semiconductor device according to any one of (1) to (5), wherein a distance between the first p-type region and the second p-type region is 200 microns or less.
(7) The carrier concentration of the second p-type region is 5 × 10 19 cm −3 or more and 1 × 10 21 cm −3 or less, and any one of (1) to (6) above A semiconductor device according to 1.
(8) The semiconductor device according to any one of (1) to (7), wherein a thickness of the second p-type region is 50 nm or less.
(9) A power supply control module comprising a plurality of the semiconductor devices according to any one of (1) to (8).
(10) a first step of forming a first p-type region on the first region of the first n-type region;
A second step of forming a second n-type region on the first p-type region apart from the first n-type region;
A third step of forming a gate insulating film on the p-type region;
A fourth step of forming a gate electrode on the gate insulating film;
A fifth step of forming a second p-type region on a second region different from the first region of the first n-type region;
A fifth step of forming a third n-type region on the second p-type region to form a tunnel junction between the second p-type region and the third n-type region;
A method of manufacturing a semiconductor device, comprising: a sixth step of connecting different electrodes to the second p-type region and the third n-type region, respectively.
(11) The above (10), wherein the fourth step includes a step of cleaning a surface of the first n-type region and a step of forming the second p-type region by epitaxial growth. Semiconductor device manufacturing method.
(12) The method of manufacturing a semiconductor device according to (11), wherein the cleaning step includes a step of heating while supplying hydrogen to the surface of the first n-type region.
(13) The flow rate of the hydrogen gas immediately before the step of forming the second p-type region by epitaxial growth is set to be the same as the total flow rate of the gas used for the epitaxial growth. 12) A method for producing a semiconductor device according to item 12).
(14) The method for manufacturing a semiconductor device according to (11), wherein the cleaning step uses atomic hydrogen.
(15) The method of manufacturing a semiconductor device according to any one of (10) to (14), wherein the fifth step includes a step of selectively epitaxially growing the third n-type region. .
(16) The semiconductor according to any one of (10) to (15), wherein a third p-type region is formed between the second p-type region and the electrode. Device manufacturing method.
(17) The fourth step includes a step of forming the second p-type region using ion implantation,
The method of manufacturing a semiconductor device according to (10), wherein the fifth step includes a step of forming the third n-type region using ion implantation.
１、１０１…低濃度ｎ型シリコン層（基板）、２、１０２…ｐ型エミッタ、３、１０３…ｎ型領域、４、１０４…ゲート絶縁膜、５、１０５…ゲート、６、１０、１９、１０６…絶縁膜、７、１５、１０７…ｎ型バッファ層、８、１６…高濃度ｐ型層、９、１７…高濃度ｎ型層、１１、１２、１３、１４、１１０、１１１、１１２…電極、１８…高濃度ｐ型領域、１０８…高濃度ｐ型層、１０９…高濃度ｎ型層。 DESCRIPTION OF SYMBOLS 1,101 ... Lightly doped n-type silicon layer (substrate), 2, 102 ... p-type emitter, 3, 103 ... n-type region, 4, 104 ... Gate insulating film, 5, 105 ... Gate, 6, 10, 19, 106: insulating film, 7, 15, 107 ... n-type buffer layer, 8, 16 ... high-concentration p-type layer, 9, 17 ... high-concentration n-type layer, 11, 12, 13, 14, 110, 111, 112 ... Electrode, 18 ... high concentration p-type region, 108 ... high concentration p-type layer, 109 ... high concentration n-type layer.

Claims (17)

  1. 　第１のｎ型領域と、
      前記第１のｎ型領域の第１領域上に設けられた第１のｐ型領域と、
      前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて設けられた第２のｎ型領域と、
      前記ｐ型領域上に設けられたゲート絶縁膜と、
      前記ゲート絶縁膜上に設けられたゲート電極と、
      前記第１のｎ型領域の前記第１領域とは異なる第２領域上に形成された第２のｐ型領域と、
      前記第２のｐ型領域上に設けられた第３のｎ型領域を有し、
      前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合が形成され、前記第２のｐ型領域と前記第３のｎ型領域が異なる電極にそれぞれ接続されていることを特徴とする半導体装置。     A first n-type region;
    A first p-type region provided on a first region of the first n-type region;
    A second n-type region provided on the first p-type region and separated from the first n-type region;
    A gate insulating film provided on the p-type region;
    A gate electrode provided on the gate insulating film;
    A second p-type region formed on a second region different from the first region of the first n-type region;
    A third n-type region provided on the second p-type region;
    A tunnel junction is formed between the second p-type region and the third n-type region, and the second p-type region and the third n-type region are respectively connected to different electrodes. A semiconductor device.
  2. 　前記第１のｎ型領域の前記第１領域と前記第２領域とは、前記第１のｎ型領域の互いに反対の面に設けられていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first region and the second region of the first n-type region are provided on opposite surfaces of the first n-type region.
  3. 　前記第１のｎ型領域の前記第１領域と前記第２領域とは、前記第１のｎ型領域の同じ面に設けられていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the first region and the second region of the first n-type region are provided on the same surface of the first n-type region.
  4. 　前記第２のｐ型領域がシリコンおよびゲルマニウムの少なくとも一方を含むことを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the second p-type region includes at least one of silicon and germanium.
  5. 　前記第２のｐ型領域は、絶縁膜により複数に分離されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the second p-type region is separated into a plurality by an insulating film.
  6. 　前記第１のｐ型領域と前記第２のｐ型領域の距離が２００ミクロン以下であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a distance between the first p-type region and the second p-type region is 200 microns or less.
  7. 　前記第２のｐ型領域のキャリア濃度が５×１０１９ｃｍ―３以上、１×１０２１ｃｍ―３以下であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a carrier concentration of the second p-type region is 5 × 10 19 cm −3 or more and 1 × 10 21 cm −3 or less.
  8. 　前記第２のｐ型領域の厚さが５０ｎｍ以下であることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the thickness of the second p-type region is 50 nm or less.
  9. 　請求項５記載の半導体装置を用いた電源制御用モジュール。 A power supply control module using the semiconductor device according to claim 5.
  10. 　第１のｎ型領域の第１領域上に第１のｐ型領域を形成する第１工程と、
      前記第１のｐ型領域上に前記第１のｎ型領域とは隔てて第２のｎ型領域を形成する第２工程と、
      前記ｐ型領域上にゲート絶縁膜を形成する第３工程と、
      前記ゲート絶縁膜上にゲート電極を形成する第４工程と、
      前記第１のｎ型領域の前記第１領域とは異なる第２領域上に第２のｐ型領域を形成する第５工程と、
      前記第２のｐ型領域上に第３のｎ型領域を形成して前記第２のｐ型領域と前記第３のｎ型領域とでトンネル接合を形成する第５工程と、
      前記第２のｐ型領域と前記第３のｎ型領域にそれぞれ異なる電極を接続する第６工程とを有することを特徴とする半導体装置の製造方法。     Forming a first p-type region on the first region of the first n-type region;
    A second step of forming a second n-type region on the first p-type region apart from the first n-type region;
    A third step of forming a gate insulating film on the p-type region;
    A fourth step of forming a gate electrode on the gate insulating film;
    A fifth step of forming a second p-type region on a second region different from the first region of the first n-type region;
    A fifth step of forming a third n-type region on the second p-type region to form a tunnel junction between the second p-type region and the third n-type region;
    A method of manufacturing a semiconductor device, comprising: a sixth step of connecting different electrodes to the second p-type region and the third n-type region, respectively.
  11. 　前記第４工程は、前記第１のｎ型領域の表面をクリーニングする工程と、前記第２のｐ型領域をエピタキシャル成長により形成する工程とを含むことを特徴とする請求項１０記載の半導体装置の製造方法。 11. The semiconductor device according to claim 10, wherein the fourth step includes a step of cleaning a surface of the first n-type region and a step of forming the second p-type region by epitaxial growth. Production method.
  12. 　前記クリーニングする工程は、前記第１のｎ型領域の表面へ水素を供給しながら加熱する工程を含むことを特徴とする請求項１１記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the cleaning step includes a heating step while supplying hydrogen to the surface of the first n-type region.
  13. 　前記第２のｐ型領域をエピタキシャル成長により形成する工程の直前における前記水素ガスの流量は、前記エピタキシャル成長で用いるガスの総流量と同じとなるように設定されることを特徴とする請求項１２記載の半導体装置の製造方法。 13. The flow rate of the hydrogen gas immediately before the step of forming the second p-type region by epitaxial growth is set to be the same as the total flow rate of the gas used for the epitaxial growth. A method for manufacturing a semiconductor device.
  14. 　前記クリーニングする工程は、原子状水素を用いることを特徴とする請求項１１記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the cleaning step uses atomic hydrogen.
  15. 　前記第５工程は、前記第３のｎ型領域を選択的にエピタキシャル成長する工程を含むことを特徴とする請求項１０記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 10, wherein the fifth step includes a step of selectively epitaxially growing the third n-type region.
  16. 　前記第２のｐ型領域と前記電極との間には、第３のｐ型領域が形成されることを特徴とする請求項１０記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 10, wherein a third p-type region is formed between the second p-type region and the electrode.
  17. 　前記第４工程は、イオン打ち込みを用いて前記第２のｐ型領域を形成する工程を含み、
      前記第５工程は、イオン打ち込みを用いて前記第３のｎ型領域を形成する工程を含むことを特徴とする請求項１０記載の半導体装置の製造方法。     The fourth step includes the step of forming the second p-type region using ion implantation,
    The method of manufacturing a semiconductor device according to claim 10, wherein the fifth step includes a step of forming the third n-type region using ion implantation.
PCT/JP2010/067673 2010-10-07 2010-10-07 Semiconductor device and method of production thereof WO2012046329A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012537530A JP5618430B2 (en) 2010-10-07 2010-10-07 Semiconductor device and manufacturing method thereof
PCT/JP2010/067673 WO2012046329A1 (en) 2010-10-07 2010-10-07 Semiconductor device and method of production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/067673 WO2012046329A1 (en) 2010-10-07 2010-10-07 Semiconductor device and method of production thereof

Publications (1)

Publication Number Publication Date
WO2012046329A1 true WO2012046329A1 (en) 2012-04-12

Family

ID=45927343

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/067673 WO2012046329A1 (en) 2010-10-07 2010-10-07 Semiconductor device and method of production thereof

Country Status (2)

Country Link
JP (1) JP5618430B2 (en)
WO (1) WO2012046329A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014118664A1 (en) * 2014-12-15 2016-06-16 Infineon Technologies Ag Power semiconductor device with improved stability and method for producing the same
EP3016144A4 (en) * 2013-06-27 2017-01-04 CSMC Technologies Fab1 Co., Ltd. Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0267766A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Bipolar-type semiconductor switching device
JPH0358482A (en) * 1989-07-26 1991-03-13 Nissan Motor Co Ltd Turn-off gate thyristor
JPH0414263A (en) * 1990-05-07 1992-01-20 Fuji Electric Co Ltd Insulated gate type bipolar transistor
JPH0575110A (en) * 1991-09-13 1993-03-26 Fuji Electric Co Ltd Semiconductor device
JP2006066692A (en) * 2004-08-27 2006-03-09 Mitsubishi Electric Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0267766A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Bipolar-type semiconductor switching device
JPH0358482A (en) * 1989-07-26 1991-03-13 Nissan Motor Co Ltd Turn-off gate thyristor
JPH0414263A (en) * 1990-05-07 1992-01-20 Fuji Electric Co Ltd Insulated gate type bipolar transistor
JPH0575110A (en) * 1991-09-13 1993-03-26 Fuji Electric Co Ltd Semiconductor device
JP2006066692A (en) * 2004-08-27 2006-03-09 Mitsubishi Electric Corp Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HUA YE ET AL.: "A MOS Gated Power Semiconductor Switch Using Band-to-Band Tunneling and Avalanche Injection Mechanism", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 55, no. 6, 2008, pages 1524 - 1528 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3016144A4 (en) * 2013-06-27 2017-01-04 CSMC Technologies Fab1 Co., Ltd. Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor
US10096699B2 (en) 2013-06-27 2018-10-09 Csmc Technologies Fab1 Co., Ltd. Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor
DE102014118664A1 (en) * 2014-12-15 2016-06-16 Infineon Technologies Ag Power semiconductor device with improved stability and method for producing the same
CN105702719A (en) * 2014-12-15 2016-06-22 英飞凌科技股份有限公司 Power Semiconductor Device with Improved Stability and Method for Producing the Same
US9698138B2 (en) 2014-12-15 2017-07-04 Infineon Technologies Ag Power semiconductor device with improved stability and method for producing the same
DE102014118664B4 (en) * 2014-12-15 2020-02-13 Infineon Technologies Ag Power semiconductor device with improved stability and method of manufacturing the same

Also Published As

Publication number Publication date
JPWO2012046329A1 (en) 2014-02-24
JP5618430B2 (en) 2014-11-05

Similar Documents

Publication Publication Date Title
JP3660897B2 (en) Manufacturing method of semiconductor device
US7679147B2 (en) Semiconductor device fabricated by selective epitaxial growth method
JP2005011915A (en) Semiconductor device, semiconductor circuit module and its manufacturing method
US20220157945A1 (en) Sic epitaxial wafer, manufacturing apparatus of a sic epitaxial wafer, fabrication method of a sic epitaxial wafer, and semiconductor device
KR20050119662A (en) Method of epitaxial deposition of an n-doped silicon layer
JPH08153688A (en) Manufacture of semiconductor device and semiconductor device
CN102194885A (en) N-type buried-channel silicon carbide metal oxide semiconductor field effect transistor (DEMOSFET) device and preparation method thereof
US7122488B2 (en) High density plasma process for the formation of silicon dioxide on silicon carbide substrates
WO2013111173A1 (en) Semiconductor light receiving element and light receiver
US20130023111A1 (en) Low temperature methods and apparatus for microwave crystal regrowth
KR101321424B1 (en) Method of surface treatment and thin film growth, and equipment for surface treatment and thin film growth
US20070202669A1 (en) Epitaxial growth method and semiconductor device fabrication method
WO2011158534A1 (en) Silicon carbide semiconductor device manufacturing method
WO2018185850A1 (en) Manufacturing method for silicon carbide epitaxial wafer and manufacturing method for silicon carbide semiconductor device
JP4359287B2 (en) Manufacturing method of semiconductor device
JP5618430B2 (en) Semiconductor device and manufacturing method thereof
JP5742712B2 (en) Method for manufacturing silicon carbide semiconductor device
JP2013168458A (en) Semiconductor device and manufacturing method of the same
JP5921089B2 (en) Epitaxial wafer manufacturing method and semiconductor device manufacturing method
JP2008153454A (en) Method of manufacturing mos type semiconductor device
JP2004193454A (en) Semiconductor device and method for manufacturing same
JP2010074016A (en) Semiconductor device and method for manufacturing the same
US7776751B2 (en) Process for producing silicon compound
JP2009206325A (en) Semiconductor device, and manufacturing method thereof
JP2008235726A (en) Manufacturing method of semiconductor multilayer film

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10858137

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2012537530

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10858137

Country of ref document: EP

Kind code of ref document: A1