WO2011089258A2

WO2011089258A2 - A variability-aware reliability simulation method of electronic systems

Info

Publication number: WO2011089258A2
Application number: PCT/EP2011/050936
Authority: WO
Inventors: Elie Maricau; Georges Gielen
Original assignee: Imec; Katholieke Universiteit Leuven
Priority date: 2010-01-25
Filing date: 2011-01-25
Publication date: 2011-07-28

Description

A variabiiity-aware reliability simulation method of electronic systems

Field of the invention

The invention relates to methods and devices to perform a computational efficient variability- aware reliability simulation of an electronic system, e.g. an integrated circuit such as for example a mixed-signal Integrated Circuit (IC). Background art

Scaling towards smaller transistor sizes in order to achieve smaller, faster, lower power and less expensive chips, creates evermore design problems. Die level reliability issues (e.g. Negative Bias Temperature Instability (NBTI) and Hot Carrier degradation (HC)) and increasing process variability are at the forefront of problems to be dealt with in modern and future CMOS technologies, as described in "Critical Reliability Challenges for the ITRS", Int. Sematech, Tech. Rep., 2007. The effect of transistor ageing (e.g. NBTI and HC) on circuit behaviour, especially when combined with process variability, is very complicated and not always well understood. The lack of adequate knowledge about circuit ageing can cause unreliable products or unnecessary design margins.

Existing solutions (e.g. post-production accelerated stress testing) become too expensive due to an increasing demand for very low failure rates augmented with evermore reliability and variability problems. A designer needs a statistical circuit analysis tool that includes circuit ageing. Such a tool must be fast (e.g. no more than a few hours of simulation time, even for large circuits) but must also have a good simulation accuracy. Moreover, a designer must be able to extract information (e.g. weak-spot detection) to improve his design or to implement countermeasures (circuit tuning). In literature, most reliability simulation methods have been developed a few years ago and are therefore intended for CMOS technologies where variability was not yet an issue. Examples are R. Tu et al, "Bert - berkeley reliability tools," EECS Department, University of California, Berkeley, Tech. Rep., 1991 or X. Xuan et al, "IC reliability simulator ARET and its application in design-for-reliability," ATS, 2003. To make a reliable design in a sub 90nm technology, however, the proposed solutions are no longer satisfactory. C. Bestory et al., in "Statistical analysis during the reliability simulation," Microelectronics Reliability, 2007 did include the effect of variability, using a Monte-Carlo (MC) simulation wrapped around a nominal reliability simulator based on high-level behavioural transistor models. This approach is fast, but it lacks accuracy, especially for analogue circuits where the effects of time-varying stress voltages are important. In E. Maricau and G. Gielen, "Efficient Reliability Simulation of Analogue ICs Including Variability and Time-varying Stress," DATE, 2009, a more accurate reliability simulator able to cope with time-varying stress is presented. In this document, the authors also used a MC-approach in order to include variability effects.

But, although an MC-based reliability simulation is accurate, it also has a large number of disadvantages: i) It is very cpu intensive, ii) There are no weak-spot detection capabilities. And iii) the simulation has to be rerun every time new or extra process data is included. Summary of the invention

It is an object of embodiments of the present invention to provide a reliability simulator for electronic systems, e.g. integrated circuits such as for example mixed signal ICs, which overcomes the disadvantages of prior art solutions.

In a first aspect, embodiments of the present invention concern a novel deterministic modelling and simulation method to calculate circuit ageing, including time varying stress, and process variability. A response model of the circuit behaviour is built, based on the result of an experimental design, e.g. a RSM (response surface model) may be built for exploring a relationship between several independent variables, available at the start of a process, and one or more response variables created by the process based on the independent variables. To speed up the analysis, in accordance with embodiments of the present invention a regression design may be combined with a screening analysis.

In one embodiment of the first aspect, the present invention provides a method for performing a computational efficient variability-aware reliability simulation of an electronic system using a response model of the electronic system under variability effects whereby a Design of Experiments is used to build said Response Model, the method comprising:

- Extracting a process variability sensitive circuit factor list from a netlist of said electronic system comprising circuit specifications and parameters;

- Selecting a plurality of process variability sensitive circuit factors from said extracted process variability sensitive circuit factor list by performing a screening analysis, followed by a non-linear regression analysis on said extracted circuit factors list;

- Simulating said selected process variability sensitive circuit factors;

- Calculating a Response Model using the results from the plurality of simulated circuit factors; and - Using said calculated Response Model to perform variability-aware reliability simulation and analysis of said electronic system.

In embodiments of the present invention, the circuit specific specifications and parameters may comprise one or more of circuit design parameters, circuit specifications, process parameters, environmental parameters and stress parameters.

In embodiments of the present invention, the screening analysis may be done using a fractional replicate screening analysis, for example using a 2-level systematic fractional replicate screening analysis.

In particular embodiments, the screening analysis may be followed by a regression analysis on the extracted circuit factors list, in order to make the model more accurate. Such regression analysis may be based on an error analysis. The regression analysis may be performed for example using fractional factorial design of experiments, such as a resolution V fractional factorial design of experiments.

In embodiments of the present invention, the simulation on said selected process variability sensitive circuit factors may be performed by a nominal reliability simulator, where the latter includes the effect of time-varying stress voltages and ageing-induced BIAS-condition variations on the electronic system behavior.

The calculation of the response model may be done using any of a physical, an empirical or a tabular model.

A method according to embodiments of the present invention may furthermore comprise a residual analysis on the response model for providing an estimate for the standard deviation on every evaluation of the model.

A method according to embodiments of the present invention may furthermore comprise generating a list with electronic system reliability weak spots.

A method according to embodiments of the present invention may furthermore comprise extracting electronic system yield as a function of circuit age, based on provided application- specific circuit specifications.

A method according to embodiments of the present invention tackles at least some of the before-mentioned problems of the prior art and have one or more of the following advantages: 1 ) A method according to embodiments of the present invention is systematic and applicable to analogue, digital and mixed-signal circuits.

2) A set of experimental designs ensures the generation of valid, defensible and accurate engineering conclusions.

3) A screening design for finding factors having a significant impact from a list of many potential ones, identifies circuit weak spots and reduces circuit simulation time guaranteeing a quasi-linear complexity. 4) A regression design for investigating a response over several different levels of an independent variable enables the generation of a circuit response model, e.g. Response Surface Model (RSM), of the circuit behaviour as a function of time.

5) When compared to a traditional random-sampling based reliability simulation, up to three orders reduction in simulation time can be achieved.

6) The response model error, e.g. the RSM error, and the error on the predicted yield is being estimated, based on the limited set of experimental design simulations.

7) A list with circuit reliability weak spots is being generated, enabling the designer to improve his/her design.

In a second aspect, the present invention provides a system-level simulator adapted for carrying out a method according to an embodiment of the present invention.

The present invention also provides a computer program product for executing a method according to embodiments of the present invention when executed on a computing device associated with a system-level simulator.

A machine readable data storage storing the computer program product according to embodiments of the present invention is also provided. The terms "machine readable data storage" or "carrier medium" or "computer readable medium" as used herein refer to any medium that participates in providing instructions to a processor for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as a storage device which is part of mass storage. Volatile media include dynamic memory such as RAM. Common forms of computer readable media include, for example, a floppy disk, a flexible disk, a hard disk, magnetic tape or any other magnetic medium, a CD- ROM, any other optical medium, punch cards, paper tapes, any other physical medium with patterns of holes, a RAM, a PROM, an EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave as described hereafter, or any other medium from which a computer can read.

Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to a processor for execution. For example, the instructions may initially be carried on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instruction over a telephone line using a modem. A modem local to the computer system can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to a bus can receive the data carried in the infrared signal and place the data on the bus. The bus may carry data to main memory, from which a processor may retrieve and execute the instructions. The instructions received by main memory may optionally be stored on a storage device either before or after execution by a processor. The instructions can also be transmitted via a carrier wave in a network, such as a LAN, a WAN or the internet. Transmission media can take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that form a bus within a computer. In an aspect, the present invention thus provides transmission of the computer program product according to an embodiment of the present invention over a local or wide area telecommunications network.

In a further aspect, the present invention provides transmission over a local or wide area telecommunications network of results of a method implemented by a computer program product according to embodiments of the present invention and executed on a computing device associated with a system-level simulator. Here again, the signals can be transmitted via a carrier wave in a network, such as a LAN, a WAN or the internet. Transmission media can take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that form a bus within a computer. In an aspect, the present invention thus provides transmission of the results of methods according to an embodiment of the present invention over a local or wide area telecommunications network.

It is an advantage of the methodology for characterization of electronic systems according to embodiments of the present invention that it leads to a two orders of magnitude speedup compared to Monte Carlo, without noticeable loss of accuracy.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Brief description of the drawings

Fig. 1. Representation of a nominal reliability simulation method.

Fig. 2. A variability-aware reliability simulation approach according to embodiments of the present invention, based on experimental design, ensures good coverage of the design space and strong reduction of simulation time.

Fig. 3. The circuit factor space with factors Λ and Λ (top left) is linked to a corresponding circuit performance space with performance parameters ^/:¾ and ¾ (top right). Circuit performance changes over time due to circuit ageing. When adding maximum and minimum values for each performance parameter, the time-dependent production yield Y can be calculated (bottom).

Fig. 4. A circuit is considered a black box with a number of inputs and the circuit yield as an output.

Fig. 5. Simulator flow for a one-stage amplifier.

Fig. 6. Simulation result for two versions of the one-stage amplifier of Fig. 5 over a life-time of 4 months.

Fig. 7. Yield of the original and the improved circuit as simulated in Fig. 6.

Fig. 8. RBF-model error, simulated over a life-time of 4 months and compared to a traditional random-sampling simulation for 500 samples.

Detailed description of illustrative embodiments of the invention Definitions "Circuit factor": A circuit design, environmental, technology or application dependent parameter that affects the circuit performance parameters. Circuit factors can vary, e.g. due to product process variability. Examples: transistor width, transistor oxide thickness, operating voltage, temperature. "Circuit performance parameter": A parameter describing part of the performance of the circuit. Examples: amplifier gain, oscillator start-up time, analog-digital converter accuracy.

"Weak Spot": A circuit factor with a large impact on the circuit performance, both as a function of process variability or as a function of time (i.e. circuit ageing). Detailed description of embodiments of the present invention

Embodiments of the present invention concern a method to perform a computational efficient variability-aware reliability simulation of electronic systems such as Integrated Circuits (ICs), e.g. mixed-signal Integrated Circuits. The input of the simulator is a netlist of the circuit under study. The netlist consists of a description of all circuit elements, the connection between the elements, the circuit bias conditions and a set of circuit performance parameters. As an output, the method provides:

1 . An aged version of the circuit netlist; and/or

2. A model for the behaviour of all circuit performance parameters as a function of process variability-parameters and circuit age; and/or

3. The production yield as a function of circuit age; and/or

4. The estimated model error and yield error.

5. A list with circuit weak-spots.

To guarantee a fast and accurate simulation, a response model, e.g. a Response Surface Model (RSM), based simulation technique is used. The vast number of computational intensive simulations, to perform a conventional variability analysis (e.g. Monte-Carlo (MC)), is thus replaced, in accordance with embodiments of the present invention, by the evaluation of an analytical model of the circuit. The response model, e.g. RSM, is a function of design parameters and circuit operation time and is built, based on a limited number of circuit simulations. In order to guarantee quasi-linear computational complexity, a set of Design of Experiments (DoE) is used to build the response model, e.g. the RSM. A method according to embodiments of the present invention may comprise the following steps:

1. Extraction of a list of process variability sensitive circuit factors from the input circuit netlist (e.g. circuit element values, technology parameters, etc.).

2. The circuit factors are combined with process variability parameters to form a circuit factor space. Every circuit factor has an average value (i.e. design value) and a statistical spread defined by the process variability parameters.

3. Every point in the circuit factor space, corresponding to one discrete circuit, can be mapped on a point in a circuit performance space. Every dimension of the latter corresponds to one circuit performance parameter. Since the performance of a circuit may be susceptible to ageing effects, the link between the circuit factor space and the circuit performance space may be a function of time. Every point in the circuit factor space can be evaluated via a reliability simulator; however, this is very computation intensive. Therefore, this link between the circuit factor space and the circuit performance space may be modelled with a response model, e.g. a Response Surface Model, based on a limited set of reliability simulations, described by a set of Design of Experiments.

4. A screening design, with a linear computational complexity, may provide a linear model and may eliminate unimportant design parameters.

5. A residual analysis on the linear model error may indicate whether this model is sufficiently accurate. If needed, a second design of experiments is conducted: a regression design.

6. The regression design may provide, if needed, a more accurate non-linear model. 7. Ordinary least squares regression may fit the simulations done in step 4 and 6 on a polynomial model.

8. A regression analysis on the model error may be used to estimate the error on every evaluation of the model and may also be passed on to estimate the error on the yield calculation.

9. The polynomial model can be evaluated very fast, when compared to a conventional reliability simulation on one circuit sample, and may be used to:

i. Perform a yield calculation: calculate the percentage of failing circuits, in an entire population, as a function of time.

ii. Detect circuit weak spots: identify circuit factors that have a large impact on circuit ageing. Weak spots can be used by a designer to improve the circuit design.

A method according to embodiments of the present invention concerns a deterministic, variability aware reliability modelling and simulation method. An advantage of embodiments of the method is that they allow to, for example, efficiently simulate failure-time dispersion in circuits subjected to die-level stress effects. A Design of Experiments (DoE) with a quasi- linear complexity may be used to build a response model, e.g. a Response Surface Model (RSM), of the time-dependent circuit behaviour. This reduces simulation time, when compared to random-sampling techniques such as for example Monte Carlo (MC), and guarantees good coverage of the circuit factor space. The DoE in accordance with embodiments of the present invention may comprise a screening design of experiments, which typically results in a model with linear complexity, to filter out important circuit factors, followed by a factorial regression design, e.g. a fractional factorial regression design, such as for example a resolution 5 fractional factorial regression design, to model the circuit behaviour. The method according to embodiments of the present invention is validated over a broad range of both analogue, digital and mixed-signal circuits and compared to traditional random- sampling reliability simulation techniques. It is shown to outperform existing simulators with a simulation speed improvement of up to several orders of magnitude. Also, it is proven to have a good simulation accuracy, with an average model error varying from 1.5 to 5 % over all test circuits.

The method according to embodiments of the present invention is built around a nominal reliability simulator explained in the section below. The variability-aware simulation framework of embodiments of the present invention is introduced in the next section.

I. NOMINAL RELIABILITY SIMULATION

The core of a reliability simulator is a method to calculate the performance of a circuit with fixed design parameters (i.e. without process variability) under variability effects, e.g. process variability effects such as random process variability effects or effects of variability due to ageing.

Following subsections give a brief overview, for example for effects of variability due to ageing, of both the simulation method and the degradation models which may be used. A. Simulation Methodology

Most degradation effects have an exponential dependence on the transistor gate voltage. Therefore, time-varying stress voltages have to be included when calculating circuit degradation.

To obtain accurate information about the time-varying stress at every circuit node, a transient simulation is required. Extrapolation of transistor degradation ensures a fast simulation result over very long circuit life-times. In Fig. 1 a schematic representation of the nominal simulation method 10 is depicted. The input to the simulator 1 1 is a fresh (i.e. unstressed) netlist. In a first step, a transient simulation over one period of the input signal is performed in a transient simulator 12. Then, the waveform on every node of every transistor is extracted and passed on to a transistor degradation model 13. Next, the degradation of every transistor is calculated and extracted over a longer time scale, and a degraded netlist is generated in a degraded netlist generator 14.

To mimicking the effect of degradation-induced, time-dependent bias voltage shifts, the simulator 11 does in reality not extrapolate the transistor degradation over one large time step, but does this iteratively over smaller time steps, determined in a time step determinator 15. To still obtain a good simulation speed, the magnitude of every time step is, for every iteration, maximized. At the same time, simulation accuracy is guaranteed by enforcing a maximum shift to all circuit performance parameters (see the step-size Algorithm 1 below). After every iteration the updated parameters of the aged circuit are fed back to the input of the transient simulator 12, and are resimulated to get an input for the next extrapolation. This procedure is repeated until the circuit is simulated over its entire operation time.

Finally, a degraded version of the netlist is generated. The entire algorithm has a linear complexity O(n) with respect to the number of transistors in the circuit.

Algorithm 1 S i i r s i/ i A LGORITHM

1: INPUT: i, J_H, 7*_/ei/ , P'- \ P^l (see Fig. 1 )

2: Determine error vector Ί :

3: Evaluate error vector

6: else

7: Fail= 1

8: end if

¾

If): OUTPUT: Fail

B. Transistor Degradation Modelling

As an example only, both HC degradation and NBTI are taken into account, since these effects are considered to be two of the most important phenomena in modern and future nanometer CMOS designs. Both phenomena affect different transistor model parameters, e.g. threshold voltage ^TH. The time dependent behaviour of these parameters can, for HC as well as for NBTI, be described as a power-law function of time, as indicated by C. Parthasarathy, "Etude de la fiabilite des technologies cmos avancees," Ph.D. dissertation, Universite d'Aix-Marseille, 2006:

A = fiy_Ds, V_GS, VrH₀, T, W, L, . , , ) (2) where ^rwo is the initial threshold voltage (for an unstressed device) and ^?? is a time-related parameter (about 0.5 for HC and 0.18 for NBTI). A is a function of design parameters (e.g. transistor gate length L, transistor gate width W), environmental parameters (e.g. temperature

7) and process-related parameters (e.g. VTHO, io ) . A general degradation model, including the effect of time- ced from:

where 'TH represents the degradation present at time *'> ^a is a process-dependent parameter, to be determined through measurements, β is a parameter to include the effect of time-varying stress signals, with a DC value equal to Vas. C is a parameter that is a function of other transistor parameters (e.g. ^DS, T, L, ...) _ancj j_s different for each degradation phenomenon.

II. VARIABILITY-AWARE RELIABILITY SIMULATION A. Simulation Methodology

Existing random-sampling techniques (e.g. Monte-Carlo) are accurate, but very cpu intensive, since they often tend to sample designs with a high probability of occurrence. It therefore takes a long time to identify designs at the edge of the design space (which tend to be the designs that typically create yield problems).

A response model, e.g. RSM, of the circuit behaviour, on the other hand, can be evaluated very fast and thus allows quick yield calculation. To build a sufficiently accurate circuit model, a design of experiments (DoE) can be used. These well known information gathering techniques (see also D. Montgomery, "Design and analysis of experiments." 2009) allow to extract a maximum of information, with a minimum of experiments (or simulations).

Unfortunately, the time to build a response model, e.g. an RSM, grows exponentially with the number of transistors in a circuit. For example, to model a linear system with n factors (inputs), including possible interactions between different factors, a design with a 0(2") complexity is needed. In order to reduce circuit model build time, the number of factors to build the response model, e.g. RSM, should thus advantageously be limited. However, for a designer, it is very hard to distinguish important design factors from less important ones, since the relationship between circuit design factors and the circuit response under variability effects, e.g. circuit ageing, can be very complex and is circuit and application dependent. In accordance with embodiments of the present invention, first relevant circuit factors are filtered out, for example using a compact set of experiments design (typically referred to as a screening design) and then a more complex regression design may be used to build an accurate response model, e.g. an RSM model, of the circuit. Finally, this response model, e.g. RSM, can be evaluated to characterise the circuit under variability effects, e.g. to calculate the circuit yield.

Fig. 2 shows a schematic representation of the simulation method 20 according to embodiments of the present invention. The input to a simulator 20 according to embodiments of the present invention is a circuit netlist, e.g. a SPICE-netlist, and a corresponding testbench (see Fig. 2). The simulator 20 itself comprises three main parts:

1 ) A circuit factor extractor 22. In a first step (Circuit Factor Extraction on Fig. 2), a circuit factor list, with values for all circuit design, environmental and input parameters, forming a circuit factor space F, is extracted from the input netlist. The DoEs can consist of a set of points taken directly from the factor space F, but it is numerically more stable and more accurate to map the factor space F on a normalised and orthogonalised space F' and to sample from there to create the DoEs. Every point (see 'Circuit Factor NORMALIZATION' on Fig. 2). f Η./ ; · ./^ ; /::

with / ! /; S = 0, a(fj' ) = 1

with each normalised factor f'_j uncorrelated. Linear mapping from F to F' and vice-versa can be found in literature (see also D. Montgomery, "Design and analysis of experiments." 2009). The combination of both the circuit factor list and a process parameter file define a circuit factor space (see Fig. 3, top left).

2) The nominal reliability simulator (NRS) 1 1 , presented in section I above, is used to evaluate the behaviour of the circuit under variability, in the example given the time- dependent behaviour, (measured via circuit performance parameters) of a single sample in the circuit factor space. Evaluation of all samples will create a corresponding performance space (see Fig. 3, top right). In accordance with embodiments of the present invention, the NRS 1 1 is applied on samples defined by a screening DoE 23 and optionally a regression design 24, which allows to analyze the circuit factor space with a limited number of simulations. Since the goal of this work is not to obtain a highly accurate model, but to analyze the spatial (e.g. process variability) and temporal (e.g. transistor ageing) reliability of a circuit in a reasonably short time frame, the second set of regression DoEs is only executed if really needed.

A residual analysis assesses whether the linear model, resulting from the screening design, is sufficiently accurate. The model errors are given by:

where M represents the number of DoE experiments. If the model fits the simulation data well, the errors should be fairly small and distributed evenly around zero. A non-parametric statistical hypothesis test, such as e.g. a Wilcoxon signed-rank test, tests whether the mean error for each circuit specification differs significantly from zero, with:

Additionally, to test whether the errors are small enough, the standard deviation of the model error is compared to the standard deviation of the data itself. If the model error standard deviation is at least a pre-determined value, e.g. 10 times, smaller then the standard deviation of the data, the model error is considered sufficiently small. If one or both tests fail, extra simulations are needed in order to get a more complex non-linear model (e.g. defined by a regression DoE). This approach now ensures a good model accuracy, but still guaranteeing a limited simulation complexity.

3) The results of the analysis in the second step are used to create a response model, e.g. an RSM (25, 26), to quantify the link between the factor space and the performance space. Adding specification limits to the circuit (e.g. minimum and maximum values for the performance parameters) allows to characterise the circuit under variability, e.g. allows to calculate the production yield in a characterising device, e.g. a yield calculator 27 (also see Fig. 2 and Fig. 3, bottom).

In the following three sections the different parts of the simulator 20, introduced above, will be discussed in more detail.

B. Circuit Factors

Every circuit 40 is considered as a black box (see Fig. 4) with a number of inputs: e.g. circuit design parameters, circuit specifications, process parameters, environmental parameters, stress parameters, etc. Due to variability effects such as e.g. process variations, different circuit application, environmental conditions or user interaction, every input varies around a mean value. Every set of input factors n.ab* can therefore be written as:

^ t n.abs— ^m an ^ ar^^'in (4)

where (mean represents the mean value for every factor (specified in the input circuit netlist), fin is a vector with normalised variations for every factor and A_var is a diagonal denormalisation matrix (defined in the process parameter file, also see Fig. 2). Vector , with n the number of factors, can be changed to walk over the circuit factor space. The output of the system is a characterisation of the system under variability effects, e.g. in the example illustrated the production yield of the circuit.

C. Experimental Design: Screening and Regression

To analyze and to model the circuit, a screening design 23, and optionally a linear and/or a non-linear regression experimental design 24, 25, 26 may be used (see Algorithm 1 ). This combination of experimental designs results in a simulator 20 with a quasi-linear complexity

0{n + / / lOO^ _wj h n the number of circuit factors, and is therefore very cpu efficient. Each experimental design D consists of a set of different input factor vectors

i⁾ = if ., , : . . . : !;,._.,] (5)

with g the number of experiments in the design. The different experimental designs, used in embodiments of the present invention, will now be explained in more detail.

Algorithm 1 EXPERIMENTAL DESIGN ANALYSIS

I: Inputs: f_in = [f . , . , f_n]

2: Outputs: ,. ∑>R W^{n x k}, P_R e l^mx?>

3: SCREENING Analysis:

4: Set up D_s€ N^{'2Ti+2> ^{x ,t} (see Table 1}

5: Ps€ 1²"+² = NRSiDs)

6: k = Q

7: for i— 1 to II do

8: Eliminate Factors using Pg and Eq. 7 and 8:

fi_£j j > > 0, with i φ j then

12: end if

13: end for

Ϊ4: REGRESSION Analysis:

15: Set up Dfi : q - l, :] e K« ^fc {see Eq. 9 and Table 11}

16: Set up Dn[q : m, :] = Dec€ E ^{2¾+ l}>^{x fe} {see Table 01}

17: p_R e m^m = NRS(Dn)

In the first step, a screening DoE 23, for example a fractional replicate screening analysis such as e.g. a 2-level systematic fractional replicate screening analysis as described in S. Cotter, "A screening design for factorial experiments with interactions," Biometrika, 1979, with a 0(2n + 2} complexity, may be used TABLE f

SYSTEMATIC FRACTIONAL REPLICATE SCREENING DESIGN SETUP

to screen out the factors with the largest impact on the circuit output P. This results in a factor set ^in, a subset of the original input factor set The screening design DS and the corresponding output vector Ps are listed in Table I. Vector ^Ps = [Ps.i , . . . , Ps n+n] _s obtained by applying the Nominal Reliability Simulator 1 1 (indicated as NRS in Algorithm 1 ) on the input circuit netlist. For every simulation a different input factor combination, defined by is used. Ps is then used to estimate the main effect a% of every circuit factor f< ^e f™ on the circuit output P. The behaviour of a linear system with P as function of inputs [fii^■■■ _* fn}₎ where each factor takes the value +1 or -1 , can be written as:

n 3 n

^{P = a}° ⁺∑ ^ +∑■∑ " ·.·· ·· /.; + · ^■ · ^ftt...n i . . . /_re (6) where

Oi = [(-¾,¾,+ _ - P_S,n+i) + (Ps,i - ¾o)| (7)

Also, the sum of first-order interaction effects of each factor > with any other factor /J > Φ 3 can be estimated:

T a_l3 = [(P_S,2n+l - P_S,n+i) ^~ (¾ " ¾ø)] (8) If, for a given factor .ft , the main effect or the interaction with other factors is large, will have a significant impact on the circuit behaviour and is screened out for further analysis if ⁱ - f n ), if not, fi can be neglected (/» i fLl A factor with a large interaction with another factor and an equally large, but opposite, interaction with a third factor, will wrongfully be neglected. However, this event is considered to be very unlikely. Typically, circuit behaviour is determined by only a small set of factors.

The above model does not include non-linear effects, therefore a center design (i.e. a design at the center of the factor space) may be added to the screening design 23 (e.g. DS[2n + 2, :] in Table I), which may be included to detect non-linearities. With a residual analysis, the model accuracy is tested. The model errors e'_j are given by:

= {/^ - ¾} witIi = {0. , . , , 2H + 2}

If the model fits the simulation data well, the errors should be fairly small and distributed evenly around zero. A non-parametric statistical hypothesis test such as e.g. a Wilcoxon signed-rank test may be used to determine whether the mean error e_j for each circuit specification P, differs signific

Additionally, to test whether the errors are small enough, the standard deviation of the model error may be taken into account. This standard deviation of the model error may be compared to the standard deviation of the data itself, in a comparator 28. If the error standard deviation is a pre-determined factor, e.g. one hundred times, smaller than the standard deviation on the model output, the model error is considered sufficiently small. If one or both tests fail, extra simulations are needed in order to get a more complex non-linear model. These extra simulations may be given by a regression design.

Screening will thus result in only a limited subset of the original circuit factors. Factors with the largest contribution to the circuit behaviour are identified as weak spots. This information can also be used by the designer to improve his design.

The factor set ^e ^^fc j_{s usec}j _{as an} j_nput to a regression analysis 24 in the second step, k is the number of factors screened out in the first analysis, with k < for large circuits. In the concept of embodiments of the present invention, large circuits are defined as circuits with n > 50.

To model the circuit behaviour, a fractional factorial DoE may be used. Factorial and fractional factorial designs are used a lot in industrial experimentation and regression modelling. Two-level factorial designs provide high power for testing or estimating linear effects, while fractional factorial designs allow this to be accomplished with fewer experiments. As an example, a Resolution V Fractional Factorial (R5 FF) design may be used. This allows to identify both the main effect for every factor <¾, as well as first-order interaction effects <¾ (cfr. equation 6). However, few R5 FF designs are readily available. To be able to model a circuit with any number of factors, an orthogonal discrete-valued basis set, called Walsh functions, is used to find a suitable R5 FF design for every circuit. S. Sanchez and P. Sanchez, in "Very large fractional factorial and central composite designs," ACM Transactions on Modelling and Computer Simulation, 2005 presented a method, using a Hadamard-ordered matrix to generate the Walsh functions. This matrix ■¾.< with dimensions 2^C 2^V = N x iVcan be generated using:

The columns *o»^■■ · · ' ^*> .of H_v define the Walsh functions with corresponding Walsh indices 0. . . N - 1 and all elements take values +1 or -1 . A R5 FF design for k factors, coincides with a subset of the N Walsh functions. The elements of each function in this subset each represent one factor in the design. The Walsh indices can be found through an algorithm that is described in the above Sanchez document. Table II lists the Walsh indices for R5 FF designs up to 1 1 factors. For example, for a circuit with 4 factors, the columns with indices {1 , 2, 4, 8, 15} of a ¾ Hadamard matrix represent a R5 FF design. In Algorithm 1 , q indicates the number of experiments for the R5 FF design, which can only be used to estimate the linear effect of all relevant factors in the circuit. To also capture non-linear effects, the design may be augmented with a central composite design and a center design, which requires 2k + 1 extra simulations. The setup of these experiments and the corresponding outputs are listed in Table III. To perform the entire regression analysis ^m — q + '2 t + I experiments are needed (also see Algorithm 1 ).

TABLE H

WALSH INDICES FOR R5 FRACTIONAL FACTORIAL DESIGNS.

TABLE lii

CK TKR AN! ) (.'! Μ Λ Ι COMPOS 1TK DES IGN S KTU P

D. Response Surface Modelling

The simulation results obtained via the design of experiments are used to design a response model, e.g. a Response Surface Model (RSM). Different response models, e.g. RSMs, are possible. As an example, four different models were considered:

1 . A Physical Model: a model based upon approximate modeling of physical phenomena within the circuit.

2. An Empirical Model: tuning parameters of an analytical model to adequately fit a data set:

a. Ordinary Least Squares (OLS): a widely applied technique, limiting the sum of squared residuals for a pre-defined polynomial model.

b. Radial Basis Function (RBF) neural network: a system with one hidden layer of artificial neurons, using the input data set as training data.

3. A Tabular Model: a model evaluated through interpolation or extrapolation of a data set in a look-up table.

a. Locally Weighted Scatterplot Smoothing (LOESS): fitting simple OLS models to localized subsets of the input data set.

A physical model can be very accurate, even if only a small input data set is available, but it requires a thorough knowledge of the circuit and is therefore very circuit dependent. Since a simulation tool in accordance with embodiments of the present invention would advantageously be application and circuit independent, the physical model is not considered to be the most preferred model.

A tabular model, such as LOESS, can also be very accurate, but requires a user-defined smoothing parameter, which will, again, be circuit dependent. Combined with a large model evaluation time and poor extrapolation capabilities, LOESS is therefore also not preferred for embodiments of the present invention.

An empirical model, e.g. empirical RSM, is considered to be a good type of model for being used in embodiments of the present invention. Both a neural network (e.g. RBF) and a parametric polynomial model (e.g. OLS) were implemented and evaluated. An RBF has a better behaviour when modeling highly non-linear functions, but performs worse when the correlation coefficient R^A2 is large (i.e. in case of a linear function). The accuracy of an RBF also deteriorates fast with increasing number of dimensions and increasing number of data values to be fitted. Since in embodiments of the present invention the number of dimensions can be fairly large and the deviation from the nominal design point will be rather small (e.g. only determined by process-dependent variations), a parametric polynomial response model, e.g. OLS RSM, results in a good fit. The OLS RSM consists of an polynomial with an average term, linear terms for each factor and quadratic and interaction terms to model weak non- linearities. III. APPLICATION OF THE ANALYSIS RESULTS

In section II, a method to analyse the reliability of a circuit subjected to variability effects, e.g. production process variations, was discussed. This analysis results in a response model, e.g. an RSM, that models the link between the circuit factor space F and the circuit performance space P. The response model, e.g. RSM, can be evaluated very fast and is therefore not only suited to characterize the circuit under variability effects, e.g. to study the ageing of circuit performance specifications, but also to use the results thereof, e.g. to perform a very fast yield calculation or to detect circuit reliability weak spots. These two examples are worked out somewhat more hereinbelow.

A. Yield Estimation

If the circuit is to be used in a specific application, circuit specifications can be added to the problem. Next, a statistical analysis, e.g. a Monte-Carlo (MC) analysis, may be used to find a description for the yield function A(t). But instead of simulating every sample using a nominal reliability simulator 1 1 , in accordance with embodiments of the present invention the equivalent response model, e.g. RSM model, is evaluated to obtain each result, providing an approximation for the yield function A(t), denoted as Aft). Using the response model, e.g. RSM, being an analytical model, reduces the yield calculation time with more than 4 orders of magnitude.

B. Weak Spot Detection

Once a designer has analyzed his/her circuit, to find out how it ages and how yield changes over time, (s)he will be interested in changing some design parameters in order improve reliability or to decrease overdesign. In order to do so, a weak spot analysis returns a list of circuit design parameters that are sensitive to process variability and/or circuit ageing. This list is based on a sensitivity analysis of the response model, e.g. response surface model:

IV. EXPERIMENTAL RESULTS

The following experiments were conducted, the results of which will be described hereinafter:

• Simulation of a one-stage amplifier: a simple example allows to demonstrate the simulator according to embodiments of the present invention and to also illustrate how to use circuit weak-spot detection to create a more reliable circuit.

• Validation of the simulator according to embodiments of the present invention: five analogue and digital circuits were simulated using a simulator according to embodiments of the present invention and were compared to traditional random-sampling simulation techniques. The circuits under study are designed in a 90nm CMOS technology. The experiments were executed on a dual-quad core 2.8GHz Intel Xeon processor with 8GB of RAM.

A. Demonstration

A one-stage resistive amplifier (depicted in Fig. 5 on the right) was used as a simple circuit to demonstrate the simulator according to embodiments of the present invention. Two performance parameters were monitored: the AC output voltage V_out and the DC output voltage VOUT. The circuit was simulated over a life-time of 4 months in which the circuit degrades due to hot carrier effects. Fig. 5 gives a schematic representation of the simulation flow and the corresponding outputs. Screening indicated that i) factor L (the transistor length) has the largest impact on the circuit reliability and ii) increasing this factor improves the circuit reliability. Therefore, a second amplifier was designed and simulated for which both the width and the length of the transistor were doubled. This is expected to improve circuit reliability, while circuit performance remains the same.

It is to be noted that this improvement in reliability, due to an increased transistor length, cannot be quantified, since the RBF-model is based on process variations over a small range, rather than design variations (e.g. 2xL) over a large range. The polynomial models were evaluated for both circuits, in 50 points randomly distributed over the circuit factor space and at time t=0 and time t=4 months. The results are shown in Fig. 6.

Fig. 7 depicts the yield of the original and the improved circuit. Due to circuit ageing, both circuit performance parameters change over time. However, the improved circuit degrades much less compared to the original circuit and is therefore much more reliable.

TABLE IV

RELIABILITY ANALYSIS MODEL VALIDATION.

[ I]: Single Stage Amplifier [Gain]

f2j: LC-VCO n;.„i

[3 J; Differential Pair Amplifier [Owiput Offset]

|4|: Symmetrica) OTA [Gain]

[5{: Ring Oscillator [Frequenc |

f6J: AND Gate [Fail Time)

B. Validation

To validate the accuracy and speed-up of a simulator according to embodiments of the present invention, six commonly used circuits were simulated. The resulting polynomial model for each circuit was compared to the simulation result of a traditional random-sampling simulation with a uniform distribution of the input factors (see Table IV). Every circuit was simulated over a life-time of 4 months. The average model error was calculated with respect to the circuit parameter output range:

Fig. 8 depicts the distribution of the model error for every circuit under test. The largest average error between a circuit model and the simulations is 5%, while the simulation speedup is at least three orders in magnitude. To further reduce the model error, extra simulations can be performed, though, this would dramatically increase simulation time, which is not always wanted. For all circuits the model errors are evenly distributed around 0, indicating a good model fit, with no constant variation between the model and the data. To quantize the model accuracy (i.e. MA in Table IV), the error was compared to the standard deviation of the data:

To validate the simulator speed, the yield (at time t=0) was calculated with a Monte-Carlo analysis using the model generated by the reliability analysis tool. The standard deviation on the yield Y, when calculated with a Monte-Carlo loo , is given by:

with M the number of Monte-Carlo simulations. However, since there is also an error on the output generated by the circuit model (i.e. model error), the standard deviation on the estimated yield will be larger than predicted by the equation above. To reduce the yield error caused by the Monte-Carlo simulation itself, the simulation was conducted over 100000 samples (i.e. M=1 e5). Furthermore, every sample was evaluated 100 times, using the average model response and the estimated model accuracy to estimate the impact of the model error on the yield error. Both the yield and its standard deviation are listed in Table V. The equation above can now be used to calculate the sample size needed to calculate the yield with the same accuracy, but using a conventional Monte-Carlo simulation (i.e. using a nominal reliability simulation to evaluate every sample instead of the model). Comparing this result with the number of nominal reliability simulations needed to analyze the circuit and to find a circuit model, results in a simulation speed-up for every circuit. This speed-up is also listed in Table V and varies between 4200 and 51000 for the circuits under test, which is a speed-up up to 4 orders of magnitude. TABLE V

YIELD CALCULATI ON COMPARED TO MONTE-CARLO S IMULATION.

Y (t=0) σγ (t=0) Speed-up [%] [%] Compared to MC

1 99.3 0.02 15000

1 96.7 0.009 35900

3 99.8 0.02 16500

4 97.4 0.01 6100

5 98.9 0.02 4200

6 99.1 0.005 1000

Claims

1 . - A method for performing a computational efficient variability-aware reliability simulation of an electronic system using a response model of the electronic system under variability effects whereby a Design of Experiments is used to build said Response

Model, the method comprising:

- Simulating said selected process variability sensitive circuit factors;

- Calculating a Response Model using the results from the plurality of simulated circuit factors;

- Using said calculated Response Model to perform variability-aware reliability simulation and analysis of said electronic system.

2. - The method according to claim 1 , wherein circuit specific specifications and parameters comprise one or more of circuit design parameters, circuit specifications, process parameters, environmental parameters and stress parameters.

3. - The method according to any of the previous claims, wherein said screening analysis is done using a fractional replicate screening analysis.

4. - The method according to claim 3, wherein said fractional replicate screening analysis is a 2-!evel systematic fractional replicate screening analysis.

5. - The method according to any of the previous claims, wherein the screening analysis is followed by a regression analysis on the extracted circuit factors list, based on an error analysis.

6. - The method according to claim 5, wherein said regression analysis is performed using fractional factorial design of experiments.

7. - The method according to claim 6, wherein said fractional factorial design of experiments is a resolution V fractional factorial design of experiments.

8. - The method according to any of the previous claims, wherein said simulation on said selected process variability sensitive circuit factors is performed by a nominal reliability simulator, where the latter includes the effect of time-varying stress voltages and ageing-induced BIAS-condition variations on the electronic system behavior.

9. - The method according to any of the previous claims, wherein said calculation of response model is be done using any of a physical, an empirical or a tabular model.

10. - The method according to any of the previous claims, furthermore comprising a residual analysis on the response model for providing an estimate for the standard deviation on every evaluation of the model.

1 1. - The method according to any of the previous claims, furthermore comprising generating a list with electronic system reliability weak spots.

12. - The method according to any of the previous claims, furthermore comprising extracting electronic system yield as a function of circuit age, based on provided application- specific circuit specifications.

13. - System-level simulator adapted for carrying out a method as in any of claims 1 to 12.

14. - Computer program product for executing any of the methods as claimed in claims 1 to

12 when executed on a computing device associated with a system-level simulator.

15. - A machine-readable data storage storing the computer program product of claim 14.

16. - Transmission of the computer program product of claim 14 over a local or wide area telecommunications network.