WO2011087120A1 - Logic circuit and integrated circuit - Google Patents

Logic circuit and integrated circuit Download PDF

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Publication number
WO2011087120A1
WO2011087120A1 PCT/JP2011/050650 JP2011050650W WO2011087120A1 WO 2011087120 A1 WO2011087120 A1 WO 2011087120A1 JP 2011050650 W JP2011050650 W JP 2011050650W WO 2011087120 A1 WO2011087120 A1 WO 2011087120A1
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Prior art keywords
magnetic field
pair
type
state
type element
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PCT/JP2011/050650
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French (fr)
Japanese (ja)
Inventor
勝彦 鈴木
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独立行政法人国立高等専門学校機構
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Priority to JP2011550033A priority Critical patent/JP5573850B2/en
Publication of WO2011087120A1 publication Critical patent/WO2011087120A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00

Definitions

  • the present invention relates to a logic circuit and an integrated circuit having this as a component.
  • PAL Programmable Array Logic
  • PLD Programmable Logic device
  • an object of the present invention is to provide a logic circuit or the like that can be reconstructed but can be reduced in size and power consumption as compared with the prior art.
  • the logic circuit of the present invention includes a first type element composed of a first free layer and a first semi-fixed layer as a pair of electrode layers sandwiching an insulator tunnel barrier layer, and having a negative magnetoresistance effect, A first type element comprising a second free layer and a second semi-fixed layer as a pair of ferromagnetic electrode layers sandwiching a body tunnel barrier layer, and having an inverse magnetoresistive effect, And an assembly element configured by connecting the second type elements in series, a conducting wire through which a current for forming a magnetic field in the assembly element flows, and ON / OFF of the current of the conducting wire is switched.
  • An input terminal configured; a voltage applying element configured to apply a voltage to the collective element; and an output terminal connected to a connection point between the first type element and the second type element.
  • the first free layer and the second free layer are made of a conductive ferromagnetic material whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a first threshold, and the first semi-fixed layer and the second half layer
  • the fixed layer is made of a conductive ferromagnetic material whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a second threshold greater than the first threshold, and having a strength greater than or equal to the first threshold and less than the second threshold.
  • the magnetization directions of the first free layer and the second free layer coincide with the direction of the magnetic field, and a magnetic field having a strength equal to or greater than the second threshold is applied to the collective element.
  • a magnetic field having a strength equal to or greater than the second threshold is applied to the collective element.
  • the collective element includes a pair of the first type elements connected in parallel and a pair of the second type elements connected in series, and each of the pair of first type elements and the pair of second type elements.
  • a pair of conducting wires configured to be connected to one of the seed elements, and through which a current that forms a magnetic field applied to each of the pair of combinations of the first seed element and the second seed element flows; You may provide a pair of said input terminal comprised so that ON / OFF of each electric current of a pair of conducting wire may be switched.
  • the integrated circuit of the present invention includes at least one of the logic circuits as a component.
  • the present invention it is possible to reconstruct as described below, and the level of current (ON / OFF or 1/0) of the current flowing through the input terminal through the input terminal is used as an input signal, and the level of the output terminal voltage of the collective element is determined.
  • a small logic circuit is formed as an output signal.
  • the strength of the magnetic field in the collective element is adjusted, and the first type element (first tunnel magnetoresistive effect element) and the second type constituting the collective element.
  • the magnetization state of each element is adjusted. Specifically, the magnetization direction of the free layer is adjusted by a magnetic field having a strength equal to or greater than the first threshold. Since the fixed layer and the free layer are made of ferromagnetic metals having different coercive forces, the magnetization direction of the fixed layer is not reversed by a magnetic field having a strength higher than the first threshold and less than the second threshold.
  • each magnetic tunnel junction element is switched.
  • the combination pattern of the resistance values of the first type element and the second type element is switched.
  • the logic configuration can be changed by one logic circuit of the present invention regardless of the configuration of a plurality of circuits, and each magnetic tunnel junction element is created as an element having a nano-sized electrode area. Is achieved.
  • the degree of integration of an integrated circuit including a large number of logic circuits can be increased and the size thereof can be reduced.
  • the direction of magnetization of not only the free layer but also the fixed layer can be changed by a magnetic field having a strength equal to or greater than the second threshold.
  • the combination pattern of the magnetization direction of the free layer and the magnetization direction of the fixed layer according to ON / OFF of the current can be changed. That is, a logic circuit different from the original logic circuit can be constructed by changing the magnetization direction of the fixed layer.
  • FIG. 1 is a configuration explanatory diagram of a logic circuit as a first embodiment of the present invention.
  • FIG. Explanatory drawing regarding the function of the logic circuit as 1st Embodiment of this invention.
  • FIG. 5 is a configuration explanatory diagram of a logic circuit as a second embodiment of the present invention. Explanatory drawing regarding the function of the logic circuit as 2nd Embodiment of this invention.
  • FIG. 5 is a configuration explanatory diagram of a logic circuit as a second embodiment of the present invention.
  • the configuration of the logic circuit according to the first embodiment of the present invention is schematically shown in FIG.
  • the logic circuit shown in FIG. 1 includes a collective element ITMR.
  • the collective element ITMR is composed of a first type element TMR1 having a negative magnetoresistance effect and a second type element TMR2 having an inverse magnetoresistance effect.
  • the first type element TMR1 is composed of a first free layer ML1 and a first semi-fixed layer FL1 as a pair of electrode layers sandwiching an insulator tunnel barrier layer TL1 having a thickness of several nm or less.
  • the second type element TMR2 is composed of a second free layer ML2 and a second semi-fixed layer FL2 as a pair of ferromagnetic electrode layers sandwiching an insulator tunnel barrier layer TL2 having a thickness of several nanometers or less.
  • aluminum oxide (AlO x ) or magnesium oxide (MgO) is used as the tunnel barrier layers TL1 and TL2.
  • first type element TMR1 and the second type element TMR2 are connected in series by connecting the first semi-fixed layer FL1 and the second free layer ML2.
  • first-type element TMR1 and the second-type element TMR2 may be connected in series by any connection form, such as the first semi-fixed layer FL1 and the second semi-fixed layer FL2.
  • the first free layer ML1 and the second free layer ML2 are made of a conductive ferromagnetic material (for example, Fe) whose magnetization direction can be reversed by a magnetic field having a strength equal to or higher than the first threshold value Hc1.
  • the first semi-fixed layer FL1 and the second semi-fixed layer FL2 are conductive ferromagnets whose magnetization directions can be reversed by a magnetic field having a strength greater than or equal to a second threshold Hc2 greater than the first threshold Hc1 (for example, Co, Fe 3 O 4 ).
  • the logic circuit further includes a lead Iq through which a current forming a magnetic field applied to the first type element TMR1 and the second type element TMR2 flows, and an input terminal IN configured to adjust the current flowing through the lead Iq.
  • a voltage applying element configured to apply a voltage to the collective element ITMR (configured to generate a potential difference between VDD and GND), an output terminal OUT connected to the collective element ITMR, and It has.
  • the input terminal IN is composed of a MOS-FET, and the switching of the input terminal IN switches the presence / absence of current in the conducting wire Iq or ON / OFF.
  • a current flows through the lead Iq in a direction perpendicular to the plane of FIG. 1, and a magnetic field having a clockwise or counterclockwise component around the lead Iq is formed.
  • the other side of the conducting wire Iq is provided on the opposite side of the conducting wire Iq with respect to the collective element ITMR, and the current flowing through the conducting wire Iq is adjusted in a state where current is also flowing through the other conducting wire. By doing so, the magnetic field in the collective element may be adjusted.
  • the output terminal OUT is connected between the first type element TMR1 and the second type element TMR2.
  • the logic circuit is manufactured, for example, as a nano artificial crystal lattice in which the layers and elements are formed on an Si substrate by an epitaxial growth method.
  • a magnetic field having a strength less than the second threshold value Hc2 is applied to the collective element ITMR.
  • the magnetization directions of the free layers ML1 and ML2 of the first type element TMR1 and the second type element TMR2 constituting the collective element ITMR but also the magnetization directions of the fixed layers FL1 and FL2 Match the direction. That is, when the original magnetization directions of the fixed layers FL1 and FL2 are opposite to the magnetic field direction, the magnetization directions of the fixed layers FL1 and FL2 are reversed by the magnetic field.
  • That the magnetization directions of the pair of electrode layers constituting the magnetic tunnel junction element are parallel is expressed as the “para state” of the magnetic tunnel junction element. That the magnetization directions of the pair of electrode layers constituting the magnetic tunnel junction element are anti-parallel is expressed as the “anti-para state” of the magnetic tunnel junction element.
  • the OFF state of the input terminal IN (the state where no current flows through the conductor Iq) is defined as the state where the input x is “0”, and the ON state of the input terminal IN (a state where the current flows through the conductor Iq) Is defined as a state where the input x is “1”.
  • a state where the voltage at the output terminal OUT is low is defined as a state where the output y is “0”, and a state where the voltage at the output terminal is high is defined as a state where the output y is “1”.
  • NOT circuit When the first type element TMR1 and the second type element TMR2 are in the para state in a state where no magnetic field is applied, a NOT circuit is configured by the logic circuit having the above configuration. For example, when a magnetic field having a strength equal to or greater than the second threshold value Hc2 is applied to the collective element ITMR, both the first-type element TMR1 and the second-type element TMR2 can be set to the para state.
  • the logic circuit is not a NOT circuit.
  • a magnetic field equal to or higher than the second threshold value Hc2 is applied to the collective element ITMR, so that both the first type element TMR1 and the second type element TMR2 are set to the para state, and then the first threshold value Hc1 and the second value.
  • both the first type element TMR1 and the second type element TMR2 can be in the anti-para state.
  • the configuration of the logic circuit according to the second embodiment of the present invention is schematically shown in FIG.
  • the logic circuit shown in FIG. 3 includes the collective element ITMR.
  • the collective element ITMR is composed of a pair of first-type elements TMR11 and TMR12 having a negative magnetoresistance effect and a pair of second-type elements TMR21 and TMR22 having an inverse magnetoresistance effect.
  • the first first free layer ML11 and the second first free layer ML12 are connected, and the first first semi-fixed layer FL11 and the second first semi-fixed layer FL12 are connected.
  • the pair of first-type elements TMR11 and TMR12 are connected in parallel.
  • the first first free layer ML11 and the second first semi-fixed layer FL12 are connected, and the first first semi-fixed layer FL11 and the second first free layer ML12 are connected.
  • the pair of first-type elements TMR11 and TMR12 may be connected in parallel.
  • the second second semi-fixed layer FL22 and the first second semi-fixed layer FL12 are connected, so that the pair of second-type elements TMR21 and TMR22 are connected in series.
  • the pair of second-type elements TMR21 and TMR22 may be connected in series by any form such as connection of the first second free layer ML21 and the second second free layer ML22.
  • a pair of first type elements TMR11, TMR12 and a pair of second type elements TMR21, TMR22 is connected.
  • at least one of the connection form of the pair of first type elements TMR11 and TMR12 and the connection form of the pair of second type elements TMR21 and TMR22 is changed in various forms in accordance with the change.
  • the seed elements TMR11, TMR12 and a pair of second type elements TMR21, TMR22 may be connected.
  • the i-th input terminal INi is composed of a MOS-FET, and the switching of the i-th input line Iqi switches the presence / absence of current or ON / OFF.
  • a current flows in the i-th lead Iqi in a direction perpendicular to the paper surface of FIG. 3, and a magnetic field having a clockwise or counterclockwise component around the i-th lead Iqi is formed.
  • the other side of the conducting wire Iqi is provided on the opposite side of the conducting wire Iqi with the collective element ITMR as a reference, and the current passed through the conducting wire Iqi is adjusted in a state where current is also passed through the other conducting wire. By doing so, the magnetic field in the collective element may be adjusted.
  • the output terminal OUT is connected between the first type element TMR12 and the second type element TMR22.
  • the logic circuit is manufactured, for example, as a nano artificial crystal lattice in which each layer and element are formed on a Si substrate by an epitaxial growth method.
  • a magnetization reversal conducting wire Z through which a current flows in a direction perpendicular to the paper surface may be provided as necessary.
  • the first free layers ML11 and ML12 are constituted by positive spin polarizability magnetic free layers, and the first semi-fixed layers FL11 and FL12 are constituted by positive spin polarizability magnetic semi-fixed layers.
  • the second free layers ML21 and ML22 are constituted by negative spin polarizability magnetic free layers, and the second semi-fixed layers FL21 and FL22 are constituted by positive spin polarizability magnetic semi-fixed layers.
  • a magnetic field having a strength less than the second threshold Hc2 causes the i-th type 1 element TMR1i and the i-th type 2 element constituting the collective element ITMR Take TMR2i.
  • the magnetization directions of the free layers ML1i and ML2i coincide with the direction of the magnetic field. That is, when the original magnetization directions of the semi-fixed layers FL1i and FL2i are opposite to the magnetic field directions, the magnetization directions of the semi-fixed layers FL1i and FL2i are reversed by the magnetic field.
  • the OFF state of the i-th input terminal INi (the state in which no current flows through the conducting wire Iqi) is defined as the state where the input x i is “0”, and the ON state of the i-th input terminal INi (the i-th conducting wire Iqi)
  • the state in which current is flowing is defined as a state in which the input x i is “1”.
  • a state where the voltage at the output terminal OUT is low is defined as a state where the output y is “0”, and a state where the voltage at the output terminal is high is defined as a state where the output y is “1”.
  • NAND circuit When the first type element TMR11, TMR12 side is a high potential side (bias voltage application side) and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in a para state in a state where no magnetic field is applied, the configuration A NAND circuit is configured by these logic circuits.
  • the first type element TMR11 when the first input x 1 is 0, as shown in FIG. 4A, the first type element TMR11 is in the para state and the low resistance state, while the second type element TMR21 is in the para state. And it is in a high resistance state.
  • the first input x 1 is 1, one first type element TMR11 as shown in FIG. 4 (b) is Anchipara state and high resistance state, the second type device TMR21 is Anchipara state and a low resistance State.
  • the first type element TMR12 when the second input x 2 is 0, as shown in FIG. 4A, the first type element TMR12 is in the para state and the low resistance state, while the second type element TMR22 is in the para state and High resistance state.
  • the second input x 2 is 1, as shown in FIG. 4B, the first type element TMR12 is in the anti-para state and high resistance state, while the second type element TMR 22 is in the anti-para state and low resistance. State.
  • the logic circuit performs AND A circuit is constructed.
  • the tunnel junction device TMR11 corresponding to the first input x 1 and the second input x 2, TMR12, TMR21 and each state transition aspects of TMR22 is similar to the NAND circuit (FIG. 4 (a) (b) reference).
  • the first type element TMR11 when the first input x 1 is 0, as shown in FIG. 4B, the first type element TMR11 is in the antiparasitic state and the high resistance state, while the second type element TMR21 is in the antiparasitic state. And it is in a low resistance state.
  • the first input x 1 is 1, as shown in FIG. 4A, the first type element TMR11 is in the para state and the low resistance state, while the second type element TMR21 is in the para state and the high resistance. State.
  • the first type element TMR12 is in the antiparasitic state and the high resistance state
  • the second type element TMR22 is in the antiparasitic state. Low resistance state.
  • the second input x 2 is 1, while the one element TMR12 as shown in FIG. 4 (a) is para state and low resistance state, the second type device TMR22 para state and high-resistance State.
  • NOR circuit When the first type element TMR11, TMR12 side is the low potential side (ground side), and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in the para state with no magnetic field applied, the logic circuit performs NOR. A circuit is constructed. In this case, the tunnel junction device TMR11 corresponding to the first input x 1 and the second input x 2, TMR12, TMR21 and each state transition aspects of TMR22 is similar to the OR circuit (FIG. 4 (a) (b) reference).
  • a current is passed through the conducting wire connected to the two FETs and the magnetization reversal conducting wire (e), and the first type element and the second type element are both upper and lower electrodes.
  • the logical circuit of this embodiment realizes the negative logical product shown in the truth table of the NAND circuit as shown in Table 1. In any state, since no current flows except when the logic state is changed, the power consumption is suppressed to a low level.
  • a NOT logic circuit is realized by electrically connecting two INs.
  • the output terminal voltage of the collective element can be reconstructed as described below, and the level of the current (ON / OFF or 1/0) flowing through the input line through the input terminal is used as the input signal.
  • a small logic circuit having an output signal as the output signal is configured.
  • the strength of the magnetic field H in the collective element ITMR is adjusted, and the first type element TMR1 and the second type element TMR2 constituting the collective element ITMR are adjusted.
  • Each magnetization state is adjusted. Specifically, the magnetization directions of the free layers ML11 and ML12 are adjusted by a magnetic field having a strength equal to or greater than the first threshold value Hc1.
  • each magnetic tunnel junction element is formed as an element having a nano-sized electrode area, the logic circuit can be miniaturized. In addition, the degree of integration of an integrated circuit including a large number of logic circuits can be increased and the size thereof can be reduced.
  • the magnetization direction of the semi-fixed layers FL1 and FL2 as well as the free layers ML1 and 2ML2 can be changed by the magnetic field having the second threshold value Hc2 or more.
  • the combination pattern of the magnetization directions of the free layers ML1 and ML2 and the magnetization directions of the semi-fixed layers FL1 and 2FL2 according to ON / OFF of the current can be changed.
  • a logic circuit different from the original logic circuit can be constructed by changing the magnetization direction of the fixed layer.
  • the logic circuit using the C-MOS is switched on / off by “current”, whereas the logic circuit of the present invention is switched on / off by “magnetic field”. For this reason, according to the logic circuit of the present invention, only the power necessary for the magnetization reversal is consumed, so that the power consumption can be saved as compared with the logic circuit using the C-MOS.
  • the logic configuration cannot be changed with only the C-MOS, but the logic configuration can be changed with the logic circuit of the present invention.

Abstract

Provided is a logic circuit that is reconfigurable while enabling the pursuit of downsizing and power saving more than ever. The ON/OFF of currents flowing in a conductive line through an input terminal (IN) is switched, thereby the strength of a magnetic field (H) in the collective elements (ITMR) is adjusted, and respective magnetization statuses of a first-kind element (TMR1) and a second-kind element (TMR2) that constitute the collective elements (ITMR) are adjusted. Thereby, a combination pattern of the magnetization directions of a free layer (ML1) and a fixed layer (ML2) that constitute respective magnetic tunnel junction elements is switched.

Description

論理回路および集積回路Logic and integrated circuits
　本発明は論理回路およびこれを構成要素として有する集積回路に関する。 The present invention relates to a logic circuit and an integrated circuit having this as a component.
　ＰＡＬ（Programmable Array Logic）にしたがい、ＰＬＤ（Programmable Logic device）を用いた論理回路が提案されている（非特許文献１参照）。 According to PAL (Programmable Array Logic), a logic circuit using a PLD (Programmable Logic device) has been proposed (see Non-Patent Document 1).
　しかし、ＰＡＬによれば、さまざまな演算処理を実行するには、論理回路の構成要素である素子数、さらには配線数が多くなるため、回路が全体として大型化してしまう。 However, according to PAL, in order to execute various arithmetic processes, the number of elements and further the number of wirings that are components of the logic circuit increases, so that the circuit becomes large as a whole.
　そこで、本発明は、再構築可能でありながら、従来よりも小型化および省電力化を図ることができる論理回路等を提供することを解決課題とする。 Therefore, an object of the present invention is to provide a logic circuit or the like that can be reconstructed but can be reduced in size and power consumption as compared with the prior art.
　本発明の論理回路は、絶縁体トンネル障壁層を挟む一対の電極層としての第１自由層および第１半固定層により構成され、かつ、負の磁気抵抗効果を奏する第１種素子と、絶縁体トンネル障壁層を挟む一対の強磁性電極層として第２自由層および第２半固定層により構成され、かつ、インバース型の磁気抵抗効果を奏する第２種素子とを備え、前記第１種素子および前記第２種素子が直列接続されることにより構成されている集合素子と、前記集合素子における磁場を形成するための電流が流される導線と、前記導線の電流のＯＮ／ＯＦＦを切り替えるように構成されている入力端子と、前記集合素子に電圧を印加するように構成されている電圧印加要素と、前記第１種素子と前記第２種素子との接続箇所に接続されている出力端子とを備え、前記第１自由層および前記第２自由層は、第１閾値以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体からなり、前記第１半固定層および前記第２半固定層は、前記第１閾値より大きい第２閾値以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体からなり、前記第１閾値以上かつ前記第２閾値未満の強さの磁界が前記集合素子にかけられることにより、前記第１自由層および前記第２自由層のそれぞれの磁化の向きが当該磁界の方向に一致し、前記第２閾値以上の強さの磁界が集合素子にかけられることにより、前記第１自由層および前記第２自由層のそれぞれの磁化の向きのみならず、前記第１固定層および前記第２固定層のそれぞれの磁化の向きが当該磁界の方向に一致するように構成されていることを特徴とする。 The logic circuit of the present invention includes a first type element composed of a first free layer and a first semi-fixed layer as a pair of electrode layers sandwiching an insulator tunnel barrier layer, and having a negative magnetoresistance effect, A first type element comprising a second free layer and a second semi-fixed layer as a pair of ferromagnetic electrode layers sandwiching a body tunnel barrier layer, and having an inverse magnetoresistive effect, And an assembly element configured by connecting the second type elements in series, a conducting wire through which a current for forming a magnetic field in the assembly element flows, and ON / OFF of the current of the conducting wire is switched. An input terminal configured; a voltage applying element configured to apply a voltage to the collective element; and an output terminal connected to a connection point between the first type element and the second type element. Be equipped The first free layer and the second free layer are made of a conductive ferromagnetic material whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a first threshold, and the first semi-fixed layer and the second half layer The fixed layer is made of a conductive ferromagnetic material whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a second threshold greater than the first threshold, and having a strength greater than or equal to the first threshold and less than the second threshold. By applying a magnetic field to the collective element, the magnetization directions of the first free layer and the second free layer coincide with the direction of the magnetic field, and a magnetic field having a strength equal to or greater than the second threshold is applied to the collective element. As a result, not only the magnetization directions of the first free layer and the second free layer but also the magnetization directions of the first fixed layer and the second fixed layer coincide with the direction of the magnetic field. Be configured as And features.
　前記集合素子が、並列接続されている一対の前記第１種素子と、直列接続されている一対の前記第２種素子を備え、前記一対の第１種素子のそれぞれと、前記一対の第２種素子のうち一方とが接続されることにより構成され、前記第１種素子および前記第２種素子の組み合わせの対のそれぞれに加えられる磁界を形成する電流が流される一対の前記導線と、前記一対の導線のそれぞれの電流のＯＮ／ＯＦＦを切り替えるように構成されている一対の前記入力端子とを備えていてもよい。 The collective element includes a pair of the first type elements connected in parallel and a pair of the second type elements connected in series, and each of the pair of first type elements and the pair of second type elements. A pair of conducting wires configured to be connected to one of the seed elements, and through which a current that forms a magnetic field applied to each of the pair of combinations of the first seed element and the second seed element flows; You may provide a pair of said input terminal comprised so that ON / OFF of each electric current of a pair of conducting wire may be switched.
　本発明の集積回路は、前記論理回路のうち少なくとも１つを構成要素として備えていることを特徴とする。 The integrated circuit of the present invention includes at least one of the logic circuits as a component.
　本発明によれば、次に説明するように再構築可能、かつ、入力端子を通じて導線に流れる電流の高低（ＯＮ／ＯＦＦまたは１／０）を入力信号とし、集合素子の出力端子電圧の高低を出力信号とする小型の論理回路が構成される。 According to the present invention, it is possible to reconstruct as described below, and the level of current (ON / OFF or 1/0) of the current flowing through the input terminal through the input terminal is used as an input signal, and the level of the output terminal voltage of the collective element is determined. A small logic circuit is formed as an output signal.
　入力端子を通じて導線を流れる電流のＯＮ／ＯＦＦが切り替えられることにより、集合素子における磁界の強弱が調節され、この集合素子を構成する第１種素子（第１トンネル磁気抵抗効果素子）および第２種素子（第２トンネル磁気抵抗効果素子）のそれぞれの磁化状態が調節される。具体的には、第１閾値以上の強さの磁界により、自由層の磁化の方向が調節される。固定層および自由層は保持力が異なる強磁性金属により構成されているので、第１閾値よりも高い第２閾値未満の強さの磁界では固定層の磁化の方向は反転されない。 By switching ON / OFF of the current flowing through the conducting wire through the input terminal, the strength of the magnetic field in the collective element is adjusted, and the first type element (first tunnel magnetoresistive effect element) and the second type constituting the collective element. The magnetization state of each element (second tunnel magnetoresistive element) is adjusted. Specifically, the magnetization direction of the free layer is adjusted by a magnetic field having a strength equal to or greater than the first threshold. Since the fixed layer and the free layer are made of ferromagnetic metals having different coercive forces, the magnetization direction of the fixed layer is not reversed by a magnetic field having a strength higher than the first threshold and less than the second threshold.
　これにより、各磁気トンネル接合素子を構成する自由層および固定層の磁化の方向の組み合わせパターンが切り替えられる。これに応じて、第１種素子および第２種素子のそれぞれの抵抗値の高低の組み合わせパターンが切り替えられる。複数の回路の構成に依らずに本発明１個の論理回路で論理構成を変えることができ、各磁気トンネル接合素子はナノサイズの電極面積を有する素子として作成されるので、当該論理回路の小型化が図られる。また、多数の論理回路により構成される集積回路の集積度を高め、その小型化を図ることができる。 Thereby, the combination pattern of the magnetization directions of the free layer and the fixed layer constituting each magnetic tunnel junction element is switched. In accordance with this, the combination pattern of the resistance values of the first type element and the second type element is switched. The logic configuration can be changed by one logic circuit of the present invention regardless of the configuration of a plurality of circuits, and each magnetic tunnel junction element is created as an element having a nano-sized electrode area. Is achieved. In addition, the degree of integration of an integrated circuit including a large number of logic circuits can be increased and the size thereof can be reduced.
　また、第２閾値以上の強さの磁界により、自由層のみならず固定層の磁化の方向が変更されうる。これにより、電流のＯＮ／ＯＦＦに応じた自由層の磁化の方向と、固定層の磁化の方向との組み合わせパターンが変更されうる。すなわち、固定層の磁化の方向が変更されることによって、元の論理回路とは異なる論理回路が構築されうる。 Also, the direction of magnetization of not only the free layer but also the fixed layer can be changed by a magnetic field having a strength equal to or greater than the second threshold. Thereby, the combination pattern of the magnetization direction of the free layer and the magnetization direction of the fixed layer according to ON / OFF of the current can be changed. That is, a logic circuit different from the original logic circuit can be constructed by changing the magnetization direction of the fixed layer.
本発明の第１実施形態としての論理回路の構成説明図。1 is a configuration explanatory diagram of a logic circuit as a first embodiment of the present invention. FIG. 本発明の第１実施形態としての論理回路の機能に関する説明図。Explanatory drawing regarding the function of the logic circuit as 1st Embodiment of this invention. 本発明の第２実施形態としての論理回路の構成説明図。FIG. 5 is a configuration explanatory diagram of a logic circuit as a second embodiment of the present invention. 本発明の第２実施形態としての論理回路の機能に関する説明図。Explanatory drawing regarding the function of the logic circuit as 2nd Embodiment of this invention. 本発明の第２実施形態としての論理回路の構成説明図。FIG. 5 is a configuration explanatory diagram of a logic circuit as a second embodiment of the present invention.
　（本発明の第１実施形態としての論理回路の構成）
　本発明の第１実施形態としての論理回路の構成が図１に模擬的に示されている。図１に示されている論理回路は、集合素子ITMRを備えている。集合素子ITMRは、負の磁気抵抗効果を奏する第１種素子TMR1と、インバース型の磁気抵抗効果を奏する第２種素子TMR2とにより構成されている。 (Configuration of Logic Circuit as First Embodiment of the Present Invention)
The configuration of the logic circuit according to the first embodiment of the present invention is schematically shown in FIG. The logic circuit shown in FIG. 1 includes a collective element ITMR. The collective element ITMR is composed of a first type element TMR1 having a negative magnetoresistance effect and a second type element TMR2 having an inverse magnetoresistance effect.
　第１種素子TMR1は厚さ数ｎｍ以下の絶縁体トンネル障壁層TL1を挟む一対の電極層としての第１自由層ML1および第１半固定層FL1により構成されている。同様に、第２種素子TMR2は厚さ数ｎｍ以下の絶縁体トンネル障壁層TL2を挟む一対の強磁性電極層として第２自由層ML2および第２半固定層FL2により構成されている。トンネル障壁層TL1およびTL2としては、酸化アルミニウム（AlOx）または酸化マグネシウム（MgO）が用いられる。 The first type element TMR1 is composed of a first free layer ML1 and a first semi-fixed layer FL1 as a pair of electrode layers sandwiching an insulator tunnel barrier layer TL1 having a thickness of several nm or less. Similarly, the second type element TMR2 is composed of a second free layer ML2 and a second semi-fixed layer FL2 as a pair of ferromagnetic electrode layers sandwiching an insulator tunnel barrier layer TL2 having a thickness of several nanometers or less. As the tunnel barrier layers TL1 and TL2, aluminum oxide (AlO x ) or magnesium oxide (MgO) is used.
　本実施形態では、第１半固定層FL1と、第２自由層ML2とが接続されることにより、第１種素子TMR1と第２種素子TMR2とが直列接続されている。このほか、第１半固定層FL1と、第２半固定層FL2とが接続される等、任意の接続形態により第１種素子TMR1と第２種素子TMR2とが直列接続されていてもよい。 In the present embodiment, the first type element TMR1 and the second type element TMR2 are connected in series by connecting the first semi-fixed layer FL1 and the second free layer ML2. In addition, the first-type element TMR1 and the second-type element TMR2 may be connected in series by any connection form, such as the first semi-fixed layer FL1 and the second semi-fixed layer FL2.
　第１自由層ML1および第２自由層ML2は、第１閾値Hc1以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体（たとえばFe）からなる。第１半固定層FL1および第２半固定層FL2は、第１閾値Hc1より大きい第２閾値Hc2以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体（たとえば，それぞれCo，Fe3O4）からなる。 The first free layer ML1 and the second free layer ML2 are made of a conductive ferromagnetic material (for example, Fe) whose magnetization direction can be reversed by a magnetic field having a strength equal to or higher than the first threshold value Hc1. The first semi-fixed layer FL1 and the second semi-fixed layer FL2 are conductive ferromagnets whose magnetization directions can be reversed by a magnetic field having a strength greater than or equal to a second threshold Hc2 greater than the first threshold Hc1 (for example, Co, Fe 3 O 4 ).
　さらに、論理回路は、第１種素子TMR1および第２種素子TMR2に加えられる磁界を形成する電流が流される導線Iqと、導線Iqに流れる電流を調節するように構成されている入力端子INと、集合素子ITMRに電圧を印加するように構成されている電圧印加要素（VDDおよびGNDの間に電位差を生じさせるように構成されている）と、集合素子ITMRに接続されている出力端子OUTとを備えている。 The logic circuit further includes a lead Iq through which a current forming a magnetic field applied to the first type element TMR1 and the second type element TMR2 flows, and an input terminal IN configured to adjust the current flowing through the lead Iq. A voltage applying element configured to apply a voltage to the collective element ITMR (configured to generate a potential difference between VDD and GND), an output terminal OUT connected to the collective element ITMR, and It has.
　入力端子INはMOS-FETにより構成されており、そのスイッチングにより導線Iqにおける電流の有無またはＯＮ／ＯＦＦが切り替えられる。導線Iqには図１の紙面に垂直な方向に電流が流れ、導線Iqを中心として時計回りまたは反時計回りの成分を有する磁界が形成される。なお、集合素子ITMRを基準として導線Iqの反対側に、当該導線Iqに直交する他の導線が設けられ、他の導線にも電流が流されている状態で、導線Iqに流される電流が調節されることにより集合素子における磁界が調節されてもよい。 The input terminal IN is composed of a MOS-FET, and the switching of the input terminal IN switches the presence / absence of current in the conducting wire Iq or ON / OFF. A current flows through the lead Iq in a direction perpendicular to the plane of FIG. 1, and a magnetic field having a clockwise or counterclockwise component around the lead Iq is formed. In addition, the other side of the conducting wire Iq is provided on the opposite side of the conducting wire Iq with respect to the collective element ITMR, and the current flowing through the conducting wire Iq is adjusted in a state where current is also flowing through the other conducting wire. By doing so, the magnetic field in the collective element may be adjusted.
　出力端子OUTは、第１種素子TMR1および第２種素子TMR2の間に接続されている。 The output terminal OUT is connected between the first type element TMR1 and the second type element TMR2.
　論理回路は、たとえばSi基板の上に、エピタキシャル成長法によって前記各層および要素が形成されたナノ人工結晶格子として製造される。 The logic circuit is manufactured, for example, as a nano artificial crystal lattice in which the layers and elements are formed on an Si substrate by an epitaxial growth method.
　（本発明の第１実施形態としての論理回路の機能）
　入力端子INがＯＦＦからＯＮに切り替えられると、導線Iqに電流が流れることにより、第１閾値Hc1以上かつ第２閾値Hc2未満の強さの磁界が集合素子ITMRにかかる。その結果、集合素子ITMRを構成する第１種素子TMR1および第２種素子TMR2のそれぞれの自由層ML1, ML2の磁化の向きが、当該磁界の方向に一致する。すなわち、自由層ML1, ML2の元の磁化方向が、磁界の方向と逆であった場合、当該磁界によって自由層ML1, ML2の磁化の向きが反転する。 (Function of Logic Circuit as First Embodiment of the Present Invention)
When the input terminal IN is switched from OFF to ON, a current flows through the conducting wire Iq, so that a magnetic field having a strength greater than or equal to the first threshold value Hc1 and less than the second threshold value Hc2 is applied to the collective element ITMR. As a result, the magnetization directions of the free layers ML1 and ML2 of the first type element TMR1 and the second type element TMR2 constituting the collective element ITMR coincide with the direction of the magnetic field. That is, when the original magnetization directions of the free layers ML1 and ML2 are opposite to the magnetic field direction, the magnetization directions of the free layers ML1 and ML2 are reversed by the magnetic field.
　さらに、たとえば、導線Iqにおける電流が増加されることにより、第２閾値Hc2未満の強さの磁界が集合素子ITMRにかかる。その結果、集合素子ITMRを構成する第１種素子TMR1および第２種素子TMR2のそれぞれの自由層ML1, ML2の磁化の向きのみならず、固定層FL1, FL2の磁化の向きが、当該磁界の方向に一致する。すなわち、固定層FL1, FL2の元の磁化の向きが、磁界の方向と逆であった場合、当該磁界によって固定層FL1, FL2の磁化の向きが反転する。 Furthermore, for example, when the current in the conducting wire Iq is increased, a magnetic field having a strength less than the second threshold value Hc2 is applied to the collective element ITMR. As a result, not only the magnetization directions of the free layers ML1 and ML2 of the first type element TMR1 and the second type element TMR2 constituting the collective element ITMR but also the magnetization directions of the fixed layers FL1 and FL2 Match the direction. That is, when the original magnetization directions of the fixed layers FL1 and FL2 are opposite to the magnetic field direction, the magnetization directions of the fixed layers FL1 and FL2 are reversed by the magnetic field.
　磁気トンネル接合素子を構成する一対の電極層の磁化の向きが平行であることを、当該磁気トンネル接合素子が「パラ状態」であると表現する。磁気トンネル接合素子を構成する一対の電極層の磁化の向きが反平行であることを、当該磁気トンネル接合素子が「アンチパラ状態」であると表現する。 That the magnetization directions of the pair of electrode layers constituting the magnetic tunnel junction element are parallel is expressed as the “para state” of the magnetic tunnel junction element. That the magnetization directions of the pair of electrode layers constituting the magnetic tunnel junction element are anti-parallel is expressed as the “anti-para state” of the magnetic tunnel junction element.
　入力端子INのＯＦＦ状態（導線Iqに電流が流れていない状態）は入力ｘが「０」である状態であると定義され、入力端子INのＯＮ状態（導線Iqに電流が流れている状態）は入力ｘが「１」である状態であると定義される。出力端子OUTの電圧が低電圧である状態は出力ｙが「０」である状態と定義され、出力端子の電圧が高電圧である状態は出力ｙが「１」である状態と定義される。 The OFF state of the input terminal IN (the state where no current flows through the conductor Iq) is defined as the state where the input x is “0”, and the ON state of the input terminal IN (a state where the current flows through the conductor Iq) Is defined as a state where the input x is “1”. A state where the voltage at the output terminal OUT is low is defined as a state where the output y is “0”, and a state where the voltage at the output terminal is high is defined as a state where the output y is “1”.
　（ＮＯＴ回路）
　磁場が印加されていない状態で第１種素子TMR1および第２種素子TMR2がパラ状態である場合、前記構成の論理回路によりＮＯＴ回路が構成される。たとえば、第２閾値Hc2以上の強さの磁界が集合素子ITMRに加えられることにより、第１種素子TMR1および第２種素子TMR2の両方がパラ状態とされうる。 (NOT circuit)
When the first type element TMR1 and the second type element TMR2 are in the para state in a state where no magnetic field is applied, a NOT circuit is configured by the logic circuit having the above configuration. For example, when a magnetic field having a strength equal to or greater than the second threshold value Hc2 is applied to the collective element ITMR, both the first-type element TMR1 and the second-type element TMR2 can be set to the para state.
　この場合、入力ｘが０であるとき、図２（ａ）に示されているように、第１種素子TMR1がパラ状態かつ低抵抗状態（斜線付）である一方、第２種素子TMR2がパラ状態かつ高抵抗状態である。一方、入力ｘが１であるとき、図２（ｂ）に示されているように、第１種素子TMR1がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR2がアンチパラ状態かつ低抵抗状態である。このため、入力ｘ＝０である場合、出力ｙ＝１となる一方、入力ｘ＝１である場合、出力ｙ＝０となる。 In this case, when the input x is 0, as shown in FIG. 2 (a), the first type element TMR1 is in the para state and the low resistance state (with diagonal lines), while the second type element TMR2 is It is a para state and a high resistance state. On the other hand, when the input x is 1, as shown in FIG. 2B, the first type element TMR1 is in the antiparasitic state and the high resistance state, while the second type element TMR2 is in the antiparasitic state and the low resistance. State. Therefore, when the input x = 0, the output y = 1, whereas when the input x = 1, the output y = 0.
　（ＮＯＴ回路の消滅）
　磁場が印加されていない状態で第１種素子TMR1および第２種素子TMR2がアンチパラ状態である場合、論理回路はＮＯＴ回路ではなくなる。たとえば、まず、第２閾値Hc2以上の磁界が集合素子ITMRに加えられることにより、第１種素子TMR1および第２種素子TMR2の両方がパラ状態とされた後、第１閾値Hc1以上かつ第２閾値Hc2未満の強さで、先とは逆向きの磁界が集合素子ITMRに加えられることにより、第１種素子TMR1および第２種素子TMR2の両方がアンチパラ状態とされうる。 (Disappearance of NOT circuit)
When the first type element TMR1 and the second type element TMR2 are in the anti-para state in the state where the magnetic field is not applied, the logic circuit is not a NOT circuit. For example, first, a magnetic field equal to or higher than the second threshold value Hc2 is applied to the collective element ITMR, so that both the first type element TMR1 and the second type element TMR2 are set to the para state, and then the first threshold value Hc1 and the second value. By applying a magnetic field in the opposite direction to the collective element ITMR with a strength less than the threshold value Hc2, both the first type element TMR1 and the second type element TMR2 can be in the anti-para state.
　この場合、入力ｘが０であるとき、図２（ｂ）に示されているように、第１種素子TMR1がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR2がアンチパラ状態かつ低抵抗状態である。一方、入力ｘが１であるとき、図２（ａ）に示されているように、第１種素子TMR1がパラ状態かつ低抵抗状態である一方、第２種素子TMR2がパラ状態かつ高抵抗状態である。このため、入力ｘ＝０である場合、出力ｙ＝０となる一方、入力ｘ＝１である場合、出力ｙ＝１となる。 In this case, when the input x is 0, as shown in FIG. 2B, the first type element TMR1 is in the antiparasitic state and the high resistance state, while the second type element TMR2 is in the antiparasitic state and low. The resistance state. On the other hand, when the input x is 1, as shown in FIG. 2A, the first type element TMR1 is in the para state and the low resistance state, while the second type element TMR2 is in the para state and the high resistance. State. Therefore, when the input x = 0, the output y = 0, whereas when the input x = 1, the output y = 1.
　（本発明の第２実施形態としての論理回路の構成）
　本発明の第２実施形態としての論理回路の構成が図３に模擬的に示されている。図３に示されている論理回路は、集合素子ITMRを備えている。集合素子ITMRは、負の磁気抵抗効果を奏する一対の第１種素子TMR11およびTMR12と、インバース型の磁気抵抗効果を奏する一対の第２種素子TMR21およびTMR22とにより構成されている。 (Configuration of Logic Circuit as Second Embodiment of the Present Invention)
The configuration of the logic circuit according to the second embodiment of the present invention is schematically shown in FIG. The logic circuit shown in FIG. 3 includes the collective element ITMR. The collective element ITMR is composed of a pair of first-type elements TMR11 and TMR12 having a negative magnetoresistance effect and a pair of second-type elements TMR21 and TMR22 having an inverse magnetoresistance effect.
　第１種素子TMR1i(i=1,2)は、第１実施形態における第１種素子TMR1と同様の構成であり、また、第２種素子TMR2i(i=1,2)は、第１実施形態における第２種素子TMR2と同様の構成なので、更なる説明を省略する。 The first type element TMR1i (i = 1, 2) has the same configuration as the first type element TMR1 in the first embodiment, and the second type element TMR2i (i = 1, 2) Since the configuration is similar to that of the second type element TMR2 in the embodiment, further description is omitted.
　本実施形態では、第１の第１自由層ML11と第２の第１自由層ML12とが接続され、かつ、第１の第１半固定層FL11と第２の第１半固定層FL12とが接続されることにより、一対の第１種素子TMR11, TMR12が並列接続されている。このほか、第１の第１自由層ML11と第２の第１半固定層FL12とが接続され、かつ、第１の第１半固定層FL11と第２の第１自由層ML12とが接続されることにより、一対の第１種素子TMR11, TMR12が並列接続されていてもよい。 In the present embodiment, the first first free layer ML11 and the second first free layer ML12 are connected, and the first first semi-fixed layer FL11 and the second first semi-fixed layer FL12 are connected. By being connected, the pair of first-type elements TMR11 and TMR12 are connected in parallel. In addition, the first first free layer ML11 and the second first semi-fixed layer FL12 are connected, and the first first semi-fixed layer FL11 and the second first free layer ML12 are connected. Thus, the pair of first-type elements TMR11 and TMR12 may be connected in parallel.
　本実施形態では、第２の第２半固定層FL22と第１の第２半固定層FL12とが接続されることにより、一対の第２種素子TMR21, TMR22が直列接続されている。このほか、第１の第２自由層ML21と第２の第２自由層ML22とが接続される等の任意の形態により、一対の第２種素子TMR21, TMR22が直列接続されていてもよい。 In the present embodiment, the second second semi-fixed layer FL22 and the first second semi-fixed layer FL12 are connected, so that the pair of second-type elements TMR21 and TMR22 are connected in series. In addition, the pair of second-type elements TMR21 and TMR22 may be connected in series by any form such as connection of the first second free layer ML21 and the second second free layer ML22.
　本実施形態では、第２の第１半固定層FL12と第２の第２自由層ML22とが接続されることにより、一対の第１種素子TMR11, TMR12と、一対の第２種素子TMR21, TMR22とが接続されている。このほか、一対の第１種素子TMR11, TMR12の接続形態および一対の第２種素子TMR21, TMR22の接続形態のうち少なくとも一方が、変更されることに応じて、さまざまな形態で一対の第１種素子TMR11, TMR12と、一対の第２種素子TMR21, TMR22とが接続されてもよい。 In the present embodiment, by connecting the second first semi-fixed layer FL12 and the second second free layer ML22, a pair of first type elements TMR11, TMR12 and a pair of second type elements TMR21, TMR22 is connected. In addition, at least one of the connection form of the pair of first type elements TMR11 and TMR12 and the connection form of the pair of second type elements TMR21 and TMR22 is changed in various forms in accordance with the change. The seed elements TMR11, TMR12 and a pair of second type elements TMR21, TMR22 may be connected.
　さらに、論理回路は、第１種素子TMR1i(i=1,2)および第２種素子TMR2iの組み合わせの対のそれぞれに加えられる磁界を形成する電流が流される一対の導線Iqiと、当該一対の導線Iqiのそれぞれの電流のＯＮ／ＯＦＦを切り替えるように構成されている一対の入力端子INiと、集合素子ITMRに電圧を印加するように構成されている電圧印加要素（VDDおよびGNDの間に電位差を生じさせるように構成されている）と、集合素子ITMRに接続されている出力端子OUTとを備えている。 Further, the logic circuit includes a pair of conductors Iqi through which a current for forming a magnetic field applied to each pair of the combination of the first type element TMR1i (i = 1, 2) and the second type element TMR2i flows, A pair of input terminals INi configured to switch ON / OFF of each current of the conducting wire Iqi, and a voltage applying element configured to apply a voltage to the collective element ITMR (potential difference between VDD and GND And an output terminal OUT connected to the collective element ITMR.
　第ｉ入力端子INiはＭＯＳ－ＦＥＴにより構成されており、そのスイッチングにより第ｉ導線Iqiにおける電流の有無またはＯＮ／ＯＦＦが切り替えられる。第ｉ導線Iqiには図３の紙面に垂直な方向に電流が流れ、第ｉ導線Iqiを中心として時計回りまたは反時計回りの成分を有する磁界が形成される。 The i-th input terminal INi is composed of a MOS-FET, and the switching of the i-th input line Iqi switches the presence / absence of current or ON / OFF. A current flows in the i-th lead Iqi in a direction perpendicular to the paper surface of FIG. 3, and a magnetic field having a clockwise or counterclockwise component around the i-th lead Iqi is formed.
　なお、集合素子ITMRを基準として導線Iqiの反対側に、当該導線Iqiに直交する他の導線が設けられ、他の導線にも電流が流されている状態で、導線Iqiに流される電流が調節されることにより集合素子における磁界が調節されてもよい。 In addition, the other side of the conducting wire Iqi is provided on the opposite side of the conducting wire Iqi with the collective element ITMR as a reference, and the current passed through the conducting wire Iqi is adjusted in a state where current is also passed through the other conducting wire. By doing so, the magnetic field in the collective element may be adjusted.
　出力端子OUTは、第１種素子TMR12および第２種素子TMR22の間に接続されている。 The output terminal OUT is connected between the first type element TMR12 and the second type element TMR22.
　論理回路は、図５に示されているように、たとえばSi基板の上に、エピタキシャル成長法によって前記各層および要素が形成されたナノ人工結晶格子として製造される。紙面に対して垂直な方向に電流が流される磁化反転用導線Ｚが必要に応じて設けられてもよい。 As shown in FIG. 5, the logic circuit is manufactured, for example, as a nano artificial crystal lattice in which each layer and element are formed on a Si substrate by an epitaxial growth method. A magnetization reversal conducting wire Z through which a current flows in a direction perpendicular to the paper surface may be provided as necessary.
　第１自由層ML11, ML12は、正スピン分極率磁性体自由層により構成され、第１半固定層FL11, FL12は、正スピン分極率磁性体半固定層により構成されている。第２自由層ML21, ML22は、負スピン分極率磁性体自由層により構成され、第２半固定層FL21, FL22は、正スピン分極率磁性体半固定層により構成されている。 The first free layers ML11 and ML12 are constituted by positive spin polarizability magnetic free layers, and the first semi-fixed layers FL11 and FL12 are constituted by positive spin polarizability magnetic semi-fixed layers. The second free layers ML21 and ML22 are constituted by negative spin polarizability magnetic free layers, and the second semi-fixed layers FL21 and FL22 are constituted by positive spin polarizability magnetic semi-fixed layers.
　（第２実施形態の論理回路の機能）
　第ｉ入力端子INiがＯＦＦからＯＮに切り替えられると、第ｉ導線Iqiに電流が流れることにより、第１閾値Hc1以上かつ第２閾値Hc2未満の強さの磁界が集合素子ITMRを構成する、第ｉの第１種素子TMR1iおよび第ｉの第２種素子TMR2iにかかる。その結果、第ｉの第１自由層ML1iおよび第ｉの第２自由層ML2iの磁化の向きが、当該磁界の方向に一致する。すなわち、自由層ML1i, ML2iの元の磁化方向が、磁界の方向と逆であった場合、当該磁界によって当該自由層ML1i, ML2iの磁化の向きが反転する。 (Function of Logic Circuit of Second Embodiment)
When the i-th input terminal INi is switched from OFF to ON, a current flows through the i-th lead Iqi, whereby a magnetic field having a strength not less than the first threshold value Hc1 and less than the second threshold value Hc2 constitutes the collective element ITMR. This is applied to the i-th type element TMR1i and the i-th type 2 element TMR2i. As a result, the magnetization directions of the i-th first free layer ML1i and the i-th second free layer ML2i coincide with the direction of the magnetic field. That is, when the original magnetization directions of the free layers ML1i and ML2i are opposite to the magnetic field directions, the magnetization directions of the free layers ML1i and ML2i are reversed by the magnetic fields.
　さらに、たとえば、第ｉ導線Iqiにおける電流が増加されることにより、第２閾値Hc2未満の強さの磁界が集合素子ITMRを構成する第ｉの第１種素子TMR1iおよび第ｉの第２種素子TMR2iにかかる。その結果、自由層ML1i, ML2iの磁化の向きのみならず、第ｉの第１半固定層FL1iおよび第ｉの第２半固定層FL2iの磁化の向きが、当該磁界の方向に一致する。すなわち、半固定層FL1i, FL2iの元の磁化の向きが、磁界の方向と逆であった場合、当該磁界によって当該半固定層FL1i, FL2iの磁化の向きが反転する。 Further, for example, when the current in the i-th lead Iqi is increased, a magnetic field having a strength less than the second threshold Hc2 causes the i-th type 1 element TMR1i and the i-th type 2 element constituting the collective element ITMR Take TMR2i. As a result, not only the magnetization directions of the free layers ML1i and ML2i but also the magnetization directions of the i-th first semi-fixed layer FL1i and the i-th second semi-fixed layer FL2i coincide with the direction of the magnetic field. That is, when the original magnetization directions of the semi-fixed layers FL1i and FL2i are opposite to the magnetic field directions, the magnetization directions of the semi-fixed layers FL1i and FL2i are reversed by the magnetic field.
　第ｉ入力端子INiのＯＦＦ状態（導線Iqiに電流が流れていない状態）は入力ｘiが「０」である状態であると定義され、第ｉ入力端子INiのＯＮ状態（第ｉ導線Iqiに電流が流れている状態）は入力ｘiが「１」である状態であると定義される。出力端子OUTの電圧が低電圧である状態は出力ｙが「０」である状態と定義され、出力端子の電圧が高電圧である状態は出力ｙが「１」である状態と定義される。 The OFF state of the i-th input terminal INi (the state in which no current flows through the conducting wire Iqi) is defined as the state where the input x i is “0”, and the ON state of the i-th input terminal INi (the i-th conducting wire Iqi) The state in which current is flowing is defined as a state in which the input x i is “1”. A state where the voltage at the output terminal OUT is low is defined as a state where the output y is “0”, and a state where the voltage at the output terminal is high is defined as a state where the output y is “1”.
　（ＮＡＮＤ回路について）
　第１種素子TMR11, TMR12側が高電位側（バイアス電圧印加側）であり、かつ、磁場が印加されていない状態で磁気トンネル接合素子TMR11, TMR12, TMR21およびTMR22がパラ状態である場合、前記構成の論理回路によりＮＡＮＤ回路が構成される。 (NAND circuit)
When the first type element TMR11, TMR12 side is a high potential side (bias voltage application side) and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in a para state in a state where no magnetic field is applied, the configuration A NAND circuit is configured by these logic circuits.
　この場合、第１入力ｘ1が０であるとき、図４（ａ）に示されているように第１種素子TMR11がパラ状態かつ低抵抗状態である一方、第２種素子TMR21がパラ状態かつ高抵抗状態である。第１入力ｘ1が１であるとき、図４（ｂ）に示されているように第１種素子TMR11がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR21がアンチパラ状態かつ低抵抗状態である。 In this case, when the first input x 1 is 0, as shown in FIG. 4A, the first type element TMR11 is in the para state and the low resistance state, while the second type element TMR21 is in the para state. And it is in a high resistance state. When the first input x 1 is 1, one first type element TMR11 as shown in FIG. 4 (b) is Anchipara state and high resistance state, the second type device TMR21 is Anchipara state and a low resistance State.
　さらに、第２入力ｘ2が０であるとき、図４（ａ）に示されているように第１種素子TMR12がパラ状態かつ低抵抗状態である一方、第２種素子TMR22がパラ状態かつ高抵抗状態である。第２入力ｘ2が１であるとき、図４（ｂ）に示されているように第１種素子TMR12がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR22がアンチパラ状態かつ低抵抗状態である。 Further, when the second input x 2 is 0, as shown in FIG. 4A, the first type element TMR12 is in the para state and the low resistance state, while the second type element TMR22 is in the para state and High resistance state. When the second input x 2 is 1, as shown in FIG. 4B, the first type element TMR12 is in the anti-para state and high resistance state, while the second type element TMR 22 is in the anti-para state and low resistance. State.
　このため、第１入力ｘ1＝０、第２入力ｘ2＝０である場合、出力ｙ＝１となる。第１入力ｘ1＝１、第２入力ｘ2＝０である場合、出力ｙ＝１となる。第１入力ｘ1＝０、第２入力ｘ2＝１である場合、出力ｙ＝１となる。第１入力ｘ1＝１、第２入力ｘ2＝１である場合、出力ｙ＝０となる。 Therefore, when the first input x 1 = 0 and the second input x 2 = 0, the output y = 1. When the first input x 1 = 1 and the second input x 2 = 0, the output y = 1. When the first input x 1 = 0 and the second input x 2 = 1, the output y = 1. When the first input x 1 = 1 and the second input x 2 = 1, the output y = 0.
　（ＡＮＤ回路について）
　第１種素子TMR11, TMR12側が低電位側（接地側）であり、かつ、磁場が印加されていない状態で磁気トンネル接合素子TMR11, TMR12, TMR21およびTMR22がパラ状態である場合、論理回路によりＡＮＤ回路が構成される。この場合、第１入力ｘ1および第２入力ｘ2に応じたトンネル接合素子TMR11, TMR12, TMR21およびTMR22のそれぞれの状態遷移態様は、ＮＡＮＤ回路と同様である（図４（ａ）（ｂ）参照）。 (About AND circuit)
When the first type element TMR11, TMR12 side is the low potential side (ground side) and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in the para state with no magnetic field applied, the logic circuit performs AND A circuit is constructed. In this case, the tunnel junction device TMR11 corresponding to the first input x 1 and the second input x 2, TMR12, TMR21 and each state transition aspects of TMR22 is similar to the NAND circuit (FIG. 4 (a) (b) reference).
　第１入力ｘ1＝０、第２入力ｘ2＝０である場合、出力ｙ＝０となる。第１入力ｘ1＝１、第２入力ｘ2＝０である場合、出力ｙ＝０となる。第１入力ｘ1＝０、第２入力ｘ2＝１である場合、出力ｙ＝０となる。第１入力ｘ1＝１、第２入力ｘ2＝１である場合、出力ｙ＝１となる。 When the first input x 1 = 0 and the second input x 2 = 0, the output y = 0. When the first input x 1 = 1 and the second input x 2 = 0, the output y = 0. When the first input x 1 = 0 and the second input x 2 = 1, the output y = 0. When the first input x 1 = 1 and the second input x 2 = 1, the output y = 1.
　（ＯＲ回路について）
　第１種素子TMR11, TMR12側が高電位側（バイアス電圧印加側）であり、かつ、磁場が印加されていない状態で磁気トンネル接合素子TMR11, TMR12, TMR21およびTMR22がアンチパラ状態である場合、論理回路によりＯＲ回路が構成される。 (About OR circuit)
When the first type element TMR11, TMR12 side is the high potential side (bias voltage application side) and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in the anti-para state with no magnetic field applied, a logic circuit Constitutes an OR circuit.
　この場合、第１入力ｘ1が０であるとき、図４（ｂ）に示されているように第１種素子TMR11がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR21がアンチパラ状態かつ低抵抗状態である。第１入力ｘ1が１であるとき、図４（ａ）に示されているように第１種素子TMR11がパラ状態かつ低抵抗状態である一方、第２種素子TMR21がパラ状態かつ高抵抗状態である。 In this case, when the first input x 1 is 0, as shown in FIG. 4B, the first type element TMR11 is in the antiparasitic state and the high resistance state, while the second type element TMR21 is in the antiparasitic state. And it is in a low resistance state. When the first input x 1 is 1, as shown in FIG. 4A, the first type element TMR11 is in the para state and the low resistance state, while the second type element TMR21 is in the para state and the high resistance. State.
　さらに、第２入力ｘ2が０であるとき、図４（ｂ）に示されているように第１種素子TMR12がアンチパラ状態かつ高抵抗状態である一方、第２種素子TMR22がアンチパラ状態かつ低抵抗状態である。第２入力ｘ2が１であるとき、図４（ａ）に示されているように第１種素子TMR12がパラ状態かつ低抵抗状態である一方、第２種素子TMR22がパラ状態かつ高抵抗状態である。 Further, when the second input x 2 is 0, as shown in FIG. 4B, the first type element TMR12 is in the antiparasitic state and the high resistance state, while the second type element TMR22 is in the antiparasitic state. Low resistance state. When the second input x 2 is 1, while the one element TMR12 as shown in FIG. 4 (a) is para state and low resistance state, the second type device TMR22 para state and high-resistance State.
　このため、第１入力ｘ1＝０、第２入力ｘ2＝０である場合、出力ｙ＝０となる。第１入力ｘ1＝１、第２入力ｘ2＝０である場合、出力ｙ＝１となる。第１入力ｘ1＝０、第２入力ｘ2＝１である場合、出力ｙ＝１となる。第１入力ｘ1＝１、第２入力ｘ2＝１である場合、出力ｙ＝１となる。 Therefore, when the first input x 1 = 0 and the second input x 2 = 0, the output y = 0. When the first input x 1 = 1 and the second input x 2 = 0, the output y = 1. When the first input x 1 = 0 and the second input x 2 = 1, the output y = 1. When the first input x 1 = 1 and the second input x 2 = 1, the output y = 1.
　（ＮＯＲ回路について）
　第１種素子TMR11, TMR12側が低電位側（接地側）であり、かつ、磁場が印加されていない状態で磁気トンネル接合素子TMR11, TMR12, TMR21およびTMR22がパラ状態である場合、論理回路によりＮＯＲ回路が構成される。この場合、第１入力ｘ1および第２入力ｘ2に応じたトンネル接合素子TMR11, TMR12, TMR21およびTMR22のそれぞれの状態遷移態様は、ＯＲ回路と同様である（図４（ａ）（ｂ）参照）。 (NOR circuit)
When the first type element TMR11, TMR12 side is the low potential side (ground side), and the magnetic tunnel junction elements TMR11, TMR12, TMR21, and TMR22 are in the para state with no magnetic field applied, the logic circuit performs NOR. A circuit is constructed. In this case, the tunnel junction device TMR11 corresponding to the first input x 1 and the second input x 2, TMR12, TMR21 and each state transition aspects of TMR22 is similar to the OR circuit (FIG. 4 (a) (b) reference).
　このため、第１入力ｘ1＝０、第２入力ｘ2＝０である場合、出力ｙ＝１となる。第１入力ｘ1＝１、第２入力ｘ2＝０である場合、出力ｙ＝１となる。第１入力ｘ1＝０、第２入力ｘ2＝１である場合、出力ｙ＝１となる。第１入力ｘ1＝１、第２入力ｘ2＝１である場合、出力ｙ＝０となる。 Therefore, when the first input x 1 = 0 and the second input x 2 = 0, the output y = 1. When the first input x 1 = 1 and the second input x 2 = 0, the output y = 1. When the first input x 1 = 0 and the second input x 2 = 1, the output y = 1. When the first input x 1 = 1 and the second input x 2 = 1, the output y = 0.
　図５に示されている論理回路において、２つのＦＥＴに接続されている導線と、磁化反転用導線（ｅ）とに電流が流され、第１種素子および第２種素子がともに上下の電極磁性体の磁化の向きが平行にされている状態について考察する。 In the logic circuit shown in FIG. 5, a current is passed through the conducting wire connected to the two FETs and the magnetization reversal conducting wire (e), and the first type element and the second type element are both upper and lower electrodes. Consider the state in which the magnetization direction of the magnetic material is parallel.
　ＶＤＤ電圧が印加され、両方のＦＥＴの入力端子ＩＮの入力が「０」に制御されている状態において、２つの第１種素子はともに導通状態「１」となる。その一方、２つの第２種素子はともに非導通状態「０」となる。これにより、出力端子ＯＵＴの出力は「１」となり、否定論理積となる。 In a state where the VDD voltage is applied and the inputs of the input terminals IN of both FETs are controlled to “0”, the two first-type elements are both in the conductive state “1”. On the other hand, the two second-type elements are both in the non-conductive state “0”. As a result, the output of the output terminal OUT becomes “1”, which is a negative logical product.
　さらに、一方の入力端子ＩＮの入力のみが「０」であっても、いずれか一方の第１種素子は導通状態となる。その一方、いずれか一方の第２種素子が非導通状態となる。これにより、出力端子ＯＵＴの出力は「１」となり、否定論理積となる。 Furthermore, even if only the input of one input terminal IN is “0”, one of the first type elements is in a conductive state. On the other hand, either one of the second-type elements is turned off. As a result, the output of the output terminal OUT becomes “1”, which is a negative logical product.
　このように、本実施形態の論理回路により、表１に示されているようなＮＡＮＤ回路の真理値表に示されている否定論理積が実現される。いずれの状態においても、論理状態を変化させるとき以外は電流が流されないので消費電力が低く抑制される。 As described above, the logical circuit of this embodiment realizes the negative logical product shown in the truth table of the NAND circuit as shown in Table 1. In any state, since no current flows except when the logic state is changed, the power consumption is suppressed to a low level.
Figure JPOXMLDOC01-appb-T000001
 　表２に示されているように、通常の上下電極の磁化の向きとしてパラ（平行）とアンチパラ（反平行）とが切り替えられ、これに代えてまたは加えて、ＶＤＤとＧＮＤとが入れ替えられることにより、ＮＡＮＤ論理回路、ＯＲ論理回路、ＡＮＤ論理回路およびＮＯＲ論理回路が相互に切り替えられうる、または、変換されうる。
Figure JPOXMLDOC01-appb-T000001
 As shown in Table 2, para (parallel) and anti-para (anti-parallel) are switched as normal magnetization directions of the upper and lower electrodes, and VDD and GND are switched instead of or in addition to this. Thus, the NAND logic circuit, the OR logic circuit, the AND logic circuit, and the NOR logic circuit can be switched to each other or converted.
Figure JPOXMLDOC01-appb-T000002
 　また、２つのＩＮによって発生する磁界が逆向きにされ、ＶＤＤとＧＮＤとが交換されることにより、ＸＯＲ回路と一致回路とが実現される。さらに、２個のＩＮが電気的に接続されることによりＮＯＴ論理回路が実現される。
Figure JPOXMLDOC01-appb-T000002
 Further, the magnetic fields generated by the two INs are reversed, and VDD and GND are exchanged, thereby realizing an XOR circuit and a coincidence circuit. Furthermore, a NOT logic circuit is realized by electrically connecting two INs.
　（本発明の論理回路の作用効果）
　本発明の論理回路によれば、次に説明するように再構築可能、かつ、入力端子を通じて導線に流れる電流の高低（ＯＮ／ＯＦＦまたは１／０）を入力信号とし、集合素子の出力端子電圧の高低を出力信号とする小型の論理回路が構成される。 (Operational effect of the logic circuit of the present invention)
According to the logic circuit of the present invention, the output terminal voltage of the collective element can be reconstructed as described below, and the level of the current (ON / OFF or 1/0) flowing through the input line through the input terminal is used as the input signal. A small logic circuit having an output signal as the output signal is configured.
　入力端子INを通じて導線Iqを流れる電流のＯＮ／ＯＦＦが切り替えられることにより、集合素子ITMRにおける磁界Hの強弱が調節され、この集合素子ITMRを構成する第１種素子TMR1および第２種素子TMR2のそれぞれの磁化状態が調節される。具体的には、第１閾値Hc1以上の強さの磁界により、自由層ML11, ML12の磁化の方向が調節される。 By switching ON / OFF of the current flowing through the conductor Iq through the input terminal IN, the strength of the magnetic field H in the collective element ITMR is adjusted, and the first type element TMR1 and the second type element TMR2 constituting the collective element ITMR are adjusted. Each magnetization state is adjusted. Specifically, the magnetization directions of the free layers ML11 and ML12 are adjusted by a magnetic field having a strength equal to or greater than the first threshold value Hc1.
　これにより、各磁気トンネル接合素子を構成する自由層ML1, ML2および半固定層FL1, FL2の磁化の方向の組み合わせパターンが切り替えられる。これに応じて、第１種素子TMR1および第２種素子TMR2のそれぞれの抵抗値の高低の組み合わせパターンが切り替えられる。各磁気トンネル接合素子はナノサイズの電極面積を有する素子として作成されるので、当該論理回路の小型化が図られる。また、多数の論理回路により構成される集積回路の集積度を高め、その小型化を図ることができる。 Thereby, the combination pattern of the magnetization directions of the free layers ML1, ML2 and semi-fixed layers FL1, FL2 constituting each magnetic tunnel junction element is switched. In accordance with this, the combination pattern of the resistance values of the first type element TMR1 and the second type element TMR2 is switched. Since each magnetic tunnel junction element is formed as an element having a nano-sized electrode area, the logic circuit can be miniaturized. In addition, the degree of integration of an integrated circuit including a large number of logic circuits can be increased and the size thereof can be reduced.
　また、第２閾値Hc2以上の強さの磁界により、自由層ML1, ML2のみならず半固定層FL1, FL2の磁化の方向が変更されうる。これにより、電流のＯＮ／ＯＦＦに応じた自由層ML1, ML2の磁化の方向と、半固定層FL1, FL2の磁化の方向との組み合わせパターンが変更されうる。すなわち、固定層の磁化の方向が変更されることによって、元の論理回路とは異なる論理回路が構築されうる。 In addition, the magnetization direction of the semi-fixed layers FL1 and FL2 as well as the free layers ML1 and 2ML2 can be changed by the magnetic field having the second threshold value Hc2 or more. As a result, the combination pattern of the magnetization directions of the free layers ML1 and ML2 and the magnetization directions of the semi-fixed layers FL1 and 2FL2 according to ON / OFF of the current can be changed. In other words, a logic circuit different from the original logic circuit can be constructed by changing the magnetization direction of the fixed layer.
　また、Ｃ－ＭＯＳを用いた論理回路は「電流」によりＯＮ／ＯＦＦが切り替えられるのに対して、本発明の論理回路は「磁場」によりＯＮ／ＯＦＦが切り替えられるという点で相違する。このため、本発明の論理回路によれば、磁化反転のために必要な電力が消費されるにしか過ぎないので、Ｃ－ＭＯＳを用いた論理回路と比較して消費電力の節約が図られる。また，Ｃ－ＭＯＳのみでは，論理構成を変えることができないが，本発明の論理回路で論理構成を変えることができる。 Also, the logic circuit using the C-MOS is switched on / off by “current”, whereas the logic circuit of the present invention is switched on / off by “magnetic field”. For this reason, according to the logic circuit of the present invention, only the power necessary for the magnetization reversal is consumed, so that the power consumption can be saved as compared with the logic circuit using the C-MOS. In addition, the logic configuration cannot be changed with only the C-MOS, but the logic configuration can be changed with the logic circuit of the present invention.

Claims (3)

  1. 　絶縁体トンネル障壁層を挟む一対の電極層としての第１自由層および第１半固定層により構成され、かつ、負の磁気抵抗効果を奏する第１種素子と、絶縁体トンネル障壁層を挟む一対の強磁性電極層として第２自由層および第２半固定層により構成され、かつ、インバース型の磁気抵抗効果を奏する第２種素子とを備え、前記第１種素子および前記第２種素子が直列接続されることにより構成されている集合素子と、
    　前記集合素子における磁場を形成するための電流が流される導線と、
    　前記導線の電流のＯＮ／ＯＦＦを切り替えるように構成されている入力端子と、
    　前記集合素子に電圧を印加するように構成されている電圧印加要素と、
    　前記第１種素子と前記第２種素子との接続箇所に接続されている出力端子とを備え、
    　前記第１自由層および前記第２自由層は、第１閾値以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体からなり、前記第１半固定層および前記第２半固定層は、前記第１閾値より大きい第２閾値以上の強さの磁界によって磁化の向きが反転可能な伝導性強磁性体からなり、
    　前記第１閾値以上かつ前記第２閾値未満の強さの磁界が前記集合素子にかけられることにより、前記第１自由層および前記第２自由層のそれぞれの磁化の向きが当該磁界の方向に一致し、前記第２閾値以上の強さの磁界が集合素子にかけられることにより、前記第１自由層および前記第２自由層のそれぞれの磁化の向きのみならず、前記第１固定層および前記第２固定層のそれぞれの磁化の向きが当該磁界の方向に一致するように構成されていることを特徴とする論理回路。     A first type element composed of a first free layer and a first semi-fixed layer as a pair of electrode layers sandwiching an insulator tunnel barrier layer and having a negative magnetoresistance effect, and a pair sandwiching the insulator tunnel barrier layer And a second type element having an inverse magnetoresistive effect, wherein the first type element and the second type element include the second free layer and the second semi-fixed layer. A collective element configured by being connected in series;
    A conducting wire through which a current for forming a magnetic field in the collective element flows;
    An input terminal configured to switch ON / OFF of the current of the conducting wire; and
    A voltage application element configured to apply a voltage to the assembly element;
    An output terminal connected to a connection point between the first type element and the second type element;
    The first free layer and the second free layer are made of a conductive ferromagnet whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a first threshold, and the first semi-fixed layer and the second semi-fixed layer. The layer is made of a conductive ferromagnetic material whose magnetization direction can be reversed by a magnetic field having a strength greater than or equal to a second threshold value greater than the first threshold value,
    By applying a magnetic field having a strength greater than or equal to the first threshold and less than the second threshold to the collective element, the magnetization directions of the first free layer and the second free layer coincide with the direction of the magnetic field. By applying a magnetic field having a strength equal to or greater than the second threshold value to the collective element, not only the respective magnetization directions of the first free layer and the second free layer, but also the first fixed layer and the second fixed layer. A logic circuit characterized in that each of the magnetization directions of the layers is configured to coincide with the direction of the magnetic field.
  2. 　請求項１記載の論理回路において、
    　前記集合素子が、並列接続されている一対の前記第１種素子と、直列接続されている一対の前記第２種素子を備え、前記一対の第１種素子のそれぞれと、前記一対の第２種素子のうち一方とが接続されることにより構成され、
    　前記第１種素子および前記第２種素子の組み合わせの対のそれぞれに加えられる磁界を形成する電流が流される一対の前記導線と、
    　前記一対の導線のそれぞれの電流のＯＮ／ＯＦＦを切り替えるように構成されている一対の前記入力端子とを備えていることを特徴とする論理回路。     The logic circuit according to claim 1, wherein
    The collective element includes a pair of the first type elements connected in parallel and a pair of the second type elements connected in series, and each of the pair of first type elements and the pair of second type elements. It is configured by connecting one of the seed elements,
    A pair of said conducting wires through which a current that forms a magnetic field applied to each of the combination of the first type element and the second type element is passed;
    A logic circuit comprising: a pair of input terminals configured to switch ON / OFF of current of each of the pair of conductive wires.
  3. 　請求項１または２のうち少なくとも１つに記載の論理回路を構成要素として備えていることを特徴とする集積回路。 An integrated circuit comprising the logic circuit according to claim 1 as a constituent element.
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US8476925B2 (en) 2010-08-01 2013-07-02 Jian-Gang (Jimmy) Zhu Magnetic switching cells and methods of making and operating same
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US8400066B1 (en) 2010-08-01 2013-03-19 Lawrence T. Pileggi Magnetic logic circuits and systems incorporating same
US8476925B2 (en) 2010-08-01 2013-07-02 Jian-Gang (Jimmy) Zhu Magnetic switching cells and methods of making and operating same
JP2015015597A (en) * 2013-07-04 2015-01-22 独立行政法人国立高等専門学校機構 Logical operation element
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