WO2011060313A1 - Burst access protocol and priority initialization of a second processor - Google Patents
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- FIG. 1 is a hardware architecture diagram of a prior art data interface between a mobile subscriber modem and a mobile television receiver chip.
- FIG. 2 is a hardware architecture diagram of two processors interfaced by a high capacity data interface that would present a communication bottleneck if all data accesses were performed in a single access mode.
- FIG. 3 is a process flow diagram of an embodiment method for communicating instructions and data between two processors using a burst access protocol according to the various embodiments.
- FIG. 4 is an example hardware architecture diagram of a data interface between a mobile subscriber modem and a UBM2 mobile television receiver chip implementing the burst access protocol of the various embodiments.
- FIG. 5 is a process flow diagram of an embodiment method for writing data from a first processor to a second processor using the burst access protocol of the various embodiments.
- FIG, 6 is a call flow diagram showing communications and processes that may be implemented in the example hardware architecture illustrated in FIG. 4 using the burst access protocol of the various embodiments.
- FIG. 7 is a process flow diagram illustrating a method for handling error messages associated with a data table write access using the burst access protocol of the various embodiments.
- FIG. 8 is a process flow diagram of another embodiment method for programming and configuring a second processor at an early point within an initialization process managed by a first processor.
- FIGs. 9A and 9B together are a process flow diagram of an example embodiment method for programming and configuring a digital signal processor within a multimedia receiver chip from a processor within a mobile station modem (MSM) chip.
- MSM mobile station modem
- FIG. 10 is a component block diagram of a mobile device suitable for use in an embodiment.
- the terms “mobile device” refers to any one or all of cellular telephones, personal data assistants (PDA's), palm-top computers, lap-top computers, wireless electronic mail receivers (e.g., the Blackberry® and Treo® devices), multimedia Internet enabled cellular telephones (e.g., the Blackberry Storm®), Global Positioning System (GPS) receivers, wireless gaming controllers, and similar personal electronic devices which include a first programmable processor, a second programmable processor coupled to the first programmable processor via a data interface circuit.
- An example mobile device is a mobile TV broadcast receiver.
- the various embodiments provide mechanisms and systems for solving communication bottlenecks that may arise between integrated circuit elements within computing devices.
- the bottleneck in data communication is due to the time required to set up a data transfer over any interfacing databus.
- SDIO Secure Digital input/output
- the Secure Digital input/output (SDIO) interface which is used in many electronic devices, can transfer large amounts of data in contiguous blocks, but requires a set up sequence that is not time-efficient for single data transfer operations.
- the relatively long access set up time of the SDIO interface means that the circuit may become a communication bottleneck in electronic devices that require real-time operations and data communications among various internal components.
- the SDIO interface is affordable, well understood in the industry, and very efficient for moving large blocks of data, its relatively slow setup process makes it unsuitable for many integrated circuits that require real time read/write operations.
- the various embodiments provide a communication protocol that can overcome communication bottlenecks in data interface circuits (e.g., the SDIO interface).
- the various embodiments enable integrated circuit implementing such a protocol to take advantage of the large block writing efficiency of such data interface circuits while compensating for their slow single access characteristics. This is accomplished by configuring and transferring data, indices, and/or instructions from a first processor to a second processor in two data tables that the second processor can use to implement instructions specified by the first processor.
- a first table is a relatively static table that is referred to herein as a "static interface table” or simply as a "static table.
- the static table is used for transferring instructions, data, register indices, and set up parameters in a large block of data that can be transmitted in advance of being use by the second processor.
- a second table used for communicating instruction sequences and frequently changing data is referred to herein as a “dynamic interface table” or simply as a “dynamic table.”
- the dynamic table is used for controlling the second processor by including information, such as individual or sequences of data tables within the static table that are to be implemented, along with dynamic data that the
- J second processor can use as a guide for executing processes stored in the static table.
- a data interface with a long setup time can be used efficiently by a first processor to control a second processor by reducing the number and frequency of a data transfers over the interface.
- An example application of the various embodiments involves an interface between a Qualcomm MediaPLO receiver chip, referred to as a UBM2 chip, and a Qualcomm Mobile Subscriber Modem (MSM) chip.
- the UBM2 chip is being coupled with an MSM chip using the SDIO interface.
- the SDIO interface can transmit large bocks of data very quickly; however, each data transfer requires set up processing that makes the interface unsuitable for frequent transmissions of real time instructions and data.
- the burst access protocol described herein may be implemented to permit the ARM (Advanced reduced instruction set computer (RISC) Machine) processor within the MSM chip to configure and control the receiver digital signal processor (RDSP) within the UBM2.
- RISC Advanced reduced instruction set computer
- FIG. 1 illustrates the hardware architecture 100 previously used for interfacing MSM chips 102 with UBM2 chips 104 using the LB 12 interface 1 10.
- an ARM core 104 within the MSM 102 executes the FLO physical layer software.
- the FLO physical layer software running on the ARM core 102 must configure the RDSP 106 with firmware instructions and the FLO hardware 108 with hardware configurations.
- the EBI2 interface was able to provide real time write transactions to enable the MSM and UBM2 chips to interface properly.
- the SDIO interface is an industry standard data exchange interface that supports two forms of data transfer, one being the single access and the other being the block or burst access.
- the disadvantage of the SDIO single access mode is that it takes a relatively long time to set up the data interface compared to that of other high speed interfaces, such as the EB12. This long access time can be attributed to the setup time involved with the SDIO access.
- the burst access mode of the SDIO interface is much faster when compared to the single (i.e.. byte) access mode because it uses the hardware direct memory access (DMA) engine to do the actual transfer.
- DMA hardware direct memory access
- the data transfer is so fast that it can perform better than the EBI2 access for large data transfers.
- there is an inherent setup cost involved in using the DMA engine which can result in diminishing to negative returns for small transactions.
- the problem with FPS software is that, currently most of the hardware accesses, especially writes, are done to non-contiguous hardware registers. Access writes to non-contiguous registers over an SDIO interface resemble single access SDIO transactions. Given the relatively long time required to complete single access transactions, many real time requirements of the FPS would break.
- burst transactions require a contiguous memory space. Since the hardware registers to be programmed for any given scenario in an FPS software configuration do not present a contiguous memor map to software, the burst access protocol of the various embodiments is used to program these random lists into contiguous blocks that can be stored in the RDSP memory and that the RDSP can parse to write particular values to the appropriate hardware registers.
- the RDSP may be used to program the FLO hardware (e.g., store appropriate data within particular registers).
- the values to be programmed in to the hardware have to come from the ARM, since the ARM executes the FPS software which determines the values that need to be programmed into particular hardware registers. If the ARM was to transfer the complete information to the RDSP regarding the registers to be programmed along with the values to be programmed, such transfer operations would be prohibitively expensive because the ARM would end up sending more data to the RDSP than it would have done for programming the hardware registers directly.
- the ARM-to-RDSP interface should allow for most of the information to be sent upfront (e.g., during power up, initialization or during a period of little activity) when there are no real-time constraints, and only send critical selection parameters to the RDSP when real time processing kicks in.
- the physical layer system hardware registers typically must be reconfigured or reprogrammed from time to time due to factors such as fine tuning, field test results, discovery of hardware limitations, etc. The biggest bottleneck in completing such reconfigurations is the effort in rewriting firmware if any of the factors mentioned above change. In other words, a firmware implementation that hard codes the hardware registers to be programmed, the sequence to be used, and possibly the values to be programmed would require a rewrite of the code at a later date.
- the burst access protocol of the various embodiments addresses these design requirements to provide a generic interface in firmware.
- This generic interface of the burst access protocol includes a static interface and a dynamic interface, as well as control and signaling interfaces.
- the static interface provides a mechanism and storage for transferring most of the data and instructions required for a firmware initialization.
- the dynamic interface provides a mechanism and storage for transferring minimum information required for programming hardware when real time requirements kick in.
- the burst access protocol also provides an interface for a first processor to generically inform a second processor of the list of hardware registers to be programmed.
- the burst access protocol also provides an interface for the first processor to generically inform the second processor of the sequence in which hardware registers should be programmed.
- the burst access protocol also provides an interface for the first processor to generically inform the second processor of the possible sets of values to program for hardware registers in a time efficient manner.
- the burst access protocol also and provides an interface for the first processor to generically inform the second processor of a delay instruction to be inserted in between hardware writes along with a value for the number of cycles to delay, These interfaces together are referred to herein as the burst access protocol.
- FIG. 2 illustrates a hardware architecture 200 for use with the burst access protocol of the various embodiments.
- a hardware architecture 200 suitable for use with the burst access protocol will typically involve a first processor 202, such as an ARM processor or processor core, that communicates data and/or instructions to a second processor 204 via a high-capacity data access circuit 206 that features an access set up process which may present a
- a first processor 202 such as an ARM processor or processor core
- the first processor 202 may need to pass configuration data, such as hardware and firmware initialization and configuration data for program registers, to the second processor 204.
- configuration data such as hardware and firmware initialization and configuration data for program registers
- the burst access protocol enables the first processor 202 to pass most of the required information regarding programming of the registers to the second processor 204 during initialization, and only pass minimum information thereafter when real-time considerations kick in.
- initialization data and instructions are transferred from the first processor 202 to the second processor 204 for storage in a static interface 208
- runtime parameters e.g., instruction sequences and data only available at runtime
- the static interface 208 ma allow the first processor 202 to send to the second processor 204 information regarding the hardware registers to be programmed, alternative programming sequences, and alternative possible sets of values to choose from for programming each hardware register.
- FIG. 2 also illustrates communications between the first and second processors 202, 204 that are part of the burst access protocol.
- the first processor 202 may communicate in signal 220 to processor 204 information (i.e., table parameters) regarding the table that is about to be transferred via the access circuit 206.
- processor 204 information i.e., table parameters
- the first processor 202 may send a signal 220 that informs the second processor 204 that the static table is about to be communicated as well as information that the second processor 204 requires two properly as received and stored in memory, such as the length of the table.
- This table parameters signal 220 may be sent via the access circuit 206 or via a different circuit between the first and second processors.
- the first processor 202 may initialize the access circuit 206, as shown in arrow 222, and then transmit the static table in a single large data transfer 224.
- the second processor receives the static table and stores it within the static interface table portion of memory 208. Later, such as during runtime, the first processor 202 may perform a similar operation to transmit the dynamic table, by sending a signal 260 to the proper second processor 204 informing it that a dynamic table is about to be transmitted along with the table parameters required for reception and storage.
- the first processor 202 may then configure the access circuit 206 (as indicated by arrow 228) and then transmit the dynamic table in message 230.
- the second processor 204 receives the dynamic table and stores it within the dynamic interface table portion of memory 210. [0027] FIG.
- an initiation process may define memory buffers for the static and dynamic interface tables at step 302.
- the first processor 202 may inform the second processor that a static table is about to be sent along with the table's parameters, step 304.
- the second processor receives this information in step 306 and prepares to receive the static table.
- the first processor 204 may initiate the data write set up sequence to configure the access circuit for transferring the static table at step 308.
- the first processor may initiate transfer of the static table to the second processor at step 310.
- the second processor 204 receives the static table at step 312, and stores the table in the static interface portion of memory coupled to the second processor at step 330.
- the first processor may conduct other operations 316 until such time that a run time
- the first processor 202 may send a message to the second processor 204 informing it that a dynamic table is about to be transmitted, along with the table parameters required for receiving and storing of the data at step 328.
- the second processor 204 receives the table properties and prepares to receive the dynamic table at step 330.
- the first processor 202 sets up the data access circuit for transferring the dynamic table at step 332, and transfers the dynamic table to the second processor at step 334.
- the second processor 204 receives the dynamic table via the access circuit at step 336, and stores the dynamic table in the dynamic access portion of memory at step 338.
- the second processor 204 implements the processes directed by the first processor by using information stored in the dynamic table to determine the sequences, data tables, or processes stored in the static table that should be executed, including the sequence in which multiple processes should be at executed, along with the data stored in the static table that should be used in the processes, such as to configure registers.
- the second processor 204 is configured with software to use information stored in the dynamic table to perform operations and configure registers using information in the static table as if the first processor were transferring information to the second processor in a sequence of single access operations.
- the burst access protocol may be implemented using a variety of interrupts and message resources that are shared between the first and second processors to support transferring data from one to the other. Such interrupts and shared resources will depend upon the status registers included within the first and second processors or the functional chips in which the first and second processors reside. To provide an example of such interrupts and shared resources, the following description refers to the MSM-to-UBM2 architecture 400 illustrated in FIG. 4.
- the MSM-to-UBM2 architecture 400 includes an MSM chip 402 which features an ARM core 404, operating the FLO physical layer software, that sends configuration instructions to the RDSP 408 within the UBM2 via an SDIO interface 410.
- the ARM core 404 may configure the SDIO interface in message 420 using the bus access layer.
- the ARM core 404 may configure the RDSP 408 and necessary RDSP dependencies.
- the ARM core 404 may download the firmware and configuration parameters in the static table for storage within the RDSP memory.
- the ARM core 404 may download the dynamic table providing the RDSP 408 with all of the necessary runtime parameters.
- the RDSP 408 may then run the firmware using the dynamic table to determine the information from the static table necessary to program the FLO hardware 428.
- the UBM2 hardware 406 includes a dedicated bit in the interrupt status register to identify an interrupt fired by the RDSP 408.
- the interrupt status register to identify an interrupt fired by the RDSP 408.
- floSWCmdResponse RDSP register may be used to distinguish between various RDSP interrupts.
- the RDSP driver which is maintained on the ARM processor 404, may include a mechanism (on the ARM) to generate a software interrupt to the RDSP 408.
- the floSWCmd RDSP register is used by the RDSP 408 to identify the type of interrupt fired by the ARM 404.
- Table 1 describes ARM interface interrupts that may be implemented with the burst access protocol in the architecture illustrated in FIG. 4.
- RDSP_to_micro_irq RDSP This interrupt is fired by RDSP to the ARM
- ARM when it has completed all of its processing.
- ARM When ARM receives this interrupt it reads the RDSP command response register (floSWCmdResponse) to determine which command was completed by the DSP.
- micro Jo rDSP cmdJrq ARM This interrupt is fired by ARM when it has a
- the command ready for the RDSP to process.
- the command would be set by ARM in the floSWCommand register, which the RDSP would fetch to determine which command it needs to process.
- the static and dynamic interfaces of the burst access protocol enable the ARM 404 to transmit hardware writes to the RDSP 408 for programming of the UBM2 hardware using the burst access capabilities of the SDIO interface 410.
- the static interface may be an open buffer of length 2000 in MEMC (32 bit) RDSP memory, although larger or smaller buffers may be utilized.
- This memory may be packed by the ARM 408 with consecutive tables in a specific format. Each table may contain a list of hardware registers in sequence that are tied together by a common criteria that selects a specific value from a range of possible values for that given register, e.g., FFT-CP combinations.
- a given configuration scenario requires a certain set of hardware registers tied to a certain criteria (e.g., setl) to be programmed in a particular sequence followed by another (e.g., set2), and so on until setN.
- the static interface programming could be accomplished by packing and programming table 1 followed by table2 and so on until tableN, and storing the tables in sequence within the static interface memory buffer.
- the RDSP 408 would only need to be informed of the start address of the burst access protocol array and its total size. All information regarding the burst access protocol tables may be maintained by
- a register interface for enabling the ARM 404 to program the burst access protocol static interface table may be those values listed Table 2 in below.
- Table 2 DSP - ARM Register Interface for Static BAP Table Programming
- the software executing within the ARM 404 may determine the appropriate set of values to be programmed into hardware of the UBM2 406. Since the various possible data sets already exists in the static table within the RDSP memory, all that the ARM 404 needs to inform the RDSP 408 of is which indexes to use in each table within the static interface table. Since the number of tables within the static interface table programmed by ARM 404 is dynamic (i.e., the ARM 404 can specify as many tables as necessary in the static interface as long as the tables fit within the 2000 long memory allocation provided by the RDSP 408).
- the number of indices to be provided to access the static tables may be dynamic as well.
- the burst access protocol provides a very flexible programming capability.
- the dynamic interface may be designed to allow up to 50 indices, although this number can be changed as needed.
- FLO_bapTransactionTableOffsetsArray locations one new reserved table offset may be introduced to address the configurable delays required between hardware writes.
- the ARM 404 can use this special offset to indicate to the firmware that it requires special delay processing. When using this special offset, the corresponding index value set in
- FLO_bapTransactionStaticTableIndicesArray will indicate the delay value.
- a register interface for enabling the ARM 404 to program the burst access protocol static dynamic table may be those values listed Table 3 in below.
- Table 1 S DSP - Arm register interface for dynamic BAP programming
- Steps that may be taken to make use of the burst access protocol for programming burst non-conducive hardware registers may involve the following.
- memory may need to be allocated for the static and dynamic interfaces, and registers for first processor to access interface locations may need to be declared and exported.
- Additional software command codes may be required for the first processor to use to interrupt the second processor and notify it of pending hardware writes for the burst access protocol.
- Command parsing logic may be added to detect burst access protocol commands and invoke the burst access protocol based hardware programming module.
- Top level burst access protocol parsing logic may be added that can parse the burst access protocol dynamic interface packet and invoke hardware programmer logic for each table.
- Generic hardware programmer logic may be added that can program hardware registers generically given a pointer to a static table (e.g., a table within the static interface table) and an index to use for that table.
- Task completion logic may be added that can fire the appropriate interrupt to the first processor upon completion of programming in the second processor.
- Test framework may be added to test and debug the generic programmer.
- Logging support may be added if needed to capture the algorithm sequence and/or results.
- the following provides an outline of steps that may be taken on the software side for implementing a burst access protocol. Identify the list of registers, sequence of programming and values to program. Create tables based on the information gathered from system team that conform to the static interface. Identify programming sequences in existing software-hardware interactions, where the hardware programming through the second processor needs to be accomplished. Add logic to determine the index to be used to select the appropriate values in each table based on different operating modes and any other criteria that form the indices into the tables. Interlace required time delays using the reserved table offset along with the delay values as indices. Pack the computed indices into the dynamic interface as described above.
- FIG. 5 illustrates an example method 500 for the ARM 404 to program the RDSP 408 to configure single wire serial bus interface (SSBI) registers.
- the ARM 404 software may transmit the static table to the RDSP 408 including the SSBI configuration table.
- the ARM 404 may inform the RDSP 408 using a burst access protocol dynamic interface packet about the details of the SSBI configuration table.
- the RDSP 408 may use the information in the static table to write data into the SSBI registers.
- the RDSP may poll an SSBI write status register for every write operation.
- FIG. 6 illustrates an example of call flows that may be implemented in the architecture illustrated in FIG. 4 using the burst access protocol.
- the ARM 404 may send a message 602 to the RDSP 408 informing it of the properties of a static table that is about the transmitted.
- the ARM 404 may download the static table to the RDSP 408 which stores the table in the static interface buffer portion of memory.
- the ARM 404 may send message 606 to the RDSP 408 informing it that the dynamic table is about to be transmitted, including table properties required for the RDSP to receive the dynamic table. Thereafter, the ARM 404 may download the dynamic table to the RDSP 408 in message 608.
- the ARM 404 may generate an interrupt 610 to the RDSP 408 to cause it to implement the programming defined in the dynamic and static interface tables.
- the RDSP 408 may respond to this interrupt by an appropriate RDSP interrupt handler 612.
- the RDSP 408 may then implement a burst access protocol header parser 614, and determine whether the burst access protocol input parameters are valid in processes 616. If the burst access protocol parameters are invalid, process 618 may generate an error interrupt 620 that is transmitted to the ARM 404.
- process 622 may initiate an operations loop 624 that loops through each of the static tables according to the sequence defined in the dynamic table to program data stored in the static table into indicated registers of the FEO hardware 428 in a series of write operations 626.
- the RDSP 408 may send an interrupt 628 to the ARM 404 to inform it that the programming has been successful.
- FIG, 7 illustrates an example method 700 that may be implemented in the architecture illustrated in FIG. 4 for programming FLO hardware 428 using the burst access protocol.
- a register or variable e.g., the "floSWCmdResponse” value
- the RDSP 408 may fire an interrupt at step 716 to inform the ARM 404 that it should check the success/failure register or value, before ending the process at step 718.
- the RDSP may execute the processes of step 712 to loop through each of the indicated tables in the static table and program the hardware 428 registers using the appropriate indices and data specified in the static table. Once all of the hardware registers have been properly program in step 712, the RDSP 408 may store a value to a register or variable (e.g., the
- RDSP 408 may fire an interrupt at step 716 to inform the ARM 404 that it should check the success/failure register or value, before ending the process at step 718.
- control processor e.g., the ARM 404
- the second processor e.g., the RJDSP 408
- This embodiment enables the second processor to begin performing operations early in the initialization sequence.
- Providing a second processor operating during the initialization sequence can increase the number of operations that can be performed in a short amount of time and add additional functionality that can be leveraged during the initialization sequence.
- One application for this early initialization of the second processor is the burst access protocol of the
- the first processor configures the second processor sufficient to enable the second processor to receive the static table as one of the first operations in the initialization sequence.
- first processor typically configures all of the registers and programming of system hardware prior to finishing the programming and configuration of the second processor.
- Such a conventional approach enables the first processor to control all the configuration and initialization steps before the second processor begins operation.
- FIG. 8 illustrates an example method 800 for initializing the second processor as an early operation within the initialization sequence.
- the first processor 202 begins the initialization sequence.
- the first processor 202 loads registers associated with the second processor 204 and accomplishes any other programming of the second processor 204 to enable the second processor to begin operations.
- the second processor receives such programming.
- the first processor 202 sends a command or other signal to the second processor 204 because it to begin operations.
- the second processor receives the activation command, and at step 814, begins operations according to its programming. The first processor 202 may then continue with other
- initialization sequence processes 812 such as transmitting the static and dynamic tables of the burst access protocol to the second processor as described above with reference to FIG. 3.
- the second processor 204 may perform operations, such as receiving the static and dynamic tables of the burst access protocol to the second processor as described above with reference to FIG, 3. 10048]
- Methods for activating a second processor as an early process within an initialization retain may be described by way of a particular example which is illustrated in FIG. 9A and 9B.
- MediaFLO chips such as the UBM2 chip
- the process of bringing up the chip's RDSP processor at the earliest convenient time can provide operational benefits. This is primarily because, various hardware programming tasks can be off loaded to the RDSP.
- Drivers for broadcast technologies like MediaFLO (e.g., DVBH) program the receiver hardware in a sequence block by block from the hardware.
- This block by block programming is intended to ensure that any inter-dependencies within the hardware are taken care of while programming the hardware.
- Conventional approaches for configuring hardware in the MediaFLO chips have programmed the RDSP at the last step of the Initialization Sequence. This conventional approach makes the RDSP available so late in the power up sequence that the functionality of the RDSP is not fully utilized. In some cases, activating the RDSP as a last step in the initialization sequence results in the processor missing time critical functions that could have been accomplished with the help of RDS if that processor had been programmed earlier on.
- RDSP RDSP
- An illustrative example of a process that the RDSP can support is the Hardware Initialization at Power up. This process involves a catch22 situation, in that the RDSP need to be up and running before ARM processor within the MSM can download tables used in the burst access protocol described herein. However, for the Power up case, the ARM processor needs to initialize the RDSP before it can transfer the static and dynamic tables to the RDSP.
- the conventional power up hardware initialization of the MFLO Drivers enables a number of blocks and registers before the ARM processor downloads the RDSP Firmware image. This conventional approach poses problems for burst access protocol when the static and dynamic tables are transferred via anSDIO interface.
- This embodiment provides a mechanism for fine tuning the necessary blocks and a special way of configuring them so that the RDSP can be programmed at the earliest possible time, enabling the RDSP to be initialized early and in an efficient manner.
- the following example identifies the hardware blocks that are needed, and a mechanism for programming these hardware blocks, providing for the necessary settling time, downloading the RDSP firmware image, and activating the RDSP.
- the ARM processor may disable the MediaFLO UBM2 chip interrupt service routines.
- the ARM processor may turn on the general purpose input/output pins between the MSM chip in the UBM2 chip. Configuring these input/output pins puts the UBM chip out of the reset state.
- the ARM processor may set up the voltage regulators for the MediaFLO devices. This is an optional step based upon the physical layer characteristics of the underlying radio receiver hardware.
- the ARM processor may test to confirm that the UBM2 chip is powered down, and wait 300 ⁇ at step 10.
- the ARM processor may configured the UBM2 mode control pins which configure the UBM2 to support underlying bus types.
- the ARM processor may topple the MBP reset pin and wait 20 ms.
- step 916 the ARM processor may perform a UBM chip detection algorithm to confirm that the software can detect the UBM2 chip.
- the ARM processor may program the phase locked loops (PLL) for given radio frequency characteristics and bandwidth considerations, and programmed the clock control registers.
- the ARM processor may also wait 50 ⁇ 8 for the PLLs to settle down.
- the ARM processor may enable the RDSP to be driven by its core clock instead of the TLL clock.
- the ARM processor may also enable the RDSP clock divider.
- the ARM processor may program the top level logic (TLL) with various parameters, including the EBI2 parameters, and 10 at noon settings, and the TCXO control registers.
- the ARM processor may reset the sleep controller block, and program the block with initial values.
- the ARM processor may also reset the SSBl block, called the logic enable, and all of the relevant system clocks.
- the ARM processor may initialize new clocks. In the example of the UBM2 chip, such new clocks may include: a
- the ARM processor may download the RDSP firmware image to the RDSP and initiate processing of the firmware. This step may involve setting the RDSP clocks, downloading the DSP firmware image, and activating the DSP firmware image.
- mfrxd.hw_state MFRXD_HW_INITIALIZING
- mfrxd.hw_ state MFRXD_HW_UNINITIALIZED;
- the embodiment of configuring the second processor as an early operation within an initialization sequence is not limited to the burst access protocol. While the burst access protocol represents a useful application of this invention, the invention may also be useful in electronic devices in which the second processor can perform other operations. Another use case for this embodiment is where the UBM chip can be leveraged to use its RJDSP to out source other functionality. This additional functionality that can be out sourced may or may not be related to MediaFLO operations.
- a Media FLO mobile receiver 1000 suitable for use with the various embodiments will have in common the components illustrated in FIG. 10.
- a Media FLO mobile receiver 1000 may include a MSM chip 1001 that includes a first processor 1002 (e.g., an ARM processor 404) coupled to internal memory 1004.
- a Media FLO mobile receiver 1000 may further include a mobile broadcast receiver 1006, which includes a second processor 1007 (e.g., an RDSP 408).
- the first processor 1002 and the second processor 1007 may connected to a data interface 1008, such as an SDK) access bus.
- the Media FLO mobile receiver 1000 may have an antenna 1014 for sending and receiving electromagnetic radiation that is connected to the MSM 1001 and to the mobile broadcast receiver 1006.
- the MSM 1001 may be coupled to a display 1003 for displaying video images, and to a speaker 1019 for generating sound.
- a Media FLO mobile receiver 1000 may also include a key pad 1016 or miniature keyboard and menu selection buttons or rocker switches 1017 for receiving user inputs.
- the processors 1002, 1007 may be any programmable microprocessor, microcomputer or multiple processor chip or chips that can be configured by software instructions (applications) to perform a variety of functions, including the functions of the various embodiments described herein. In some mobile devices, multiple processors 1002, 1007 may be provided, such as one processor dedicated to wireless communication functions and one processor dedicated to running other applications. Typically, software applications may be stored in the internal memory 1004 before they are accessed and loaded into the processor 1002, 1007. In some implementations, the processors 1002, 1007 may include internal memory sufficient to store the application software instructions and data tables (e.g., the static and dynamic interface tables). For the purposes of this description, a general reference to memory refers to all memory accessible by the processors 1002, 1007, including internal memory 1004, removable memory plugged into the device or server (not shown), and memory within the processors 1002, 1007 themselves.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- a general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any combination thereof designed to perform the functions described herein.
- a general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any combination thereof designed to perform the functions described herein.
- a general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any combination thereof designed to perform the functions described herein.
- a general-purpose processor may be a microprocessor, but, in the alternative, the processor may be any combination thereof designed to perform the functions described herein.
- the processor may be any combination thereof designed to perform the functions described herein.
- a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some steps or methods may be performed by circuitry that is specific to a given function.
- the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
- the steps of a method or algorithm disclosed herein may be embodied in a processor-executable software module executed which may reside on a computer- readable medium.
- Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
- a storage media may be any available media that may be accessed by a computer.
- such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessed by a computer.
- any connection is properly termed a computer-readable medium.
- the software is transmitted from a website, serv er, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL. or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.
- Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combinat ion or set of codes and/or instructions on a machine readable medium and/or computer-readable medium, which may be incorporated into a computer program product.
Abstract
Description
Claims
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KR1020127015204A KR101368543B1 (en) | 2009-11-13 | 2010-11-12 | Burst access protocol and priority initialization of a second processor |
CN201080050302.XA CN102640138B (en) | 2009-11-13 | 2010-11-12 | Burst access protocol and priority initialization of a second processor |
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US26113309P | 2009-11-13 | 2009-11-13 | |
US61/261,133 | 2009-11-13 | ||
US12/887,206 US8639852B2 (en) | 2009-11-13 | 2010-09-21 | Burst access protocol |
US12/887,206 | 2010-09-21 | ||
US12/887,196 US8938609B2 (en) | 2009-11-13 | 2010-09-21 | Methods and apparatus for priority initialization of a second processor |
US12/887,196 | 2010-09-21 |
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CN103988191A (en) * | 2011-12-22 | 2014-08-13 | 英特尔公司 | Sideband initialization |
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