WO2011052112A1

WO2011052112A1 - System clock monitoring device, and motor control system

Info

Publication number: WO2011052112A1
Application number: PCT/JP2010/003807
Authority: WO
Inventors: 田中聖浩; 木元勝斗; 藤阪孝誠; 今村勝幸
Original assignee: パナソニック株式会社
Priority date: 2009-10-29
Filing date: 2010-06-08
Publication date: 2011-05-05

Abstract

A clock anomaly detection unit determines whether or not the frequency of each of the input clocks which constitute the N system input clock group is normal, and generates an anomaly detection signal. A clock determination unit identifies the clock with an abnormal frequency on the basis of the anomaly detection signal, determines whether or not said clock is being employed by the system at that moment as the system clock, and, once it is determined that said clock is employed as the system clock, generates a clock switching signal for identifying an input clock other than the clock with the abnormal frequency. A clock switching unit selects an input clock other than the clock with the abnormal frequency on the basis of the clock switching signal, and delivers the input clock thus selected to the system as the system clock.

Description

System clock monitoring device and motor control system

The present invention relates to a system clock monitoring device that is mounted on a system driven by a system clock and monitors a frequency abnormality of the system clock, and more particularly as a countermeasure when a frequency abnormality occurs in an input clock. The present invention relates to a technology for making it compatible. The present invention also relates to a motor control system equipped with such a system clock monitoring device. In particular, the present invention relates to a technology for improving product stability of an information processing apparatus such as a semiconductor integrated circuit.

As a system clock monitoring device of the prior art, a monitoring clock of a system different from the system clock that drives the system is prepared, and the number of pulses of the system clock is counted within a certain period (monitoring cycle) defined by this monitoring clock In addition, there is known one that determines an abnormal frequency of the system clock by comparing this with an expected value (number of pulses corresponding to normal operation) (see, for example, Patent Document 1).

FIG. 15 is a block diagram showing the configuration of a system clock monitoring device in the prior art. The CPU and peripheral circuit 91 operate using the system clock CK11 as a clock source. The monitoring clock CK12 is a clock of a different system from the system clock CK11. The count unit 92 receives the system clock CK11 and the monitoring clock CK12. The count unit 92 counts the number of pulses PN11 of the system clock CK11 in the monitoring period defined by the monitoring clock CK12. The comparison unit 94 compares the number of pulses PN11 of the system clock CK11 output from the count unit 92 with the expected value Ex11 read from the storage unit 93, and an abnormality detection signal Sa indicating a frequency abnormality when the comparison result does not match. Is output to the CPU and peripheral circuit 91. Upon receiving the abnormality detection signal Sa, the CPU and the peripheral circuit 91 perform a predetermined safe operation.

16 and 17 are timing charts showing the operation of the system clock monitoring device of FIG. First, the normal system clock monitoring operation will be described with reference to FIG. The monitoring operation involves a pulse number count of the system clock CK11 and an expected value comparison. When the monitoring operation is turned on, the pulse of the system clock CK11 is counted nine times within one cycle period of the monitoring clock CK12. This pulse number PN11 (= 9) is compared with the expected value Ex11 (= 9). Since the comparison results are the same at the normal time, the abnormality detection signal Sa is not output and the normal operation is continued.

Next, the operation at the time of abnormality will be described with reference to FIG. It is assumed that the frequency of the system clock CK11 is unexpectedly decreased due to some cause in the middle of the monitoring cycle (timing t21). Here, it is assumed that the pulse of the system clock CK11 is counted five times within one cycle period of the monitoring clock CK12. This pulse number PN11 (= 5) is compared with the expected value Ex11 (= 9). Since the comparison result does not match at the time of abnormality, the abnormality detection signal Sa is output. In response to the abnormality detection signal Sa, the CPU and the peripheral circuit 91 bring the system to a safe state by stopping or waiting.

JP-A-4-326410

It is more preferable to take a quick transition to a safe state without stopping or waiting for the system as a countermeasure when a system abnormality is detected. In the configuration having two clocks, that is, the system clock CK11 and the monitoring clock CK12, frequency anomalies rarely occur in both clocks. Therefore, in order to promptly shift to a safe state without stopping or waiting for the system, it is conceivable to reset one of the safe clocks as the system clock.

However, in the configuration of the above prior art, when a frequency abnormality occurs in the monitoring clock CK12, even if the system clock CK11 is normal, it is detected as a clock abnormality. As a result, the system cannot be kept safe when an abnormality is detected.

In a configuration having two input clocks, if one is a monitoring target input clock and the other is a monitoring clock, if a frequency abnormality occurs in the monitoring target input clock, it will naturally cause a system clock frequency abnormality. Connected. On the other hand, when a frequency abnormality occurs in the monitoring input clock, the comparison reference itself is out of order, so that even if the monitoring target input clock is normal, it is determined as a frequency abnormality. It will be.

The present invention was created in view of such circumstances, and can exhibit a more flexible function as a countermeasure when a frequency abnormality occurs in the input clock, making the system clock frequency normal maintenance more dynamic. The purpose is to do.

The present invention solves the above problems by taking the following measures.

(1) The basic idea of the present invention is that at least three or more input clocks are used instead of the two clocks of the system clock and the monitoring clock in the case of the prior art, and the input clock group is selected from the group of input clocks. A normal input clock is always adopted as a system clock by selecting a normal frequency input clock. Here, the number of systems of the input clock is N (N is a natural number of 3 or more).

The system clock monitoring device according to the present invention has three components having the following functions: a clock abnormality detection unit, a clock determination unit, and a clock switching unit. The clock abnormality detection unit detects abnormality in frequency of each input clock included in the N system input clock groups where N is a natural number of 3 or more, and detects abnormality for identifying the input clock in which the frequency abnormality has occurred. Generate a signal.

The clock determination unit determines a frequency abnormal clock included in the input clock group based on the abnormality detection signal, and determines whether the specified frequency abnormal clock is currently adopted as a system clock in the system. If it is determined that the frequency abnormal clock is adopted as the system clock, a clock switching signal for specifying an input clock other than the frequency abnormal clock included in the input clock group is generated.

The clock switching unit selects an input clock other than the frequency abnormal clock from the input clock group based on the clock switching signal and supplies the selected clock to the system as the system clock.

The probability (probability) that two or more of the N system input clocks simultaneously cause frequency abnormality is low. Even when a certain input clock (s) has a frequency abnormality, there is a high possibility (probability) that the remaining input clocks are normal. As a comparative example, consider a configuration in which only two input clocks are provided, one of which serves as a monitoring target input clock and the other serves as a monitoring clock. In the comparative example, if a frequency abnormality occurs in the monitored input clock, it naturally leads to a system clock frequency abnormality, and if a frequency abnormality occurs in the monitoring input clock, the comparison reference itself Therefore, even if the input clock to be monitored is normal, it is determined that the frequency is abnormal as a result.

Compared to the possibility of the state of the comparative example described above (a state in which a frequency abnormality occurs in both input clocks) occurring, there is a sufficiently low possibility that a frequency abnormality will occur simultaneously in two or more of the input clocks. it is conceivable that. The present invention utilizes such a phenomenon.

Ｎ Prepare N input clocks (N ≧ 3) and select one of them as a system clock when it is normal, and monitor the N input clocks constantly in the clock error detection unit. When detecting that a frequency abnormality has occurred in any of the input clocks, the clock abnormality detection unit generates an abnormality detection signal and outputs it to the clock determination unit. The clock determination unit that has received the abnormality detection signal identifies the frequency abnormality clock and then determines whether or not the identified frequency abnormality clock is an input clock that is currently being employed. If it is determined that the frequency abnormal clock is an input clock that is currently being used, the clock determination unit regards that there is a possibility of system abnormality if this state is left as it is, and the normal frequency input clock (specifically, A clock switching signal for specifying an input clock other than the frequency abnormal clock included in the input clock group is generated. The clock switching unit that has received the clock switching signal replaces the currently used input clock according to the instruction content of the clock switching signal, and maintains other normal frequencies from the N input clocks that are being input. An input clock (specifically, an input clock other than the frequency abnormal clock) is selected and output as a system clock.

In the present invention, when an abnormal frequency of the input clock is detected, the abnormal frequency clock is specified in the N input clock groups, and it is determined whether or not the abnormal frequency clock is currently being adopted as the system clock. If it is determined that the system clock is being used, the system clock is switched from the N system input clocks to the input clock selection at the normal frequency. Sex is secured.

(2) Here, in the configuration of (1) above, the configuration of the lower level of the clock abnormality detection unit is examined. It is assumed that the clock abnormality detection unit includes an N-system count unit and an N-system comparison / determination unit. Each counting unit takes in two input clocks out of the N system input clocks, sets one of the input clocks as a monitoring target clock, and sets the other as a monitoring clock, and with a monitoring cycle defined by the monitoring clock. The number of pulses of the monitoring target clock is counted and sent to the corresponding comparison / determination unit. The comparison / determination unit determines frequency abnormality by comparing the number of pulses of the input clock to be monitored with an expected value (number of pulses corresponding to normal operation).

Suppose that N count units have different combinations of input clocks. Incidentally, in the case of three systems, the three system input clocks are represented by first to third input clocks CK1, CK2, and CK3, and the three system count units are referred to as first to third count units. The system comparison / determination unit is referred to as first to third comparison / determination units. In such an aspect, the first count unit is supplied with the first and third input clocks CK1 and CK3, and the second count unit is supplied with the second and first input clocks CK2 and CK1. The third count unit is supplied with third and second input clocks CK3 and CK2. That is, the supply form of the input clock is cyclic (cyclic). The first count unit counts the number of pulses PN1 of the first input clock CK1 with reference to the duty cycle of the third input clock CK3, and supplies the count result to the first comparison / determination unit. The second count unit counts the number of pulses PN2 of the second input clock CK2 with reference to the duty cycle of the first input clock CK1, and supplies the count result to the second comparison / determination unit. The third count unit counts the number of pulses PN3 of the third input clock CK3 with reference to the duty cycle of the second input clock CK2, and supplies the count result to the third comparison determination unit. In the first comparison / determination unit, the pulse number PN1 of the first count unit is compared with the expected value Ex1, and if it is different, the abnormality detection signal Sa1 is activated. In the second comparison / determination unit, the pulse number PN2 of the second count unit is compared with the expected value Ex2, and if they are different, the abnormality detection signal Sa2 is activated. In the third comparison / determination unit, the pulse number PN3 of the third count unit is compared with the expected value Ex3, and if it is different, the abnormality detection signal Sa3 is activated.

The clock determination unit is one of the first to third input clocks CK1, CK2, and CK3 having three frequency abnormality clocks based on the combination logic of the three abnormality detection signals Sa1, Sa2, and Sa3. Further, it is determined whether or not the specified frequency abnormal clock is an input clock currently being employed. If it is determined that the identified frequency abnormal clock is an input clock that is currently being employed, the clock determination unit generates a clock switching signal and supplies the generated clock switching signal to the clock switching unit. The clock switching signal instructs switching to selection of an input clock having a normal frequency from among three system input clocks as a system clock.

The combination logic of the three systems of abnormality detection signals Sa1, Sa2, Sa3 will be described with reference to FIG.

[1] As shown in FIG. 1A, it is assumed that a frequency abnormality has occurred in the first input clock CK1. In this case, since the pulse number PN1 of the first input clock CK1 is different from the expected value Ex1, the abnormality detection signal Sa1 becomes “H”. If the frequency of the first input clock CK1 is abnormal, the second input clock CK2 using the first input clock CK1 as a duty cycle reference is also pulsed even if the second input clock CK2 itself is not abnormal in frequency. The number PN2 is different from the expected value Ex2, and the abnormality detection signal Sa2 becomes “H”. If the third input clock CK3 and the second input clock CK2 are normal frequencies, the abnormality detection signal Sa3 is “L” for the third input clock CK3. Here, the logic “H” means active, and the logic “L” means inactive. The combination logic of the abnormality detection signals Sa1, Sa2, Sa3 is [HHL], and this combination logic [HHL] means that a frequency abnormality has occurred in the first input clock CK1. When the clock determination unit detects the combinational logic [HHL], the clock determination unit specifies that the input clock causing the frequency abnormality is the first input clock CK1.

[2] Next, as shown in FIG. 1B, it is assumed that a frequency abnormality has occurred in the second input clock CK2. In this case, since the pulse number PN2 of the second input clock CK2 is different from the expected value Ex2, the abnormality detection signal Sa2 becomes “H”. If the frequency of the second input clock CK2 is abnormal, the number of pulses PN3 of the third input clock CK3 using the second input clock CK2 as a reference for the duty cycle causes a frequency abnormality even in the third input clock CK3 itself. Even if not, it will be different from the expected value Ex3, and the abnormality detection signal Sa3 becomes "H". If the first and third input clocks CK1 and CK3 have normal frequencies, the abnormality detection signal Sa1 in the first input clock CK1 is “L”. Therefore, the combination logic of the abnormality detection signals Sa1, Sa2, Sa3 in this case is [LHH], and this combination logic [LHH] means that a frequency abnormality has occurred in the second input clock CK2. When the clock determination unit detects the combinational logic [LHH], the clock determination unit specifies that the input clock causing the frequency abnormality is the second input clock CK2.

[3] Next, as shown in FIG. 1C, it is assumed that a frequency abnormality has occurred in the third input clock CK3. In this case, since the pulse number PN3 of the third input clock CK3 is different from the expected value Ex3, the abnormality detection signal Sa3 becomes “H”. If the frequency of the third input clock CK3 is abnormal, the number of pulses PN1 of the first input clock CK1 based on the duty cycle of the third input clock CK3 causes the frequency abnormality in the first input clock CK1 itself. Even if not, it will be different from the expected value Ex1, and the abnormality detection signal Sa1 becomes "H". If the second and first input clocks CK2 and CK1 have normal frequencies, the abnormality detection signal Sa2 in the second input clock CK2 is “L”. Therefore, the combination logic of the abnormality detection signals Sa1, Sa2, Sa3 in this case is [HLH], and this combination logic [HLH] means that a frequency abnormality has occurred in the third input clock CK3. When detecting the combinational logic [HLH], the clock determination unit specifies that the input clock causing the frequency abnormality is the third input clock CK3.

If the input clock currently used as the system clock in the state where the frequency abnormality occurs in the first input clock CK1 of [1] is the second input clock CK2 or the third input clock CK3, The clock determination unit does not need to activate the clock switching signal. However, if the currently used input clock is the first input clock CK1, the clock determination unit activates the clock switching signal Sc. The active clock switching signal Sc in this state serves as an instruction content that the third input clock CK3 or the second input clock CK2 should be selected as the system clock.

Similarly, if the input clock currently used as the system clock is the third input clock CK3 or the first input clock CK1 in the state where the frequency abnormality has occurred in the second input clock CK2 in [2] above. The clock determination unit 50 does not need to activate the clock switching signal Sc. However, when the currently used input clock is the second input clock CK2, the clock determination unit activates the clock switching signal Sc. The active clock switching signal Sc in this state serves as an instruction content that the first input clock CK1 or the third input clock CK3 should be selected as the system clock.

Similarly, when the frequency of the third input clock CK3 in [3] is abnormal and the input clock currently used as the system clock is the first input clock CK1 or the second input clock CK2. The clock determination unit does not need to activate the clock switching signal Sc. However, if the currently used input clock is the third input clock CK3, the clock determination unit activates the clock switching signal Sc. The active clock switching signal Sc in this state is an instruction content that the second input clock CK2 or the first input clock CK1 should be selected as the system clock.

The above description is for the case where there are three input clocks, but in general, the same logic as described above can be used for N input clocks. Therefore, here, it is only mentioned that the input clock capturing mode is cyclic, that is, cyclic sampling with periodic exchange, and a detailed description is omitted.

According to this aspect, even if a frequency abnormality occurs in any of the N system input clocks used as the source of the system clock, this does not immediately cause a system clock frequency abnormality, and the frequency abnormality can be dealt with. Can afford. Furthermore, even if a frequency abnormality that leads to a system clock frequency abnormality has occurred in the input clock, the input clock is automatically switched to another input clock having a normal frequency, so that the normal state of the frequency in the system clock is restored. Maintained to ensure system stability.

Suppose that a frequency abnormality has occurred in the first input clock CK1 as described in FIG. 1A, and the system clock CKo has been switched to the third input clock CK3. In this state, it is assumed that although the first input clock CK1 has returned to the normal frequency, a frequency abnormality has occurred in the third input clock CK3 as shown in FIG. In this state, the system clock CKo is switched to the second input clock CK2. Further, in this state, it is assumed that although the third input clock CK3 has returned to the normal frequency, a frequency abnormality has occurred in the second input clock CK2 as shown in FIG. In this state, the system clock CKo is switched to the first input clock CK1. As described above, it is possible to flexibly cope with the occurrence of frequency abnormality in the input clock, and to dynamically maintain the normal frequency of the system clock.

According to the present invention, when an abnormal frequency of the input clock is detected, it is specified which input clock is the abnormal frequency input clock. If the input clock is currently employed, the normal frequency is input as the system clock. Since switching to the clock selection is performed, the entire system is not affected by the clock frequency abnormality, and the stability of the system can be ensured.

FIG. 1 is an explanatory diagram of combinational logic of three systems of abnormality detection signals in the system clock monitoring apparatus of the present invention. FIG. 2 is a block diagram showing the configuration of the system clock monitoring apparatus according to Embodiment 1 of the present invention. FIG. 3 is a block diagram showing a configuration of the clock abnormality detection unit in the first embodiment of the present invention. FIG. 4 shows an operation waveform (part 1) when the system clock monitoring apparatus according to the first embodiment of the present invention is normal. FIG. 5 shows normal operation waveforms (part 2) of the system clock monitoring apparatus according to the first embodiment of the present invention. FIG. 6 is an operation waveform (part 1) when an abnormality is detected in the system clock monitoring apparatus according to the first embodiment of the present invention. FIG. 7 is an operation waveform (part 2) when an abnormality is detected in the system clock monitoring apparatus according to the first embodiment of the present invention. FIG. 8 is a block diagram showing the configuration of the system clock monitoring apparatus according to Embodiment 2 of the present invention. FIG. 9 is an operation waveform (part 1) when an abnormality is detected in the system clock monitoring apparatus according to the second embodiment of the present invention. FIG. 10 is an operation waveform (part 2) when the system clock monitoring device according to the second embodiment of the present invention detects an abnormality. FIG. 11 is a block diagram showing a configuration of the system clock monitoring apparatus according to Embodiment 3 of the present invention. FIG. 12 is a block diagram showing a configuration of a motor control system according to Embodiment 4 of the present invention. FIG. 13 shows operation waveforms at the normal time of the motor control terminal of the inverter control microcomputer according to the fourth embodiment of the present invention. FIG. 14 is an operation waveform when abnormality is detected in the motor control terminal of the inverter control microcomputer according to the fourth embodiment of the present invention. FIG. 15 is a block diagram showing a configuration of a conventional system clock monitoring apparatus. FIG. 16 shows operation waveforms of the conventional system clock monitoring apparatus when it is normal. FIG. 17 shows operation waveforms when an abnormality is detected in the conventional system clock monitoring apparatus.

The system clock monitoring apparatus according to the present invention having the configurations (1) and (2) described in the above [Means for Solving the Problems] can be further advantageously developed in the following embodiments. Is possible.

(3) In the configurations of (1) and (2) above, there is no particular question about the magnitude (high or low) relationship of the frequencies for the N input clocks. Here, a system clock monitoring device in the case where N input clocks have different frequencies will be considered.

In order to take in N input clocks having different frequencies and generate a system clock based on the input clocks, a frequency optimization unit is further provided in the configuration of the present invention. In this aspect, the frequency optimization unit is configured to generate N optimized clock groups by changing the frequency of each of the N input clocks to the same frequency. In the case of the configurations (1) and (2), the clock switching unit is supplied with the N input clocks. In this embodiment, instead of receiving the N input clocks, The system is configured to switch the optimized clock to be used as the system clock based on the clock switching signal from the clock determination unit after receiving the N optimized clock groups.

In short, such an aspect is one aspect in the above configurations (1) and (2), and the aspect is
A frequency optimizing unit that changes the frequency of each of the input clocks to the same frequency to generate N optimized clock groups;
The clock switching unit is supplied with the optimized clock group instead of the input clock, and the clock switching unit converts the optimized clock generated based on an input clock other than the frequency abnormal clock to the clock switching Selecting from the optimized clock group based on a signal and supplying the system clock as the system clock;
It has the configuration.

According to this aspect, since the optimized clocks that are the basis of the system clock all have the same frequency, a stable switching operation is hardly affected even by a minute time before and after switching and is hardly affected by frequency fluctuations. Can be realized.

(4) In the configurations (1) to (3) above, the N system input clocks are those generated outside the apparatus. In this configuration, it is necessary to provide N clock generation circuits outside the apparatus, which increases the cost burden. In contrast, here, it is considered to use one input clock generated from an AC power supply.

As a simple clock generation unit, there is one configured to generate a zero cross clock whose logic is inverted at the timing when a zero cross point crossing the zero level of the AC voltage from the AC power source is detected. In the present invention, there is an aspect further including a clock generation unit having such a configuration. In this configuration, the zero cross clock is supplied to the clock switching unit or the frequency optimization unit so as to be a system clock selection candidate, and further supplied to the clock abnormality detection unit in order to detect a frequency abnormality. The clock anomaly detection unit is configured to monitor frequency anomalies of a total of N input clocks including (N-1) input clocks and zero cross clocks.

In short, this aspect further includes a clock generation unit that generates a zero cross clock by detecting a zero cross point of an AC voltage supplied from the outside in the present invention,
At least one input clock constituting the input clock group is the zero cross clock.

According to this aspect, by using the zero cross clock for frequency abnormality determination, the clock generation circuit outside the apparatus can be reduced, and a cost reduction effect can be expected.

Furthermore, the motor control system according to the present invention includes:
The system clock monitoring device of the present invention,
The system is a motor;
When the system clock monitoring device detects the occurrence of a clock frequency abnormality, the motor is controlled to a safe state.

In this specification, each component of the clock abnormality detection unit, the count unit, the comparison determination unit, the clock determination unit, and the clock switching unit is configured by hardware, or by individual steps or routines in software. Also good. Or you may comprise by the combination of hardware and software.

Hereinafter, an embodiment of a system clock monitoring apparatus according to the present invention will be described in detail with reference to the drawings. The embodiment described below is merely an example, and various modifications can be made.

(Embodiment 1)
A first embodiment of the present invention will be described with reference to FIGS. FIG. 2 shows a configuration of a system clock monitoring apparatus 100 having three (N = 3) clocks.

The system clock monitoring device 100 includes a clock abnormality detection unit 20, a clock determination unit 50, and a clock switching unit 70.

The clock abnormality detection unit 20 takes in an input clock group composed of three systems of first to third input clocks CK1 to CK3, and determines whether there is a frequency abnormality in the first to third input clocks CK1 to CK3. . Further, the clock abnormality detection unit 20 outputs an abnormality detection signal Sa to the clock determination unit 50 when detecting a frequency abnormality of at least one input clock in the input clock group.

When the clock determination unit 50 receives the abnormality detection signal Sa from the clock abnormality detection unit 20, the clock determination unit 50 specifies the input clocks CK1 to CK3 in which the frequency abnormality has occurred based on the abnormality detection signal Sa. Further, the clock determination unit 50 determines whether or not the identified input clock in the abnormal frequency state is an input clock that is currently being employed. If the clock determination unit 50 determines that the input clock is currently being employed, the clock determination unit 50 generates a clock switching signal Sc Output to the switching unit 70. The clock switching signal Sc is a control signal instructing to select an input clock having a normal frequency as the system clock from the first to third input clocks CK1 to CK3.

The clock switching unit 70 selects the normal frequency input clock CKx from the first to third input clocks CK1 to CK3 in accordance with the instruction of the clock switching signal Sc, and outputs the selected input clock CKx as the system clock CKo. . The clock switching unit 70 is configured not to select (delay) the first to third input clocks CK1 to CK3 until the determination result of the clock determination unit 50 is obtained. Therefore, even when the input clock is switched, the system clock CKo can continue to output a normal frequency without being affected by the abnormal input clock.

FIG. 3 is an example of a circuit configuration of the clock abnormality detection unit 20. The clock abnormality detection unit 20 includes three (first to third) counting units 21 to 23, three (first to third) comparison / determination units 31 to 33, and a storage unit 40. Prepare.

The first count unit 21 measures the number of pulses of the first input clock CK1 during a period in which pulses in the third input clock CK3 are counted a predetermined number of times (hereinafter referred to as a third monitoring cycle). Furthermore, the first count unit 21 counts the number of pulses of the first input clock CK1 at the end of the third monitoring period (when the specified number of pulses of the third input clock CK3 is counted) (hereinafter, the number of pulses PN1). Output).

The second count unit 22 measures the number of pulses of the second input clock CK2 during a period in which the pulses in the first input clock CK1 are counted a predetermined number of times (hereinafter referred to as a first monitoring cycle). Further, the second count unit 22 counts the number of pulses of the second input clock CK2 at the end of the second monitoring period (when the specified number of pulses of the first input clock CK3 is counted) (hereinafter, the number of pulses PN2). Output).

The third counting unit 23 measures the number of pulses of the third input clock CK3 in a period during which the pulses in the second input clock CK2 are counted a predetermined number of times (hereinafter referred to as a second monitoring cycle). Further, the third count unit 23 counts the number of pulses of the third input clock CK3 at the end of the second monitoring period (when the specified number of pulses of the second input clock CK2 is counted) (hereinafter, the number of pulses PN3). Output).

The storage unit 40 stores expected values Ex1 to Ex3. The expected values Ex1 to Ex3 are expected values for the pulse numbers PN1 to PN3 of the first to third count units 21 to 23, and specifically, the first to third count units 21 to 23 during normal operation. The number of pulses corresponding to the count result of 23.

The first comparison / determination unit 31 is configured to compare the pulse number PN1 from the count unit 21 with the expected value Ex1 and to output an abnormality detection signal Sa1 when the comparison results do not match. Similarly, the second comparison / determination unit 32 is configured to compare the number of pulses PN2 from the count unit 22 with the expected value Ex2 and to output an abnormality detection signal Sa2 when the comparison results do not match. Similarly, the third comparison determination unit 33 is configured to compare the number of pulses PN3 from the count unit 23 with the expected value Ex3, and output the abnormality detection signal Sa3 when the comparison results do not match. A set of three abnormality detection signals Sa1 to Sa3 corresponds to the abnormality detection signal Sa in FIG.

FIG. 4 is a timing chart showing the operation of the first to third count units 21 to 23 and the first to third comparison determination units 31 to 33 when the frequencies of the first to third clocks CK1 to CK3 are normal. It is a chart. The comparison results between the number of pulses PN1 and the expected value Ex1 in the first comparison / determination unit 31 match. Therefore, the abnormality detection signal Sa1 remains inactive. The comparison result between the number of pulses PN2 and the expected value Ex2 in the second comparison / determination unit 32 also matches. Therefore, the abnormality detection signal Sa2 remains inactive. The comparison result between the number of pulses PN3 and the expected value Ex3 in the third comparison determination unit 33 also matches. Therefore, the abnormality detection signal Sa3 remains inactive.

FIG. 5 is a timing chart showing operations of the clock determination unit 50 and the clock switching unit 70 corresponding to the state of FIG. Here, it is assumed that the clock switching unit 70 selects the first clock CK1, and the first clock CK1 is output as the system clock CKo. Since the abnormality detection signals Sa1 to Sa3 do not change, the system clock CKo continues to output the first clock CK1.

(A) State in which frequency abnormality has occurred in first input clock CK1 FIG. 6 shows first to third counting units 21 to 23 in a state in which frequency abnormality has occurred in first input clock CK1, 10 is a timing chart showing operations of first to third comparison determination units 31 to 33. The first comparison / determination unit 31 monitors the number of pulses PN1 of the first clock CK1 based on the specified number of counts of the third input clock CK3. In this state, the number of pulses PN1 and the expected value Ex1 are different. Upon detecting this, the first comparison / determination unit 31 sets the abnormality detection signal Sa1 to the abnormality detection output state. Specifically, the abnormality detection signal Sa1 is changed to active.

In the second comparison / determination unit 32 that monitors the number of pulses PN2 of the second input clock CK2 with reference to the specified number of counts of the first input clock CK1, the monitoring period based on the first input clock CK1 Since the fluctuation itself, the pulse number PN2 fluctuates. As a result, the pulse number PN2 does not match the expected value Ex2. Upon detecting this, the second comparison / determination unit 32 sets the abnormality detection signal Sa2 to the abnormality detection output state. Specifically, the abnormality detection signal Sa2 is changed to active. However, in this state, no frequency abnormality has occurred in the second input clock CK2 itself.

In the third comparison / determination unit 33 that monitors the number of pulses PN3 of the third input clock CK3 with reference to the specified number of counts of the second input clock CK2, the second and third input clocks CK2 and CK3 are Since both are normal, the abnormality detection signal Sa3 remains inactive.

This state corresponds to the state shown in FIG. 1A in which the combinational logic of the abnormality detection signals Sa1, Sa2, and Sa3 is [HHL], and this is a frequency abnormality occurring in the first input clock CK1. Means.

FIG. 7 shows the operation of the first to third count units 21 to 23, the clock determination unit 50, and the first to third clock switching units 70 in a state where the frequency abnormality occurs in the first input clock CK1. It is a timing chart which shows. The clock determination unit 50 comprehensively determines the abnormality detection signals Sa1 to Sa3 and determines that a frequency abnormality has occurred in the first clock CK1. Based on this determination, the clock determination unit 50 selects to change from the first clock CK1 having an abnormal frequency to the normal third input clock CK3, and changes the output information of the clock switching signal Sc from “1” to “ Switch to 3 ”. The clock switching unit 70 switches the system clock CKo from the first clock CK1 to the third input clock CK3 based on the output information of the clock switching signal Sc. At this time, the first to third input clocks CK1 to CK3 input to the clock switching unit 70 are delayed in advance until the determination result of the clock determination unit 50 is obtained, and the first input clock CK1 is output by the clock switching unit 70. Even when switching from 3 to the third input clock CK3, the system clock CKo can continue to output a normal frequency without being affected by the abnormal input clock.

In the state where the first input clock CK1 is selected as the system clock CKo, when a frequency abnormality occurs in the second input clock CK2 and when a frequency abnormality occurs in the third input clock CK3, The clock switching signal Sc does not become active, and the selection state of the system clock CKo does not change.

(B) State in which frequency abnormality has occurred in second input clock CK2 Although a timing chart is omitted, in a state in which second input clock CK2 is selected as system clock CKo, second input clock CK2 is When a frequency abnormality occurs, the abnormality detection signal Sa2 is active in the second comparison / determination unit 32 that monitors the number of pulses PN2 of the second clock CK2 based on the specified number of counts of the first clock CK1. become. In the third comparison / determination unit 33 that monitors the number of pulses PN3 of the third input clock CK3 on the basis of the specified number of counts of the second clock CK2, the monitoring cycle itself based on the second input clock CK2 is the same. As a result, the pulse number PN3 fluctuates and the pulse number PN3 does not coincide with the expected value Ex3. Therefore, the abnormality detection signal Sa3 becomes active. However, the third input clock CK3 itself is not abnormal in frequency.

In the first comparison / determination unit 31 that monitors the number of pulses PN1 of the first clock CK1 on the basis of the specified number of counts of the third input clock CK3, the input clocks CK3 and CK1 are both normal, so that an abnormality is detected. Signal Sa1 remains inactive.

This state corresponds to the state (b) of FIG. 1 in which the combination logic [LHH] of the abnormality detection signals Sa1, Sa2 and Sa3 is obtained, which means that a frequency abnormality has occurred in the second input clock CK2. To do. The clock determination unit 50 that has detected this selects to change from the second clock CK2 having an abnormal frequency to the normal first clock CK1. Specifically, the clock determination unit 50 switches the output information of the clock switching signal Sc from “2” to “1”. The clock switching unit 70 switches the system clock CKo from the second clock CK2 to the first clock CK1 based on the output information of the clock switching signal Sc.

In the state where the second input clock CK2 is selected as the system clock CKo, when a frequency abnormality occurs in the third input clock CK3 and when a frequency abnormality occurs in the first input clock CK1, The clock switching signal Sc does not become active, and the selection state of the system clock CKo does not change.

(C) State in which frequency abnormality has occurred in the third input clock CK3 Although the timing chart is omitted, in the state in which the third input clock CK3 is selected as the system clock CKo, the third input clock CK3 is When the frequency abnormality occurs, the third comparison / determination unit 33 that monitors the number of pulses PN3 of the third input clock CK3 based on the specified number of counts of the second clock CK2 activates the abnormality detection signal Sa3. To. The first comparison / determination unit 31 that monitors the number of pulses PN1 of the first clock CK1 with reference to the specified number of counts of the third input clock CK3 is the monitoring period itself based on the third input clock CK3. Fluctuates, the number of pulses PN1 fluctuates. As a result, the number of pulses PN1 does not match the expected value Ex1. The first comparison / determination unit 31 that has detected this changes the abnormality detection signal Sa1 to be active. However, there is no frequency abnormality in the first input clock CK1 itself.

In the second comparison / determination unit 32 that monitors the number of pulses PN2 of the second clock CK2 with reference to the specified number of counts of the first clock CK1, the input clocks CK1 and CK2 are both normal, so an abnormality detection signal Sa2 remains inactive.

This state corresponds to the case of FIG. 1C in which the combination logic of the abnormality detection signals Sa1, Sa2 and Sa3 is [HLH], and means that a frequency abnormality has occurred in the third input clock CK3. To do. The clock determination unit 50 that has detected this selects to change from the third input clock CK3 having an abnormal frequency to the normal second clock CK2. Specifically, the clock determination unit 50 switches the output information of the clock switching signal Sc from “3” to “2”. The clock switching unit 70 switches the system clock CKo from the third input clock CK3 to the second clock CK2 based on the output information of the clock switching signal Sc.

In the state where the third input clock CK3 is selected as the system clock CKo, when a frequency abnormality occurs in the first input clock CK1 and when a frequency abnormality occurs in the second input clock CK2, The clock switching signal Sc does not become active, and the selection state of the system clock CKo does not change. In addition, the above (a), (b), and (c) can be flexibly switched to dynamically maintain the normal frequency of the system clock.

As described above, according to the present embodiment, when the system clock monitoring device detects a clock frequency abnormality, it determines the input clock that is operating normally, and the system clock can be used even when the input clock frequency is abnormal. By switching to the input clock that is operating normally, the effect of ensuring the stability of the system can be obtained without affecting the entire system due to the abnormal clock frequency.

Note that the same effect as described above can be expected for inputs of N = 4 or more systems.

(Embodiment 2)
In the first embodiment, the three input clocks CK1, CK2, and CK3 have the same frequency, but in the second embodiment of the present invention, the three input clocks CK1, CK2, and CK3 have different frequencies. The present invention relates to a system clock monitoring device.

FIG. 8 is a block diagram showing a configuration of the system clock monitoring apparatus 200 according to the second embodiment of the present invention. In FIG. 8, the same reference numerals as those in FIG. 2 of the first embodiment indicate the same components, and thus detailed description thereof is omitted. A configuration unique to the present embodiment is that a frequency optimization unit 60 is added. The frequency optimizing unit 60 generates optimized clocks CC1 to CC3 having the same frequency set in advance by dividing or multiplying the three input clocks CK1 to CK3 as source clocks, and the generated optimized clocks. CC 1 to CC 3 are configured to be input to the clock switching unit 70. The clock switching unit 70 selects one of the optimized clocks CC1 to CC3 based on the clock switching signal Sc from the clock determination unit 50, and outputs the selected clock as the system clock CKo. Substantially the same as in the first embodiment.

The optimized clocks CC1 to CC3 input to the clock switching unit 70 are configured to be delayed in advance until the determination result of the clock determining unit 50 is obtained. The clock switching unit 70 switches the optimized clocks CC1 to CC3. Even in this case, the system clock CKo can continue to output a normal frequency without being affected by the abnormal input clock. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

FIG. 9 is a timing chart showing the operation when the first input clock CK1 causes a frequency abnormality. The first input clock CK1 has the lowest frequency, then the third input clock CK3 has the highest frequency, and the second input clock CK2 has the highest frequency. The clock abnormality detection unit 20 has the same function as that of the first embodiment, and the abnormality detection signals Sa1 to Sa3 are the same as the abnormality detection signal Sa of FIG.

In this case, since the frequency of the first input clock CK1 is abnormal, the number of pulses PN1 is different from the expected value Ex1. Upon detecting this, the first comparison / determination unit 31 sets the abnormality detection signal Sa1 to the abnormality detection state. Specifically, the abnormality detection signal Sa1 is changed to active.

Since the monitoring cycle itself based on the first input clock CK1 varies, the number of pulses PN2 varies in the second comparison / determination unit 32. As a result, the number of pulses PN2 does not match the expected value Ex2. The second comparison / determination unit 32 that has detected this causes the abnormality detection signal Sa2 to be in an abnormality detection state. Specifically, the abnormality detection signal Sa2 is changed to active. However, in this state, no frequency abnormality has occurred in the second input clock CK2 itself. In the third comparison / determination unit 33, since the second to third input clocks CK2 and CK3 are both normal, the abnormality detection signal Sa3 remains inactive.

FIG. 10 is a timing chart showing the operations of the clock determination unit 50 and the clock switching unit 70 when the first input clock CK1 causes a frequency abnormality. Based on the abnormality detection signals Sa1 to Sa3, the clock determination unit 50 determines whether an abnormality has occurred in the frequency of the first input clock CK1. The clock determination unit 50 that has confirmed that an abnormality has occurred in the frequency of the first input clock CK1 uses the output (system clock CKo) of the clock switching unit 70 as the first optimized clock CC1 in which an abnormality has occurred in the frequency. To change to the third optimized clock CC3 having a normal frequency. Based on this selection, the clock determination unit 50 switches the output information of the clock switching signal Sc from “1” to “3”. Based on the clock switching signal Sc supplied from the clock determination unit 50, the clock switching unit 70 switches the system clock CKo from the first optimized clock CC1 to the third optimized clock CC3. At this time, the optimized clocks CC1 to CC3 input to the clock switching unit 70 are delayed in advance until the determination result of the clock determination unit 50 is obtained, and the clock switching unit 70 outputs the output from the first optimized clock CC1. Even when the optimization clock CC3 is switched to 3, the system clock CKo (output of the clock switching unit 70) can continue to output a normal frequency without being affected by the abnormal input clock.

According to the present embodiment, since the optimization clocks CC1 to CC3 that are the inputs of the system clock CKo all have the same frequency, there is no need to be aware of frequency fluctuations even within a minute time before and after switching.

With the configuration as described above, when the system clock monitoring device detects a clock frequency abnormality, the input clock is determined, and the system clock operates normally even when an abnormality occurs in the frequency of the input clock. By switching to the optimized clock, the entire system is not affected by the abnormal clock frequency. Furthermore, since the system clock is switched in a minute time, there is no need to be aware of the influence of frequency fluctuations before and after switching. As described above, high stability of the system can be ensured.

Other operations are the same as those in the first embodiment, and a description thereof will be omitted. Note that the present embodiment can be expected to have the same effect as that of the first embodiment for inputs of N = 4 systems or more.

(Embodiment 3)
Embodiment 3 of the present invention is characterized in that a part of the input clock is an input clock generated from an AC voltage. FIG. 11 is a block diagram showing a configuration of the system clock monitoring apparatus 300 according to the third embodiment of the present invention. In FIG. 11, the same reference numerals as those in FIG. 8 of the second embodiment indicate the same components, and detailed description thereof will be omitted. A configuration unique to the present embodiment is that a clock generator 10 is added. The clock generator 10 receives the AC voltage Va from the AC power supply 400, generates a zero-cross clock CKz whose logic is inverted at the timing when a zero-cross point crossing the zero level of the AC voltage Va is detected, and the clock abnormality detector 20 It is configured to output to. The clock abnormality detection unit 20 is configured to receive the first input clock CK1, the second input clock CK2, and the zero cross clock CKz from the clock generation unit 10 and monitor the frequency abnormality of these three clocks. Has been. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

The clock abnormality detection unit 20 outputs the abnormality detection signal Sa when detecting the frequency abnormality of the first and second input clocks CK1 and CK2 or the zero cross clock CKz. Based on the abnormality detection signal Sa, the clock determination unit 50 identifies the clock that has caused the frequency abnormality, and further outputs the clock switching signal Sc that suggests a normal clock based on the identification of the clock that has caused the frequency abnormality. The frequency optimization unit 60 receives the first and second input clocks CK1 and CK2 and the zero cross clock CKz. The frequency optimizing unit 60 generates the optimized clocks CC1 to CC3 by using the supplied clocks CK1, CK2, and CKz as source clocks and dividing or multiplying the source clocks to the same preset frequency. The generated optimization clocks CC1 to CC3 all have the same frequency. The clock switching unit 70 selects an arbitrary clock from the optimized clocks CC1 to CC3 based on the clock switching signal Sc, and outputs the selected clock as the system clock CKo.

At this time, the optimized clocks CC1 to CC3 connected to the clock switching unit 70 are configured to be delayed in advance until the determination result of the clock determining unit 50 is obtained. Even when CC3 is switched, the system clock CKo can continue to output a normal frequency without being affected by the abnormal input clock. The operation of the present embodiment is the same as that of the second embodiment only in the input clock source.

In the configuration of the present embodiment, by using the zero cross clock CKz for frequency abnormality determination, it is possible to reduce the clock generation circuit outside the apparatus and to expect a cost reduction effect.

(Embodiment 4)
The present embodiment relates to a motor control system. FIG. 12 is a block diagram showing the configuration of a motor control system that is widely used in industrial and household appliance applications. In FIG. 12, 81 is an AC power supply, 82 is a converter circuit, 83 is an inverter circuit, 84 is a switching element (IGBT element) constituting the

inverter circuit

83, and 85 is a microcomputer for inverter control. Yes, 86 is a three-phase motor. IGBT (Insulated Gate Bipolar Transistor) is an insulated gate bipolar transistor.

The inverter control microcomputer 85 is equipped with the system clock monitoring device A having any one of the configurations of the first to third embodiments, and controls the three-phase motor 86. The converter circuit 82 converts the AC power supply 81 into a DC power supply, and supplies the converted DC power supply to the inverter circuit 83. The switching element 84 in the inverter circuit 83 has six output terminals [U-phase output (U1, U2), V-phase output (V1, V2), W-phase output (W1, W2)] of the inverter control microcomputer 85. Based on the control, the current control of the three-phase motor 86 is performed to control the rotation direction and the rotation speed of the three-phase motor 86.

FIG. 13 is a timing chart showing the operation of each output terminal of the inverter control microcomputer 85 in a normal state. The U-phase output (U1, U2), the V-phase output (V1, V2), and the W-phase output (W1, W2) each have a pair of outputs, and both the + side and − side switching elements 84 are active (control signal) Does not become H). This is because if both the + side and − side switching elements 84 become active, a through current flows through the entire system, which may destroy the system.

FIG. 14 is a timing chart showing the operation of each output terminal of the inverter control microcomputer 85 and the abnormality detection signal Sa at the time of abnormality. When an abnormality occurs in the command control of the inverter control microcomputer 85 due to an abnormality in the clock frequency, and there is a section in which both U-phase outputs (U1, U2) are active, a through current is generated. In order to eliminate such a problem, the present embodiment operates as follows. That is, the system clock monitoring device A mounted on the inverter control microcomputer 85 outputs an abnormality detection signal Sa to the clock determination unit 50 when detecting an abnormality in the clock frequency. The clock determination unit 50 that has received the abnormality detection signal Sa switches the system clock to a clock having a normal frequency, and forcibly changes the six output terminals of the inverter control microcomputer 85 to a safe state. Thereby, generation | occurrence | production of a through current can be prevented.

As described above, according to this embodiment, the inverter control can be continued safely and the system clock monitoring device can be effectively used in the inverter control system of the three-phase motor.

Note that the present invention is not limited to the above-described embodiment, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention.

Although Embodiments 1 to 4 have been described so far, these embodiments are merely examples, and it goes without saying that various modifications are possible.

In addition, although several embodiment and embodiment were described in the above, you may combine each component in several embodiment and embodiment arbitrarily in the range which does not deviate from the meaning of this invention.

The system clock monitoring device of the present invention is widely useful in fields where safety of semiconductor products is required because it can constantly monitor the system clock that is the backbone of the system.

DESCRIPTION OF SYMBOLS 10 Clock generation part 20 Clock abnormality detection part 21-23 Count part 31-33 Comparison determination part 40 Memory | storage part 50 Clock determination part 60 Frequency optimization part 70 Clock switching part 81 AC power supply 82 Converter circuit 83 Inverter circuit 84 Switching element (IGBT) element)
85 Inverter control microcomputer 86 Three-

phase motor

100, 200, 300 System clock monitoring device 400 AC power supply A System clock monitoring device CK1 to CK3 Input clock CKz Zero cross clock CKo System clock CC1 to CC3 Optimization clock Ex1 to Ex3 Expected value PN1 ~ PN3 Number of pulses Sa Abnormality detection signal Sa1 ~ Sa3 Abnormality detection signal Sc Clock switching signal Va AC voltage U1 U phase output +
U2 U phase output-
V1 V phase output +
V2 V phase output-
W1 W phase output +
W2 W phase output-

Claims

A clock abnormality that generates an abnormality detection signal for determining an input clock in which a frequency abnormality has occurred by determining whether or not there is a frequency abnormality in each of the input clocks included in the N system input clock groups in which N is a natural number of 3 or more A detection unit;
The frequency abnormal clock included in the input clock group is specified based on the abnormality detection signal, and then it is determined whether the specified frequency abnormal clock is currently used as a system clock in the system, and the frequency abnormal clock When determining that a clock is employed as the system clock, a clock determination unit that generates a clock switching signal for specifying an input clock other than the frequency abnormal clock included in the input clock group;
A clock switching unit that selects an input clock other than the frequency abnormal clock from the input clock group based on the clock switching signal and supplies the selected clock to the system as the system clock;
A system clock monitoring device comprising:
The clock abnormality detection unit includes an N system count unit and an N system comparison determination unit,
The counting unit takes two input clocks from the input clock group, sets one of the input clocks to be a monitoring target clock, and sets the other as a monitoring clock, and has a monitoring cycle defined by the monitoring clock. It is configured to count the number of pulses of the monitoring target clock,
The comparison determination unit is configured to compare the number of pulses counted by the counting unit with an expected value and generate the abnormality detection signal when the comparison result indicates a mismatch.
The system clock monitoring device according to claim 1.
The counting unit cyclically collects the two input clocks by periodically replacing the two input clocks,
The system clock monitoring device according to claim 2.
A frequency optimizing unit that changes the frequency of each of the input clocks to the same frequency to generate N optimized clock groups;
The clock switching unit is supplied with the optimized clock group instead of the input clock, and the clock switching unit converts the optimized clock generated based on an input clock other than the frequency abnormal clock to the clock switching Selecting from the optimized clock group based on a signal and supplying the system clock as the system clock;
The system clock monitoring device according to claim 1.
A clock generation unit that generates a zero cross clock by detecting a zero cross point of an AC voltage supplied from the outside;
At least one input clock constituting the input clock group is the zero cross clock.
The system clock monitoring device according to claim 1.
The system clock monitoring device according to claim 1,
The system is a motor;
A microcomputer that controls the motor to a safe state when the system clock monitoring device detects the occurrence of a clock frequency abnormality;
Comprising
Motor control system.