WO2011039871A1 - Bias generating circuit, power amplifier module, and semiconductor device - Google Patents

Bias generating circuit, power amplifier module, and semiconductor device Download PDF

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WO2011039871A1
WO2011039871A1 PCT/JP2009/067088 JP2009067088W WO2011039871A1 WO 2011039871 A1 WO2011039871 A1 WO 2011039871A1 JP 2009067088 W JP2009067088 W JP 2009067088W WO 2011039871 A1 WO2011039871 A1 WO 2011039871A1
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circuit
transistor
current mirror
bias
current
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PCT/JP2009/067088
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French (fr)
Japanese (ja)
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聡 田中
文雅 森沢
慎 田部井
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ルネサスエレクトロニクス株式会社
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Priority to PCT/JP2009/067088 priority Critical patent/WO2011039871A1/en
Priority to US13/383,976 priority patent/US8519796B2/en
Priority to JP2011534009A priority patent/JP5429296B2/en
Publication of WO2011039871A1 publication Critical patent/WO2011039871A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/34—Dc amplifiers in which all stages are dc-coupled
    • H03F3/343—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only
    • H03F3/345—Dc amplifiers in which all stages are dc-coupled with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/18—Indexing scheme relating to amplifiers the bias of the gate of a FET being controlled by a control signal

Definitions

  • the present invention relates to a method for correcting variation among products of a power amplifier module that performs multistage amplification, and more particularly, to suppression of variation between products in a bias circuit caused by variation in gate length of a transistor (in many cases, MOSFET).
  • Wireless transceivers are widely used in general.
  • UMTS W-CDMA
  • CDMA Code Division Multiple Access
  • GSM Time Division Multiple Access
  • TDMA Time Division Multiple Access
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-237656
  • Non-patent Document 1 P132 FIG. 6.1 discloses a technique for adjusting the amount of current flowing through a bias circuit by a current mirror circuit.
  • FIG. 1 is a circuit diagram showing the configuration of the bias circuit described in Non-Patent Document 1.
  • the current mirror circuit in this figure is a circuit that controls the constant current source IREF to flow a current determined by the ratio of the threshold voltage of the FET. In this case, the following equation is given.
  • V th is a threshold voltage of the MOSFET constituting the current mirror circuit.
  • ⁇ represents a coefficient described later. If this equation is transformed,
  • n the ratio of the gate width of the reference FET and the FET transistor To.
  • Non-Patent Document 1 There is also a problem with the method described in Non-Patent Document 1.
  • W in (Expression 4) is the gate width of the MOSFET constituting the current mirror circuit
  • L is the gate length of the MOSFET
  • ⁇ is the mobility
  • C ox is the gate oxide film capacitance
  • the gate width W included in the denominator of (Expression 4) can be increased in accuracy by setting a large value.
  • C ox is determined by the oxide film thickness and is relatively unaffected by process variations.
  • An object of the present invention is to provide a bias circuit for a power amplifier that reduces the effect of variation in the gate length L and has little variation in gain between products.
  • a bias generation circuit is connected to a first current mirror circuit composed of a pair of NPN transistors, and operates based on an output current from the first current mirror circuit.
  • a constant current is input to the collector terminal of the first transistor constituting the first current mirror circuit including the bias circuit, and the bias circuit is fed from the collector terminal of the second transistor constituting the first current mirror circuit.
  • An input current is output, and the gate length of the base terminal of the second transistor is longer than the gate length of the base terminal of the first transistor.
  • a current output from the second transistor may be input to the bias circuit via a second current mirror circuit.
  • Another bias generation circuit includes a first current mirror circuit configured by a pair of NPN transistors and a second current configured by a pair of NPN transistors.
  • a bias circuit that operates based on the output current of the mirror circuit and the second current mirror circuit, and a constant current is input to the collector terminal of the first transistor that constitutes the first current mirror circuit;
  • the current input to the second current mirror circuit is output from the collector terminal of the second transistor constituting the mirror circuit, and the first transistor is connected to the collector terminal of the third transistor constituting the second current mirror circuit.
  • the output of the second transistor constituting the current mirror circuit is input, and the fourth transistor constituting the second current mirror circuit is input.
  • the gate length of the base terminal of the second transistor and the gate length of the base terminal of the fourth transistor are equal to the gate length of the base terminal of the first transistor and It is characterized by being longer than the gate length of the base terminal of the third transistor.
  • the bias generation circuit inputs the current output from the second transistor to the second current mirror circuit via the third current mirror circuit, and outputs the current output from the fourth transistor to the fourth current mirror circuit. It is good also as inputting to a bias circuit via this.
  • a first amplifier, a second amplifier, and a third amplifier are connected in series, and between the first amplifier and the second amplifier.
  • a bias generation circuit according to the present invention is used for both.
  • the power amplifier module includes a first amplifier, a second amplifier, and a third amplifier connected in series, and the first amplifier and the second amplifier.
  • a bias generation circuit exists between the second amplifier and the third amplifier, and the bias generation circuit according to the present invention is used for the bias generation circuit.
  • the transconductance gm on the side of the FET having a long gate length in which the variation in the transconductance gm is relatively small is equivalently short in gate length.
  • the bias is set by applying a current mirror circuit so that it looks like the transconductance gm of the FET. As a result, it is possible to suppress the gain deviation due to the gate length, which is the main cause of variation.
  • FIG. 2 is a circuit diagram illustrating a configuration of a bias generation circuit described in Non-Patent Document 1.
  • FIG. 1 is a circuit diagram illustrating a configuration of a bias generation circuit according to a first embodiment of the present invention. It is a circuit diagram showing the structure of the bias generation circuit in connection with the 2nd Embodiment of this invention.
  • FIG. 3 is a configuration diagram showing a configuration of a power amplifier module to which the first embodiment or the second embodiment of the present invention is applied.
  • FIG. 5 is a conceptual diagram showing a movement of a bias point of a transistor in an amplification stage of the power amplifier in FIG. 4.
  • FIG. 3 is a configuration diagram showing a configuration of another power amplifier module to which the first embodiment or the second embodiment of the present invention is applied.
  • FIG. 7 is a conceptual diagram illustrating the movement of a bias point of a transistor in an amplification stage of the power amplifier in FIG. 6.
  • FIG. 2 is a circuit diagram showing the configuration of the bias generation circuit according to the first embodiment of the present invention.
  • This bias circuit is characterized in that current mirror circuits 101 and 102 are added in front of the bias circuit 103. First, these circuits will be described.
  • the current mirror circuit 101 is a constant current circuit for inputting the current of the constant current source 1001 to the current mirror circuit 102.
  • the gate length Lg of the MOSFET constituting the current mirror circuit 101 is characterized by being longer than the gate length Lo of other MOSFETs used in this circuit.
  • the current mirror circuit 102 is a constant current circuit that outputs the output current of the current mirror circuit 101, that is, the output current of the constant current source 1001, to the bias circuit 103.
  • the current mirror circuit 101 is an NPN type and the current mirror circuit 102 is a PNP type.
  • the threshold voltages of the MOSFETs constituting these current mirror circuits are all common and Vth .
  • the constant current source 1001 is a constant current source that supplies a reference current I ref .
  • the current value output from the constant current source 1001 is input to the bias circuit 103.
  • the reference current I ref of the constant current source 1001 can be defined as follows.
  • ⁇ 0 is a coefficient of the transistor Q 0 included in the current mirror circuit 101.
  • V G0 is the potential of the base terminal of the current mirror circuit 101, and V th is the threshold voltage of the transistor Q0.
  • I vref1 output by the current mirror circuit 101 takes the following equation.
  • ⁇ 1 is a coefficient of the transistor Q 1 included in the current mirror circuit 101.
  • the transistor Q0 and the transistor Q1 are characterized in that the length of the gate terminal (gate length) is different. That is, the gate length L g1 of the transistor Q1 is longer than the gate length L g0 of the transistor Q0.
  • This I vref1 is input to the bias circuit 103 by the current mirror circuit 102.
  • the gate length of the transistor Q2 used in the bias circuit 103 is equal to the gate length of the transistor Q0 of the current mirror circuit 101.
  • the transconductor can be determined by the transistor Q1 having a long gate length.
  • FIG. 3 is a circuit diagram showing a configuration of a bias generation circuit according to the second embodiment of the present invention.
  • This bias generation circuit is characterized in that current mirror circuits 201, 202, 203, and 204 are added to the input side of the bias circuit 205.
  • the current mirror circuit 201 is a constant current circuit for using the current of the constant current source 2001 as an input to the current mirror circuit 202.
  • the current mirror circuit 201 corresponds to the current mirror circuit 101 of the first embodiment. That is, the gate lengths of the transistors Q10 and Q11 constituting the current mirror circuit 201 are different. The gate length of the transistor Q11 is longer than the gate length Lg0 of the transistor Q10.
  • the operation of the current mirror circuit 201 is the same as (Equation 6) to (Equation 8) in the first embodiment.
  • the reference current of the constant current source 2001 is expressed as I ref as in the first embodiment.
  • I ref11 is used as the output of the current mirror circuit 201.
  • the potential of the base terminal of the current mirror circuit 201 is expressed as VG10 .
  • the coefficient ⁇ 10 is a coefficient of the transistor Q 10 in the current mirror circuit 201
  • the coefficient ⁇ 11 is a coefficient of the transistor Q 11 in the current mirror circuit 201.
  • the current mirror circuit 202 is a constant current circuit for using I ref11 that is an output of the current mirror circuit 201 as an input of the current mirror circuit 203.
  • the current mirror circuit 202 is composed of a PNP transistor.
  • the current mirror circuit 203 is a current mirror circuit having a configuration in which the gate lengths of the NPN transistors Q12 and Q13 are different.
  • this current mirror circuit is also the same as (Equation 6) to (Equation 8) of the first embodiment.
  • I ref12 is used as the output of the current mirror circuit 203.
  • the potential of the base terminal of the current mirror circuit 203 is denoted by V G11 .
  • the coefficient ⁇ 12 is a coefficient of the transistor Q 12 in the current mirror circuit 203
  • the coefficient ⁇ 13 is a coefficient of the transistor Q 13 in the current mirror circuit 203.
  • the threshold voltage of the transistors Q12 and Q 13 is a V th1.
  • the current mirror circuit 204 is a constant current circuit for using Iref12 , which is the output of the current mirror circuit 203, as an input to the bias circuit 205.
  • the bias circuit 205 is a bias circuit having the same configuration as that of the bias circuit 103 according to the first embodiment.
  • the operation of the transistor Q 14 in the bias circuit 205, using the current I REF12 inputted is expressed as follows. Note the threshold voltage of the transistor Q 14 and V th2, the coefficient beta 14. In addition, the voltage of the base terminal of the transistor Q 14 and V G12.
  • the transconductor gm increases as the gate length Lg decreases.
  • the transistors Q11 and Q13 and the like obtain a bias such that the transconductor gm2 becomes smaller as the gate length Lg becomes shorter. It becomes possible.
  • the power amplifier module is configured by using a plurality of bias circuits, by applying the bias circuit according to the present embodiment to one stage, the sensitivity to the transconductor gm of the entire amplifier circuit is canceled, and an amplifier with a constant gain can be obtained. It can be realized.
  • FIG. 4 is a configuration diagram showing a configuration of a power amplifier module to which the first embodiment or the second embodiment of the present invention is applied.
  • FIG. 5 is a conceptual diagram showing the movement of the bias point of the transistor in the amplification stage when the first embodiment is applied.
  • 5A is a graph showing the correspondence between voltage and current
  • FIG. 5B is a graph showing the correspondence between voltage and transconductor.
  • the amplifier circuit shown in FIG. 4 includes amplifiers M1, M2, and M3 and bias circuits B1 and B2.
  • the bias circuits B1 and B2 are controlled by independent current sources I REF1 and I REF2 . These bias circuits realize detailed bias control such as temperature characteristics of each stage.
  • bias circuits of the first and second embodiments of the present invention to the bias circuits B1 and B2.
  • the first bias circuit is preferably applied to both.
  • the second embodiment of the present invention is preferable to apply the bias circuit B2.
  • FIG. 5 shows the relationship between the default value (design center) Lg 0 of the gate length and the actual gate length Lg, and three change lines are shown in each figure.
  • the gate length Lg of the transistor is changed, as the gate length Lg is shorter as shown in FIG. 5A, the current driving capability is increased, so that a larger amount of current flows. It is assumed that the gate voltage Vg 0 is applied when the gate length Lg 0 is applied, the current I do is passed, and gm 0 is obtained.
  • the drive current and the like are determined by the characteristics of the FET Q1 having a long gate length Lg.
  • gate voltages Vg 1 and Vg 2 are generated as shown in FIG.
  • ⁇ Gm is controlled to be constant by this bias change.
  • the gm constant bias circuit is inserted only in one of the first and second stages.
  • Such a behavior makes it possible to realize a power amplifier that can stably adjust the gain.
  • FIG. 6 is a configuration diagram showing the configuration of another power amplifier module to which the first embodiment or the second embodiment of the present invention is applied.
  • FIG. 7 is a conceptual diagram showing the movement of the bias point of the transistor in the amplification stage. As in FIG. 5 of application example 1, FIG. 7A is a graph showing the correspondence between voltage and current, and FIG. 7B is a graph showing the correspondence between voltage and transconductor.
  • This amplifying circuit includes amplifiers M1, M2, and M3, a bias circuit B1, and a constant current source I3.
  • the bias circuit shown in the first embodiment for making the transconductor gm constant is mounted in both the first stage and the second stage.
  • the gate voltage may be reduced when the gate length is shortened. The distortion increases due to the decrease.
  • the case where the first stage bias is in such a situation is considered.
  • the gm constant circuit is not installed in the first stage to avoid distortion, and the bias circuit of the second embodiment is provided in the last stage.
  • the transconductor gm is controlled to cancel the gain deviation for the first stage.
  • a gm control circuit can be provided in the first stage depending on the bias setting.
  • the semiconductor device in which the power amplifier module described in these application examples is mounted, a wireless transceiver using the semiconductor device, and a mobile phone are also included in the scope of the present invention.

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Abstract

Provided is a power amplifier bias circuit that will reduce the effect of variation in gate length (L) and that has little variation in gain between products. Two current mirror circuits (101) (NPN type) and (102) (PNP type) are inserted at the input side of a bias circuit (103). The gate length of a transistor (Q1) at the output side of the current mirror circuit (101) is designed to be longer than that of the other transistors. Thus, even when error occurs, the effects thereof can be kept small.

Description

バイアス生成回路、パワーアンプモジュール及び半導体装置Bias generation circuit, power amplifier module, and semiconductor device
　本発明は、多段増幅を行うパワーアンプモジュールの製品間ばらつきの補正方法、特にトランジスタ（多くの場合はＭＯＳＦＥＴ）のゲート長ばらつきに起因するバイアス回路の製品間ばらつきの抑止に関する。 The present invention relates to a method for correcting variation among products of a power amplifier module that performs multistage amplification, and more particularly, to suppression of variation between products in a bias circuit caused by variation in gate length of a transistor (in many cases, MOSFET).
　無線送受信器は広く一般的に用いられている。無線送受信器を用いる携帯電話機では、多元接続方式としてＣＤＭＡ（Ｃｏｄｅ　Ｄｉｖｉｓｉｏｎ　Ｍｕｌｔｉｐｌｅ　Ａｃｃｅｓｓ）を用いたＵＭＴＳ（Ｗ－ＣＤＭＡ）方式や、ＴＤＭＡ（Ｔｉｍｅ　Ｄｉｖｉｓｉｏｎ　Ｍｕｌｔｉｐｌｅ　Ａｃｃｅｓｓ）方式を用いたＧＳＭが主要な方式である。 Wireless transceivers are widely used in general. In mobile phones using wireless transceivers, UMTS (W-CDMA) method using CDMA (Code Division Multiple Access) and GSM using TDMA (Time Division Multiple Access) method are the main methods as a multiple access method. .
　ＵＭＴＳ・ＧＳＭの双方に対応したＵＭＴＳ・ＧＳＭマルチモードＰＡモジュールにおいては、製品間の利得ばらつきの抑圧が重要な課題となっている。 In the UMTS / GSM multimode PA module compatible with both UMTS / GSM, suppression of gain variation between products is an important issue.
　従来のＰＡモジュールの利得を安定させる手法としては、プロセスばらつきに応じて、外付け抵抗の値を調整する手法が挙げられる。 As a technique for stabilizing the gain of the conventional PA module, there is a technique for adjusting the value of the external resistor according to the process variation.
　製造時の変動を補償する先行技術としては、特開２００１－２３７６５６号公報（特許文献１）記載の技術が上げられる。 As a prior art for compensating for variations during manufacturing, there is a technique described in Japanese Patent Laid-Open No. 2001-237656 (Patent Document 1).
　また、実用アナログ電子回路設計法（非特許文献１）Ｐ１３２図６．１には、カレントミラー回路でバイアス回路に流れる電流量を調整する技術が開示されている。 Practical analog electronic circuit design method (Non-patent Document 1) P132 FIG. 6.1 discloses a technique for adjusting the amount of current flowing through a bias circuit by a current mirror circuit.
　図１は、この非特許文献１に記載のバイアス回路の構成を表す回路図である。 FIG. 1 is a circuit diagram showing the configuration of the bias circuit described in Non-Patent Document 1.
　この図のカレントミラー回路は、定電流源ＩＲＥＦに対して、ＦＥＴの閾値電圧の比で決まる電流を流すように制御する回路である。この場合、以下の式が与えられる。 The current mirror circuit in this figure is a circuit that controls the constant current source IREF to flow a current determined by the ratio of the threshold voltage of the FET. In this case, the following equation is given.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
で記載される関係が成り立つ。ここでＶｔｈはカレントミラー回路を構成するＭＯＳＦＥＴの閾値電圧である。また、βは後述する係数を表す。この式を変形すると、 The relationship described in is established. Here, V th is a threshold voltage of the MOSFET constituting the current mirror circuit. Β represents a coefficient described later. If this equation is transformed,
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
で記述される関係が成り立つ。これらの関係からＦＥＴトランジスタＴｏのトランスコンダクタンス（電流電圧変換利得）ｇｍを求めると、以下の式で与えられる。 The relationship described in holds. When these relationships determine the transconductance (current-voltage conversion gain) g m of the FET transistor To, it is given by the following equation.
Figure JPOXMLDOC01-appb-M000003
  
Figure JPOXMLDOC01-appb-M000003
  
　ここｎはリファレンスＦＥＴとＦＥＴトランジスタＴｏのゲート幅の比を表す。 Here, n represents the ratio of the gate width of the reference FET and the FET transistor To.
特開２００１－２３７６５６号公報JP 2001-237656 A
　しかし、プロセスばらつきに応じて実装時に調整を行う方式では、製造をアウトソーシングする際に、画一的な指示が行えない問題が生じる。 However, in the method of adjusting at the time of mounting according to process variations, there is a problem that uniform instructions cannot be given when manufacturing is outsourced.
　また非特許文献１に記載の方法についても問題は存在する。 There is also a problem with the method described in Non-Patent Document 1.
　上記の（数１）では係数βが登場する。この係数は式で表すと以下の２式のようになる。 In the above (Equation 1), the coefficient β appears. This coefficient is expressed by the following two equations.
Figure JPOXMLDOC01-appb-M000004
  
Figure JPOXMLDOC01-appb-M000004
  
Figure JPOXMLDOC01-appb-M000005
  
Figure JPOXMLDOC01-appb-M000005
  
　ここで（数４）のＷはカレントミラー回路を構成するＭＯＳＦＥＴのゲート幅であり、ＬはＭＯＳＦＥＴのゲート長、μは移動度、Ｃｏｘはゲート酸化膜容量を現す。（数３）より、デバイスの加工ばらつきで、Ｗ、Ｌ、Ｃｏｘなどの値が変動することによりトランスコンダクタンスｇｍがばらつくことが理解できる。 Here, W in (Expression 4) is the gate width of the MOSFET constituting the current mirror circuit, L is the gate length of the MOSFET, μ is the mobility, and C ox is the gate oxide film capacitance. From equation (3), the machining device variation, W, L, can be seen that the transconductance g m varies by values such as C ox is varied.
　また、（数５）より、移動度μは絶対温度Ｔに依存する。 Also, from (Equation 5), the mobility μ depends on the absolute temperature T.
　これらの中で、（数４）の分母に含まれるゲート幅Ｗは大きな値を設定することで、精度を上げることができる。また、Ｃｏｘは酸化膜厚で決まるもので比較的プロセス変動の影響を受けない。 Among these, the gate width W included in the denominator of (Expression 4) can be increased in accuracy by setting a large value. Also, C ox is determined by the oxide film thickness and is relatively unaffected by process variations.
　一方、（数５）の移動度については、別手段で電流に温度特性を持たせることができる。 On the other hand, for the mobility of (Equation 5), the temperature can be given to the current by another means.
　したがって、担保手段の無いゲート長Ｌのばらつきの影響により、電流を一定に保ってもトランスコンダクタンスｇｍが一定に保てないという問題点が存在した。 Therefore, the influence of variations of no gate length L of collateral means, is a problem that even if maintaining the current constant transconductance g m not maintain constant was present.
　また、バイアス回路の出力側トランジスタＴｏの増幅率を単純に大きくするだけでは、周波数特性が悪化する。 Also, simply increasing the amplification factor of the output side transistor To of the bias circuit deteriorates the frequency characteristics.
　本発明の目的は、このゲート長Ｌのばらつきの影響を軽減し、製品間の利得のばらつきの少ない電力増幅器のバイアス回路を提供することにある。 An object of the present invention is to provide a bias circuit for a power amplifier that reduces the effect of variation in the gate length L and has little variation in gain between products.
　本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次の通りである。 The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows.
　本発明の代表的な実施の形態に関わるバイアス生成回路は、1対のＮＰＮ型トランジスタにより構成される第1のカレントミラー回路が接続され、この第1のカレントミラー回路による出力電流に基づき動作するバイアス回路を含み、第1のカレントミラー回路を構成する第1のトランジスタのコレクタ端子には定電流が入力され、第1のカレントミラー回路を構成する第２のトランジスタのコレクタ端子からはバイアス回路に入力される電流が出力され、第２のトランジスタのベース端子のゲート長が第1のトランジスタのベース端子のゲート長よりも長いことを特徴とする。 A bias generation circuit according to a representative embodiment of the present invention is connected to a first current mirror circuit composed of a pair of NPN transistors, and operates based on an output current from the first current mirror circuit. A constant current is input to the collector terminal of the first transistor constituting the first current mirror circuit including the bias circuit, and the bias circuit is fed from the collector terminal of the second transistor constituting the first current mirror circuit. An input current is output, and the gate length of the base terminal of the second transistor is longer than the gate length of the base terminal of the first transistor.
　このバイアス生成回路において、第２のトランジスタの出力する電流を第２のカレントミラー回路を介して前記バイアス回路に入力することを特徴としても良い。 In this bias generation circuit, a current output from the second transistor may be input to the bias circuit via a second current mirror circuit.
　本発明の代表的な実施の形態に関わる別のバイアス生成回路は、1対のＮＰＮ型トランジスタにより構成される第1のカレントミラー回路と、1対のＮＰＮ型トランジスタにより構成される第２のカレントミラー回路と、第２のカレントミラー回路の出力電流に基づき動作するバイアス回路を含み、第１のカレントミラー回路を構成する第1のトランジスタのコレクタ端子には定電流が入力され、第1のカレントミラー回路を構成する第２のトランジスタのコレクタ端子からは第２のカレントミラー回路に入力される電流が出力され、第２のカレントミラー回路を構成する第３のトランジスタのコレクタ端子には第１のカレントミラー回路を構成する第２のトランジスタの出力が入力され、第２のカレントミラー回路を構成する第４のトランジスタのコレクタ端子からはバイアス回路に入力される電流が出力され、第２のトランジスタのベース端子のゲート長及び第４のトランジスタのベース端子のゲート長が、第1のトランジスタのベース端子のゲート長及び第３のトランジスタのベース端子のゲート長よりも長いことを特徴とする。 Another bias generation circuit according to the representative embodiment of the present invention includes a first current mirror circuit configured by a pair of NPN transistors and a second current configured by a pair of NPN transistors. A bias circuit that operates based on the output current of the mirror circuit and the second current mirror circuit, and a constant current is input to the collector terminal of the first transistor that constitutes the first current mirror circuit; The current input to the second current mirror circuit is output from the collector terminal of the second transistor constituting the mirror circuit, and the first transistor is connected to the collector terminal of the third transistor constituting the second current mirror circuit. The output of the second transistor constituting the current mirror circuit is input, and the fourth transistor constituting the second current mirror circuit is input. Current from the collector circuit is output to the bias circuit, and the gate length of the base terminal of the second transistor and the gate length of the base terminal of the fourth transistor are equal to the gate length of the base terminal of the first transistor and It is characterized by being longer than the gate length of the base terminal of the third transistor.
　このバイアス生成回路は、第２のトランジスタの出力する電流を第３のカレントミラー回路を介して第２のカレントミラー回路に入力し、第４のトランジスタの出力する電流を第４のカレントミラー回路を介してバイアス回路に入力することを特徴としても良い。 The bias generation circuit inputs the current output from the second transistor to the second current mirror circuit via the third current mirror circuit, and outputs the current output from the fourth transistor to the fourth current mirror circuit. It is good also as inputting to a bias circuit via this.
　本発明の代表的な実施の形態に関わるパワーアンプモジュールは、第1の増幅器と、第２の増幅器と、第３の増幅器を直列に接続し、第1の増幅器と第２の増幅器の間には第１のバイアス発生回路が、第２の増幅器と第３の増幅器の間には第２のバイアス発生回路が存在し、第1のバイアス発生回路及び第２のバイアス発生回路のいずれか一方、または双方に本発明に関するバイアス生成回路が用いられていることを特徴とする。 In a power amplifier module according to a representative embodiment of the present invention, a first amplifier, a second amplifier, and a third amplifier are connected in series, and between the first amplifier and the second amplifier. Has a first bias generation circuit, and a second bias generation circuit exists between the second amplifier and the third amplifier, and one of the first bias generation circuit and the second bias generation circuit, Alternatively, a bias generation circuit according to the present invention is used for both.
　また、本発明の代表的な実施の形態に関わるパワーアンプモジュールは、第1の増幅器と、第２の増幅器と、第３の増幅器を直列に接続し、第1の増幅器と第２の増幅器の間、または第２の増幅器と第３の増幅器の間にはバイアス発生回路が存在し、このバイアス発生回路に本発明に関するバイアス生成回路が用いられていることを特徴とする。 The power amplifier module according to the representative embodiment of the present invention includes a first amplifier, a second amplifier, and a third amplifier connected in series, and the first amplifier and the second amplifier. A bias generation circuit exists between the second amplifier and the third amplifier, and the bias generation circuit according to the present invention is used for the bias generation circuit.
　これらのパワーアンプモジュールを含む半導体装置も本発明の射程に入る。 Semiconductor devices including these power amplifier modules also fall within the scope of the present invention.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下の通りである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　本発明の代表的な実施の形態に関わる電力増幅器のバイアス回路では、トランスコンダクタンスｇｍの変動が相対的に小さくなる長いゲート長を有するＦＥＴの側のトランスコンダクタンスｇｍが、等価的にゲート長の短いＦＥＴのトランスコンダクタンスｇｍに見えるようにカレントミラー回路を応用してバイアス設定を行う。これにより、ばらつきの主要因であるゲート長による利得偏差を抑圧することが可能となる。 In the bias circuit of the power amplifier according to the representative embodiment of the present invention, the transconductance gm on the side of the FET having a long gate length in which the variation in the transconductance gm is relatively small is equivalently short in gate length. The bias is set by applying a current mirror circuit so that it looks like the transconductance gm of the FET. As a result, it is possible to suppress the gain deviation due to the gate length, which is the main cause of variation.
非特許文献１に記載のバイアス生成回路の構成を表す回路図である。2 is a circuit diagram illustrating a configuration of a bias generation circuit described in Non-Patent Document 1. FIG. 本発明の第１の実施の形態に関わるバイアス生成回路の構成を表す回路図である。1 is a circuit diagram illustrating a configuration of a bias generation circuit according to a first embodiment of the present invention. 本発明の第２の実施の形態に関わるバイアス生成回路の構成を表す回路図である。It is a circuit diagram showing the structure of the bias generation circuit in connection with the 2nd Embodiment of this invention. 本発明の第1の実施の形態、または第2の実施の形態を適用したパワーアンプモジュールの構成を表す構成図である。FIG. 3 is a configuration diagram showing a configuration of a power amplifier module to which the first embodiment or the second embodiment of the present invention is applied. 図４のパワーアンプの増幅段のトランジスタのバイアス点の動きを示す概念図である。FIG. 5 is a conceptual diagram showing a movement of a bias point of a transistor in an amplification stage of the power amplifier in FIG. 4. 本発明の第1の実施の形態、または第２の実施の形態を適用した別のパワーアンプモジュールの構成を表す構成図である。FIG. 3 is a configuration diagram showing a configuration of another power amplifier module to which the first embodiment or the second embodiment of the present invention is applied. 図６のパワーアンプの増幅段のトランジスタのバイアス点の動きを示す概念図である。FIG. 7 is a conceptual diagram illustrating the movement of a bias point of a transistor in an amplification stage of the power amplifier in FIG. 6.
　以下、図を用いて本発明の実施の形態について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第１の実施の形態）
　図２は本発明の第１の実施の形態に関わるバイアス生成回路の構成を表す回路図である。 (First embodiment)
FIG. 2 is a circuit diagram showing the configuration of the bias generation circuit according to the first embodiment of the present invention.
　本バイアス回路には、バイアス回路１０３の前段に、カレントミラー回路１０１、１０２が付加されている点に特徴がある。まず、これらの回路について説明する。 This bias circuit is characterized in that current mirror circuits 101 and 102 are added in front of the bias circuit 103. First, these circuits will be described.
　カレントミラー回路１０１は、定電流源１００１の電流をカレントミラー回路１０２の入力にするための定電流回路である。このカレントミラー回路１０１を構成するＭＯＳＦＥＴのゲート長Ｌｇは本回路で使われる他のＭＯＳＦＥＴのゲート長Ｌｏより長い点が特徴である。 The current mirror circuit 101 is a constant current circuit for inputting the current of the constant current source 1001 to the current mirror circuit 102. The gate length Lg of the MOSFET constituting the current mirror circuit 101 is characterized by being longer than the gate length Lo of other MOSFETs used in this circuit.
　カレントミラー回路１０２は、カレントミラー回路１０１の出力電流、すなわち定電流源１００１の出力電流をバイアス回路１０３に出力する定電流回路である。図の通り、カレントミラー回路１０１がＮＰＮ型、カレントミラー回路１０２がＰＮP型で構成されている。これらのカレントミラー回路を構成するＭＯＳＦＥＴの閾値電圧は全て共通でＶｔｈあるものとする。 The current mirror circuit 102 is a constant current circuit that outputs the output current of the current mirror circuit 101, that is, the output current of the constant current source 1001, to the bias circuit 103. As shown in the figure, the current mirror circuit 101 is an NPN type and the current mirror circuit 102 is a PNP type. The threshold voltages of the MOSFETs constituting these current mirror circuits are all common and Vth .
　定電流源１００１は基準電流Ｉｒｅｆを供給する定電流源である。この定電流源１００１の出力する電流値を、バイアス回路１０３に入力する。 The constant current source 1001 is a constant current source that supplies a reference current I ref . The current value output from the constant current source 1001 is input to the bias circuit 103.
　これらの諸構成からなる本発明のバイアス回路の動作について説明する。 The operation of the bias circuit according to the present invention having these configurations will be described.
　まず、定電流源１００１の基準電流Ｉｒｅｆは以下のように定義できる。 First, the reference current I ref of the constant current source 1001 can be defined as follows.
Figure JPOXMLDOC01-appb-M000006
  
Figure JPOXMLDOC01-appb-M000006
  
　ここでβ０はカレントミラー回路１０１に含まれるトランジスタＱ０の係数である。また、ＶＧ０はカレントミラー回路１０１のベース端子の電位、Ｖｔｈは該トランジスタＱ０の閾値電圧である。 Here, β 0 is a coefficient of the transistor Q 0 included in the current mirror circuit 101. V G0 is the potential of the base terminal of the current mirror circuit 101, and V th is the threshold voltage of the transistor Q0.
　また、一方カレントミラー回路１０１によって出力されるＩｖｒｅｆ１は以下の式を取る。 On the other hand, I vref1 output by the current mirror circuit 101 takes the following equation.
Figure JPOXMLDOC01-appb-M000007
  
Figure JPOXMLDOC01-appb-M000007
  
　ここで、β１はカレントミラー回路１０１に含まれるトランジスタＱ１の係数である。ここで、トランジスタＱ０とトランジスタＱ１はゲート端子の長さ（ゲート長）が相違する点が特徴である。すなわち、トランジスタＱ１のゲート長Ｌｇ１はトランジスタＱ０のゲート長Ｌｇ０よりも長いものとする。 Here, β 1 is a coefficient of the transistor Q 1 included in the current mirror circuit 101. Here, the transistor Q0 and the transistor Q1 are characterized in that the length of the gate terminal (gate length) is different. That is, the gate length L g1 of the transistor Q1 is longer than the gate length L g0 of the transistor Q0.
　係数β１及びβ２のいずれも（数４）に支配される。そして（数４）は各トランジスタのゲート長に支配される。 Both coefficients β 1 and β 2 are governed by (Equation 4). (Equation 4) is governed by the gate length of each transistor.
　したがってベース電位ＶＧ０が共通であっても、ゲート長の相違によって、β１及びβ２の性質は異なったものとなる。 Therefore, even when the base potential V G0 is common, the properties of β 1 and β 2 differ depending on the gate length.
　この（数６）および（数７）からＩｒｅｆ１を求めると以下のようになる。 From this ( Equation 6) and ( Equation 7), I ref1 is obtained as follows.
Figure JPOXMLDOC01-appb-M000008
  
Figure JPOXMLDOC01-appb-M000008
  
　このＩvref1はカレントミラー回路１０２によって、バイアス回路１０３に入力される。 This I vref1 is input to the bias circuit 103 by the current mirror circuit 102.
　したがって以下の式が成立する。 Therefore, the following formula is established.
Figure JPOXMLDOC01-appb-M000009
  
Figure JPOXMLDOC01-appb-M000009
  
　すなわち、このバイアス回路１０３で用いられるトランジスタＱ２のゲート長は、カレントミラー回路１０１のトランジスタＱ０のゲート長と等しいことを想定する。 That is, it is assumed that the gate length of the transistor Q2 used in the bias circuit 103 is equal to the gate length of the transistor Q0 of the current mirror circuit 101.
　このバイアス回路１０３のゲート電圧でのトランスコンダクタンスｇｍ１を（数８）を代入して求めると、以下のようになる。 When the transconductance gm1 at the gate voltage of the bias circuit 103 is obtained by substituting (Equation 8), it is as follows.
Figure JPOXMLDOC01-appb-M000010
  
Figure JPOXMLDOC01-appb-M000010
  
　このようにゲート長の長いトランジスタＱ１によってトランスコンダクタを決めることが可能になる。結果、製造段階におけるゲート長のばらつきによって決まる係数βのばらつきにロバストなバイアス生成回路を構成することが可能となる。 Thus, the transconductor can be determined by the transistor Q1 having a long gate length. As a result, it is possible to configure a bias generation circuit that is robust to variations in coefficient β determined by variations in gate length at the manufacturing stage.
　（第２の実施の形態）
　次に本発明の第２の実施の形態について図を用いて説明する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.
　図３は本発明の第２の実施の形態に関わるバイアス生成回路の構成を表す回路図である。 FIG. 3 is a circuit diagram showing a configuration of a bias generation circuit according to the second embodiment of the present invention.
　このバイアス生成回路は、バイアス回路２０５の入力側にカレントミラー回路２０１、２０２、２０３、２０４が付加されている点に特徴がある。 This bias generation circuit is characterized in that current mirror circuits 201, 202, 203, and 204 are added to the input side of the bias circuit 205.
　カレントミラー回路２０１は、定電流源２００１の電流をカレントミラー回路２０２の入力にするための定電流回路である。 The current mirror circuit 201 is a constant current circuit for using the current of the constant current source 2001 as an input to the current mirror circuit 202.
　このカレントミラー回路２０１は、第１の実施の形態のカレントミラー回路１０１に対応する。すなわちカレントミラー回路２０１を構成するトランジスタＱ１０とＱ１１のゲート長は異なる。トランジスタＱ１０のゲート長Ｌｇ０よりもトランジスタＱ１１のゲート長が長い。 The current mirror circuit 201 corresponds to the current mirror circuit 101 of the first embodiment. That is, the gate lengths of the transistors Q10 and Q11 constituting the current mirror circuit 201 are different. The gate length of the transistor Q11 is longer than the gate length Lg0 of the transistor Q10.
　このカレントミラー回路２０１の動作は第１の実施の形態の（数６）ないし（数８）と同じ動作になる。なお、定電流源２００１の基準電流は第1の実施の形態同様にＩｒｅｆとして表す。また、カレントミラー回路２０１の出力としてＩｒｅｆ１１を用いる。また、カレントミラー回路２０１のベース端子の電位をＶＧ１０で表記する。また係数β10はカレントミラー回路２０１内のトランジスタＱ１０の係数であり、係数β11はカレントミラー回路２０１内のトランジスタＱ11の係数である。 The operation of the current mirror circuit 201 is the same as (Equation 6) to (Equation 8) in the first embodiment. Note that the reference current of the constant current source 2001 is expressed as I ref as in the first embodiment. Also, I ref11 is used as the output of the current mirror circuit 201. Further, the potential of the base terminal of the current mirror circuit 201 is expressed as VG10 . The coefficient β 10 is a coefficient of the transistor Q 10 in the current mirror circuit 201, and the coefficient β 11 is a coefficient of the transistor Q 11 in the current mirror circuit 201.
Figure JPOXMLDOC01-appb-M000011
  
Figure JPOXMLDOC01-appb-M000011
  
Figure JPOXMLDOC01-appb-M000012
  
Figure JPOXMLDOC01-appb-M000012
  
Figure JPOXMLDOC01-appb-M000013
  
Figure JPOXMLDOC01-appb-M000013
  
　カレントミラー回路２０２は、カレントミラー回路２０１の出力であるＩｒｅｆ１１をカレントミラー回路２０３の入力とするための定電流回路である。カレントミラー回路２０２はＰＮＰ型トランジスタで構成されている。 The current mirror circuit 202 is a constant current circuit for using I ref11 that is an output of the current mirror circuit 201 as an input of the current mirror circuit 203. The current mirror circuit 202 is composed of a PNP transistor.
　カレントミラー回路２０３は、カレントミラー回路２０１及び第１の実施の形態のカレントミラー回路１０１同様に、ＮＰＮ型のトランジスタＱ１２とＱ１３のゲート長が異なる構成をとるカレントミラー回路である。 Like the current mirror circuit 201 and the current mirror circuit 101 of the first embodiment, the current mirror circuit 203 is a current mirror circuit having a configuration in which the gate lengths of the NPN transistors Q12 and Q13 are different.
　このカレントミラー回路の動作も第１の実施の形態の（数６）ないし（数８）と同じ動作になる。カレントミラー回路２０３の出力としてＩｒｅｆ１２を用いる。また、カレントミラー回路２０３のベース端子の電位をＶＧ１１で表記する。また係数β12はカレントミラー回路２０３内のトランジスタＱ12の係数であり、係数β13はカレントミラー回路２０３内のトランジスタＱ13の係数である。なお、トランジスタＱ１２及びＱ１３の閾値電圧はＶｔｈ１とする。 The operation of this current mirror circuit is also the same as (Equation 6) to (Equation 8) of the first embodiment. I ref12 is used as the output of the current mirror circuit 203. Further, the potential of the base terminal of the current mirror circuit 203 is denoted by V G11 . The coefficient β 12 is a coefficient of the transistor Q 12 in the current mirror circuit 203, and the coefficient β 13 is a coefficient of the transistor Q 13 in the current mirror circuit 203. The threshold voltage of the transistors Q12 and Q 13 is a V th1.
Figure JPOXMLDOC01-appb-M000014
  
Figure JPOXMLDOC01-appb-M000014
  
Figure JPOXMLDOC01-appb-M000015
  
Figure JPOXMLDOC01-appb-M000015
  
Figure JPOXMLDOC01-appb-M000016
  
Figure JPOXMLDOC01-appb-M000016
  
　ここで、ゲート長の対応関係により、カレントミラー回路２０１中のトランジスタＱ１０とカレントミラー２０３中のトランジスタＱ１２、カレントミラー回路２０１中のトランジスタＱ１１とカレントミラー２０３中のトランジスタＱ１３が同じ特性を持つものとする（β１０＝β１２、β１１＝β１３）。この条件下で（数１６）は以下のように変形することが可能となる。 Here, the correspondence relation between the gate length, the transistor Q 12 in the transistor Q 10 and the current mirror 203 in the current mirror circuit 201, the transistor Q 11 and the transistor Q 13 in the current mirror 203 in the current mirror circuit 201 have the same characteristics (Β 10 = β 12 , β 11 = β 13 ). Under this condition, (Equation 16) can be modified as follows.
Figure JPOXMLDOC01-appb-M000017
  
Figure JPOXMLDOC01-appb-M000017
  
　カレントミラー回路２０４は、カレントミラー回路２０３の出力であるＩｒｅｆ１２をバイアス回路２０５の入力とするための定電流回路である。 The current mirror circuit 204 is a constant current circuit for using Iref12 , which is the output of the current mirror circuit 203, as an input to the bias circuit 205.
　バイアス回路２０５は、第1の実施の形態に関わるバイアス回路１０３と同様の構成を取るバイアス回路である。 The bias circuit 205 is a bias circuit having the same configuration as that of the bias circuit 103 according to the first embodiment.
　このバイアス回路２０５中のトランジスタＱ１４の動作は、入力される電流Ｉｒｅｆ１２を用いて以下のように表される。なおトランジスタＱ１４の閾値電圧はＶｔｈ２と、係数をβ14とする。また、トランジスタＱ１４のベース端子の電圧をＶＧ１２とする。 The operation of the transistor Q 14 in the bias circuit 205, using the current I REF12 inputted is expressed as follows. Note the threshold voltage of the transistor Q 14 and V th2, the coefficient beta 14. In addition, the voltage of the base terminal of the transistor Q 14 and V G12.
Figure JPOXMLDOC01-appb-M000018
  
Figure JPOXMLDOC01-appb-M000018
  
　（数１７）（数１８）から、トランジスタＱ１４のゲート電圧でのトランスコンダクタンスｇｍ２は、以下のようになる。 From (Equation 17) and (Equation 18), the transconductance gm2 at the gate voltage of the transistor Q14 is as follows.
Figure JPOXMLDOC01-appb-M000019
  
Figure JPOXMLDOC01-appb-M000019
  
　トランジスタＱ１４のゲート長が、トランジスタＱ１０、Ｑ１２のゲート長と同じ長さと設計すると、β10=β14となる。 If the gate length of the transistor Q14 is designed to be the same as the gate length of the transistors Q10 and Q12, β10 = β14.
Figure JPOXMLDOC01-appb-M000020
  
Figure JPOXMLDOC01-appb-M000020
  
　通常、ゲート長Ｌｇが短くなるとトランスコンダクタｇｍは大きくなる。しかし（数２０）を見ても明らかな様に、本実施の形態を採用することで、トランジスタＱ１１及びＱ１３などはゲート長Ｌｇが短くなると、トランスコンダクタｇｍ２は逆に小さくなるようなバイアスを得ることが可能になる。 Usually, the transconductor gm increases as the gate length Lg decreases. However, as apparent from (Equation 20), by adopting the present embodiment, the transistors Q11 and Q13 and the like obtain a bias such that the transconductor gm2 becomes smaller as the gate length Lg becomes shorter. It becomes possible.
　パワーアンプモジュールとしてバイアス回路を複数用いて構成するような場合、1段に本実施の形態によるバイアス回路を適用することで、増幅回路全体のトランスコンダクタｇｍへの感度を打ち消し、利得一定の増幅器を実現することが可能となる。 When the power amplifier module is configured by using a plurality of bias circuits, by applying the bias circuit according to the present embodiment to one stage, the sensitivity to the transconductor gm of the entire amplifier circuit is canceled, and an amplifier with a constant gain can be obtained. It can be realized.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更が可能であることは言うまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
　最後に本発明の適用事例について説明する。 Finally, application examples of the present invention will be described.
　（応用例１）
　第２の実施の形態で述べたように、複数のバイアス回路を直列多段に構成したパワーアンプモジュールについて本実施例で説明する。 (Application 1)
As described in the second embodiment, a power amplifier module in which a plurality of bias circuits are configured in series in multiple stages will be described in this embodiment.
　図４は本発明の第1の実施の形態、または第2の実施の形態を適用したパワーアンプモジュールの構成を表す構成図である。また図５は第１の実施の形態を適用した場合の増幅段のトランジスタのバイアス点の動きを示す概念図である。なお図５（ａ）は電圧と電流との対応を表すグラフであり、（ｂ）は電圧とトランスコンダクタとの対応を表すグラフである。 FIG. 4 is a configuration diagram showing a configuration of a power amplifier module to which the first embodiment or the second embodiment of the present invention is applied. FIG. 5 is a conceptual diagram showing the movement of the bias point of the transistor in the amplification stage when the first embodiment is applied. 5A is a graph showing the correspondence between voltage and current, and FIG. 5B is a graph showing the correspondence between voltage and transconductor.
　図４に示す増幅回路は、増幅器Ｍ１、Ｍ２、Ｍ３とバイアス回路Ｂ１、Ｂ２より構成される。 The amplifier circuit shown in FIG. 4 includes amplifiers M1, M2, and M3 and bias circuits B1 and B2.
　本応用例においてはバイアス回路Ｂ１及びＢ２は独立した電流源ＩＲＥＦ１、ＩＲＥＦ２によって制御される。これらのバイアス回路は各段の温度特性など詳細なバイアス制御を実現している。 In this application example, the bias circuits B1 and B2 are controlled by independent current sources I REF1 and I REF2 . These bias circuits realize detailed bias control such as temperature characteristics of each stage.
　このバイアス回路Ｂ１及びＢ２に本発明の第1の実施の形態及び第２の実施の形態のバイアス回路を適用することが考えられる。この際、両方のバイアス回路に本発明のバイアス回路を適用する際には、第1のバイアス回路を双方に適用することが好ましい。また、いずれか一方に適用する場合には、バイアス回路Ｂ２に対して本発明の第２の実施の形態を適用することが好ましい。 It is conceivable to apply the bias circuits of the first and second embodiments of the present invention to the bias circuits B1 and B2. At this time, when the bias circuit of the present invention is applied to both bias circuits, the first bias circuit is preferably applied to both. When applied to either one, it is preferable to apply the second embodiment of the present invention to the bias circuit B2.
　次に、本応用例の挙動について図５を用いて説明する。 Next, the behavior of this application example will be described with reference to FIG.
　半導体基板上にＭＯＳＦＥＴとして実装した場合、各素子間でのばらつきは一定になる場合がほとんどである。そこで、上記実施の形態で説明した各トランジスタのゲート長Ｌｇは全てのトランジスタで一定のばらつきがあるものとして説明する。 When mounted on a semiconductor substrate as a MOSFET, the variation between elements is almost constant. Therefore, description will be made assuming that the gate length Lg of each transistor described in the above embodiment has a certain variation in all the transistors.
　図５はゲート長のデフォルト値（設計中心）Ｌｇ０と実際のゲート長Ｌｇとの関係で、各図に３本の変化線が記載されている。 FIG. 5 shows the relationship between the default value (design center) Lg 0 of the gate length and the actual gate length Lg, and three change lines are shown in each figure.
　トランジスタのゲート長Ｌｇが変化したとすると、図５（ａ）に示すようにゲート長Ｌｇが短いほど電流駆動の能力が上がるため、多くの電流が流れる。ゲート長Ｌｇ０のときゲート電圧Ｖｇ０を印加し、Ｉｄｏの電流を流し、ｇｍ０を得る設計にしたとする。 If the gate length Lg of the transistor is changed, as the gate length Lg is shorter as shown in FIG. 5A, the current driving capability is increased, so that a larger amount of current flows. It is assumed that the gate voltage Vg 0 is applied when the gate length Lg 0 is applied, the current I do is passed, and gm 0 is obtained.
　従来のカレントミラー回路でバイアスした場合にはバイアス電流をＩｄｏと一定に保つ動作をする。このため、製品毎のばらつきでゲート長Ｌｇが変動すると図５（ａ）のＶｇａ、Ｖｇｂのようにバイアスが変化する。この場合、図５（ｂ）に示すようにｇｍを一定に保つことはできない。 When biased by a conventional current mirror circuit, the bias current is kept constant at I do . For this reason, when the gate length Lg varies due to variations among products, the bias changes as shown by V ga and V gb in FIG. In this case, gm cannot be kept constant as shown in FIG.
　しかし、本発明の第１の実施の形態のバイアス回路を用いた場合には、ゲート長Ｌｇの長いＦＥＴＱ１の特性によって駆動電流などが決定されるため、ｇｍを一定にする動作となる。この結果、図５（ｂ）に示すようにゲート電圧Ｖｇ１、Ｖｇ２が発生する。 However, when the bias circuit according to the first embodiment of the present invention is used, the drive current and the like are determined by the characteristics of the FET Q1 having a long gate length Lg. As a result, gate voltages Vg 1 and Vg 2 are generated as shown in FIG.
　このバイアス変化によりｇｍを一定に制御する。勿論初段、２段目一方のみにｇｍ一定バイアス回路を挿入しても改善効果がある。 ¡Gm is controlled to be constant by this bias change. Of course, there is an improvement effect even if the gm constant bias circuit is inserted only in one of the first and second stages.
　このような挙動により安定して利得を調整できる電力増幅器が実現できる。 Such a behavior makes it possible to realize a power amplifier that can stably adjust the gain.
　（応用例２）
　更に別の応用例として、本発明の実施の形態に関わるバイアス回路について説明する。 (Application example 2)
As another application example, a bias circuit according to an embodiment of the present invention will be described.
　図６は本発明の第1の実施の形態、または第２の実施の形態を適用した別のパワーアンプモジュールの構成を表す構成図である。また図７は増幅段のトランジスタのバイアス点の動きを示す概念図である。なお応用例１の図５同様、図７（ａ）は電圧と電流との対応を表すグラフであり、（ｂ）は電圧とトランスコンダクタとの対応を表すグラフである。 FIG. 6 is a configuration diagram showing the configuration of another power amplifier module to which the first embodiment or the second embodiment of the present invention is applied. FIG. 7 is a conceptual diagram showing the movement of the bias point of the transistor in the amplification stage. As in FIG. 5 of application example 1, FIG. 7A is a graph showing the correspondence between voltage and current, and FIG. 7B is a graph showing the correspondence between voltage and transconductor.
　この増幅回路は、増幅器Ｍ１、Ｍ２、Ｍ３とバイアス回路Ｂ１、定電流源Ｉ３より構成される。 This amplifying circuit includes amplifiers M1, M2, and M3, a bias circuit B1, and a constant current source I3.
　応用例１では初段と２段目両方にトランスコンダクタｇｍを一定にする第１の実施例に示したバイアス回路を搭載したが、バイアス点の設定によってはゲート長が短くなった場合にゲート電圧の低下により歪みが増加する。ここでは初段のバイアスがそのような状況にある場合を考察している。 In the application example 1, the bias circuit shown in the first embodiment for making the transconductor gm constant is mounted in both the first stage and the second stage. However, depending on the setting of the bias point, the gate voltage may be reduced when the gate length is shortened. The distortion increases due to the decrease. Here, the case where the first stage bias is in such a situation is considered.
　本応用例では、ひずみを回避するため初段にはｇｍ一定回路を搭載せず、最終段に第２の実施の形態のバイアス回路を設ける。これによりトランスコンダクタｇｍの制御を行い、初段分の利得偏差も含めキャンセルするようにしたものである。 In this application example, the gm constant circuit is not installed in the first stage to avoid distortion, and the bias circuit of the second embodiment is provided in the last stage. As a result, the transconductor gm is controlled to cancel the gain deviation for the first stage.
　この場合、図７に示すようにゲートバイアス電圧の変化が更におおきくなるので、最終段のバイアス点が線形性に対してゆとりがある必要がある点配慮すべきである。 In this case, since the change of the gate bias voltage is further increased as shown in FIG. 7, it should be considered that the bias point of the final stage needs to have a margin for the linearity.
　本応用例では最終段に使用した例をしめした。しかし、バイアス設定によっては逆に初段にｇｍ制御回路を設けることも可能である。 In this application example, the example used in the last stage is shown. However, a gm control circuit can be provided in the first stage depending on the bias setting.
　このように、設計段階においてひずみに対して配慮を行うことで、多段増幅を行うパワーアンプモジュールに対して、本発明のバイアス回路を1つ適用するだけでも安定して利得を調整することが可能となる。 In this way, by considering distortion at the design stage, it is possible to adjust the gain stably even if only one bias circuit of the present invention is applied to a power amplifier module that performs multi-stage amplification. It becomes.
　これらの応用例に記載したパワーアンプモジュールを実装した半導体装置、及びその半導体装置を用いた無線送受信器及び携帯電話機も本発明の射程に含まれる。 The semiconductor device in which the power amplifier module described in these application examples is mounted, a wireless transceiver using the semiconductor device, and a mobile phone are also included in the scope of the present invention.

Claims (7)

　1対のＮＰＮ型トランジスタにより構成される第1のカレントミラー回路が接続され、前記第1のカレントミラー回路による出力電流に基づき動作するバイアス回路を含むバイアス生成回路であって、
　前記第1のカレントミラー回路を構成する第1のトランジスタのコレクタ端子には定電流が入力され、前記第1のカレントミラー回路を構成する第２のトランジスタのコレクタ端子からは前記バイアス回路に入力される電流が出力され、
　前記第２のトランジスタのベース端子のゲート長が前記第1のトランジスタのベース端子のゲート長よりも長いことを特徴とするバイアス生成回路。 A bias generation circuit including a bias circuit connected to a first current mirror circuit configured by a pair of NPN transistors and operating based on an output current from the first current mirror circuit,
A constant current is inputted to the collector terminal of the first transistor constituting the first current mirror circuit, and inputted to the bias circuit from the collector terminal of the second transistor constituting the first current mirror circuit. Current is output,
A bias generation circuit, wherein a gate length of a base terminal of the second transistor is longer than a gate length of a base terminal of the first transistor.
　請求項１記載のバイアス生成回路において、前記第２のトランジスタの出力する電流を第２のカレントミラー回路を介して前記バイアス回路に入力することを特徴とするバイアス生成回路。 2. The bias generation circuit according to claim 1, wherein a current output from the second transistor is input to the bias circuit via a second current mirror circuit.
　1対のＮＰＮ型トランジスタにより構成される第1のカレントミラー回路と、1対のＮＰＮ型トランジスタにより構成される第２のカレントミラー回路と、前記第２のカレントミラー回路の出力電流に基づき動作するバイアス回路を含むバイアス生成回路であって、
　前記第１のカレントミラー回路を構成する第1のトランジスタのコレクタ端子には定電流が入力され、前記第1のカレントミラー回路を構成する第２のトランジスタのコレクタ端子からは前記第２のカレントミラー回路に入力される電流が出力され、
　前記第２のカレントミラー回路を構成する第３のトランジスタのコレクタ端子には前記第１のカレントミラー回路を構成する第２のトランジスタの出力が入力され、前記第２のカレントミラー回路を構成する第４のトランジスタのコレクタ端子からは前記バイアス回路に入力される電流が出力され、
　前記第２のトランジスタのベース端子のゲート長及び前記第４のトランジスタのベース端子のゲート長が、前記第1のトランジスタのベース端子のゲート長及び前記第３のトランジスタのベース端子のゲート長よりも長いことを特徴とするバイアス生成回路。 A first current mirror circuit composed of a pair of NPN transistors, a second current mirror circuit composed of a pair of NPN transistors, and an operation based on the output current of the second current mirror circuit A bias generation circuit including a bias circuit,
A constant current is inputted to the collector terminal of the first transistor constituting the first current mirror circuit, and the second current mirror is inputted from the collector terminal of the second transistor constituting the first current mirror circuit. The current input to the circuit is output,
The output of the second transistor that constitutes the first current mirror circuit is input to the collector terminal of the third transistor that constitutes the second current mirror circuit, and the second transistor that constitutes the second current mirror circuit. The current input to the bias circuit is output from the collector terminal of the transistor No. 4;
The gate length of the base terminal of the second transistor and the gate length of the base terminal of the fourth transistor are greater than the gate length of the base terminal of the first transistor and the gate length of the base terminal of the third transistor. A bias generation circuit characterized by being long.
　請求項３記載のバイアス生成回路において、前記第２のトランジスタの出力する電流を第３のカレントミラー回路を介して前記第２のカレントミラー回路に入力し、前記第４のトランジスタの出力する電流を第４のカレントミラー回路を介して前記バイアス回路に入力することを特徴とするバイアス生成回路。 4. The bias generation circuit according to claim 3, wherein a current output from the second transistor is input to the second current mirror circuit through a third current mirror circuit, and a current output from the fourth transistor is input. A bias generation circuit, wherein the bias generation circuit inputs the bias circuit via a fourth current mirror circuit.
　第1の増幅器と、第２の増幅器と、第３の増幅器を直列に接続したパワーアンプモジュールであって、
　前記第1の増幅器と前記第２の増幅器の間には第１のバイアス発生回路が、前記第２の増幅器と前記第３の増幅器の間には第２のバイアス発生回路が存在し、
　前記第1のバイアス発生回路及び前記第２のバイアス発生回路のいずれか一方、または双方に請求項１ないし４のいずれか１に記載のバイアス生成回路が用いられていることを特徴とするパワーアンプモジュール。 A power amplifier module in which a first amplifier, a second amplifier, and a third amplifier are connected in series,
A first bias generation circuit exists between the first amplifier and the second amplifier, and a second bias generation circuit exists between the second amplifier and the third amplifier;
5. A power amplifier, wherein the bias generation circuit according to claim 1 is used in one or both of the first bias generation circuit and the second bias generation circuit. module.
　第1の増幅器と、第２の増幅器と、第３の増幅器を直列に接続したパワーアンプモジュールであって、
　前記第1の増幅器と前記第２の増幅器の間、または前記第２の増幅器と前記第３の増幅器の間にはバイアス発生回路が存在し、
　前記バイアス発生回路に請求項１ないし４のいずれか１に記載のバイアス生成回路が用いられていることを特徴とするパワーアンプモジュール。 A power amplifier module in which a first amplifier, a second amplifier, and a third amplifier are connected in series,
A bias generation circuit exists between the first amplifier and the second amplifier or between the second amplifier and the third amplifier;
5. A power amplifier module, wherein the bias generation circuit according to claim 1 is used in the bias generation circuit.
　請求項５または請求項６に記載のパワーアンプモジュールを含むことを特徴とする半導体装置。 A semiconductor device comprising the power amplifier module according to claim 5.
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