WO2011039859A1

WO2011039859A1 - Analog/digital converter and semiconductor integrated circuit device using the same

Info

Publication number: WO2011039859A1
Application number: PCT/JP2009/067044
Authority: WO
Inventors: 俊大島; 友美高橋
Original assignee: 株式会社日立製作所
Priority date: 2009-09-30
Filing date: 2009-09-30
Publication date: 2011-04-07
Also published as: JP5286420B2; JPWO2011039859A1

Abstract

Provided is a digital calibration type analog/digital converter formed by a main analog/digital converter and a reference analog/digital converter and having a high sample rate and a high resolution. The converter can reduce the power consumption and eliminate the need of a sample and hold circuit at the front end. For this, the converter compensates the affect of the skew between the sampling clocks of the main analog/digital converter and the reference analog/digital converter by post calibration by a skew correction unit.

Description

Analog-digital converter and semiconductor integrated circuit device using the same

The present invention relates to an analog-to-digital converter that samples an input analog signal at a predetermined rate to convert the analog signal into a digital signal having a predetermined resolution, and particularly to achieve both a high sample rate and a high resolution. The present invention relates to a digital calibration type analog-digital converter and a semiconductor integrated circuit device in which it is integrally formed on a semiconductor substrate together with other circuits.

Conventionally, as a time-interleaved analog-to-digital converter that attempts to achieve high sampling rate and high-resolution characteristics by operating multiple high-resolution analog-to-digital converters in parallel, the skew between the operation clocks of each analog-to-digital converter In some cases, the influence of the above is detected by digital Fourier transform (DFT), and then the influence is digitally canceled by a correction unit (see, for example, Patent Document 1).

Conventionally, as a time interleave type analog-digital converter, there is one that corrects a skew between operation clocks of each analog-digital converter by FIR filter processing (for example, see Patent Document 2).

Conventionally, as a time interleave type analog-digital converter, the actual skew amount between clocks of each analog-digital converter is detected by a phase comparison circuit and a digital filter, and the phase of one clock signal is variable delay element based on the detected amount of skew. In some cases, the clock skew is set to zero by adjusting (see, for example, Patent Document 3).

In addition, as a configuration for realizing a high-sample-rate and high-resolution analog-digital converter with a single-channel analog-digital converter, an auxiliary analog-digital converter is provided in addition to the main analog-digital converter. While the analog-digital converter periodically interrupts the conversion process for calibration, there is an auxiliary analog-digital converter that performs the conversion process (see, for example, Patent Document 4).

Conventionally, the main analog-to-digital converter and reference analog-to-digital converter connected in parallel to the input and the sample-and-hold circuit connected to the front end constitute an analog unit, and the main analog-to-digital converter Some digital outputs perform digital post-calibration (see, for example, Non-Patent Documents 1 and 2).

International Publication No. WO06 / 126672 Japanese Patent Application Laid-Open No. 2002-100808 JP 2008-011189 A Special table 2003-527027 gazette

An analog-to-digital converter with a high sample rate, high resolution, and low power consumption is a technology necessary for next-generation advanced medical equipment, next-generation wireless / wired communication, and the like. In order to realize such a high sample rate, high resolution analog-digital converter, there is a method of using a plurality of the same or different analog-digital converters.

FIG. 16 is a diagram uniquely created by the inventors of the present invention based on the diagram described in Patent Document 1. As shown in the figure, there is a time interleaved analog-digital converter that can realize a high sample rate and high resolution by operating a plurality of high-resolution analog-digital converters in parallel. However, in general, in time interleaved analog-digital converters, the effect of skew between the operation clocks of each analog-digital converter degrades the effective resolution. Therefore, in the example in this document, the effect is affected by digital Fourier transform (DFT). After the detection, the influence is digitally offset by the correction unit. However, since DFT processing requires a large amount of calculation, power consumption and mounting area can be tolerated like a measuring instrument rather than application to medical devices and IC chips for communication systems that require low power consumption. Suitable for the system.

FIG. 17 is a diagram uniquely created by the inventors of the present invention based on the diagram described in Patent Document 2. The configuration shown in the figure is also for correcting a skew between operation clocks of each analog-to-digital converter by FIR filter processing in a time-interleaved analog-to-digital converter. However, in this case, there is a problem that a multi-tap FIR filter is required to perform highly accurate skew correction. In particular, since it is necessary to determine each tap coefficient in the filter according to the correction amount, since there are many correction variables when the number of taps is large, the determination method is not easy. Patent Document 2 does not describe a specific method for determining tap coefficients, but for example, when LMS (Least Mean Square) algorithm control is performed, the convergence result of tap coefficients has a large signal dependency. Therefore, it is suitable for a system in which the input signal has a relatively steady pattern rather than a system in which the amplitude and frequency of the input analog signal change irregularly, such as a medical device and a communication system.

FIG. 18 is a diagram uniquely created by the inventors of the present invention based on the diagram described in Patent Document 3. As shown in the figure, in the time interleave type analog-digital converter, the actual skew amount between the clocks of each analog-digital converter is detected by the phase comparison circuit and the digital filter, and based on that, one of the clock signals is converted. There is also a method in which the clock skew is zero by adjusting the phase with a variable delay element. In this method, since one delay step unit by the variable delay element is discrete, the number of stages of the variable delay element becomes large when highly accurate correction is performed. Therefore, it is considered suitable for realizing a resolution up to about 10 bits.

In addition to the above-described problems individually, the time interleave type analog-digital converter requires a plurality of the same analog-digital converters, and thus has a problem of large area and power consumption. Therefore, it can only be realized by a non-time interleave type, that is, a single channel analog-digital converter.

For example, FIG. 15 is a diagram uniquely created by the inventor of the present invention based on the diagram described in Patent Document 4, which is a single-channel analog-digital converter with a high sample rate and high resolution. A method for implementing an analog-to-digital converter is disclosed. This analog-to-digital converter has an auxiliary analog-to-digital converter in addition to the main analog-to-digital converter, while the main analog-to-digital converter interrupts the conversion process periodically for calibration. This is a method in which an auxiliary analog-digital converter substitutes the conversion process. However, in this method, the calibration opportunities given to the main analog-digital converter are limited, so that the calibration becomes insufficient or it takes a long time to converge the calibration.

On the other hand, FIG. 19 is a diagram originally created by the inventor of the present invention based on the diagrams described in Non-Patent Document 1 and Non-Patent Document 2. In the configuration of FIG. The main analog-to-digital converter, the reference analog-to-digital converter, and the sample-and-hold circuit connected to the front end form an analog unit, and the digital output of the main analog-to-digital converter is digital post-calibrated, resulting in high sampling. A rate high-resolution analog-to-digital converter is realized. First, the front-end sample and hold circuit 191 repeats sampling and holding of the input analog signal in synchronization with a signal having a frequency equal to the sample rate (f _CLK ). The reference analog-digital converter 193 and the main analog-digital converter 192 convert the voltage value held at the output of the sample and hold circuit 191 into a digital value, respectively, and output the digital value. Here, the main analog-digital converter 192 performs a sampling clock with a frequency f _CLK , and the reference analog-digital converter 193 performs an analog-digital conversion with a sampling clock with a frequency f _CLK / M that is M times slower. Further, the sampling of both analog-digital converters is synchronized by aligning the edges of both clocks. The digital output of the main analog / digital converter 192 is corrected by the digital output generator 193 and then output as the output of the entire analog / digital converter. In the digital output generation unit 193, for example, an inner product operation between the digital output D _i of the main analog-digital converter and the weight vector W _i is performed. Weight vector W _i is as follows, for example, obtained by the LMS algorithm. That is, taking the difference between the outputs of the reference analog-digital conversion unit 1910 of the digital output generation unit 193, the result as a conversion error, to form a negative feedback loop to update the value of the current weight vector W _i on the basis thereof . Specifically, in order to perform negative feedback control, the code conversion of the conversion error is performed by the code conversion unit 197, and then the step size m _W of the LMS algorithm and the output D _{i of the} main analog-digital converter 192 are added thereto. Are multiplied by an integrator composed of a delay unit 194 and an adder 195. This integration result is used as the above weight vector W _i for D _i . Since the above forms a negative feedback loop, the digital output generation unit 193 is automatically updated until the output of the digital output generation unit 193 becomes equal to the output of the reference analog digital unit 1910, that is, until the weight W _i becomes an appropriate value. . As a result, after convergence of the algorithm, the output of the digital output generator 193 has a high sample rate equal to the sample rate of the main analog-to-digital converter 191 and a high-resolution equivalent to the resolution of the reference analog-to-digital converter 1910. An analog-digital conversion result can be obtained. Even if the operational amplifier used in the analog circuit section of the main analog-to-digital converter 192 has a finite gain or non-linear characteristics, the effect is linear using the appropriate weight vector Wi determined by the LMS algorithm. Compensation is performed by performing correction processing in the correction unit 12. Therefore, the operational amplifier of the main analog-digital converter 192 is not required to have a high gain, so that power consumption can be reduced. On the other hand, the reference analog-to-digital converter 1910 may operate M times slower than the main analog-to-digital converter 192, so that the operational amplifier used does not need to have a wide bandwidth and still consumes low power.

In this method, unlike the case of Patent Document 4, sufficient calibration accuracy can be achieved with a small convergence time. However, it is assumed that the main analog-to-digital converter 192 and the reference analog-to-digital converter 1910 sample the same voltage value. Therefore, in order to avoid the sampling voltage error due to the skew between the sampling clocks of both analog-digital converters, it is necessary to fix the voltage value for a certain period by the sample-and-hold circuit 1910 of the front end as described above. In particular, analog-to-digital converters required for next-generation advanced medical devices and next-generation wireless / wired communication systems require a sample rate of 50 MS / s or higher and a resolution of 10 bits or higher. An excessive load is applied. That is, in order to achieve high-speed operation of the sample and hold circuit, the operational amplifier used needs to have a wide band, and in order to hold the voltage with high accuracy, the operational amplifier needs to have a high gain. This is because such a broadband and high gain operational amplifier consumes a large amount of power or is physically unrealizable.

In order to realize a high sample rate and high resolution analog-digital converter, a time interleaved analog converter can be considered, but it requires a large chip area and power consumption. A single-channel digital calibration analog-digital converter using a main analog-digital converter and a reference analog-digital converter is more advantageous than a time-interleaved analog-digital converter in terms of area and power consumption. If the sample rate exceeds 50 MS / s, the demand for the front-end sample and hold circuit becomes strict and the power consumption increases.

For example, in the case of a 50 MS / s digital calibration type analog-digital converter, the sample and hold circuit occupies about 1/4 of the total power consumption. At higher sample rates, the percentage of total power consumption is expected to increase rapidly.

An example of a representative example of the present invention is as follows. That is, the analog-digital converter of the present invention is connected to a high-speed, low-precision main analog-digital converter connected in parallel to the input, a low-speed, high-precision reference analog-digital converter, and an output of the main analog-digital converter. And a digital skew correction unit connected to the linearity correction unit, wherein the linearity correction unit and the skew correction unit are the main analog-to-digital converter and the reference It is controlled based on the difference between the conversion outputs of the analog-digital converter, and allows a sampling timing of the main analog-digital converter and the reference analog-digital converter to be skewed.

The semiconductor integrated circuit device of the present invention is connected to a high-speed and low-precision main analog-digital converter connected in parallel to an input, a low-speed and high-precision reference analog-digital converter, and an output of the main analog-digital converter. The analog front-end constituting the probe unit of the ultrasonic diagnostic apparatus has an analog-to-digital converter having a digital linearity correction unit and a digital skew correction unit connected to the linearity correction unit. In the semiconductor integrated circuit device used, the linearity correction unit and the skew correction unit are controlled based on a difference in conversion output between the main analog-digital converter and the reference analog-digital converter, and Occurs between sampling timings of the main analog-digital converter and the reference analog-digital converter Characterized in that to compensate for the effects of that skew.

According to the present invention, an analog-digital converter having a high sample rate (for example, 50 MS / s or more) and a high resolution (for example, 10 bits or more) can be realized with low power consumption.

It is a figure which shows the block configuration of the 1st Example of the analog-digital converter of this invention. It is a figure which shows the block configuration of the 2nd Example of the analog-digital converter of this invention. FIG. 3 is a diagram showing details of a configuration example of a skew primary correction unit 13 in FIGS. 1 and 2. FIG. 3 is a diagram illustrating details of one configuration example of the skew secondary correction unit 14 of FIGS. 1 and 2 and a connection relationship with the skew primary correction unit 13; A third embodiment of the analog-digital converter of the present invention, which is an example in which at least one of the time first-order differentiator 34 and the time second-order differentiator 42 of FIGS. 3 and 4 is configured by a K + 1 tap FIR filter. FIG. It is a figure which shows the 4th Example of the analog / digital converter of this invention which applied another structural example to the skew primary correction | amendment part 13 of FIG. 1 and FIG. It is a figure which shows the example of 1 structure of the FIR filter 61 of FIG. It is a figure which shows the block configuration of the 5th Example of the analog-digital converter of this invention. It is a figure which shows the block configuration of the 6th Example of the analog-digital converter of this invention. It is a figure which shows the block configuration of the 7th Example of the analog-digital converter of this invention. It is a figure which shows the block configuration of the 8th Example of the analog-digital converter of this invention. FIG. 12 is a diagram illustrating details of a configuration example of a primary error correction unit 103 in FIGS. 10 and 11. FIG. 12 is a diagram illustrating details of a configuration example of a secondary error correction unit 104 in FIGS. 10 and 11. It is a figure which shows the block configuration of the 9th Example which is an example which applied the analog-digital converter of this invention to the probe part of the ultrasound diagnosing device. It is a figure which shows an example of the analog-digital converter examined prior to this invention based on the prior art. It is a figure which shows another example of the analog-digital converter examined prior to this invention based on the prior art. It is a figure which shows another example of the analog-digital converter examined prior to this invention based on the prior art. It is a figure which shows another example of the analog-digital converter examined prior to this invention based on the prior art. It is a figure which shows another example of the analog-digital converter examined prior to this invention based on the prior art. It is a figure which shows the detail of the example of 1 structure of the linearity correction | amendment part 12 of FIG. 1 and FIG.

The present invention eliminates the sample-and-hold circuit at the front end that becomes a bottleneck in the configurations shown in

Non-Patent Documents

1 and 2, and instead, between the sampling clocks of the main analog-digital converter and the reference analog-digital converter. The effect of the skew is offset by post-calibration by the skew correction unit. Correction of the skew is performed subsequent to the correction by the weight vector W _i. In addition, the correction is performed up to the high-order correction of the influence of the skew.

Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. The analog input is directly connected to the main analog-to-digital converter 11 and the reference analog-to-digital converter 15 without going through the front-end sample and hold circuit. The main analog-to-digital converter 11 performs a sampling clock with a frequency f _CLK , and the reference analog-to-digital converter 15 performs analog-to-digital conversion with a sampling clock with a frequency f _CLK / M that is M times slower. Further, by matching the edges of both clocks, the sampling of both analog-digital converters is synchronized as much as possible. The linearity correction unit 12 corrects the non-linearity of the digital output of the main analog / digital converter 11 due to the deterioration of the analog circuit unit of the main analog / digital converter 11. The output of the linearity correction unit 12 is input to the skew primary correction unit 13, and the primary term of the influence of the skew between the sampling clocks of the main analog-digital converter 11 and the reference analog-digital converter 15 is corrected. The output of the skew primary correction unit 13 is connected to the skew secondary correction unit 14, and the secondary term of the influence of the skew is corrected. The signal from which the influence of the skew is removed by the skew correction is compared with an ideal analog-digital conversion output by the reference analog-digital converter 15 by the subtractor 16, and the difference is calculated as a conversion error. This error signal is used as follows in order to perform control by the LMS algorithm in the linearity correction unit 12, the skew primary correction unit 13, and the skew secondary correction unit 14. First, the operation of the linearity correction unit 12 will be described. FIG. 20 shows a configuration example of the linearity correction unit 12. This configuration and operation are the same as the description of the digital output generation unit 193 in Non-Patent Document 1 (FIG. 19).

In the linearity correction unit 12, for example, an inner product operation between the digital output D _{i of the} main analog-digital converter 11 and the weight vector W _i is performed. Weight vector W _i is as follows, for example, obtained by the LMS algorithm. That is, in order to the negative feedback control, after code conversion of the conversion error in the code conversion unit 197, to the output D _i of the step size m _W and the main analog-to-digital converter 11 of the LMS algorithm are multiplied The multiplication output is integrated by an integrator composed of a delay unit 194 and an adder 195. This integration result is used as the above weight vector W _i for D _i .

Next, details of the skew primary correction unit 13 will be described with reference to FIG. FIG. 3 shows an example of a skew primary correction unit. An input signal to the skew primary correction unit is subjected to time first-order differentiation in a time first-order differentiator 34. On the other hand, in order to compensate for the delay in the time first-order differentiator 34, the input signal is delayed in the delay unit 31 for a predetermined time. For example, when the time first-order differentiator 34 is realized by a K + 1 tap FIR filter as will be described later, the delay unit 31 performs K sample delay in order to compensate for a delay corresponding to K sample periods. The output of the delay unit 31 is down-sampled once in M times by the M-times down-sampler 32 in order to synchronize the outputs of the main analog-digital converter 11 and the reference analog-digital converter 15. The subtractor 33 subtracts the skew primary correction signal supplied from the multiplier 38 from the output of the M-times downsampler 32 to obtain an output in which the primary term due to the skew is corrected. The skew primary correction signal is obtained by the LMS algorithm as follows, for example. That is, the conversion error, the step size m _skew of the LMS algorithm, and the output of the time first-order differentiator 34 are multiplied in the multiplier 35, and the multiplication output is integrated by an integrator composed of a delay device 37 and an adder 36. Is done. Since the integration result gives the clock skew Δt, the skew primary correction signal is obtained by multiplying this by the output of the time first-order differentiator 34. As described above, correction according to [Equation 1] is performed.

Since the above forms a negative feedback loop, it is automatically updated until the output of the skew primary correction unit 13 becomes equal to the output of the reference analog / digital unit 15, that is, until the skew Δt becomes an appropriate value. .

Next, as shown in FIG. 1, for example, a case where the correction up to the secondary correction of the influence of the skew is performed will be described. In this case, primary correction and secondary correction are performed with the configuration shown in FIG. Since the primary correction is the same as described above, the secondary correction will be mainly described below. In order to perform secondary correction, the input signal is connected not only to the time first-order differentiator 34 but also to the time second-order differentiator 42. The input signal is delayed by a predetermined time in the delay unit 31 in order to compensate for the delay in the time first-order differentiator 34 and the time second-order differentiator 42. For example, when the time first-order differentiator 34 and the time second-order differentiator 42 are realized by a K + 1 tap FIR filter as will be described later, in order to compensate for a delay corresponding to K sample periods, the delay device 31 Perform K sample delay. The output of the delay unit 31 is down-sampled once in M times by the M-times down-sampler 32 in order to synchronize the outputs of the main analog-digital converter 11 and the reference analog-digital converter 15. The subtracter 33 subtracts the skew primary correction signal supplied from the multiplier 38 from the output of the M-times downsampler 32 to obtain an output in which the primary term due to the skew is corrected. The adder 41 further adds the skew second correction signal supplied from the multiplier 46 to the first corrected output, and an output corrected to the second order term due to the influence of the skew is obtained. Similar to the skew primary correction signal, the skew secondary correction signal is obtained by the LMS algorithm as follows, for example. That is, the conversion error, the step size m _skew2 of the LMS algorithm and the output of the time second-order differentiator 42 are multiplied in the multiplier 44, and the multiplication output is integrated by an integrator composed of the delay unit 42 and the adder 43. Is done. The integration result is to provide the second order term Delta] t ^2/2 of the clock skew to this, by multiplying the output of the time second-order differentiator 42, it said skew secondary correction signal is obtained. As described above, the correction up to the second order by [Equation 2] is performed.

As a result, even if there is a skew between the sampling clocks of the main analog-to-digital converter 11 and the reference analog-to-digital converter, the effect is compensated by the skew correction unit, so calibration in the linearity correction unit 12 is normal. Can be carried out. This eliminates the need for a front-end sample and hold circuit. In this embodiment, the output of the linearity correction unit 12 is the output of the entire analog-digital converter.

FIG. 2 shows a second embodiment of the present invention. In the first embodiment, a signal that has undergone only linearity correction before skew correction is used as a conversion output, whereas in this embodiment, a signal after skew correction is used as a conversion output. As described above, the skew correction itself is necessary to justify the difference between the output of the main analog-digital converter and the output of the reference analog-digital converter as an error signal. Since the absolute phase of the sampling timing is not required, it can be performed before and after skew correction in this way. The advantage of using the conversion output before skew correction as in the first embodiment is that the skew correction is used only for calibration in this case. Therefore, the skew primary correction unit and the skew secondary correction shown in FIGS. As shown in the figure, the main operation may be performed at an operation rate of f _CLK / M. Thereby, power consumption can be reduced. On the other hand, when the post-skew correction is used as the conversion output as in this embodiment, for example, in the skew primary correction unit and the skew secondary correction unit in FIG. The multiplier 46, the adder 33, and the adder 41 need to operate at the full rate f _CLK . However, in this embodiment, since the input to the subtractor 16 for calculating the conversion error is used as the conversion output, the value is always such that the average difference from the output of the reference analog-digital converter 15 is minimized. It has become. Therefore, when the influence of higher-order skew is more noticeable than when it is mounted, or when other analog degradation factors that do not ride on the main calibration occur in the main analog-to-digital converter 11, this embodiment is the first embodiment. Thus, it is considered that high conversion accuracy can be maintained.

As a third embodiment of the present invention, FIG. 5 shows a configuration example of a time first-order differentiator and a time second-order differentiator. Both the time first-order differentiator and time second-order differentiator are represented by the K + 1 tap FIR filter shown in the figure. The inputs are delayed by 1, 2, 3, K-1, K samples by

delay units

51, 52, 53, 54, 55, respectively, and the input and each delayed output are respectively M times downsamplers 512, 513, 514, 515, 516, and 517, and the value is held once every M times so that the conversion outputs of the main analog-digital converter and the reference analog-digital converter are synchronized. The outputs of these downsamplers are connected to multipliers 56, 57, 58, 59, 510, and 511, and multiply by tap coefficients tap ₀ , tap ₁ , tap ₂ , tap ₃ , tap _K-1 and tap _K , respectively. Is done. All the multiplication outputs are added in the adder 518, and become a time first-order differential output or a time second-order differential output.

In the case of a time first-order differentiator, the theoretical tap coefficients derived from the sampling theorem are as shown in [Equation 3] and [Equation 4] below.

Actually, in order to alleviate the truncation error due to a finite number of taps, for example, [Formula 6] obtained by multiplying a well-known window function (function taking [Formula 5] as an example) is finally obtained. It may be implemented as a tap coefficient. [Equation 5] is an example in the case of a Hamming window function having a coefficient of 0.54.

Further, tap coefficients for realizing the time second-order differentiator are as shown in the following [Equation 7] and [Equation 8].

FIG. 6 shows a fourth embodiment of the present invention. In this embodiment, instead of subtracting the skew primary correction signal by the subtractor 33 using the time first-order differentiator 34 in the skew primary correction unit 13 described in FIG. This is a case where the skew is compensated by performing a time delay corresponding to the skew between the sampling clocks of the main analog-digital converter and the reference analog-digital converter using the filter 61.

FIG. 7 shows a configuration example of the FIR filter 61. The inputs are delayed by 1, 2, 3, K-1, K samples by

delay units

71, 72, 73, 74, 75, respectively, and the input and each delayed output are multiplied by

multipliers

76, 77, 78, 79, 710 and 711 are multiplied by tap coefficients tap _{0_est} , tap ₁ , tap ₂ , tap ₃ , tap _K−1 and tap _K , respectively. All the multiplication outputs are added in the adder 712 and become the output of the FIR filter 61.

The input signal to the skew correction unit (FIG. 6) is delayed by the FIR filter 61, and then synchronized with the conversion output of the main analog-digital converter and the reference analog-digital converter in the M-times down sampler 32. Once every M times, the value is retained and output. The delay amount in the FIR filter 61 is determined according to the tap coefficient. The tap coefficient may be obtained by, for example, an LMS algorithm as follows. That is, the conversion error, the step size m _tap0 of the LMS algorithm, and the input signal tap _{0_in} to the tap 0 in the FIR filter 61 are multiplied in the multiplier 35, and the multiplication output is the delay device 37 and the adder. It is integrated by an integrator consisting of 36. This integration result gives the tap coefficient tap _{0_est} for tap 0 in the FIR filter 61. After the algorithm has converged, tap _{0_est} converges to a value that can absorb the influence of the clock skew between the sampling clocks of the main analog-digital converter and the reference analog-digital converter. Note that tap coefficient estimation by such an LMS algorithm may be performed not only for tap 0 in the FIR filter 61 but also for each tap as necessary. The final convergence value of each tap coefficient has signal dependence, and the analog-digital converter of this embodiment is effective in a system in which an input analog signal has a relatively steady pattern.

FIG. 8 shows a fifth embodiment of the present invention. The present embodiment shows an example in which the main analog-digital converter is realized as the pipeline type analog-digital converter 81 in the above-described embodiments. The pipeline type analog-digital converter has a configuration in which unit analog circuit blocks called MDAC (Multiplying DAC) are connected in cascade. Each MDAC is composed of an operational amplifier and a plurality of capacitive elements, and the digital output of the pipelined analog-digital converter 81 is in an uncorrected state due to the low gain of this operational amplifier and the effect of the ratio accuracy mismatch between the capacitive elements. Then it becomes non-linear. The linearity correction unit 82 can correct this non-linearity as described in the previous embodiments. Further, when the operational amplifier has not only low gain but also nonlinearity, the correction in the linearity correction unit 82 may be extended to a higher order. Further, the linearity correction unit 82 may correct a DC offset voltage caused by an operational amplifier DC offset voltage or the like.

FIG. 9 shows a sixth embodiment of the present invention. The present embodiment shows an example in which the main analog-digital converter is realized as a successive approximation type analog-digital converter (SAR) 91 in the above-described embodiments. The SAR is composed of a capacitive array and a comparator. If there is a mismatch in the capacitance value between the capacitive elements constituting the capacitive array, the SAR becomes non-linear in an uncorrected state. The linearity correction unit 82 can correct this non-linearity as described in the previous embodiments. The linearity correction unit 82 may also correct the DC offset voltage caused by the offset voltage of the comparator.

FIG. 10 shows a seventh embodiment of the present invention. This embodiment shows an example in which the main analog-digital converter and the reference analog-digital converter are realized by a sigma-delta analog-digital converter. The main analog-digital converter is configured as, for example, a third-order cascaded sigma-delta modulator including a first-stage second-order sigma-delta modulator 101 and a first-stage first-order sigma-delta modulator 102. For example, the primary error correction unit 103 is connected to the conversion output of the first stage sigma delta modulator 101, and the secondary error correction unit 104 is connected to the conversion output of the next stage sigma delta modulator 102, for example. After each error correction, these differences are obtained by the subtractor 105, and third-order noise shaping is performed on the quantization noise generated by the quantizer inside the modulator while maintaining the quality of the input signal. As a result, a high resolution conversion output can be obtained from the output of the LPF 1010 for removing quantization noise. This conversion output is subjected to correction processing by a skew correction unit 1011 in order to compensate for the influence of skew between the first stage sigma delta modulator 101 of the main path and the sampling clock of the low-speed sample and hold circuit 106 of the reference path described later. Is called. This correction process is the same as that described with reference to FIG. The primary error correction unit 103 and the secondary error correction unit 104 perform corrections according to the deterioration of the analog circuit unit generated in the next stage sigma delta modulator 102 and the first stage sigma delta modulator 101, respectively. Examples of the deterioration factor include a finite gain of an operational amplifier, a finite band of an operational amplifier and a switch, and a specific accuracy mismatch of capacitances. In order to determine the correction amount in the primary error correction unit 103 and the secondary error correction unit 104, for example, an LMS algorithm can be used. In order to obtain a reference conversion output for this purpose, the analog input signal is also input to the reference path. That is, first, an input analog signal is periodically sampled and held by an analog voltage value in a low-speed sample-and-hold circuit 106 that operates with a low-speed clock of f _CLK / M, and an output thereof is a reference sigma-delta modulator 107. Is converted to analog to digital. Further, the LPF2 (109) suppresses the quantization noise noise-shaped in the high-frequency region in the reference sigma-delta modulator 107, and a high-resolution reference conversion output is obtained. The error between the main path conversion output and the reference conversion output obtained in this way is calculated by the subtractor 108, and the primary error correction unit 103 and the secondary error correction unit 104 are controlled based on the conversion error. Is done. As a result, even if degradation occurs in the analog circuit section of the first-stage sigma-delta modulator 101 or the next-stage sigma-delta modulator 102, after the convergence of the algorithm, the correction to compensate for the influence is corrected by the primary error correction section 103 or the secondary Since it can be implemented by the error correction unit 104, a high-resolution output can be maintained. In this embodiment, the low speed sample and hold circuit 106 is used to band limit the analog input signal. Thereby, the band of LPF2 (109) can be narrowed, so that a reference conversion output with high resolution can be supplied without increasing the order of the reference sigma-delta modulator 107 and the number of bits of the quantizer.

In the present embodiment, as specific examples of the primary error correction unit 103 and the secondary error correction unit 104 in FIG. 10, for example, the configurations shown in FIGS. 12 and 13 may be used, respectively.

In the primary error correction unit 103 shown in FIG. 12, the input is first delayed by one sample by the delay unit 121, and then multiplied by the correction coefficient a by the multiplier 122 and output. This correction coefficient a can be obtained by, for example, an LMS algorithm. That is, the above conversion error is subjected to negative feedback control, and after sign inversion by the sign inversion unit 126, it is multiplied by the multiplier 125 together with the step size m _a of the LMS algorithm and the output signal of the delay unit 121, The multiplication output is integrated by an integrator composed of a delay unit 123 and an adder 124. This integration result gives a correction coefficient a. After the algorithm has converged, the correction coefficient a converges to a value that can absorb the influence of the above-described analog degradation that occurs in the first-stage sigma-delta modulator 101 and the next-stage sigma-delta modulator 102.

In the secondary error correction unit 104 shown in FIG. 13, the input signal is multiplied by the correction coefficient b0 by the multiplier 1311. The input signal is delayed by one sample by the one-sample delay unit 136 and then multiplied by the correction coefficient b1 by the multiplier 137. Further, the input signal is delayed by the two-sample delay unit 131 and then multiplied by the correction coefficient b2 in the multiplier 132. These multiplication outputs are added by an adder 1315 and output. Note that the correction coefficients b0, b1, and b2 may be obtained by, for example, the LMS algorithm, similarly to the correction coefficient a described with reference to FIG.

FIG. 11 shows an eighth embodiment of the present invention. In this embodiment, the conversion output in the seventh embodiment is taken not from the input of the skew correction unit 1011 but from the output of the skew correction unit 1011. The advantages of the seventh embodiment and the eighth embodiment are the same as those described in the second embodiment.

In the present embodiment, as specific examples of the primary error correction unit 103 and the secondary error correction unit 104 in FIG. 11, for example, the configurations shown in FIGS. 12 and 13 may be used, respectively.

As described above, according to each embodiment of the present invention, a sample-and-hold circuit for a bottleneck is not necessary. For example, a sample rate of 50 MS predicted to be necessary for a next-generation advanced medical device, a next-generation wireless / wired communication system, etc. An analog-to-digital converter with a resolution of 10 bits or more can be realized with low power consumption.

9 shows a ninth embodiment of the present invention. The present embodiment shows an example in which the above analog-digital converter is applied to, for example, a probe unit of an ultrasonic diagnostic apparatus. The digital signal generated by the digital signal processing unit 148 is converted to an analog signal by the digital / analog converter 147, shaped by the transmission LPF (TLPF) 146, then amplified to a high voltage waveform by the power amplifier 145, and switched. It is emitted as an ultrasonic signal via the unit 141. The ultrasonic signal is reflected by the object to be measured, and then arrives again at the switch unit 141 as a weak signal, and is first amplified by the low noise amplifier 142. Further, after the interference signal is suppressed by the reception LPF (RLPF) 143, it is input to the analog-digital converter 144. The conversion output of the analog-digital converter 144 is transmitted to the digital signal processing unit 148, and necessary digital signal processing is performed. In this embodiment, as the analog-to-digital converter 144, a digital calibration type analog-to-digital converter that does not require a front-end sample-and-hold circuit described in each embodiment is used.

The probe unit for the ultrasonic diagnostic apparatus of this embodiment includes a digital signal processing unit 148, a digital / analog converter 147, a transmission LPF (TLPF) 146, a power amplifier 145, a low noise amplifier 142, a reception LPF (RLPF) 143, and an analog A part or all of the digital converter 144 may be realized as a semiconductor integrated circuit device formed integrally on a common semiconductor substrate. By doing so, further miniaturization of the ultrasonic diagnostic apparatus is expected.

According to the present embodiment, it is possible to ensure the resolution of the ultrasonic diagnostic apparatus (such as the resolution of the diagnostic image) with low power consumption. Since it is important to reduce power consumption in an ultrasonic diagnostic apparatus, the present invention that can reduce power consumption by eliminating the need for front-end sample-and-hold is effective.

11 Main analog-digital converter,
12 linearity correction unit,
13 Skew primary correction unit,
14 Skew secondary correction part,
15 Analog-to-digital converter for reference,
16 Subtractor,
31 delay,
32M down sampler,
33 Subtractor,
34 hour first-order differentiator,
35 multiplier,
36 adder,
37 delay,
38 multiplier,
41 adder,
42 hour second-order differentiator,
43 Adder,
44 multiplier,
45 delay,
46 multiplier,
51 delay,
52 delay,
53 delay,
54 delay,
55 delay,
56 multiplier,
57 multiplier,
58 multiplier,
59 multiplier,
510 multiplier,
511 multiplier,
512 M times downsampler,
513 M times down sampler,
514 M times downsampler,
515 M times down sampler,
516 M down sampler,
517 M times down sampler,
518 adder,
61 FIR filter,
71 delay,
72 delay,
73 delay,
74 delay,
75 delay,
76 multiplier,
77 multiplier,
78 multiplier,
79 multiplier,
710 multiplier,
711 multiplier,
712 adder,
81 Pipeline type analog-digital converter,
82 linearity correction unit,
83 Time differentiator,
84 delay,
85 M times down sampler,
86 adder,
87 Analog-to-digital converter for reference,
88 subtractors,
89 multiplier,
810 adder,
811 delay,
812 multiplier,
813 sign reverser,
814 multiplier,
815 adder,
816 delay,
91 successive approximation type analog-digital converter,
101 second-order sigma-delta modulator,
102 first-order sigma-delta modulator,
103 primary error correction unit,
104 secondary error correction unit,
105 subtractor,
106 Low-speed sample and hold circuit,
107 sigma delta modulator for reference,
108 Subtractor,
109 LPF2,
1010 LPF,
1011 skew correction unit,
121 delay,
122 multiplier,
123 delay,
124 adder,
125 multiplier,
126 sign inverting unit,
131 2-sample delay,
132 multipliers,
133 delay,
134 adder,
135 multiplier,
136 1 sample delay,
137 multiplier,
138 delay,
139 adder,
1310 multiplier,
1311 multiplier,
1312 delay,
1313 adder,
1314 multiplier,
1315 adder,
141 switch part,
142 low noise amplifier,
143 LPF (RLPF),
144 analog-digital converter,
145 power amplifier,
146 Transmission LPF (TLPF),
147 digital analog converter,
148 Digital signal processor,
191 Sample and hold circuit,
192 Main analog-digital converter,
193 Reference analog to digital converter,
194 delay,
195 adder,
196 multiplier,
197 code conversion unit,
198 M times down sampler,
199 subtractor,
1910 Reference analog to digital converter,
211 Sample and hold circuit

Claims

A high-speed, low-precision main analog-to-digital converter connected in parallel to the input,
A low-speed, high-precision analog-to-digital converter for reference,
A digital linearity correction unit connected to the output of the main analog-to-digital converter;
A digital skew correction unit connected to the linearity correction unit,
The linearity correction unit and the skew correction unit are controlled based on a difference between conversion outputs of the main analog-digital converter and the reference analog-digital converter, and the main analog-digital converter and the reference analog-digital conversion An analog-to-digital converter characterized by allowing a skew in the sampling timing of the device.
In claim 1,
An analog-digital converter characterized in that the output of the linearity correction unit is an analog-digital conversion output.
In claim 1,
An analog-digital converter characterized in that the output of the skew correction unit is an analog-digital conversion output.
In claim 1,
An analog-to-digital converter characterized in that linearity correction in the linearity correction unit and skew correction in the skew correction unit are performed by an LMS (Least Mean Square) algorithm.
In claim 1,
The analog-to-digital converter characterized in that the skew correction in the skew correction unit also performs second-order or higher correction.
In claim 1,
The analog-to-digital converter characterized in that the linearity correction in the linearity correction unit also performs second-order or higher correction.
In claim 1,
An analog-to-digital converter, wherein the skew correction in the skew correction unit is performed using a time differentiator.
In claim 7,
An analog-to-digital converter, wherein the time differentiator is realized with a FIR (Finite Impulse Response) filter configuration.
In claim 8,
An analog-to-digital converter, wherein a tap coefficient of the FIR (Finite Impulse Response) filter is a value obtained by multiplying a value derived from a sampling theorem by a window function.
In claim 5,
An analog-to-digital converter using a time differentiator for the first-order correction of the skew and a second-order time differentiator for the second-order correction.
In claim 10,
An analog-to-digital converter using an n-th time differentiator for time for correcting the n-th skew (n is an integer of 3 or more) of the skew.
In claim 1,
An analog-to-digital converter characterized in that the skew correction in the skew correction unit is performed by a time delay by an FIR filter.
In claim 12,
An analog-to-digital converter, wherein a tap coefficient of the FIR filter is obtained by an LMS algorithm.
In claim 1,
A pipelined analog-digital converter is used as the main analog-digital converter.
In claim 1,
A successive approximation analog-to-digital converter is used as the main analog-to-digital converter.
In claim 1,
As the main analog-digital converter, a cascade type sigma-delta analog-digital converter is used,
The cascade type sigma-delta analog-digital converter includes a plurality of cascade-connected sigma-delta modulators and error correction units subsequent thereto,
Each of the error correction sections is controlled based on a difference between the main analog-digital converter and the reference analog-digital converter.
In claim 16,
Each of the error correction units is controlled by an LMS algorithm.
A high-speed, low-precision main analog-to-digital converter connected in parallel to the input,
A low-speed, high-precision analog-to-digital converter for reference,
A digital linearity correction unit connected to the output of the main analog-to-digital converter;
A semiconductor integrated circuit device used in an analog front end that comprises an analog-to-digital converter having a digital skew correction unit connected to the linearity correction unit and constitutes a probe unit of an ultrasonic diagnostic apparatus,
The linearity correction unit and the skew correction unit are controlled based on a difference in conversion output between the main analog-digital converter and the reference analog-digital converter, and the main analog-digital converter and the reference A semiconductor integrated circuit device which compensates for an influence of a skew generated between sampling timings with an analog / digital converter.