WO2011036841A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2011036841A1
WO2011036841A1 PCT/JP2010/004821 JP2010004821W WO2011036841A1 WO 2011036841 A1 WO2011036841 A1 WO 2011036841A1 JP 2010004821 W JP2010004821 W JP 2010004821W WO 2011036841 A1 WO2011036841 A1 WO 2011036841A1
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Prior art keywords
film
semiconductor device
insulating film
dielectric constant
high dielectric
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PCT/JP2010/004821
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French (fr)
Japanese (ja)
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竹岡慎治
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a cap film containing a metal that changes a threshold voltage of a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.
  • MIS Metal Insulator Semiconductor
  • a silicon oxide film or a silicon oxynitride film is used as the gate insulating film.
  • EOT Equivalent Oxide Thickness
  • the gate leakage current increases, causing a problem that the power consumption of the circuit increases.
  • a transistor having a high dielectric constant film and a metal gate electrode a metal gate electrode is not a silicon electrode but a gate electrode made of a metal material such as titanium nitride or tantalum nitride
  • One of the problems in realizing a transistor having a high dielectric constant film and a metal gate electrode is control of the threshold voltage of the transistor.
  • the work function of the silicon electrode is adjusted by implanting impurity ions, thereby realizing a threshold voltage suitable for each of the N-type FET and the P-type FET. That is, for an N-type FET, the work function of the silicon electrode is reduced by injecting an N-type impurity such as arsenic or phosphorus into the silicon electrode.
  • an N-type FET For a P-type FET, boron or the like is used for the silicon electrode.
  • the work function of the silicon electrode is increased by implanting P-type impurities.
  • the metal gate electrode cannot control the work function by implanting impurity ions. Therefore, when a metal gate electrode is used as the gate electrode, control of the threshold voltage of the transistor is a big problem.
  • the threshold voltage is described as an absolute value in order to uniformly express the change in the threshold voltage in the N-type FET and the P-type FET.
  • the threshold voltage decreases (decreases) or the threshold voltage decreases”. Is described as "the threshold voltage increases or the threshold voltage increases”.
  • Non-Patent Document 1 discloses a method for controlling a threshold voltage in a transistor having a high dielectric constant film and a metal gate electrode.
  • a transistor having a high dielectric constant film and a metal gate electrode In the transistor disclosed in Non-Patent Document 1, an oxide film and a high dielectric constant film are sequentially formed on an element formation region, and this transistor has an electric dipole at the interface between the oxide film and the high dielectric constant film.
  • a metal oxide film (cap film) to be generated is provided.
  • FIG. 8 is a plan view of a conventional semiconductor device having a cap film.
  • 9A is a cross-sectional view taken along the line IXA-IXA shown in FIG. 8
  • FIG. 9B is a cross-sectional view taken along the line IXB-IXB shown in FIG. 8 and 9A
  • NFET indicates a region where an N-type MIS transistor is formed
  • STI indicates an element isolation region.
  • S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively
  • W” and “L” indicate a gate width and a gate length, respectively. Yes.
  • a trench 701 is formed in a silicon substrate 700.
  • An element isolation insulating film 703 is formed in the trench 701 via a base insulating film (for example, a silicon oxide film) 702, and an element isolation region STI (Shallow ⁇ ⁇ Trench Isolation) is formed by the base insulating film 702 and the element isolation insulating film 703. Is configured.
  • a portion of the silicon substrate 700 surrounded by the element isolation region STI is an element formation region 700a, and a gate insulating film 707 and a gate electrode 710 are sequentially provided on the element formation region 700a.
  • a silicon oxide film 704, a hafnium oxide film 705, and a cap film 706 are sequentially provided on the element formation region 700a.
  • a TiN film 708 and a polysilicon film 709 are formed in the gate insulating film 707. They are provided in order.
  • a sidewall 712 is provided on the side surface of the gate electrode 710.
  • an extension region 711 is formed below the side of the gate electrode 710, and a source / drain region 713 is formed below the side of the sidewall 712.
  • Non-Patent Document 1 if a lanthanum oxide film is used as a cap film, the threshold voltage of the N-type FET can be lowered by about 400 mV, and if an aluminum oxide film is used as the cap film, the threshold voltage of the P-type FET is lowered by about 300 mV. It can be done.
  • FIG. 10 is a graph schematically showing the evaluation results of the narrow channel characteristics of a conventional N-type MIS transistor.
  • the threshold voltage When the cap film was not formed, as shown by the line 91 in FIG. 10, there was almost no variation in the threshold voltage with respect to the gate width.
  • the cap film when the cap film is formed, as shown by the line 92 in FIG. 10, when the gate width is wide, the threshold voltage hardly fluctuates with respect to the gate width, but when the gate width is narrow, the gate width is small. The threshold voltage increased as it narrowed. Specifically, when the gate width is wide (when the gate width is 10 ⁇ m, for example), if a lanthanum oxide film having a film thickness of 1 nm is formed on a hafnium oxide film having a film thickness of 2 nm, the threshold voltage is 500 mV.
  • the threshold voltage increased as the gate width narrowed, and the threshold voltage increased as high as 200 mV or more ( ⁇ 2 ⁇ 200 mV) when the gate width narrowed to about 0.1 ⁇ m. That is, when the gate width is narrowed, the effect of lowering the threshold voltage by lanthanum is greatly reduced from 500 mV to 300 mV or less (degradation of narrow channel characteristics, dependence of threshold voltage on gate width).
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a transistor capable of suppressing degradation of narrow channel characteristics and a method of manufacturing the same.
  • the cap film is formed not only on the element formation region but also on the base insulating film (the base insulating film is formed on the sidewall of the trench when the element isolation region is formed).
  • the first factor is that when the cap film is formed, the cap film is thinned due to coverage deterioration in a portion of the element isolation region that is in contact with the element formation region (the edge portion of the transistor).
  • the second factor is that when the high dielectric constant film is formed, the high dielectric constant film becomes thicker due to the loading effect at the edge portion of the transistor.
  • the third factor is that the metal applied to the cap film diffuses into the metal gate electrode during the heat treatment because the stress applied to the cap film is different between the central portion of the transistor and the edge portion of the transistor.
  • the effect of the cap film is reduced only at the edge of the transistor.
  • the gate width is wide, the influence of the edge portion of the transistor on the entire transistor is small. Therefore, if a cap film is formed over the element formation region, the threshold voltage of the transistor can be reduced.
  • the gate width is narrow, the influence of the edge portion of the transistor on the entire transistor is large, and thus the reduction in the effect of the cap film at the edge portion of the transistor cannot be ignored, and therefore the threshold voltage of the transistor increases.
  • a cap film containing lanthanum or aluminum is formed on the base insulating film.
  • the film thickness of the cap film can be made thicker than before only at the edge portion of the transistor. Accordingly, it is possible to prevent a reduction in the effect of the cap film at the edge portion of the transistor. Therefore, the threshold voltage can be made substantially the same at the edge portion of the transistor and the central portion of the transistor, so that deterioration of the narrow channel characteristic can be suppressed.
  • a semiconductor device in a trench formed in a semiconductor substrate, and includes an element isolation region surrounding the element formation region, and a gate provided on the element formation region and having a high dielectric constant film.
  • An insulating film and a gate electrode provided on the gate insulating film are provided.
  • the element isolation region has a base insulating film containing oxygen formed on the sidewall of the trench.
  • the high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via a base insulating film.
  • a first cap film containing a metal that changes the threshold voltage of the MIS transistor is provided between the second portion of the high dielectric constant film and the base insulating film.
  • the first cap film is provided at the edge portion of the transistor. Therefore, the effect of the cap film at the edge portion of the transistor can be improved.
  • the element isolation region further includes an element isolation insulating film formed in the trench via the base insulating film, and the first region is between the base insulating film and the element isolation insulating film.
  • the cap film is provided.
  • the gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film.
  • the gate insulating film includes an oxygen-containing film formed on the element formation region, a first portion in the high dielectric constant film formed on the oxygen-containing film, and a high dielectric constant film. It is preferable to have a second cap film formed on the first portion and containing a metal. Thereby, the threshold voltage of the transistor can be set to a desired value.
  • the second cap film is also formed on the second portion of the high dielectric constant film.
  • the film thickness of the second cap film formed on the second portion of the high dielectric constant film is the same as that of the second cap film formed on the first portion of the high dielectric constant film. Thinner than film thickness.
  • the oxygen-containing film is a silicon oxide film or a silicon oxynitride film
  • the base insulating film is a silicon oxide film or a silicon oxynitride film.
  • the metal impurity concentration in the second portion of the high dielectric constant film is equal to or higher than the metal impurity concentration in the first portion of the high dielectric constant film.
  • the MIS transistor is an N-channel MIS transistor, and the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium.
  • the MIS transistor is a P-channel MIS transistor and the metal is aluminum.
  • the high dielectric constant film is either a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film.
  • the gate electrode is a single layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film, and a tantalum nitride carbide film, or a laminated film made of two or more.
  • a recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region, and the second portion of the high dielectric constant film is provided on the inner surface of the recess.
  • the concave portion is formed on the upper surface of the edge portion, the first cap film can be provided on the edge portion of the transistor.
  • the base insulating film contains a metal.
  • the method for manufacturing a semiconductor device includes a step (a) of forming a trench in a semiconductor substrate so as to surround an element formation region, and then providing a base insulating film containing oxygen on the sidewall of the trench; (B) providing a cap film containing a metal that changes the threshold voltage of the MIS transistor, and after the step (b), an element isolation insulating film is provided in the trench via the base insulating film, A step (c) of forming an element isolation region having an element isolation insulating film, a step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c), and gate insulation And (e) providing a gate electrode on the film.
  • a high dielectric constant film is formed on the upper side surface in the element formation region via a base insulating film and a cap film.
  • a step (f) of diffusing metal from the cap film to the base insulating film is provided after the step (b).
  • FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
  • 2A to 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 3A to 3C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 4A and 4B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 5A and 5B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
  • 6A is a cross-sectional view taken along the line VIA-VIA shown in FIG. 1, and FIG.
  • FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG.
  • FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.
  • FIG. 8 is a plan view of a conventional semiconductor device having a cap film.
  • 9A is a cross-sectional view taken along line IXA-IXA shown in FIG. 8
  • FIG. 9B is a cross-sectional view taken along line IXB-IXB shown in FIG.
  • FIG. 10 is a graph schematically showing another evaluation result of the narrow channel characteristics.
  • FIG. 1 is a plan view of the semiconductor device according to the present embodiment.
  • 2A to 5B are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps.
  • 2 (a) to 4 (b) are cross-sectional views taken along the line VIA-VIA shown in FIG. 1
  • FIGS. 5 (a) and 5 (b) are cross-sectional views taken along the line VIB-VIB shown in FIG.
  • “NFET” indicates a region where an N-type MIS transistor is formed
  • STI indicates an element isolation region.
  • FIG. 1 a method for manufacturing a semiconductor device including an N-type MIS transistor and its structure are shown.
  • S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively
  • “W” and “L” indicate a gate width and a gate length, respectively.
  • A is a portion in contact with the element formation region in the element isolation region STI (referred to as an “edge portion of the N-type FET” in the present embodiment).
  • a silicon oxide film 101 of, eg, a 10 nm-thickness is formed on a semiconductor substrate (hereinafter referred to as “substrate”) 100 made of, eg, silicon, by thermal oxidation.
  • substrate e.g. silicon
  • a silicon nitride film 102 of, eg, a 70 nm-thickness is formed on the silicon oxide film 101.
  • resist film not shown
  • an opening is formed in a portion of the resist film that becomes the element isolation region STI by using a photolithography technique.
  • a resist pattern 103 is formed on the silicon nitride film 102 so as to expose the silicon nitride film 102 in a portion serving as the element isolation region STI.
  • the silicon nitride film 102, the silicon oxide film 101, and the substrate 100 are etched using the resist pattern 103 (see FIG. 2A) as a mask.
  • a trench 104 having a depth of, for example, 300 nm is formed in the substrate 100.
  • the resist pattern 103 is removed, and then heat treatment is performed in an oxygen gas and hydrogen gas atmosphere.
  • a base insulating film 105 made of, for example, a silicon oxide film having a thickness of 2 nm is formed on the sidewall and the bottom surface of the trench 104 (step (a)).
  • the top surface and side surface of the silicon nitride film 102, the side surface of the silicon oxide film 101, and the base insulating film 105 are formed using, for example, an ALD (Atomic Layer Deposition) method.
  • a first cap film (cap film) 106 made of a lanthanum oxide film having a thickness of 1 nm is formed (step (b)).
  • heat treatment is performed in a nitrogen gas atmosphere at, for example, 800 ° C. for 30 seconds.
  • the lanthanum in the first cap film 106 diffuses into the base insulating film 105 (step (f)).
  • lanthanum exists in the base insulating film 105.
  • silicon having a film thickness of, for example, 500 nm is formed on the entire surface of the substrate 100 so as to embed the trench 104 by using, for example, plasma CVD (Chemical Vapor Deposition) or thermal CVD.
  • An oxide film (not shown) is formed.
  • CMP Chemical Mechanical Polishing
  • the surface on the substrate 100 is planarized, and the element isolation insulating film 107 made of a silicon oxide film is formed in the trench 104 on the side wall and the bottom surface of the trench 104 via the base insulating film 105 and the first cap film 106. Formed on top. That is, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104.
  • the element isolation insulating film 107, the first cap film 106, and the base insulating film 105 form an element isolation region STI (step (c)), and a portion of the substrate 100 surrounded by the element isolation region STI is formed as an element. It becomes area
  • the silicon nitride film 102 on the silicon oxide film 101 and the silicon oxide film 101 in the first cap film 106 are etched by etching using a chemical solution such as phosphoric acid. Remove the existing part.
  • impurity ions 108 are implanted into the substrate 100 using the resist pattern as a mask.
  • a P-type impurity such as boron may be used as the impurity ions 108.
  • a P-type well (not shown) is formed and the threshold voltage of the channel region is adjusted.
  • annealing is performed at 1000 ° C. for 1 minute in a nitrogen atmosphere in order to diffuse and activate impurities (P-type impurities) implanted into the substrate 100.
  • the silicon oxide film 101 is removed by etching using a chemical solution such as hydrofluoric acid.
  • a chemical solution such as hydrofluoric acid.
  • the wet etching rate of the silicon oxide film formed in the trench 104 is higher than the wet etching rate of the silicon oxide film 101 formed by the thermal oxidation method. Therefore, a recess 107 a is formed on the upper surface of the element isolation insulating film 107 at the edge portion of the N-type FET.
  • a portion of the first cap film 106 formed on the upper side wall (upper side surface in the element formation region) 104a of the trench is exposed.
  • an oxygen-containing film 109 made of, for example, a silicon oxide film having a thickness of 1 nm is formed on the element formation region 100a.
  • a high dielectric constant made of, for example, a 2 nm-thickness HfO 2 film (hafnium oxide film) is formed on the upper surface of the oxygen-containing film 109, the inner surface of the recess 107a, and the upper surface of the element isolation region STI by, for example, ALD.
  • a film 110 is formed.
  • the first cap film 106 is sandwiched between the portion (second portion) 110 b formed on the upper side surface 104 a in the element formation region of the high dielectric constant film 110 and the base insulating film 105.
  • the base insulating film 105 contains lanthanum. For these reasons, since lanthanum exists at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage can be reduced by the first cap film 106 at the edge portion of the N-type FET.
  • a second cap film 111 made of, for example, a lanthanum oxide film having a thickness of 1 nm is formed on the upper surface of the high dielectric constant film 110. Therefore, the second cap film 111 is formed not only on the upper surface of the portion (first portion) 110a formed on the upper surface of the oxygen-containing film 109 in the high dielectric constant film 110 but also on the second dielectric layer 110 of the high dielectric constant film 110. Also formed on the upper surface of the second portion 110b. Note that the film thickness of the portion of the second cap film 111 formed on the second portion 110b of the high dielectric constant film 110 is that of the high dielectric constant film 110 of the second cap film 111 due to coverage deterioration.
  • TiN film (titanium nitride film) 113 having a thickness of, for example, 10 nm is formed on the upper surface of the second cap film 111, and a polysilicon film 114 having a thickness of, for example, 80 nm is formed on the upper surface of the TiN film 113. .
  • a gate insulating film 112 formed by sequentially stacking the oxygen-containing film 109, the first portion 110a of the high dielectric constant film 110, and the second cap film 111 is formed on the upper surface of the element formation region 100a.
  • a gate electrode 115 formed by sequentially laminating the TiN film 113 and the polysilicon film 114 is formed on the upper surface of the gate insulating film 112 (Step (e)).
  • the gate insulating film 112 is also formed on the upper side surface 104a in the element formation region, and the gate electrode 115 is formed of the gate insulating film 112 (the first layer in the high dielectric constant film 110). 2 is also formed on the upper side surface 104a in the element formation region via the second portion 110b).
  • a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100.
  • N-type impurities such as arsenic ions or phosphorus ions are implanted using the resist and the gate electrode 115 as a mask.
  • the implantation energy is, for example, 2 to 5 keV, and the dose amount is, for example, 1 ⁇ 10 15 to 1 ⁇ 10 16 / cm 2 .
  • an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. Thereafter, the resist is removed.
  • a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100.
  • N-type impurities such as arsenic ions or phosphorus ions are ion-implanted using the resist, the gate electrode 115 and the sidewall spacer 117 as a mask.
  • the implantation energy is, for example, 30 keV, and the dose amount is, for example, 1 ⁇ 10 16 / cm 2 .
  • an N-type source / drain region 118 is formed below the side wall spacer 117 in the element formation region. Thereafter, the resist is removed.
  • the semiconductor device according to this embodiment is manufactured.
  • lanthanum in the second cap film 111 diffuses to the interface between the high dielectric constant film 110 and the oxygen-containing film 109. Thereby, since an electric dipole is generated at the interface, the threshold voltage of the N-type FET can be reduced.
  • lanthanum in the first cap film 106 diffuses into the second portion 110b of the high dielectric constant film 110.
  • the lanthanum in the second cap film 111 is only diffused into the first portion 110a of the high dielectric constant film 110, but the second portion 110b of the high dielectric constant film 110 is diffused into the second portion 110b.
  • the lanthanum concentration in the second portion 110b of the high dielectric constant film 110 is equal to or higher than the lanthanum concentration in the first portion 110a of the high dielectric constant film 110.
  • FIGS. 1 and 6A to 7 are cross-sectional views taken along the line VIA-VIA shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG.
  • FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.
  • a trench 104 is formed in the substrate 100.
  • a base insulating film 105 and a first cap film 106 are sequentially formed on the sidewall and the bottom surface of the trench 104, and the element is interposed in the trench 104 via the base insulating film 105 and the first cap film 106.
  • An isolation insulating film 107 is formed.
  • the base insulating film 105, the first cap film 106, and the element isolation insulating film 107 constitute an element isolation region STI, and a portion of the substrate 100 surrounded by the element isolation region STI is an element formation region 100a.
  • a gate insulating film 112 and a gate electrode 115 are sequentially formed on the element formation region 100a.
  • an oxygen-containing film 109, a high dielectric constant film 110, and a second cap film 111 are sequentially formed on the element formation region 100 a, and at the interface between the oxygen-containing film 109 and the high dielectric constant film 110.
  • a TiN film 113 and a polysilicon film 114 are sequentially formed on the gate insulating film 112.
  • the high dielectric constant film 110 is formed not only on the element formation region 100 a but also on the element isolation region STI. Specifically, in the element formation region via the base insulating film 105 and the first cap film 106. It is also provided on the upper side surface 104a (second portion 110b). Therefore, the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110 on the upper side surface 104a in the element formation region. Similarly, the second cap film 111, the TiN film 113, and the polysilicon film 114 are formed not only on the element formation region 100a but also on the element isolation region STI.
  • a sidewall spacer 117 is formed on the side surface of the gate electrode 115, and an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a.
  • An N-type source / drain region 118 is formed below the side wall spacer 117.
  • the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104, and the base is formed on the upper side surface 104a in the element formation region. It is sandwiched between the insulating film 105 and the second portion 110 b of the high dielectric constant film 110.
  • the base insulating film 105 contains lanthanum, particularly in the vicinity of the interface with the first cap film 106. For these reasons, since an electric dipole is generated at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the threshold voltage is applied by the first cap film 106 at the edge portion A of the N-type FET. Can be reduced. Therefore, in this embodiment, as shown by the line 61 in FIG. 7, it is possible to suppress a decrease in narrow channel characteristics.
  • the threshold voltage can be reduced by the first cap film 106 at the edge portion A of the N-type FET. Therefore, even when the thickness of the second cap film 111 is reduced at the edge portion A of the N-type FET when the second cap film 111 is formed (coverage deterioration), it is possible to suppress a decrease in narrow channel characteristics. . Furthermore, even when the high dielectric constant film 110 is formed and the thickness of the high dielectric constant film 110 becomes thicker at the edge portion A of the N-type FET (loading effect), it is possible to suppress a decrease in narrow channel characteristics. In addition, even if lanthanum in the second cap film 111 diffuses into the gate electrode 115 during the heat treatment, it is possible to suppress a decrease in narrow channel characteristics.
  • this embodiment may have the following configuration.
  • the silicon nitride film 102, the silicon nitride film 102, and the silicon oxide film 101 are positioned so that the etching end faces of the silicon nitride film 102 and the silicon oxide film 101 are about 5 nm from the etching end face of the substrate 100. It is preferable to etch the silicon oxide film 101 and the substrate 100. Thereby, in the process of forming the base insulating film 105 on the side wall and the bottom surface of the trench 104, which is the next process, the corner at the upper end of the side wall of the trench 104 can be rounded off. Thereby, it is possible to avoid the concentration of the electric field at the upper end of the sidewall of the trench 104.
  • the structure of the base insulating film 105, and the structure of the first cap film 106 lanthanum forms the base insulating film 105 until the first cap film 106 is completely removed. May diffuse.
  • the boundary between the base insulating film 105 and the first cap film 106 does not exist on the upper side surface 104a in the element formation region.
  • the first cap film 106 is not formed on the base insulating film 105, and instead, the base insulating film 105 is the second portion of the high dielectric constant film 110. Lanthanum is contained in the vicinity of the interface with 110b.
  • the first cap film 106 may be removed after lanthanum is diffused from the first cap film 106 to the base insulating film 105.
  • the heat treatment in FIG. 2 (c) may be omitted.
  • the lanthanum in the first cap film 106 diffuses into the base insulating film 105 by the heat treatment in FIG. 3B or the heat treatment in FIGS. 4B and 5B.
  • FIG. 2C the degradation of the narrow channel characteristics can be suppressed even when the first cap film 106 is removed after the heat treatment. Therefore, it is preferable to perform heat treatment in FIG.
  • the second cap film 111 is completely removed depending on the conditions of the heat treatment, the configuration of the high dielectric constant film 110, and the configuration of the second cap film 111.
  • Lanthanum may diffuse to the lower part of the high dielectric constant film 110 or the upper part of the oxygen-containing film 109.
  • the second cap film 111 is not formed on the high dielectric constant film 110, and instead, the interface between the oxygen-containing film 109 and the high dielectric constant film 110.
  • the second cap film 111 is replaced with the oxygen-containing film 109 and the high dielectric constant film 110. What is necessary is just to form between.
  • the base insulating film 105 is not limited to a silicon oxide film, and may be a silicon oxynitride film, for example. If the base insulating film 105 contains oxygen, the first cap film 106 can be used to suppress degradation of the narrow channel characteristics.
  • the film thickness of the base insulating film 105 is not limited to 2 nm, and may be in the range of about 1 to 10 nm. When the thickness of the base insulating film 105 is in the range of about 0.5 to 15 nm, it is possible to suppress the degradation of narrow channel characteristics.
  • the first cap film 106 only needs to contain a metal that can reduce the threshold voltage of the N-type FET.
  • a metal that can reduce the threshold voltage of the N-type FET.
  • Examples of such a metal include dysprosium (Dy), scandium (Sc), erbium (Er), magnesium (Mg), and strontium (Sr) in addition to lanthanum. Therefore, the first cap film 106 is not limited to the lanthanum oxide film, and may be a film made of any one of the above metals, or an oxide film of any one of the above metals. It may be a film containing any two or more of the metals, or a film containing an oxide of any two or more of the metals. good.
  • the film thickness of the first cap film 106 is not limited to 1 nm. It is preferable to adjust the film thickness of the first cap film 106 in accordance with the amount of decrease in the threshold voltage at the edge portion A of the N-type FET. That is, when it is assumed that the threshold voltage decrease amount at the edge portion A of the N-type FET is small (for example, when the gate width is not so narrow), the thickness of the first cap film 106 is reduced (for example, 0.5 nm), and when the reduction amount of the threshold voltage at the edge portion A of the N-type FET is assumed to be large (for example, when the gate width is narrow), the thickness of the first cap film 106 is increased.
  • a film may be formed (for example, 2 nm).
  • the first cap film 106 may be formed only on the upper side surface 104 a in the element formation region with the base insulating film 105 interposed therebetween.
  • the high dielectric constant film 110 may include only the first portion 110a and the second portion 110b.
  • the high dielectric constant film 110 may be made of a material having a higher dielectric constant than silicon oxide, silicon nitride, and silicon oxynitride. Specifically, a metal oxide, metal oxynitride having a dielectric constant of 8 or more, A silicate or a nitrogen-containing silicate may be used. Therefore, the high dielectric constant film 110 is not limited to the HfO 2 film, but is an HfSiO film (hafnium silicon oxide film), an HfSiON film (hafnium silicon oxide film), a ZrO 2 film (zirconium oxide film), or an HfZrO film (hafnium film). Zirconium oxide film) or the like.
  • the second cap film 111 is not limited to a lanthanum oxide film, and any film that can be used as the first cap film 106 may be used. Further, the first cap film 106 and the second cap film 111 may be made of the same material or different materials.
  • the gate insulating film 112 may not contain lanthanum. Even if the gate insulating film 112 does not contain lanthanum, if the first cap film 106 is formed between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, Degradation of narrow channel characteristics can be suppressed.
  • any one single layer film or two layers of TaN film (tantalum nitride film), TaC film (tantalum carbide film), TaCN (tantalum nitride carbide film), etc. More than one type of laminated film may be used. Further, the gate electrode 115 may not have the polysilicon film 114.
  • a P-type pocket region may be formed below the N-type extension region 116 in the element formation region 100a. Further, a silicide layer made of NiSi having a thickness of, for example, 20 nm may be formed on the upper surface of the gate electrode 115 and the upper surface of the N-type source / drain region 118.
  • the conductivity type of the transistor may be P-type.
  • the semiconductor device according to the present embodiment includes a P-type FET, the conductivity types in the above description are opposite to each other, and the first and second cap films 106 and 111 are aluminum films or aluminum oxide films. is there.
  • an N-type FET and a P-type FET may be formed with the element isolation region STI interposed therebetween.
  • the present invention is useful, for example, for a transistor having a high dielectric constant film.
  • substrate substrate (semiconductor substrate) 100a Element formation region 101 Silicon oxide film 102 Silicon nitride film 103 resist pattern 104 trench 104a Upper side in element formation region 105 Underlying insulating film 106 First cap membrane 107 Element isolation insulating film 107a recess 109 Oxygen-containing membrane 110 High dielectric constant film 110a first part 110b second part 111 Second cap membrane 112 Gate insulation film 113 TiN film 114 Polysilicon film 115 Gate electrode 116 N-type extension area 117 Sidewall spacer 118 N-type source / drain region STI element isolation region

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Abstract

Disclosed is a semiconductor device wherein an element isolating region (STI) is provided in a trench (104) formed on a semiconductor substrate (100), and has a base insulating film (105) formed on the side wall of the trench (104). A gate insulating film (112) is formed on an element forming region (100a), and the gate insulating film (112) has a high dielectric constant film (110). The first portion (110a) of the high dielectric constant film (110) is formed on the upper surface of the element forming region (100a), and the second portion (110b) of the high dielectric constant film (110) is formed on the upper side surface (104a) of the element forming region with the base insulating film (105) therebetween. A first cap film (106), which contains a metal that changes the threshold voltage of an MIS transistor, is provided between the second portion (110b) and the base insulating film (105).

Description

半導体装置及びその製造方法Semiconductor device and manufacturing method thereof
　本発明は、半導体装置及びその製造方法に関し、特に、ＭＩＳ（Metal Insulator Semiconductor）トランジスタの閾値電圧を変更する金属を含有するキャップ膜を備えた半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a cap film containing a metal that changes a threshold voltage of a MIS (Metal Insulator Semiconductor) transistor and a manufacturing method thereof.
　デザインルールにおける半導体装置の縮小に伴い、回路の集積度は飛躍的に向上しており、１チップ上に１億個以上の電界効果型トランジスタ（ＦＥＴ：Field Effect Transistor）の搭載が可能となっている。高性能なトランジスタを実現するためには、ゲート長の縮小だけで無く、ゲート絶縁膜の薄膜化も求められている。 With the shrinking of semiconductor devices in the design rules, the degree of circuit integration has improved dramatically, and more than 100 million field-effect transistors (FETs) can be mounted on a single chip. Yes. In order to realize a high-performance transistor, not only reduction of the gate length but also reduction of the gate insulating film is required.
　従来、ゲート絶縁膜には、シリコン酸化膜又はシリコン酸窒化膜が用いられている。しかし、ＥＯＴ（Equivalent Oxide Thickness：等価酸化膜厚）が２ｎｍ以下まで小さくなると、ゲートリーク電流が増大するため回路の消費電力が増大するという問題が発生する。ゲートリーク電流を低減しつつＥＯＴの薄膜化を実現するために、高誘電率膜に関心が寄せられている。また、ＥＯＴの更なる薄膜化のために、高誘電率膜とメタルゲート電極（メタルゲート電極はシリコン電極ではなく窒化チタン又は窒化タンタル等のメタル材料からなるゲート電極である）とを有するトランジスタについて多くの研究開発がなされている。 Conventionally, a silicon oxide film or a silicon oxynitride film is used as the gate insulating film. However, when EOT (Equivalent Oxide Thickness) is reduced to 2 nm or less, the gate leakage current increases, causing a problem that the power consumption of the circuit increases. In order to reduce the thickness of the EOT while reducing the gate leakage current, there is an interest in a high dielectric constant film. Further, a transistor having a high dielectric constant film and a metal gate electrode (a metal gate electrode is not a silicon electrode but a gate electrode made of a metal material such as titanium nitride or tantalum nitride) for further thinning of the EOT. A lot of research and development has been done.
　高誘電率膜とメタルゲート電極とを有するトランジスタを実現する上での課題の一つに、トランジスタの閾値電圧の制御がある。従来のゲート電極であるシリコン電極では、不純物イオンを注入することによりシリコン電極の仕事関数を調整し、よって、Ｎ型ＦＥＴ及びＰ型ＦＥＴのそれぞれに適した閾値電圧を実現している。すなわち、Ｎ型ＦＥＴに対しては、シリコン電極にヒ素又はリン等のＮ型不純物を注入することによりシリコン電極の仕事関数の低減を図り、Ｐ型ＦＥＴに対しては、シリコン電極にボロン等のＰ型不純物を注入することによりシリコン電極の仕事関数の増大を図っている。しかし、メタルゲート電極では、不純物イオンの注入による仕事関数の制御が出来ない。そのため、ゲート電極としてメタルゲート電極を用いたときには、トランジスタの閾値電圧の制御が大きな課題となっている。なお、本明細書中においては、Ｎ型ＦＥＴ及びＰ型ＦＥＴにおいて閾値電圧の変化を統一的に表現するために、閾値電圧は絶対値で記載する。これにより、Ｎ型ＦＥＴ及びＰ型ＦＥＴに関係なく、閾値電圧が０Ｖに近づく方向に変化した場合を「閾値電圧が低下（低減）する、又は、閾値電圧が低くなる」と記載し、閾値電圧が０Ｖから遠ざかる方向に変化した場合を「閾値電圧が上昇する、又は、閾値電圧が高くなる」と記載する。 One of the problems in realizing a transistor having a high dielectric constant film and a metal gate electrode is control of the threshold voltage of the transistor. In the conventional silicon electrode which is a gate electrode, the work function of the silicon electrode is adjusted by implanting impurity ions, thereby realizing a threshold voltage suitable for each of the N-type FET and the P-type FET. That is, for an N-type FET, the work function of the silicon electrode is reduced by injecting an N-type impurity such as arsenic or phosphorus into the silicon electrode. For a P-type FET, boron or the like is used for the silicon electrode. The work function of the silicon electrode is increased by implanting P-type impurities. However, the metal gate electrode cannot control the work function by implanting impurity ions. Therefore, when a metal gate electrode is used as the gate electrode, control of the threshold voltage of the transistor is a big problem. In this specification, the threshold voltage is described as an absolute value in order to uniformly express the change in the threshold voltage in the N-type FET and the P-type FET. As a result, regardless of the N-type FET and the P-type FET, the case where the threshold voltage changes in a direction approaching 0 V is described as “the threshold voltage decreases (decreases) or the threshold voltage decreases”. Is described as "the threshold voltage increases or the threshold voltage increases".
　高誘電率膜とメタルゲート電極とを有するトランジスタにおいて閾値電圧を制御する方法が非特許文献１に開示されている。非特許文献１に開示されたトランジスタでは、素子形成領域上に酸化膜及び高誘電率膜が順に形成されており、このトランジスタは、上記酸化膜と高誘電率膜との界面に電気双極子を発生させる金属酸化膜（キャップ膜）を備えている。 Non-Patent Document 1 discloses a method for controlling a threshold voltage in a transistor having a high dielectric constant film and a metal gate electrode. In the transistor disclosed in Non-Patent Document 1, an oxide film and a high dielectric constant film are sequentially formed on an element formation region, and this transistor has an electric dipole at the interface between the oxide film and the high dielectric constant film. A metal oxide film (cap film) to be generated is provided.
　図８はキャップ膜を有する従来の半導体装置の平面図である。図９（ａ）は図８に示すIXA－IXA線における断面図であり、（ｂ）は図８に示すIXB－IXB線における断面図である。なお、図８及び図９（ａ）において、「ＮＦＥＴ」はＮ型ＭＩＳトランジスタが形成されている領域を示しており、「ＳＴＩ」は素子分離領域を示している。また、図８において、「Ｓ」、「Ｄ」及び「Ｇ」はそれぞれソース領域、ドレイン領域及びゲート領域を示しており、「Ｗ」及び「Ｌ」はそれぞれゲート幅及びゲート長さを示している。 FIG. 8 is a plan view of a conventional semiconductor device having a cap film. 9A is a cross-sectional view taken along the line IXA-IXA shown in FIG. 8, and FIG. 9B is a cross-sectional view taken along the line IXB-IXB shown in FIG. 8 and 9A, “NFET” indicates a region where an N-type MIS transistor is formed, and “STI” indicates an element isolation region. In FIG. 8, “S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively, and “W” and “L” indicate a gate width and a gate length, respectively. Yes.
　図８～図９（ｂ）に示すように、従来の半導体装置では、シリコン基板７００内にトレンチ７０１が形成されている。トレンチ７０１内には下地絶縁膜（例えばシリコン酸化膜）７０２を介して素子分離絶縁膜７０３が形成されており、下地絶縁膜７０２と素子分離絶縁膜７０３とで素子分離領域ＳＴＩ（Shallow Trench Isolation）が構成されている。シリコン基板７００のうち素子分離領域ＳＴＩで囲まれた部分は素子形成領域７００ａであり、素子形成領域７００ａ上にはゲート絶縁膜７０７及びゲート電極７１０が順に設けられている。ゲート絶縁膜７０７では、シリコン酸化膜７０４、ハフニウム酸化膜７０５及びキャップ膜７０６が素子形成領域７００ａ上に順に設けられており、ゲート電極７１０では、ＴｉＮ膜７０８及びポリシリコン膜７０９がゲート絶縁膜７０７上に順に設けられている。ゲート電極７１０の側面上にはサイドウォール７１２が設けられている。また、素子形成領域７００ａ内には、エクステンション領域７１１がゲート電極７１０の側方下に形成されており、ソースドレイン領域７１３がサイドウォール７１２の側方下に形成されている。 As shown in FIGS. 8 to 9B, in the conventional semiconductor device, a trench 701 is formed in a silicon substrate 700. An element isolation insulating film 703 is formed in the trench 701 via a base insulating film (for example, a silicon oxide film) 702, and an element isolation region STI (Shallow 絶 縁 Trench Isolation) is formed by the base insulating film 702 and the element isolation insulating film 703. Is configured. A portion of the silicon substrate 700 surrounded by the element isolation region STI is an element formation region 700a, and a gate insulating film 707 and a gate electrode 710 are sequentially provided on the element formation region 700a. In the gate insulating film 707, a silicon oxide film 704, a hafnium oxide film 705, and a cap film 706 are sequentially provided on the element formation region 700a. In the gate electrode 710, a TiN film 708 and a polysilicon film 709 are formed in the gate insulating film 707. They are provided in order. A sidewall 712 is provided on the side surface of the gate electrode 710. In the element formation region 700a, an extension region 711 is formed below the side of the gate electrode 710, and a source / drain region 713 is formed below the side of the sidewall 712.
　このような半導体装置を製造するときには、キャップ膜７０６を形成してから熱処理を行う。すると、キャップ膜７０６中の金属（Ｎ型ＦＥＴを製造するときには例えばランタン、Ｐ型ＦＥＴを製造するときには例えばアルミニウム）がハフニウム酸化膜７０５とシリコン酸化膜７０４との界面まで拡散する。これにより、この界面には電気双極子が発生し、よって、トランジスタの閾値電圧を低減させることができる。非特許文献１には、キャップ膜としてランタン酸化膜を用いればＮ型ＦＥＴの閾値電圧を４００ｍＶ程度低くすることができ、キャップ膜としてアルミニウム酸化膜を用いればＰ型ＦＥＴの閾値電圧を３００ｍＶ程度低くすることができる，と記載されている。 When manufacturing such a semiconductor device, heat treatment is performed after the cap film 706 is formed. Then, the metal in the cap film 706 (for example, lanthanum when manufacturing an N-type FET, or aluminum when manufacturing a P-type FET) diffuses to the interface between the hafnium oxide film 705 and the silicon oxide film 704. As a result, an electric dipole is generated at this interface, so that the threshold voltage of the transistor can be reduced. In Non-Patent Document 1, if a lanthanum oxide film is used as a cap film, the threshold voltage of the N-type FET can be lowered by about 400 mV, and if an aluminum oxide film is used as the cap film, the threshold voltage of the P-type FET is lowered by about 300 mV. It can be done.
　しかしながら、非特許文献１に開示された方法でＭＩＳトランジスタの閾値電圧を低減させると、ナローチャネル特性が劣化することが分かった。図１０は、従来のＮ型ＭＩＳトランジスタのナローチャネル特性の評価結果を模式的に示すグラフ図である。 However, it has been found that when the threshold voltage of the MIS transistor is reduced by the method disclosed in Non-Patent Document 1, the narrow channel characteristics deteriorate. FIG. 10 is a graph schematically showing the evaluation results of the narrow channel characteristics of a conventional N-type MIS transistor.
　キャップ膜を形成しない場合、図１０の線９１に示すように、ゲート幅に対する閾値電圧の変動はほとんど見られなかった。一方、キャップ膜を形成すると、図１０の線９２に示すように、ゲート幅が広い場合にはゲート幅に対する閾値電圧の変動はほとんど見られなかったが、ゲート幅が狭い場合にはゲート幅が狭くなるにつれて閾値電圧は高くなった。具体的には、ゲート幅が広い場合（ゲート幅が例えば１０μｍである場合）、膜厚が１ｎｍであるランタン酸化膜を膜厚が２ｎｍであるハフニウム酸化膜上に形成すれば、閾値電圧を５００ｍＶ程度低くすることができた（Δ１≒５００ｍＶ）。この結果は、非特許文献１に記載の実験データと同程度である。しかし、ゲート幅が狭くなるに従い閾値電圧が高くなり、ゲート幅が０．１μｍ程度まで狭くなると閾値電圧が２００ｍＶ以上も高くなった（Δ２≧２００ｍＶ）。つまり、ゲート幅が狭くなると、ランタンによる閾値電圧の低下効果が５００ｍＶから３００ｍＶ以下に大きく低下した（ナローチャネル特性の劣化、閾値電圧のゲート幅依存性）。 When the cap film was not formed, as shown by the line 91 in FIG. 10, there was almost no variation in the threshold voltage with respect to the gate width. On the other hand, when the cap film is formed, as shown by the line 92 in FIG. 10, when the gate width is wide, the threshold voltage hardly fluctuates with respect to the gate width, but when the gate width is narrow, the gate width is small. The threshold voltage increased as it narrowed. Specifically, when the gate width is wide (when the gate width is 10 μm, for example), if a lanthanum oxide film having a film thickness of 1 nm is formed on a hafnium oxide film having a film thickness of 2 nm, the threshold voltage is 500 mV. It could be lowered to some extent (Δ 1 ≈500 mV). This result is comparable to the experimental data described in Non-Patent Document 1. However, the threshold voltage increased as the gate width narrowed, and the threshold voltage increased as high as 200 mV or more (Δ 2 ≧ 200 mV) when the gate width narrowed to about 0.1 μm. That is, when the gate width is narrowed, the effect of lowering the threshold voltage by lanthanum is greatly reduced from 500 mV to 300 mV or less (degradation of narrow channel characteristics, dependence of threshold voltage on gate width).
　また、不図示であるが、従来のＰ型ＭＩＳトランジスタのナローチャネル特性を調べたところ、Ｎ型ＭＩＳトランジスタと同様に、ゲート幅が広い場合にはゲート幅に対する閾値電圧の変動はほとんど見られなかったが、ゲート幅が狭い場合にはゲート幅が狭くなるにつれて閾値電圧は高くなった。 Although not shown, when the narrow channel characteristics of a conventional P-type MIS transistor are examined, as with the N-type MIS transistor, when the gate width is wide, there is almost no variation in the threshold voltage with respect to the gate width. However, when the gate width was narrow, the threshold voltage increased as the gate width narrowed.
　本発明は、かかる点に鑑みてなされたものであり、その目的とするところは、ナローチャネル特性の劣化を抑制可能なトランジスタ及びその製造方法を提供することである。 The present invention has been made in view of the above points, and an object of the present invention is to provide a transistor capable of suppressing degradation of narrow channel characteristics and a method of manufacturing the same.
　前記課題を解決するため、本発明では、キャップ膜を素子形成領域上のみならず下地絶縁膜（下地絶縁膜は、素子分離領域の形成時にトレンチの側壁上に形成される）上にも形成する。 In order to solve the above problem, in the present invention, the cap film is formed not only on the element formation region but also on the base insulating film (the base insulating film is formed on the sidewall of the trench when the element isolation region is formed). .
　キャップ膜を有する従来の半導体装置においてナローチャネル特性の劣化が生じる要因として、次の３つが考えられる。１つ目の要因は、キャップ膜の形成時、素子分離領域のうち素子形成領域と接する部分（トランジスタのエッジ部）ではカバレッジ劣化によりキャップ膜が薄膜化する，ということである。２つ目の要因は、高誘電率膜の形成時、トランジスタのエッジ部ではローディング効果により高誘電率膜が厚膜化する，ということである。３つ目の要因は、キャップ膜に加わる応力がトランジスタの中央部とトランジスタのエッジ部とでは互いに異なるのでキャップ膜中の金属が熱処理中にメタルゲート電極中に拡散する，ということである。 There are three possible causes for the deterioration of the narrow channel characteristics in a conventional semiconductor device having a cap film. The first factor is that when the cap film is formed, the cap film is thinned due to coverage deterioration in a portion of the element isolation region that is in contact with the element formation region (the edge portion of the transistor). The second factor is that when the high dielectric constant film is formed, the high dielectric constant film becomes thicker due to the loading effect at the edge portion of the transistor. The third factor is that the metal applied to the cap film diffuses into the metal gate electrode during the heat treatment because the stress applied to the cap film is different between the central portion of the transistor and the edge portion of the transistor.
　前述の３つの要因の全てに共通することは、トランジスタのエッジ部においてのみキャップ膜の効果が低減するということである。ゲート幅が広い場合、トランジスタのエッジ部がトランジスタ全体に与える影響は小さいため、素子形成領域上にキャップ膜を形成すればトランジスタの閾値電圧を低減させることができる。しかし、ゲート幅が狭い場合、トランジスタのエッジ部がトランジスタ全体に与える影響は大きいので、トランジスタのエッジ部におけるキャップ膜の効果の低減を無視できず、そのため、トランジスタの閾値電圧は上昇する。 What is common to all the above three factors is that the effect of the cap film is reduced only at the edge of the transistor. When the gate width is wide, the influence of the edge portion of the transistor on the entire transistor is small. Therefore, if a cap film is formed over the element formation region, the threshold voltage of the transistor can be reduced. However, when the gate width is narrow, the influence of the edge portion of the transistor on the entire transistor is large, and thus the reduction in the effect of the cap film at the edge portion of the transistor cannot be ignored, and therefore the threshold voltage of the transistor increases.
　本発明では、素子分離領域の形成時に、ランタン又はアルミニウム等を含むキャップ膜を下地絶縁膜上に形成する。これにより、トランジスタのエッジ部においてのみ、キャップ膜の膜厚を従来よりも厚くすることができる。よって、トランジスタのエッジ部におけるキャップ膜の効果の低下を防止することができる。従って、閾値電圧をトランジスタのエッジ部とトランジスタの中央部とで略同一にすることができるので、ナローチャネル特性の劣化を抑制できる。 In the present invention, when forming the element isolation region, a cap film containing lanthanum or aluminum is formed on the base insulating film. Thereby, the film thickness of the cap film can be made thicker than before only at the edge portion of the transistor. Accordingly, it is possible to prevent a reduction in the effect of the cap film at the edge portion of the transistor. Therefore, the threshold voltage can be made substantially the same at the edge portion of the transistor and the central portion of the transistor, so that deterioration of the narrow channel characteristic can be suppressed.
　具体的には、本発明に係る半導体装置は、半導体基板に形成されたトレンチ内に設けられ、素子形成領域を囲む素子分離領域と、素子形成領域上に設けられ、高誘電率膜を有するゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極とを備えている。素子分離領域は、トレンチの側壁上に形成された酸素を含有する下地絶縁膜を有している。高誘電率膜は、素子形成領域における上面上に形成された第１の部分と、素子形成領域における上部側面上に下地絶縁膜を介して形成された第２の部分とを有している。高誘電率膜における第２の部分と下地絶縁膜との間には、ＭＩＳトランジスタの閾値電圧を変更する金属を含有する第１のキャップ膜が設けられている。 Specifically, a semiconductor device according to the present invention is provided in a trench formed in a semiconductor substrate, and includes an element isolation region surrounding the element formation region, and a gate provided on the element formation region and having a high dielectric constant film. An insulating film and a gate electrode provided on the gate insulating film are provided. The element isolation region has a base insulating film containing oxygen formed on the sidewall of the trench. The high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via a base insulating film. A first cap film containing a metal that changes the threshold voltage of the MIS transistor is provided between the second portion of the high dielectric constant film and the base insulating film.
　このように本発明に係る半導体装置では、トランジスタのエッジ部に第１のキャップ膜が設けられている。よって、トランジスタのエッジ部におけるキャップ膜の効果を向上させることができる。 Thus, in the semiconductor device according to the present invention, the first cap film is provided at the edge portion of the transistor. Therefore, the effect of the cap film at the edge portion of the transistor can be improved.
　後述の好ましい実施形態では、素子分離領域は、トレンチ内に下地絶縁膜を介して形成された素子分離絶縁膜をさらに備えており、下地絶縁膜と素子分離絶縁膜との間には、第１のキャップ膜が設けられている。 In a preferred embodiment to be described later, the element isolation region further includes an element isolation insulating film formed in the trench via the base insulating film, and the first region is between the base insulating film and the element isolation insulating film. The cap film is provided.
　後述の好ましい実施形態では、ゲート電極は、素子形成領域における上部側面上に高誘電率膜の第２の部分を介して形成されている。 In a preferred embodiment described later, the gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film.
　本発明に係る半導体装置では、ゲート絶縁膜は、素子形成領域上に形成された酸素含有膜と、酸素含有膜上に形成された高誘電率膜における第１の部分と、高誘電率膜における第１の部分の上に形成され、金属を含有する第２のキャップ膜とを有することが好ましい。これにより、トランジスタの閾値電圧を所望値とすることができる。 In the semiconductor device according to the present invention, the gate insulating film includes an oxygen-containing film formed on the element formation region, a first portion in the high dielectric constant film formed on the oxygen-containing film, and a high dielectric constant film. It is preferable to have a second cap film formed on the first portion and containing a metal. Thereby, the threshold voltage of the transistor can be set to a desired value.
　後述の好ましい実施形態では、第２のキャップ膜は、高誘電率膜における第２の部分の上にも形成されている。また、高誘電率膜における第２の部分の上に形成されている第２のキャップ膜の膜厚は、高誘電率膜における第１の部分の上に形成されている第２のキャップ膜の膜厚よりも薄い。 In a preferred embodiment described later, the second cap film is also formed on the second portion of the high dielectric constant film. In addition, the film thickness of the second cap film formed on the second portion of the high dielectric constant film is the same as that of the second cap film formed on the first portion of the high dielectric constant film. Thinner than film thickness.
　後述の好ましい実施形態では、酸素含有膜はシリコン酸化膜又はシリコン酸窒化膜であり、下地絶縁膜はシリコン酸化膜又はシリコン酸窒化膜である。 In a preferred embodiment described later, the oxygen-containing film is a silicon oxide film or a silicon oxynitride film, and the base insulating film is a silicon oxide film or a silicon oxynitride film.
　後述の好ましい実施形態では、高誘電率膜の第２の部分における金属の不純物濃度は、高誘電率膜の第１の部分における金属の不純物濃度と同等、又はそれよりも高い。 In a preferred embodiment described later, the metal impurity concentration in the second portion of the high dielectric constant film is equal to or higher than the metal impurity concentration in the first portion of the high dielectric constant film.
　後述の好ましい実施形態では、ＭＩＳトランジスタは、Ｎチャネル型ＭＩＳトランジスタであり、金属は、ランタン、ジスプロシウム、スカンジウム、エルビウム、マグネシウム及びストロンチウムの中から選択される少なくとも１つである。 In a preferred embodiment described later, the MIS transistor is an N-channel MIS transistor, and the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium.
　後述の好ましい実施形態では、ＭＩＳトランジスタは、Ｐチャネル型ＭＩＳトランジスタであり、金属は、アルミニウムである。 In a preferred embodiment described later, the MIS transistor is a P-channel MIS transistor and the metal is aluminum.
　後述の好ましい実施形態では、高誘電率膜は、ハフニウム酸化膜、ハフニウムシリコン酸化膜、窒化ハフニウムシリコン酸化膜、ジルコニウム酸化膜又はハフニウムジルコニウム酸化膜の何れかである。 In a preferred embodiment described later, the high dielectric constant film is either a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film.
　後述の好ましい実施形態では、ゲート電極は、窒化チタン膜、窒化タンタル膜、タンタルカーバイド膜及び窒化タンタルカーバイド膜のうちの何れか１つからなる単層膜又は２つ以上からなる積層膜である。 In a preferred embodiment described later, the gate electrode is a single layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film, and a tantalum nitride carbide film, or a laminated film made of two or more.
　本発明の半導体装置では、素子分離領域における素子形成領域に隣接するエッジ部の上面には凹部が形成されており、高誘電率膜における第２の部分は凹部の内面上に設けられている。このようにエッジ部の上面に凹部が形成されているので、トランジスタのエッジ部に第１のキャップ膜を設けることができる。 In the semiconductor device of the present invention, a recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region, and the second portion of the high dielectric constant film is provided on the inner surface of the recess. As described above, since the concave portion is formed on the upper surface of the edge portion, the first cap film can be provided on the edge portion of the transistor.
　後述の好ましい実施形態では、下地絶縁膜は金属を含有している。 In a preferred embodiment described later, the base insulating film contains a metal.
　本発明の半導体装置の製造方法は、素子形成領域を囲むように半導体基板にトレンチを形成した後、トレンチの側壁上に酸素を含有する下地絶縁膜を設ける工程（ａ）と、下地絶縁膜上にＭＩＳトランジスタの閾値電圧を変更する金属を含有するキャップ膜を設ける工程（ｂ）と、工程（ｂ）の後に、トレンチ内に下地絶縁膜を介して素子分離絶縁膜を設け、下地絶縁膜と素子分離絶縁膜とを有する素子分離領域を形成する工程（ｃ）と、工程（ｃ）の後に、素子形成領域上に高誘電率膜を有するゲート絶縁膜を設ける工程（ｄ）と、ゲート絶縁膜上にゲート電極を設ける工程（ｅ）とを備えている。工程（ｄ）では、素子形成領域における上部側面上に下地絶縁膜及びキャップ膜を介して高誘電率膜を形成する。 The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a trench in a semiconductor substrate so as to surround an element formation region, and then providing a base insulating film containing oxygen on the sidewall of the trench; (B) providing a cap film containing a metal that changes the threshold voltage of the MIS transistor, and after the step (b), an element isolation insulating film is provided in the trench via the base insulating film, A step (c) of forming an element isolation region having an element isolation insulating film, a step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c), and gate insulation And (e) providing a gate electrode on the film. In the step (d), a high dielectric constant film is formed on the upper side surface in the element formation region via a base insulating film and a cap film.
　後述の好ましい実施形態では、工程（ｂ）の後に、金属をキャップ膜から下地絶縁膜へ拡散させる工程（ｆ）を備えている。 In a preferred embodiment described later, a step (f) of diffusing metal from the cap film to the base insulating film is provided after the step (b).
　本発明では、ナローチャネル特性の劣化を抑制することができる。 In the present invention, degradation of narrow channel characteristics can be suppressed.
図１は、本発明の一実施形態に係る半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. 図２（ａ）～（ｃ）は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。2A to 2C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 図３（ａ）～（ｃ）は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。3A to 3C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 図４（ａ）及び（ｂ）は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。4A and 4B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 図５（ａ）及び（ｂ）は、本発明の一実施形態に係る半導体装置の製造方法を工程順に示す断面図である。5A and 5B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. 図６（ａ）は図１に示すVIA－VIA線における断面図であり、図６（ｂ）は図１に示すVIB－VIB線における断面図である。6A is a cross-sectional view taken along the line VIA-VIA shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG. 図７は、ナローチャネル特性の評価結果を模式的に示すグラフ図である。FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics. 図８は、キャップ膜を有する従来の半導体装置の平面図である。FIG. 8 is a plan view of a conventional semiconductor device having a cap film. 図９（ａ）は図８に示すIXA－IXA線における断面図であり、図９（ｂ）は図８に示すIXB－IXB線における断面図である。9A is a cross-sectional view taken along line IXA-IXA shown in FIG. 8, and FIG. 9B is a cross-sectional view taken along line IXB-IXB shown in FIG. 図１０は、ナローチャネル特性の別の評価結果を模式的に示すグラフ図である。FIG. 10 is a graph schematically showing another evaluation result of the narrow channel characteristics.
　以下では、図面を参照しながら本発明の実施形態を説明する。なお、本発明は、以下に示す実施形態に限定されない。また、以下に示す実施形態に記載の膜厚、材料及び作製方法等は、一例に過ぎず、以下に記載の事項に限定されない。また、以下の実施形態では、実質的に同一の部材に対して同一の符号を付してその説明を省略する場合がある。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited to embodiment shown below. In addition, the film thickness, material, manufacturing method, and the like described in the following embodiments are merely examples, and are not limited to the items described below. Moreover, in the following embodiment, the same code | symbol may be attached | subjected with respect to substantially the same member, and the description may be abbreviate | omitted.
　図１～図５（ｂ）を参照しながら、本発明の実施形態に係る半導体装置の製造方法を示す。図１は、本実施形態に係る半導体装置の平面図である。図２（ａ）～図５（ｂ）は、本実施形態に係る半導体装置の製造方法を工程順に示す断面図である。図２（ａ）～図４（ｂ）は図１に示すVIA－VIA線における断面図であり、図５（ａ）及び（ｂ）は図１に示すVIB－VIB線における断面図である。図１～図４（ｂ）において、「ＮＦＥＴ」はＮ型ＭＩＳトランジスタが形成されている領域を示しており、「ＳＴＩ」は素子分離領域を示している。つまり、本実施形態では、Ｎ型ＭＩＳトランジスタを備えた半導体装置の製造方法及びその構造を示す。また、図１において、「Ｓ」、「Ｄ」及び「Ｇ」はそれぞれソース領域、ドレイン領域及びゲート領域を示しており、「Ｗ」及び「Ｌ」はそれぞれゲート幅及びゲート長さを示しており、「Ａ」は、素子分離領域ＳＴＩのうち素子形成領域と接する部分（本実施形態では、「Ｎ型ＦＥＴのエッジ部」と称する）である。 A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of the semiconductor device according to the present embodiment. 2A to 5B are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps. 2 (a) to 4 (b) are cross-sectional views taken along the line VIA-VIA shown in FIG. 1, and FIGS. 5 (a) and 5 (b) are cross-sectional views taken along the line VIB-VIB shown in FIG. In FIG. 1 to FIG. 4B, “NFET” indicates a region where an N-type MIS transistor is formed, and “STI” indicates an element isolation region. That is, in this embodiment, a method for manufacturing a semiconductor device including an N-type MIS transistor and its structure are shown. In FIG. 1, “S”, “D”, and “G” indicate a source region, a drain region, and a gate region, respectively, and “W” and “L” indicate a gate width and a gate length, respectively. “A” is a portion in contact with the element formation region in the element isolation region STI (referred to as an “edge portion of the N-type FET” in the present embodiment).
　まず、図２（ａ）に示す工程では、熱酸化法により、例えばシリコンからなる半導体基板（以下、「基板」と称する）１００の上に、例えば膜厚１０ｎｍのシリコン酸化膜１０１を形成する。続いて、シリコン酸化膜１０１の上に、例えば膜厚７０ｎｍのシリコン窒化膜１０２を形成する。続いて、シリコン窒化膜１０２の上にレジスト膜（不図示）を形成してから、フォトリソグラフィ技術を用いてレジスト膜のうち素子分離領域ＳＴＩとなる部分に開口を形成する。これにより、シリコン窒化膜１０２の上には、素子分離領域ＳＴＩとなる部分においてシリコン窒化膜１０２を露出するレジストパターン１０３が形成される。 First, in the process shown in FIG. 2A, a silicon oxide film 101 of, eg, a 10 nm-thickness is formed on a semiconductor substrate (hereinafter referred to as “substrate”) 100 made of, eg, silicon, by thermal oxidation. Subsequently, a silicon nitride film 102 of, eg, a 70 nm-thickness is formed on the silicon oxide film 101. Subsequently, after forming a resist film (not shown) on the silicon nitride film 102, an opening is formed in a portion of the resist film that becomes the element isolation region STI by using a photolithography technique. As a result, a resist pattern 103 is formed on the silicon nitride film 102 so as to expose the silicon nitride film 102 in a portion serving as the element isolation region STI.
　次に、図２（ｂ）に示す工程では、レジストパターン１０３（図２（ａ）を参照）をマスクに用いて、シリコン窒化膜１０２、シリコン酸化膜１０１、及び基板１００をエッチングする。これにより、基板１００内に、深さが例えば３００ｎｍのトレンチ１０４が形成される。続いて、レジストパターン１０３を除去し、その後、酸素ガス及び水素ガス雰囲気中で熱処理を行う。これにより、トレンチ１０４の側壁上及び底面上に、例えば膜厚２ｎｍのシリコン酸化膜からなる下地絶縁膜１０５が形成される（工程（ａ））。 2B, the silicon nitride film 102, the silicon oxide film 101, and the substrate 100 are etched using the resist pattern 103 (see FIG. 2A) as a mask. As a result, a trench 104 having a depth of, for example, 300 nm is formed in the substrate 100. Subsequently, the resist pattern 103 is removed, and then heat treatment is performed in an oxygen gas and hydrogen gas atmosphere. As a result, a base insulating film 105 made of, for example, a silicon oxide film having a thickness of 2 nm is formed on the sidewall and the bottom surface of the trench 104 (step (a)).
　次に、図２（ｃ）に示す工程では、例えばＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法を用いて、シリコン窒化膜１０２の上面及び側面、シリコン酸化膜１０１の側面、並びに、下地絶縁膜１０５の上に、例えば膜厚１ｎｍのランタン酸化膜からなる第１のキャップ膜（キャップ膜）１０６を形成する（工程（ｂ））。続いて、窒素ガス雰囲気中において、例えば８００℃で３０秒間、熱処理を行う。これにより、第１のキャップ膜１０６中のランタンが下地絶縁膜１０５へ拡散する（工程（ｆ））。よって、下地絶縁膜１０５内にはランタンが存在することになる。このとき、ランタンが下地絶縁膜１０５における第１のキャップ膜１０６との界面近傍に存在するように、熱拡散を行うことが好ましい。 Next, in the process shown in FIG. 2C, the top surface and side surface of the silicon nitride film 102, the side surface of the silicon oxide film 101, and the base insulating film 105 are formed using, for example, an ALD (Atomic Layer Deposition) method. For example, a first cap film (cap film) 106 made of a lanthanum oxide film having a thickness of 1 nm is formed (step (b)). Subsequently, heat treatment is performed in a nitrogen gas atmosphere at, for example, 800 ° C. for 30 seconds. Thereby, the lanthanum in the first cap film 106 diffuses into the base insulating film 105 (step (f)). Accordingly, lanthanum exists in the base insulating film 105. At this time, it is preferable to perform thermal diffusion so that lanthanum exists in the vicinity of the interface between the base insulating film 105 and the first cap film 106.
　次に、図３（ａ）に示す工程では、例えば、プラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）又は熱ＣＶＤ法を用いて、トレンチ１０４の内部を埋め込むように基板１００の全面上に例えば膜厚５００ｎｍのシリコン酸化膜（不図示）を形成する。その後、例えばＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）法を用いて、シリコン酸化膜におけるシリコン窒化膜１０２よりも上に存在している部分、及び、第１のキャップ膜１０６におけるシリコン窒化膜１０２よりも上に存在している部分を除去する。これにより、基板１００上の表面が平坦化され、トレンチ１０４内にはシリコン酸化膜からなる素子分離絶縁膜１０７が下地絶縁膜１０５及び第１のキャップ膜１０６を介してトレンチ１０４の側壁上及び底面上に形成される。つまり、第１のキャップ膜１０６は、トレンチ１０４内において、下地絶縁膜１０５と素子分離絶縁膜１０７とで挟まれる。この素子分離絶縁膜１０７と第１のキャップ膜１０６と下地絶縁膜１０５とで素子分離領域ＳＴＩが構成され（工程（ｃ））、基板１００のうち素子分離領域ＳＴＩで囲まれた部分が素子形成領域１００ａとなる。 Next, in the process shown in FIG. 3A, for example, silicon having a film thickness of, for example, 500 nm is formed on the entire surface of the substrate 100 so as to embed the trench 104 by using, for example, plasma CVD (Chemical Vapor Deposition) or thermal CVD. An oxide film (not shown) is formed. Thereafter, using, for example, a CMP (Chemical Mechanical Polishing) method, a portion of the silicon oxide film existing above the silicon nitride film 102 and a portion of the first cap film 106 above the silicon nitride film 102 are present. Remove the part that is. As a result, the surface on the substrate 100 is planarized, and the element isolation insulating film 107 made of a silicon oxide film is formed in the trench 104 on the side wall and the bottom surface of the trench 104 via the base insulating film 105 and the first cap film 106. Formed on top. That is, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104. The element isolation insulating film 107, the first cap film 106, and the base insulating film 105 form an element isolation region STI (step (c)), and a portion of the substrate 100 surrounded by the element isolation region STI is formed as an element. It becomes area | region 100a.
　次に、図３（ｂ）に示す工程では、例えばリン酸などの薬液を用いたエッチングにより、シリコン酸化膜１０１上のシリコン窒化膜１０２、及び第１のキャップ膜１０６におけるシリコン酸化膜１０１よりも上に存在している部分を除去する。続いて、所望の領域を開口するレジストパターン（図示せず）を形成した後、そのレジストパターンをマスクに用いて基板１００に対して不純物イオン１０８を注入する。本実施形態ではＮ型ＦＥＴを作製するので、不純物イオン１０８として例えばホウ素等のＰ型不純物を用いれば良い。このようにして、Ｐ型ウェル（不図示）の形成及びチャネル領域の閾値電圧の調整を行う。続いて、上記レジストパターンを除去してから、基板１００に注入された不純物（Ｐ型不純物）を拡散及び活性化させるために、窒素雰囲気下において１０００℃で１分間のアニールを行う。 Next, in the process shown in FIG. 3B, the silicon nitride film 102 on the silicon oxide film 101 and the silicon oxide film 101 in the first cap film 106 are etched by etching using a chemical solution such as phosphoric acid. Remove the existing part. Subsequently, after forming a resist pattern (not shown) that opens a desired region, impurity ions 108 are implanted into the substrate 100 using the resist pattern as a mask. In this embodiment, since an N-type FET is manufactured, a P-type impurity such as boron may be used as the impurity ions 108. In this manner, a P-type well (not shown) is formed and the threshold voltage of the channel region is adjusted. Subsequently, after removing the resist pattern, annealing is performed at 1000 ° C. for 1 minute in a nitrogen atmosphere in order to diffuse and activate impurities (P-type impurities) implanted into the substrate 100.
　次に、図３（ｃ）に示す工程では、例えばフッ酸などの薬液を用いたエッチングにより、シリコン酸化膜１０１を除去する。このとき、トレンチ１０４中に形成されたシリコン酸化膜のウェットエッチングレートは、熱酸化法で形成されたシリコン酸化膜１０１のウェットエッチングレートよりも高い。そのため、Ｎ型ＦＥＴのエッジ部では、素子分離絶縁膜１０７の上面に凹部１０７ａが形成される。これにより、第１のキャップ膜１０６のうちトレンチの側壁の上部（素子形成領域における上部側面）１０４ａ上に形成された部分が露出される。 Next, in the step shown in FIG. 3C, the silicon oxide film 101 is removed by etching using a chemical solution such as hydrofluoric acid. At this time, the wet etching rate of the silicon oxide film formed in the trench 104 is higher than the wet etching rate of the silicon oxide film 101 formed by the thermal oxidation method. Therefore, a recess 107 a is formed on the upper surface of the element isolation insulating film 107 at the edge portion of the N-type FET. As a result, a portion of the first cap film 106 formed on the upper side wall (upper side surface in the element formation region) 104a of the trench is exposed.
　次に、図４（ａ）及び図５（ａ）に示す工程では、素子形成領域１００ａ上に、例えば膜厚が１ｎｍのシリコン酸化膜からなる酸素含有膜１０９を形成する。続いて、例えばＡＬＤ法により、酸素含有膜１０９の上面上、凹部１０７ａの内面上、及び素子分離領域ＳＴＩの上面上に、例えば膜厚２ｎｍのＨｆＯ２膜（ハフニウム酸化膜）からなる高誘電率膜１１０を形成する。これにより、第１のキャップ膜１０６は、高誘電率膜１１０のうち素子形成領域における上部側面１０４ａ上に形成された部分（第２の部分）１１０ｂと下地絶縁膜１０５とに挟まれる。また、下地絶縁膜１０５内には、ランタンが含まれている。これらのことから、下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとの界面にランタンが存在するので、この界面には電気双極子が発生する。よって、Ｎ型ＦＥＴのエッジ部において第１のキャップ膜１０６により閾値電圧を低減させることが可能となる。 Next, in the steps shown in FIGS. 4A and 5A, an oxygen-containing film 109 made of, for example, a silicon oxide film having a thickness of 1 nm is formed on the element formation region 100a. Subsequently, a high dielectric constant made of, for example, a 2 nm-thickness HfO 2 film (hafnium oxide film) is formed on the upper surface of the oxygen-containing film 109, the inner surface of the recess 107a, and the upper surface of the element isolation region STI by, for example, ALD. A film 110 is formed. As a result, the first cap film 106 is sandwiched between the portion (second portion) 110 b formed on the upper side surface 104 a in the element formation region of the high dielectric constant film 110 and the base insulating film 105. The base insulating film 105 contains lanthanum. For these reasons, since lanthanum exists at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage can be reduced by the first cap film 106 at the edge portion of the N-type FET.
　続いて、高誘電率膜１１０の上面上に、例えば膜厚が１ｎｍであるランタン酸化膜からなる第２のキャップ膜１１１を形成する。よって、第２のキャップ膜１１１は、高誘電率膜１１０のうち酸素含有膜１０９の上面上に形成された部分（第１の部分）１１０ａの上面上だけでなく、高誘電率膜１１０の第２の部分１１０ｂの上面上にも形成される。なお、第２のキャップ膜１１１のうち高誘電率膜１１０の第２の部分１１０ｂ上に形成された部分の膜厚は、カバレッジ劣化により、第２のキャップ膜１１１のうち高誘電率膜１１０の第１の部分１１０ａ上に形成された部分の膜厚よりも薄い。それから、第２のキャップ膜１１１の上面上に、例えば膜厚１０ｎｍのＴｉＮ膜（窒化チタン膜）１１３を形成し、ＴｉＮ膜１１３の上面上に、例えば膜厚８０ｎｍのポリシリコン膜１１４を形成する。 Subsequently, a second cap film 111 made of, for example, a lanthanum oxide film having a thickness of 1 nm is formed on the upper surface of the high dielectric constant film 110. Therefore, the second cap film 111 is formed not only on the upper surface of the portion (first portion) 110a formed on the upper surface of the oxygen-containing film 109 in the high dielectric constant film 110 but also on the second dielectric layer 110 of the high dielectric constant film 110. Also formed on the upper surface of the second portion 110b. Note that the film thickness of the portion of the second cap film 111 formed on the second portion 110b of the high dielectric constant film 110 is that of the high dielectric constant film 110 of the second cap film 111 due to coverage deterioration. It is thinner than the thickness of the portion formed on the first portion 110a. Then, a TiN film (titanium nitride film) 113 having a thickness of, for example, 10 nm is formed on the upper surface of the second cap film 111, and a polysilicon film 114 having a thickness of, for example, 80 nm is formed on the upper surface of the TiN film 113. .
　次に、図４（ｂ）及び図５（ｂ）に示す工程では、ポリシリコン膜１１４の上面上にレジストマスク（不図示）を形成した後、そのレジストマスクをマスクとしてドライエッチングを行う。このとき、ゲート長Ｌが例えば５０ｎｍとなるように、ドライエッチングを行えば良い。このドライエッチングにより、酸素含有膜１０９、高誘電率膜１１０の第１の部分１１０ａ及び第２のキャップ膜１１１が順に積層されて構成されたゲート絶縁膜１１２が素子形成領域１００ａの上面上に形成され（工程（ｄ））、ＴｉＮ膜１１３及びポリシリコン膜１１４が順に積層されて構成されたゲート電極１１５がゲート絶縁膜１１２の上面上に形成される（工程（ｅ））。なお、図４（ｂ）に示すように、ゲート絶縁膜１１２は、素子形成領域における上部側面１０４ａ上にも形成されており、ゲート電極１１５は、ゲート絶縁膜１１２（高誘電率膜１１０における第２の部分１１０ｂ）を介して素子形成領域における上部側面１０４ａ上にも形成されている。 4B and 5B, after forming a resist mask (not shown) on the upper surface of the polysilicon film 114, dry etching is performed using the resist mask as a mask. At this time, dry etching may be performed so that the gate length L is, for example, 50 nm. By this dry etching, a gate insulating film 112 formed by sequentially stacking the oxygen-containing film 109, the first portion 110a of the high dielectric constant film 110, and the second cap film 111 is formed on the upper surface of the element formation region 100a. (Step (d)), a gate electrode 115 formed by sequentially laminating the TiN film 113 and the polysilicon film 114 is formed on the upper surface of the gate insulating film 112 (Step (e)). As shown in FIG. 4B, the gate insulating film 112 is also formed on the upper side surface 104a in the element formation region, and the gate electrode 115 is formed of the gate insulating film 112 (the first layer in the high dielectric constant film 110). 2 is also formed on the upper side surface 104a in the element formation region via the second portion 110b).
　続いて、基板１００の上面上に、所望の領域において開口されたレジスト（不図示）を形成する。そして、そのレジスト及びゲート電極１１５をマスクとして、砒素イオン又はリンイオン等のＮ型不純物をイオン注入する。このとき、注入エネルギーは例えば２～５ｋｅＶであり、ドーズ量は例えば１×１０１５～１×１０１６／ｃｍ２である。これにより、素子形成領域１００ａにおけるゲート電極１１５の側方下に、Ｎ型エクステンション領域１１６が形成される。その後、レジストを除去する。 Subsequently, a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100. Then, N-type impurities such as arsenic ions or phosphorus ions are implanted using the resist and the gate electrode 115 as a mask. At this time, the implantation energy is, for example, 2 to 5 keV, and the dose amount is, for example, 1 × 10 15 to 1 × 10 16 / cm 2 . As a result, an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. Thereafter, the resist is removed.
　続いて、基板１００の上面上に例えば８０ｎｍのシリコン窒化膜（不図示）を形成した後、そのシリコン窒化膜に対して異方性エッチングを行う。これにより、ゲート電極１１５の側面上には、サイドウォールスペーサー１１７が形成される。 Subsequently, after forming a silicon nitride film (not shown) of, for example, 80 nm on the upper surface of the substrate 100, anisotropic etching is performed on the silicon nitride film. As a result, sidewall spacers 117 are formed on the side surfaces of the gate electrode 115.
　続いて、基板１００の上面上に、所望の領域において開口されたレジスト（不図示）を形成する。そして、そのレジスト、ゲート電極１１５及びサイドウォールスペーサー１１７をマスクとして、砒素イオン又はリンイオン等のＮ型不純物をイオン注入する。このとき、注入エネルギーは例えば３０ｋｅＶであり、ドーズ量は例えば１×１０１６／ｃｍ２である。これにより、素子形成領域におけるサイドウォールスペーサー１１７の側方下に、Ｎ型ソースドレイン領域１１８が形成される。その後、レジストを除去する。 Subsequently, a resist (not shown) opened in a desired region is formed on the upper surface of the substrate 100. Then, N-type impurities such as arsenic ions or phosphorus ions are ion-implanted using the resist, the gate electrode 115 and the sidewall spacer 117 as a mask. At this time, the implantation energy is, for example, 30 keV, and the dose amount is, for example, 1 × 10 16 / cm 2 . As a result, an N-type source / drain region 118 is formed below the side wall spacer 117 in the element formation region. Thereafter, the resist is removed.
　それから、１０００℃で０秒のスパイクアニールを行う。これにより、Ｎ型エクステンション領域１１６に注入されたＮ型不純物が拡散及び活性化され、Ｎ型エクステンション領域１１６の接合深さが２０ｎｍ程度となる。同じく、Ｎ型ソースドレイン領域１１８に注入されたＮ型不純物が拡散及び活性化され、Ｎ型ソースドレイン領域１１８の接合深さが６０ｎｍ程度となる。このようにして本実施形態に係る半導体装置が作製される。 Then, spike annealing is performed at 1000 ° C. for 0 second. As a result, the N-type impurity implanted into the N-type extension region 116 is diffused and activated, and the junction depth of the N-type extension region 116 becomes about 20 nm. Similarly, the N-type impurity implanted into the N-type source / drain region 118 is diffused and activated, and the junction depth of the N-type source / drain region 118 becomes about 60 nm. In this way, the semiconductor device according to this embodiment is manufactured.
　このスパイクアニール工程では、第２のキャップ膜１１１中のランタンが高誘電率膜１１０と酸素含有膜１０９との界面へ拡散する。これにより、その界面には電気双極子が発生するので、Ｎ型ＦＥＴの閾値電圧を低減させることができる。 In this spike annealing process, lanthanum in the second cap film 111 diffuses to the interface between the high dielectric constant film 110 and the oxygen-containing film 109. Thereby, since an electric dipole is generated at the interface, the threshold voltage of the N-type FET can be reduced.
　それだけでなく、このスパイクアニール工程では、第１のキャップ膜１０６中のランタンが高誘電率膜１１０の第２の部分１１０ｂへ拡散する。このように、高誘電率膜１１０の第１の部分１１０ａへは第２のキャップ膜１１１中のランタンが拡散するに過ぎないが、高誘電率膜１１０の第２の部分１１０ｂへは第２のキャップ膜１１１中のランタンだけでなく第１のキャップ膜１０６中のランタンも拡散する。よって、高誘電率膜１１０の第２の部分１１０ｂにおけるランタン濃度は高誘電率膜１１０の第１の部分１１０ａにおけるランタン濃度以上になる。 In addition, in this spike annealing process, lanthanum in the first cap film 106 diffuses into the second portion 110b of the high dielectric constant film 110. As described above, the lanthanum in the second cap film 111 is only diffused into the first portion 110a of the high dielectric constant film 110, but the second portion 110b of the high dielectric constant film 110 is diffused into the second portion 110b. Not only lanthanum in the cap film 111 but also lanthanum in the first cap film 106 diffuses. Therefore, the lanthanum concentration in the second portion 110b of the high dielectric constant film 110 is equal to or higher than the lanthanum concentration in the first portion 110a of the high dielectric constant film 110.
　以下では、図１及び図６（ａ）～図７を参照しながら、本実施形態に係る半導体装置の構成を簡単に説明する。図６（ａ）は図１に示すVIA－VIA線における断面図であり、図６（ｂ）は図１に示すVIB－VIB線における断面図である。図７は、ナローチャネル特性の評価結果を模式的に示すグラフ図である。 Hereinafter, the configuration of the semiconductor device according to the present embodiment will be briefly described with reference to FIGS. 1 and 6A to 7. 6A is a cross-sectional view taken along the line VIA-VIA shown in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line VIB-VIB shown in FIG. FIG. 7 is a graph schematically showing the evaluation results of the narrow channel characteristics.
　基板１００内には、トレンチ１０４が形成されている。トレンチ１０４の側壁上及び底面上には、下地絶縁膜１０５及び第１のキャップ膜１０６が順に形成されており、トレンチ１０４内には、下地絶縁膜１０５及び第１のキャップ膜１０６を介して素子分離絶縁膜１０７が形成されている。下地絶縁膜１０５と第１のキャップ膜１０６と素子分離絶縁膜１０７とで素子分離領域ＳＴＩが構成されており、基板１００のうち素子分離領域ＳＴＩで囲まれた部分が素子形成領域１００ａである。 A trench 104 is formed in the substrate 100. A base insulating film 105 and a first cap film 106 are sequentially formed on the sidewall and the bottom surface of the trench 104, and the element is interposed in the trench 104 via the base insulating film 105 and the first cap film 106. An isolation insulating film 107 is formed. The base insulating film 105, the first cap film 106, and the element isolation insulating film 107 constitute an element isolation region STI, and a portion of the substrate 100 surrounded by the element isolation region STI is an element formation region 100a.
　素子形成領域１００ａの上にはゲート絶縁膜１１２及びゲート電極１１５が順に形成されている。ゲート絶縁膜１１２では、酸素含有膜１０９、高誘電率膜１１０及び第２のキャップ膜１１１が素子形成領域１００ａ上に順に形成されており、酸素含有膜１０９と高誘電率膜１１０との界面にはランタンが存在している。ゲート電極１１５では、ＴｉＮ膜１１３及びポリシリコン膜１１４がゲート絶縁膜１１２の上に順に形成されている。 A gate insulating film 112 and a gate electrode 115 are sequentially formed on the element formation region 100a. In the gate insulating film 112, an oxygen-containing film 109, a high dielectric constant film 110, and a second cap film 111 are sequentially formed on the element formation region 100 a, and at the interface between the oxygen-containing film 109 and the high dielectric constant film 110. There is a lantern. In the gate electrode 115, a TiN film 113 and a polysilicon film 114 are sequentially formed on the gate insulating film 112.
　高誘電率膜１１０は、素子形成領域１００ａ上だけでなく素子分離領域ＳＴＩ上にも形成されており、具体的には、下地絶縁膜１０５及び第１のキャップ膜１０６を介して素子形成領域における上部側面１０４ａ上にも設けられている（第２の部分１１０ｂ）。よって、第１のキャップ膜１０６は、素子形成領域における上部側面１０４ａ上において下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとで挟まれている。同様に、第２のキャップ膜１１１、ＴｉＮ膜１１３及びポリシリコン膜１１４は、素子形成領域１００ａ上だけでなく素子分離領域ＳＴＩ上にも形成されている。 The high dielectric constant film 110 is formed not only on the element formation region 100 a but also on the element isolation region STI. Specifically, in the element formation region via the base insulating film 105 and the first cap film 106. It is also provided on the upper side surface 104a (second portion 110b). Therefore, the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110 on the upper side surface 104a in the element formation region. Similarly, the second cap film 111, the TiN film 113, and the polysilicon film 114 are formed not only on the element formation region 100a but also on the element isolation region STI.
　ゲート電極１１５の側面上にはサイドウォールスペーサー１１７が形成されており、素子形成領域１００ａ内のうちゲート電極１１５の側方下にはＮ型エクステンション領域１１６が形成されており、素子形成領域１００ａ内のうちサイドウォールスペーサー１１７の側方下にはＮ型ソースドレイン領域１１８が形成されている。 A sidewall spacer 117 is formed on the side surface of the gate electrode 115, and an N-type extension region 116 is formed below the side of the gate electrode 115 in the element formation region 100a. An N-type source / drain region 118 is formed below the side wall spacer 117.
　以上説明したように、本実施形態では、第１のキャップ膜１０６が、トレンチ１０４内において下地絶縁膜１０５と素子分離絶縁膜１０７とで挟まれており、素子形成領域における上部側面１０４ａ上において下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとで挟まれている。また、下地絶縁膜１０５は、特に第１のキャップ膜１０６との界面近傍において、ランタンを含有している。これらのことから、下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとの界面に電気双極子が発生するので、Ｎ型ＦＥＴのエッジ部Ａにおいて第１のキャップ膜１０６により閾値電圧の低減を図ることができる。よって、本実施形態では、図７の線６１に示すように、ナローチャネル特性の低下を抑制することができる。 As described above, in the present embodiment, the first cap film 106 is sandwiched between the base insulating film 105 and the element isolation insulating film 107 in the trench 104, and the base is formed on the upper side surface 104a in the element formation region. It is sandwiched between the insulating film 105 and the second portion 110 b of the high dielectric constant film 110. The base insulating film 105 contains lanthanum, particularly in the vicinity of the interface with the first cap film 106. For these reasons, since an electric dipole is generated at the interface between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the threshold voltage is applied by the first cap film 106 at the edge portion A of the N-type FET. Can be reduced. Therefore, in this embodiment, as shown by the line 61 in FIG. 7, it is possible to suppress a decrease in narrow channel characteristics.
　本実施形態では、Ｎ型ＦＥＴのエッジ部Ａにおいて第１のキャップ膜１０６により閾値電圧を低減させることができる。そのため、第２のキャップ膜１１１を形成するときにＮ型ＦＥＴのエッジ部Ａにおいてその第２のキャップ膜１１１の膜厚が薄くなったとしても（カバレッジ劣化）、ナローチャネル特性の低下を抑制できる。さらに、高誘電率膜１１０を形成するときにＮ型ＦＥＴのエッジ部Ａにおいてその高誘電率膜１１０の膜厚が厚くなったとしても（ローディング効果）、ナローチャネル特性の低下を抑制できる。それだけでなく、熱処理中に第２のキャップ膜１１１中のランタンがゲート電極１１５に拡散しても、ナローチャネル特性の低下を抑制できる。 In this embodiment, the threshold voltage can be reduced by the first cap film 106 at the edge portion A of the N-type FET. Therefore, even when the thickness of the second cap film 111 is reduced at the edge portion A of the N-type FET when the second cap film 111 is formed (coverage deterioration), it is possible to suppress a decrease in narrow channel characteristics. . Furthermore, even when the high dielectric constant film 110 is formed and the thickness of the high dielectric constant film 110 becomes thicker at the edge portion A of the N-type FET (loading effect), it is possible to suppress a decrease in narrow channel characteristics. In addition, even if lanthanum in the second cap film 111 diffuses into the gate electrode 115 during the heat treatment, it is possible to suppress a decrease in narrow channel characteristics.
　また、本実施形態では、酸素含有膜１０９と高誘電率膜１１０との界面にはランタンが存在しているので、この界面には電気双極子が発生する。よって、Ｎ型ＦＥＴの閾値電圧を低減させることができる。 In this embodiment, since lanthanum is present at the interface between the oxygen-containing film 109 and the high dielectric constant film 110, an electric dipole is generated at this interface. Therefore, the threshold voltage of the N-type FET can be reduced.
　なお、本実施形態は以下に示す構成を有していても良い。 Note that this embodiment may have the following configuration.
　図２（ｂ）に示す工程では、シリコン窒化膜１０２及びシリコン酸化膜１０１のそれぞれのエッチング端面が基板１００のエッチング端面よりも５ｎｍ程度トランジスタの中央部側に位置するように、シリコン窒化膜１０２、シリコン酸化膜１０１、及び基板１００をエッチングすることが好ましい。これにより、次工程である下地絶縁膜１０５をトレンチ１０４の側壁上及び底面上に形成する工程において、トレンチ１０４の側壁の上端の角を落として丸めることができる。これにより、トレンチ１０４の側壁の上端において電界が集中することを回避できる。 In the step shown in FIG. 2B, the silicon nitride film 102, the silicon nitride film 102, and the silicon oxide film 101 are positioned so that the etching end faces of the silicon nitride film 102 and the silicon oxide film 101 are about 5 nm from the etching end face of the substrate 100. It is preferable to etch the silicon oxide film 101 and the substrate 100. Thereby, in the process of forming the base insulating film 105 on the side wall and the bottom surface of the trench 104, which is the next process, the corner at the upper end of the side wall of the trench 104 can be rounded off. Thereby, it is possible to avoid the concentration of the electric field at the upper end of the sidewall of the trench 104.
　図２（ｃ）における熱処理では、その熱処理の条件、下地絶縁膜１０５の構成及び第１のキャップ膜１０６の構成によっては、第１のキャップ膜１０６が完全になくなるまでランタンが下地絶縁膜１０５に拡散する場合がある。この場合、素子形成領域における上部側面１０４ａ上には、下地絶縁膜１０５と第１のキャップ膜１０６との境界が存在しない。別の言い方をすると、製造された半導体装置では、下地絶縁膜１０５上に第１のキャップ膜１０６が形成されておらず、その代わりに下地絶縁膜１０５が高誘電率膜１１０の第２の部分１１０ｂとの界面近傍にランタンを含有している。このような構成を有する半導体装置であっても、下地絶縁膜１０５と高誘電率膜１１０との界面にランタンが存在するので、ナローチャネル特性の劣化を抑制することができる。なお、ランタンが第１のキャップ膜１０６から下地絶縁膜１０５へ拡散した後に第１のキャップ膜１０６を除去しても良い。 In the heat treatment in FIG. 2C, depending on the conditions of the heat treatment, the structure of the base insulating film 105, and the structure of the first cap film 106, lanthanum forms the base insulating film 105 until the first cap film 106 is completely removed. May diffuse. In this case, the boundary between the base insulating film 105 and the first cap film 106 does not exist on the upper side surface 104a in the element formation region. In other words, in the manufactured semiconductor device, the first cap film 106 is not formed on the base insulating film 105, and instead, the base insulating film 105 is the second portion of the high dielectric constant film 110. Lanthanum is contained in the vicinity of the interface with 110b. Even in the semiconductor device having such a structure, since lanthanum exists at the interface between the base insulating film 105 and the high dielectric constant film 110, deterioration of narrow channel characteristics can be suppressed. Note that the first cap film 106 may be removed after lanthanum is diffused from the first cap film 106 to the base insulating film 105.
　図２（ｃ）における熱処理を省略しても良い。この場合には、図３（ｂ）における熱処理又は図４（ｂ）及び図５（ｂ）における熱処理により、第１のキャップ膜１０６中のランタンが下地絶縁膜１０５へ拡散する。しかし、図２（ｃ）において熱処理を行えば、その熱処理の後に第１のキャップ膜１０６が除去された場合であってもナローチャネル特性の劣化を抑制することができる。よって、図２（ｃ）において熱処理を行うことが好ましい。 The heat treatment in FIG. 2 (c) may be omitted. In this case, the lanthanum in the first cap film 106 diffuses into the base insulating film 105 by the heat treatment in FIG. 3B or the heat treatment in FIGS. 4B and 5B. However, if heat treatment is performed in FIG. 2C, the degradation of the narrow channel characteristics can be suppressed even when the first cap film 106 is removed after the heat treatment. Therefore, it is preferable to perform heat treatment in FIG.
　図４（ｂ）及び図５（ｂ）における熱処理では、その熱処理の条件、高誘電率膜１１０の構成及び第２のキャップ膜１１１の構成によっては、第２のキャップ膜１１１が完全になくなるまでランタンが高誘電率膜１１０の下部又は酸素含有膜１０９の上部へ拡散する場合がある。この場合、製造された半導体装置では、高誘電率膜１１０と第２のキャップ膜１１１との境界が存在しない。別の言い方をすると、製造された半導体装置では、高誘電率膜１１０の上に第２のキャップ膜１１１が形成されておらず、その代わりに酸素含有膜１０９と高誘電率膜１１０との界面近傍にランタンが存在している。このような構成を有する半導体装置であっても、酸素含有膜１０９と高誘電率膜１１０との界面にランタンが存在するので、Ｎ型ＦＥＴの閾値電圧を低減させることができる。 In the heat treatment in FIGS. 4B and 5B, the second cap film 111 is completely removed depending on the conditions of the heat treatment, the configuration of the high dielectric constant film 110, and the configuration of the second cap film 111. Lanthanum may diffuse to the lower part of the high dielectric constant film 110 or the upper part of the oxygen-containing film 109. In this case, in the manufactured semiconductor device, there is no boundary between the high dielectric constant film 110 and the second cap film 111. In other words, in the manufactured semiconductor device, the second cap film 111 is not formed on the high dielectric constant film 110, and instead, the interface between the oxygen-containing film 109 and the high dielectric constant film 110. There is a lantern in the vicinity. Even in the semiconductor device having such a configuration, since lanthanum exists at the interface between the oxygen-containing film 109 and the high dielectric constant film 110, the threshold voltage of the N-type FET can be reduced.
　図４（ｂ）及び図５（ｂ）における熱処理においてランタンを高誘電率膜１１０の下部まで拡散させることが難しい場合には、第２のキャップ膜１１１を酸素含有膜１０９と高誘電率膜１１０との間に形成すれば良い。 When it is difficult to diffuse lanthanum to the lower part of the high dielectric constant film 110 in the heat treatment in FIGS. 4B and 5B, the second cap film 111 is replaced with the oxygen-containing film 109 and the high dielectric constant film 110. What is necessary is just to form between.
　下地絶縁膜１０５は、シリコン酸化膜に限定されず、例えばシリコン酸窒化膜であっても良い。下地絶縁膜１０５が酸素を含有していれば、第１のキャップ膜１０６を用いてナローチャネル特性の劣化を抑制することができる。 The base insulating film 105 is not limited to a silicon oxide film, and may be a silicon oxynitride film, for example. If the base insulating film 105 contains oxygen, the first cap film 106 can be used to suppress degradation of the narrow channel characteristics.
　下地絶縁膜１０５の膜厚は、２ｎｍに限定されず、１～１０ｎｍ程度の範囲内であれば良い。下地絶縁膜１０５の膜厚が０．５～１５ｎｍ程度の範囲内であれば、ナローチャネル特性の劣化を抑制することができる。 The film thickness of the base insulating film 105 is not limited to 2 nm, and may be in the range of about 1 to 10 nm. When the thickness of the base insulating film 105 is in the range of about 0.5 to 15 nm, it is possible to suppress the degradation of narrow channel characteristics.
　第１のキャップ膜１０６は、Ｎ型ＦＥＴの閾値電圧を低下させることができる金属を含有していれば良い。このような金属としては、ランタン以外に、ジスプロシウム（Ｄｙ）、スカンジウム（Ｓｃ）、エルビウム（Ｅｒ）、マグネシウム（Ｍｇ）及びストロンチウム（Ｓｒ）等を挙げることができる。よって、第１のキャップ膜１０６は、ランタン酸化膜に限定されず、上記金属のうちの何れか１つの金属からなる膜であっても良く、上記金属のうちの何れか１つの金属の酸化膜であっても良く、上記金属のうちの何れか２つ以上の金属を含む膜であっても良く、上記金属のうちの何れか２つ以上の金属の酸化物を含有する膜であっても良い。 The first cap film 106 only needs to contain a metal that can reduce the threshold voltage of the N-type FET. Examples of such a metal include dysprosium (Dy), scandium (Sc), erbium (Er), magnesium (Mg), and strontium (Sr) in addition to lanthanum. Therefore, the first cap film 106 is not limited to the lanthanum oxide film, and may be a film made of any one of the above metals, or an oxide film of any one of the above metals. It may be a film containing any two or more of the metals, or a film containing an oxide of any two or more of the metals. good.
　第１のキャップ膜１０６の膜厚は、１ｎｍに限定されない。Ｎ型ＦＥＴのエッジ部Ａにおける閾値電圧の低下量に応じて、第１のキャップ膜１０６の膜厚を調整することが好ましい。つまり、Ｎ型ＦＥＴのエッジ部Ａにおける閾値電圧の低下量が小さいと想定される場合（例えばゲート幅がそれほど狭くない場合）には、第１のキャップ膜１０６の膜厚を薄膜化（例えば、０．５ｎｍ）すれば良く、Ｎ型ＦＥＴのエッジ部Ａにおける閾値電圧の低下量が大きいと想定される場合（例えばゲート幅が狭い場合）には、第１のキャップ膜１０６の膜厚を厚膜化（例えば、２ｎｍ）すればよい。 The film thickness of the first cap film 106 is not limited to 1 nm. It is preferable to adjust the film thickness of the first cap film 106 in accordance with the amount of decrease in the threshold voltage at the edge portion A of the N-type FET. That is, when it is assumed that the threshold voltage decrease amount at the edge portion A of the N-type FET is small (for example, when the gate width is not so narrow), the thickness of the first cap film 106 is reduced (for example, 0.5 nm), and when the reduction amount of the threshold voltage at the edge portion A of the N-type FET is assumed to be large (for example, when the gate width is narrow), the thickness of the first cap film 106 is increased. A film may be formed (for example, 2 nm).
　第１のキャップ膜１０６が下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとで挟まれていれば、ナローチャネル特性の劣化を抑制することができる。よって、第１のキャップ膜１０６は、下地絶縁膜１０５を介して素子形成領域における上部側面１０４ａ上のみに形成されていれば良く。高誘電率膜１１０は、第１の部分１１０ａ及び第２の部分１１０ｂのみからなっても良い。 If the first cap film 106 is sandwiched between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, the degradation of the narrow channel characteristics can be suppressed. Therefore, the first cap film 106 may be formed only on the upper side surface 104 a in the element formation region with the base insulating film 105 interposed therebetween. The high dielectric constant film 110 may include only the first portion 110a and the second portion 110b.
　高誘電率膜１１０は、シリコン酸化物、シリコン窒化物及びシリコン酸窒化物よりも高誘電率な材料からなれば良く、具体的には誘電率が８以上の金属酸化物、金属酸窒化物、シリケート又は窒素含有シリケートからなれば良い。よって、高誘電率膜１１０は、ＨｆＯ２膜に限定されず、ＨｆＳｉＯ膜（ハフニウムシリコン酸化膜）、ＨｆＳｉＯＮ膜（窒化ハフニウムシリコン酸化膜）、ＺｒＯ２膜（ジルコニウム酸化膜）、又はＨｆＺｒＯ膜（ハフニウムジルコニウム酸化膜）等であっても良い。 The high dielectric constant film 110 may be made of a material having a higher dielectric constant than silicon oxide, silicon nitride, and silicon oxynitride. Specifically, a metal oxide, metal oxynitride having a dielectric constant of 8 or more, A silicate or a nitrogen-containing silicate may be used. Therefore, the high dielectric constant film 110 is not limited to the HfO 2 film, but is an HfSiO film (hafnium silicon oxide film), an HfSiON film (hafnium silicon oxide film), a ZrO 2 film (zirconium oxide film), or an HfZrO film (hafnium film). Zirconium oxide film) or the like.
　第２のキャップ膜１１１は、ランタン酸化膜に限定されず、第１のキャップ膜１０６として使用可能な膜であれば良い。また、第１のキャップ膜１０６と第２のキャップ膜１１１とは、同一の材料からなっても良いし、相異なる材料からなっても良い。 The second cap film 111 is not limited to a lanthanum oxide film, and any film that can be used as the first cap film 106 may be used. Further, the first cap film 106 and the second cap film 111 may be made of the same material or different materials.
　ゲート絶縁膜１１２はランタンを含有していなくても良い。ゲート絶縁膜１１２がランタンを含有していない場合であっても、第１のキャップ膜１０６が下地絶縁膜１０５と高誘電率膜１１０の第２の部分１１０ｂとの間に形成されていれば、ナローチャネル特性の劣化を抑制することができる。 The gate insulating film 112 may not contain lanthanum. Even if the gate insulating film 112 does not contain lanthanum, if the first cap film 106 is formed between the base insulating film 105 and the second portion 110b of the high dielectric constant film 110, Degradation of narrow channel characteristics can be suppressed.
　ゲート電極１１５におけるＴｉＮ膜１１３の代わりに、ＴａＮ膜（タンタルナイトライド膜）、ＴａＣ膜（タンタルカーバイド膜）、及びＴａＣＮ（窒化タンタルカーバイド膜）等のうちのいずれか一種類の単層膜又は二種類以上の積層膜を用いても良い。また、ゲート電極１１５は、ポリシリコン膜１１４を有していなくても良い。 Instead of the TiN film 113 in the gate electrode 115, any one single layer film or two layers of TaN film (tantalum nitride film), TaC film (tantalum carbide film), TaCN (tantalum nitride carbide film), etc. More than one type of laminated film may be used. Further, the gate electrode 115 may not have the polysilicon film 114.
　素子形成領域１００ａ内のうちＮ型エクステンション領域１１６の下方に、Ｐ型ポケット領域が形成されていても良い。また、ゲート電極１１５の上面上及びＮ型ソースドレイン領域１１８の上面上に、例えば膜厚が２０ｎｍのＮｉＳｉからなるシリサイド層が形成されていても良い。 A P-type pocket region may be formed below the N-type extension region 116 in the element formation region 100a. Further, a silicide layer made of NiSi having a thickness of, for example, 20 nm may be formed on the upper surface of the gate electrode 115 and the upper surface of the N-type source / drain region 118.
　以上Ｎ型ＦＥＴについて説明したが、トランジスタの導電型はＰ型であっても良い。本実施形態に係る半導体装置がＰ型ＦＥＴを備えている場合には、上記記載における導電型は互いに逆となり、第１及び第２のキャップ膜１０６，１１１はアルミニウムからなる膜又はアルミニウム酸化膜である。また、本実施形態に係る半導体装置では、素子分離領域ＳＴＩを挟んでＮ型ＦＥＴとＰ型ＦＥＴとが形成されていても良い。 Although the N-type FET has been described above, the conductivity type of the transistor may be P-type. When the semiconductor device according to the present embodiment includes a P-type FET, the conductivity types in the above description are opposite to each other, and the first and second cap films 106 and 111 are aluminum films or aluminum oxide films. is there. In the semiconductor device according to the present embodiment, an N-type FET and a P-type FET may be formed with the element isolation region STI interposed therebetween.
　本発明は、例えば高誘電率膜を有するトランジスタにとって有用である。 The present invention is useful, for example, for a transistor having a high dielectric constant film.
　100　　　基板（半導体基板） 
　100a 　　素子形成領域 
　101　　　シリコン酸化膜 
　102　　　シリコン窒化膜 
　103　　　レジストパターン 
　104　　　トレンチ 
　104a 　　素子形成領域における上部側面 
　105　　　下地絶縁膜 
　106　　　第１のキャップ膜 
　107　　　素子分離絶縁膜 
　107a 　　凹部 
　109　　　酸素含有膜 
　110　　　高誘電率膜 
　110a 　　第１の部分 
　110b 　　第２の部分 
　111　　　第２のキャップ膜 
　112　　　ゲート絶縁膜 
　113　　　ＴｉＮ膜 
　114　　　ポリシリコン膜 
　115　　　ゲート電極 
　116　　　Ｎ型エクステンション領域 
　117　　　サイドウォールスペーサー 
　118　　　Ｎ型ソースドレイン領域 
　STI　　　素子分離領域 100 substrate (semiconductor substrate)
100a Element formation region
101 Silicon oxide film
102 Silicon nitride film
103 resist pattern
104 trench
104a Upper side in element formation region
105 Underlying insulating film
106 First cap membrane
107 Element isolation insulating film
107a recess
109 Oxygen-containing membrane
110 High dielectric constant film
110a first part
110b second part
111 Second cap membrane
112 Gate insulation film
113 TiN film
114 Polysilicon film
115 Gate electrode
116 N-type extension area
117 Sidewall spacer
118 N-type source / drain region
STI element isolation region

Claims (17)

  1. 　半導体基板における素子形成領域に形成されたＭＩＳトランジスタを備えた半導体装置であって、
    　前記半導体基板に形成されたトレンチ内に設けられ、前記素子形成領域を囲む素子分離領域と、
    　前記素子形成領域上に設けられ、高誘電率膜を有するゲート絶縁膜と、
    　前記ゲート絶縁膜上に設けられたゲート電極とを備え、
    　前記素子分離領域は、前記トレンチの側壁上に形成された酸素を含有する下地絶縁膜を有し、
    　前記高誘電率膜は、前記素子形成領域における上面上に形成された第１の部分と、前記素子形成領域における上部側面上に前記下地絶縁膜を介して形成された第２の部分とを有し、
    　前記高誘電率膜における第２の部分と前記下地絶縁膜との間には、前記ＭＩＳトランジスタの閾値電圧を変更する金属を含有する第１のキャップ膜が設けられている半導体装置。     A semiconductor device including a MIS transistor formed in an element formation region in a semiconductor substrate,
    An element isolation region provided in a trench formed in the semiconductor substrate and surrounding the element formation region;
    A gate insulating film provided on the element formation region and having a high dielectric constant film;
    A gate electrode provided on the gate insulating film,
    The element isolation region has a base insulating film containing oxygen formed on a sidewall of the trench,
    The high dielectric constant film has a first portion formed on the upper surface in the element formation region and a second portion formed on the upper side surface in the element formation region via the base insulating film. And
    A semiconductor device in which a first cap film containing a metal that changes a threshold voltage of the MIS transistor is provided between a second portion of the high dielectric constant film and the base insulating film.
  2. 　請求項１に記載の半導体装置において、
    　前記素子分離領域は、前記トレンチ内に前記下地絶縁膜を介して形成された素子分離絶縁膜をさらに備え、
    　前記下地絶縁膜と前記素子分離絶縁膜との間には、前記第１のキャップ膜が設けられている半導体装置。     The semiconductor device according to claim 1,
    The element isolation region further includes an element isolation insulating film formed in the trench through the base insulating film,
    A semiconductor device in which the first cap film is provided between the base insulating film and the element isolation insulating film.
  3. 　請求項２に記載の半導体装置において、
    　前記ゲート電極は、前記素子形成領域における上部側面上に前記高誘電率膜の前記第２の部分を介して形成されている半導体装置。     The semiconductor device according to claim 2,
    The gate electrode is formed on the upper side surface in the element formation region via the second portion of the high dielectric constant film.
  4. 　請求項３に記載の半導体装置において、
    　前記ゲート絶縁膜は、前記素子形成領域上に形成された酸素含有膜と、前記酸素含有膜上に形成された前記高誘電率膜における前記第１の部分と、前記高誘電率膜における前記第１の部分の上に形成され、前記金属を含有する第２のキャップ膜とを有する半導体装置。     The semiconductor device according to claim 3.
    The gate insulating film includes an oxygen-containing film formed on the element formation region, the first portion in the high dielectric constant film formed on the oxygen-containing film, and the first portion in the high dielectric constant film. And a second cap film formed on the first portion and containing the metal.
  5. 　請求項４に記載の半導体装置において、
    　前記第２のキャップ膜は、前記高誘電率膜における前記第２の部分の上にも形成されている半導体装置。     The semiconductor device according to claim 4,
    The semiconductor device wherein the second cap film is also formed on the second portion of the high dielectric constant film.
  6. 　請求項５に記載の半導体装置において、
    　前記高誘電率膜における前記第２の部分の上に形成されている前記第２のキャップ膜の膜厚は、前記高誘電率膜における前記第１の部分の上に形成されている前記第２のキャップ膜の膜厚よりも薄い半導体装置。     The semiconductor device according to claim 5,
    The film thickness of the second cap film formed on the second portion in the high dielectric constant film is the second thickness formed on the first portion in the high dielectric constant film. Semiconductor device thinner than the cap film thickness.
  7. 　請求項６に記載の半導体装置において、
    　前記酸素含有膜はシリコン酸化膜又はシリコン酸窒化膜である半導体装置。     The semiconductor device according to claim 6.
    The semiconductor device, wherein the oxygen-containing film is a silicon oxide film or a silicon oxynitride film.
  8. 　請求項７に記載の半導体装置において、
    　前記高誘電率膜の前記第２の部分における前記金属の不純物濃度は、前記高誘電率膜の前記第１の部分における前記金属の不純物濃度と同等、又はそれよりも高い半導体装置。     The semiconductor device according to claim 7,
    A semiconductor device in which an impurity concentration of the metal in the second portion of the high dielectric constant film is equal to or higher than an impurity concentration of the metal in the first portion of the high dielectric constant film.
  9. 　請求項８に記載の半導体装置において、
    　前記ＭＩＳトランジスタは、Ｎチャネル型ＭＩＳトランジスタであり、
    　前記金属は、ランタン、ジスプロシウム、スカンジウム、エルビウム、マグネシウム及びストロンチウムの中から選択される少なくとも１つである半導体装置。     The semiconductor device according to claim 8,
    The MIS transistor is an N-channel MIS transistor,
    The semiconductor device, wherein the metal is at least one selected from lanthanum, dysprosium, scandium, erbium, magnesium, and strontium.
  10. 　請求項８に記載の半導体装置において、
    　前記ＭＩＳトランジスタは、Ｐチャネル型ＭＩＳトランジスタであり、
    　前記金属は、アルミニウムである半導体装置。     The semiconductor device according to claim 8,
    The MIS transistor is a P-channel MIS transistor,
    The semiconductor device, wherein the metal is aluminum.
  11. 　請求項９に記載の半導体装置において、
    　前記高誘電率膜は、ハフニウム酸化膜、ハフニウムシリコン酸化膜、窒化ハフニウムシリコン酸化膜、ジルコニウム酸化膜又はハフニウムジルコニウム酸化膜の何れかである半導体装置。     The semiconductor device according to claim 9.
    The semiconductor device, wherein the high dielectric constant film is any one of a hafnium oxide film, a hafnium silicon oxide film, a hafnium silicon oxide film, a zirconium oxide film, or a hafnium zirconium oxide film.
  12. 　請求項１１に記載の半導体装置において、
    　前記ゲート電極は、窒化チタン膜、窒化タンタル膜、タンタルカーバイド膜及び窒化タンタルカーバイド膜のうちの何れか１つからなる単層膜又は２つ以上からなる積層膜である半導体装置。     The semiconductor device according to claim 11,
    The gate electrode is a semiconductor device which is a single layer film made of any one of a titanium nitride film, a tantalum nitride film, a tantalum carbide film and a tantalum nitride carbide film or a laminated film made of two or more.
  13. 　請求項１２に記載の半導体装置において、
    　前記下地絶縁膜はシリコン酸化膜又はシリコン酸窒化膜である半導体装置。     The semiconductor device according to claim 12,
    A semiconductor device in which the base insulating film is a silicon oxide film or a silicon oxynitride film.
  14. 　請求項１３に記載の半導体装置において、
    　前記素子分離領域における前記素子形成領域に隣接するエッジ部の上面には、凹部が形成されており、
    　前記高誘電率膜における前記第２の部分は前記凹部の内面上に設けられている半導体装置。     The semiconductor device according to claim 13,
    A recess is formed on the upper surface of the edge portion adjacent to the element formation region in the element isolation region,
    The semiconductor device, wherein the second portion of the high dielectric constant film is provided on an inner surface of the recess.
  15. 　請求項１４に記載の半導体装置において、
    　前記下地絶縁膜は前記金属を含有している半導体装置。     The semiconductor device according to claim 14.
    The base insulating film is a semiconductor device containing the metal.
  16. 　半導体基板における素子形成領域に形成されたＭＩＳトランジスタを備えた半導体装置の製造方法であって、
    　前記素子形成領域を囲むように前記半導体基板にトレンチを形成した後、前記トレンチの側壁上に酸素を含有する下地絶縁膜を設ける工程（ａ）と、
    　前記下地絶縁膜上に前記ＭＩＳトランジスタの閾値電圧を変更する金属を含有するキャップ膜を設ける工程（ｂ）と、
    　工程（ｂ）の後に、前記トレンチ内に前記下地絶縁膜を介して素子分離絶縁膜を設け、前記下地絶縁膜と前記素子分離絶縁膜とを有する素子分離領域を形成する工程（ｃ）と、
    　工程（ｃ）の後に、前記素子形成領域上に高誘電率膜を有するゲート絶縁膜を設ける工程（ｄ）と、
    　前記ゲート絶縁膜上にゲート電極を設ける工程（ｅ）とを備え、
    　前記工程（ｄ）では、前記素子形成領域における上部側面上に前記下地絶縁膜及び前記キャップ膜を介して前記高誘電率膜を形成する半導体装置の製造方法。     A method of manufacturing a semiconductor device including a MIS transistor formed in an element formation region in a semiconductor substrate,
    After forming a trench in the semiconductor substrate so as to surround the element formation region, a step (a) of providing a base insulating film containing oxygen on a sidewall of the trench;
    Providing a cap film containing a metal for changing a threshold voltage of the MIS transistor on the base insulating film (b);
    After the step (b), a step (c) of providing an element isolation insulating film through the base insulating film in the trench and forming an element isolation region having the base insulating film and the element isolation insulating film;
    A step (d) of providing a gate insulating film having a high dielectric constant film on the element formation region after the step (c);
    Providing a gate electrode on the gate insulating film (e),
    In the step (d), a method of manufacturing a semiconductor device, wherein the high dielectric constant film is formed on the upper side surface in the element formation region via the base insulating film and the cap film.
  17. 　請求項１６に記載の半導体装置の製造方法において、
    　前記工程（ｂ）の後に、前記金属を前記キャップ膜から前記下地絶縁膜へ拡散させる工程（ｆ）を備えている半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 16,
    A method of manufacturing a semiconductor device, comprising a step (f) of diffusing the metal from the cap film into the base insulating film after the step (b).
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