WO2011027525A1

WO2011027525A1 - Semiconductor element and method for manufacturing same

Info

Publication number: WO2011027525A1
Application number: PCT/JP2010/005292
Authority: WO
Inventors: 雅彦庭山; 正雄内田; 浩一橋本; 千秋工藤
Original assignee: パナソニック株式会社
Priority date: 2009-09-02
Filing date: 2010-08-27
Publication date: 2011-03-10

Abstract

Disclosed is a semiconductor element which is provided with: a first silicon carbide layer (2) formed on the surface of a silicon carbide substrate (1); a second silicon carbide layer (6) formed on a region of a part of the surface of the first silicon carbide layer (2); a metal silicide layer (11), which is formed on the first silicon carbide layer (2) and is in contact with the first silicon carbide layer (2); an interlayer insulating film (9), which is provided on the second silicon carbide layer (6) and has an opening (10s); and a conductive layer (12) formed in the opening (10s). The metal silicide layer (11) is provided in contact with the inner wall of the opening (10s), the conductive layer (12) is electrically connected with the first silicon carbide layer (2) with the metal silicide layer (11) therebetween, and the metal silicide layer (11) is in contact with the second silicon carbide layer (6). With such configuration, an excellent contact to the silicon carbide layer is formed, and the area of a chip is reduced.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to a semiconductor element using silicon carbide and a method for manufacturing the same.

Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material having a larger band gap than silicon (Si), such as power elements (also called power devices), environmental elements, high-temperature operating elements, and high-frequency elements. It is applied to various semiconductor devices. Especially, application to power devices, such as a switching element and a rectifier, attracts attention.

Typical switching elements of power devices using SiC include metal-insulator-semiconductor field effect transistors (Metal-Insulator-Semiconductors, MISFETs) and metal-semiconductor field-effect transistors (Metal-Semiconductor Field-Effect Transistors: MESFET). In such a switching element, the voltage applied to the gate electrode can be switched between an on state in which a drain current of several A (amperes) or more flows and an off state in which the drain current is zero. Further, a high breakdown voltage of several hundred volts or more can be realized in the off state.

Also, as a typical rectifying element, there are a Schottky diode and a pn diode. These are expected as rectifying elements that realize a large current and a high breakdown voltage.

Since SiC has a higher dielectric breakdown electric field and thermal conductivity than Si, a power device using SiC (SiC power device) can easily achieve higher breakdown voltage and lower loss than Si power devices. For this reason, when realizing the same performance as the Si power device, the area and thickness can be greatly reduced as compared with the Si power device.

The structure of a vertical metal-oxide-semiconductor field effect transistor (Metal-Oxide-Semiconductor), which is one of switching elements using SiC, is disclosed in, for example, Patent Document 1 and Patent Document 2. Yes. Hereinafter, a method for manufacturing a vertical MOSFET having the structure disclosed in these documents will be described with reference to the drawings.

5 to 8 are schematic process cross-sectional views for explaining a method of manufacturing a planar n-channel vertical power MOSFET. A MOSFET typically includes a plurality of unit cells. These drawings show one unit cell among a plurality of unit cells and a cross section of a part of a unit cell adjacent to the unit cell.

First, as shown in FIG. 5A, a silicon carbide layer 2 having the same crystal structure as that of the n-type SiC substrate 1 is formed on the main surface of the low-resistance n-type SiC substrate 1 by epitaxial growth.

Next, as shown in FIG. 5B, a mask layer 31 made of a silicon oxide film is disposed on a predetermined region of the silicon carbide layer 2, and using this as a mask, p-type impurity ions (for example, Al ( Aluminum) ions) are implanted into the silicon carbide layer 2. Thereby, p-type body region (also referred to as well region) 3 is formed in silicon carbide layer 2. The region of silicon carbide layer 2 where p type body region 3 is not formed becomes n type drift region 2d.

After removing mask layer 31, as shown in FIG. 5C, a mask layer 32 made of a silicon oxide film is arranged on a predetermined region of silicon carbide layer 2, and n-type impurity ions are used as a mask. By implanting (for example, N (nitrogen) ions), the source region 4 is formed in the p-type body region 3.

After removing mask layer 32, as shown in FIG. 6D, mask layer 33 made of a silicon oxide film is arranged on a predetermined region of silicon carbide layer 2, and p-type impurity ions are used as a mask. By implanting (for example, Al ions), a p ⁺ contact region 5 containing p-type impurities at a higher concentration than the body region 3 is formed.

After removing the mask layer 33, although not shown, an annealing process is performed in an inert gas atmosphere at a temperature of 1700 ° C. for about 30 minutes. By the annealing treatment, the impurities implanted into p type body region 3, source region 4, and p ⁺ contact region 5 are activated.

Next, as shown in FIG. 6E, a channel layer 6 made of silicon carbide is formed on the silicon carbide layer 2 by epitaxial growth.

Subsequently, a resist layer 41 is formed on a predetermined region of the channel layer 6 as shown in FIG. Thereafter, the portion of the channel layer 6 that is not covered with the resist layer 41 is removed by dry etching. During dry etching, damage may occur on the surface of the source region 4 and the p ⁺ contact region 5 exposed from the resist layer 41, resulting in surface roughness. In order to reduce such surface roughness, although not shown, the exposed portion may be thermally oxidized to remove the oxide film formed by thermal oxidation.

After removing the resist layer 41, a gate insulating film 7 and a gate electrode 8 are formed on the channel layer 6 as shown in FIG. Specifically, first, an insulating film and a conductive film are deposited in this order on the channel layer 6 and the silicon carbide layer 2, and a resist layer 42 is formed in a predetermined region on the conductive film. Thereafter, dry etching of the insulating film and the conductive film is performed using the resist layer 42 as a mask. Thereby, the gate insulating film 7 and the gate electrode 8 are obtained.

After removing the resist layer 42, as shown in FIG. 7H, an interlayer insulating film 9 is deposited on the entire surface of the substrate 1, and a resist layer 43 having an opening is formed thereon. Next, dry etching of the interlayer insulating film 9 is performed using the resist layer 43 as a mask. Thereby, a contact hole 10 s reaching a part of the source region 4 and the contact region 5 is formed in the interlayer insulating film 9.

After removing the resist layer 43, a Ni (nickel) film 51 is deposited on the interlayer insulating film 9 and inside the contact hole 10s as shown in FIG. In this state, the silicon carbide layer 2 and the Ni film 51 are reacted in the contact hole 10 s by performing an annealing process at a temperature of 950 ° C. for about 1 minute in a nitrogen atmosphere. As a result, a part of Ni diffuses into the silicon carbide layer 2 and is alloyed, whereby the Ni silicide layer 11 is formed.

Next, the portion of the Ni film 51 that has not reacted with the silicon carbide layer 2 is removed. Thereafter, as shown in FIG. 8, a contact hole 10 g reaching the gate electrode 8 is formed in the interlayer insulating film 9. Next, an Al (aluminum) film is deposited as a wiring layer on the interlayer insulating film 9 in the contact hole 10s and in the contact hole 10g, and the Al film is processed into an appropriate pattern. Thereby, from the Al film, the source wiring 12 connected to the source region 4 and the contact region 5 through the Ni silicide layer 11 in the contact hole 10s, and the gate electrode wiring 13 in contact with the gate electrode 8 in the contact hole 10g Form.

Further, a back electrode (drain electrode) 14 is formed on the entire surface opposite to the main surface of the n-type SiC substrate 1. In this way, a planar n-channel vertical power MOSFET is obtained.

The MOSFET shown in FIG. 8 has a storage channel structure. In the off state, pinch-off occurs due to the work function difference between the gate electrode 8 and the channel layer 6 and depletion due to the pn junction between the p-type body region 3 and the channel layer 6 (off state).

On the other hand, when a voltage is applied to the gate electrode 8, carriers are accumulated in the channel layer 6 to be turned on. In the on state, electrons reach the drift region 2 d of the silicon carbide layer 2 from the source region 4 through the channel layer 6. Thereafter, it flows vertically through the drift region 2 d and reaches the drain electrode 14 via the SiC substrate 1.

Further, Patent Document 2 discloses a method for forming a Ni silicide layer serving as a source electrode using a channel layer.

10A to 10C are process cross-sectional views showing a part of the MOSFET manufacturing method disclosed in Patent Document 2. FIG. For simplicity, the same components as those in FIG.

First, as shown in FIG. 10A, a channel layer 6 is formed on the silicon carbide layer 2, and a Ni film 51 serving as a source electrode is formed on a part of the silicon carbide layer 6. Next, as shown in FIG. 10B, the heat treatment is performed to cause the channel layer 6 and the Ni film 51 to react to form the Ni silicide layer 11. Thereafter, as shown in FIG. 10C, a gate electrode 8 is provided on the channel layer 6 via a gate insulating film 7.

Patent No. 3,385,938 JP 2005-39257 A

The conventional MOSFET manufacturing method shown in FIGS. 5 to 8 has the following problem (first problem).

In the step shown in FIG. 6F, the portion of the channel layer 6 that is not covered with the resist layer 41 is removed by dry etching. At this time, channel layer 6 and underlying silicon carbide layer 2 are made of the same material, and therefore it is not possible to provide a difference in etching rate between these layers. That is, it is impossible to perform etching controlled by detecting the end point during dry etching. For this reason, it is difficult to selectively remove only the channel layer 6 in the upper layer. Further, in consideration of the variation in the thickness of the channel layer 6, the thickest portion of the channel layer 6 is removed in order to reliably remove unnecessary portions (portions where no channel is formed) of the channel layer 6. The etching amount must be adjusted. As a result, the surface portions of source region 4 and p ⁺ contact region 5 in silicon carbide layer 2 underlying channel layer 6 are necessarily shaved.

Further, in the step shown in FIG. 7H, when the contact hole 10s is formed in the interlayer insulating film 9, the material of the interlayer insulating film 9 to be etched is different from the material of the silicon carbide layer 6 therebelow. If the ratio difference is used, the amount of overetching can be reduced. However, the contact hole 10s penetrating the interlayer insulating film 9 is reliably formed, and then the electrode formed in the contact hole 10s is reliably electrically connected to the source region 4 and the p ⁺ contact region 5 of the silicon carbide layer 6. Therefore, it is necessary to etch (over-etch) the surface portion of the silicon carbide layer 6 when the contact hole 10s is formed in the interlayer insulating film 9.

As a result, in the obtained MOSFET, the thickness of the source region 4 and the p ⁺ contact region 5 in the silicon carbide layer 2 is smaller than the thickness of these

regions

4 and 5 formed in the impurity implantation process.

FIGS. 9A and 9B are a cross-sectional view and a top view, respectively, illustrating a unit cell in a MOSFET actually obtained by the above method.

As shown in FIG. 9, when the thickness of the source region 4 formed by the n-type impurity implantation step is t1, the thickness of the portion of the source region 4 covered with the channel layer 6 is substantially equal to t1, In the step shown in FIG. 6F, the thickness t2 of the portion of the source region 4 that is not covered with the resist layer 41 becomes smaller than the thickness t1 due to over-etching. Further, in the step shown in FIG. 7H, the thickness of the portion of the source region 4 that is not covered with the resist layer 43 becomes smaller than the thickness t2 due to over-etching. Thereafter, since the Ni silicide layer 11 is formed on the surface portion of the source region 4, the source region 4 is further thinned.

Thus, when the source region 4 is thinned, the resistance of the source region 4 is increased, so that the on-resistance of the MOSFET is increased and the power loss is increased. Further, if the amount of the source region 4 removed during the etching of the channel layer 6 (FIG. 6F) is larger, the source region 4 (and the p ⁺ contact region 5) is completely below the contact hole 10s. May disappear. In this case, in the subsequent process (FIG. 7I), the p-type body region 3 in the silicon carbide layer 2 and the Ni film 51 react to form the Ni silicide layer 11, so that the source wiring 12 is replaced with the source region. 4 may not be electrically connected to the MOSFET, and the drain current may not flow through the MOSFET.

In order to prevent the above problem, the source region 4 having a large thickness t1 may be formed in the p-type body region 3 in the n-type impurity implantation step shown in FIG. However, if only the source region 4 is made thick while maintaining the thickness of the p-type body region 3 formed in the silicon carbide layer 2, the punch-through withstand voltage of the source region 4 is deteriorated, so that the withstand voltage of the MOSFET may be lowered. is there.

When the source region 4 is made thick and the p-type body region 3 is also made thick, a sufficient punch-through withstand voltage can be secured, but the withstand voltage of the MOSFET may be lowered. The breakdown voltage of the MOSFET is finally determined by the distance L between the lower end of the p-type body region 3 and the surface of the n-type SiC substrate 1 (FIG. 9) and the impurity concentration of the n-type SiC substrate 1. This is because if the distance L is reduced by increasing the thickness, the breakdown voltage of the MOSFET cannot be secured. On the other hand, if the p-type body region 3 is thickened and the silicon carbide layer 2 is thickened, the distance L corresponding to the set withstand voltage value can be obtained. However, if the silicon carbide layer 2 is thickened, the resistance of the drift region 2d is increased, so that the on-resistance of the MOSFET is increased and the device loss may be increased.

The method shown in FIGS. 5 to 8 has another problem (second problem).

In the step shown in FIG. 6F, a mask (hereinafter referred to as “mask A”, not shown) used for forming the resist layer 41 and a contact hole 10s shown in FIG. Since a mask (hereinafter referred to as “mask B”, not shown) used when forming the layer 43 has a different pattern, it is necessary to consider misalignment between the mask A and the mask B. Accordingly, an alignment margin having a size expected from the alignment accuracy of the stepper is usually set. Specifically, in order to form the contact hole 10 s at a desired location (in the opening of the channel layer 6) even when misalignment occurs in the mask B for forming the contact hole 10 s, It is necessary to design the mask A so that the size of the opening is larger than the contact hole 10s by the alignment margin. That is, the distance from the contact hole 10s to the channel layer 6 is increased by the alignment margin. Here, since the positional relationship between the gate electrode 8 and the source region 4 is determined by the characteristics of the power device, the distance between them cannot be increased. Therefore, in order to suppress deterioration of characteristics due to misalignment, it is necessary to enlarge the source region 4 in the lateral direction by the alignment margin between the mask A and the mask B, and the area of the source region 4 increases. As a result, the total chip area (here, the unit cell area) increases.

On the other hand, according to the method disclosed in Patent Document 2 (FIG. 10), it is not necessary to provide an opening in the channel layer 6 by etching. Therefore, it is possible to prevent a problem (first problem) caused by overetching of the source region 4 when the channel layer 6 is etched. As a result, a good ohmic contact can be formed between the source wiring and the source region 4.

However, it is difficult to solve the second problem described above by the manufacturing method of Patent Document 2. In the manufacturing method of Patent Document 2, after providing the Ni silicide layer 11 and the gate electrode 8, an interlayer insulating film is formed, and a contact hole is formed in this (not shown). In forming the contact hole, a mask (referred to as “mask D”) different from the mask used for patterning the Ni film (referred to as “mask C”) is used. Therefore, for each of the mask C and the mask D, it is necessary to set an alignment margin expected from the alignment accuracy of the stepper. Specifically, in order to form a source contact at a desired position even when misalignment occurs in the mask C and the mask D, the source region 4 is misaligned from the original design position. It is necessary to increase it as much as possible. Thus, since the area of the source region is designed in consideration of the mask alignment deviation, it is difficult to further reduce the total chip area.

The present invention has been made in view of the above circumstances, and its purpose is to form a good contact with a silicon carbide layer without deteriorating element characteristics in a semiconductor element using silicon carbide, The purpose is to keep the chip area small.

A semiconductor element of the present invention includes a silicon carbide substrate, a first silicon carbide layer disposed on the surface of the silicon carbide substrate, and a second carbonization disposed on a partial region of the surface of the first silicon carbide layer. A silicon layer, a metal silicide layer provided on the first silicon carbide layer and in contact with the first silicon carbide layer, an interlayer insulating film provided on the second silicon carbide layer and having an opening; and the opening A conductive layer disposed in a portion, wherein the metal silicide layer is provided in contact with an inner wall of the opening, and the conductive layer is electrically connected to the first silicon carbide layer via the metal silicide layer. The metal silicide layer is in contact with the second silicon carbide layer.

In a preferred embodiment, the first silicon carbide layer is in contact with the first region of the first conductivity type disposed in the first silicon carbide layer, and in the first silicon carbide layer. The second region of the second conductivity type is disposed, and the region of the first silicon carbide layer in which neither the first region nor the second region is disposed is the second conductivity type second region. The metal silicide layer is in contact with the second region.

The semiconductor device may further include a gate insulating film provided on the second silicon carbide layer and a gate electrode disposed on the gate insulating film.

In a preferred embodiment, the thickness of the metal silicide layer is greater than twice and less than or equal to four times the thickness of the second silicon carbide layer.

The metal silicide layer may be a Ni silicide layer containing carbon.

In a preferred embodiment, when viewed from above the first silicon carbide layer, a width w2 of a portion of the metal silicide layer in contact with the first or second silicon carbide layer is not less than a width w1 of the opening. The width difference w2-w1 is 0 or more and 200 nm or less.

In a preferred embodiment, a side surface of the metal silicide layer is in contact with the second silicon carbide layer, and a lower surface of the metal silicide layer is not in contact with the second silicon carbide layer.

In a preferred embodiment, the metal silicide layer and the second silicon carbide layer are in contact with each other only on the side surfaces.

The first and second regions are disposed on a surface region of the first silicon carbide layer, and the second region is disposed on the surface of the first silicon carbide layer so as to be surrounded by the first region. It may be.

The second region is disposed in a surface region of the first silicon carbide layer, the first region is disposed below the second region, penetrates the second region and the first region, and You may have further the trench which reaches 3 area | regions.

The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device having a silicon carbide layer, wherein (A) a step of preparing a silicon carbide substrate having a first silicon carbide layer formed on the surface; (B) Forming a second silicon carbide layer on the first silicon carbide layer; and (C) having an opening exposing a part of the surface of the second silicon carbide layer on the second silicon carbide layer. Forming an interlayer insulating film; (D) forming a metal film on the exposed surface of the second silicon carbide layer in the opening of the interlayer insulating film; and (E) the metal film. And a part of the second silicon carbide layer and a part of the first silicon carbide layer are reacted to form a metal silicide layer in contact with the first silicon carbide layer; and (F) the interlayer insulating film The first silicon carbide layer is electrically connected to the opening through the metal silicide layer. And forming a connecting conductive layer.

In a preferred embodiment, in the step (E), the metal contained in the metal film is diffused and silicided into the second silicon carbide layer and the first silicon carbide layer, whereby the metal silicide layer is formed. It is formed.

In a preferred embodiment, in the step (D), the thickness of the metal film is larger than the thickness of the second silicon carbide layer and twice or less.

In a preferred embodiment, the step (C) includes a step (C1) of forming the interlayer insulating film on the second silicon carbide layer, and a step (C2) of forming the opening in the interlayer insulating film. The second silicon carbide layer is not etched before the step (C2).

In a preferred embodiment, the step (C2) includes a step of etching a surface portion of the second silicon carbide layer exposed by the opening.

In a preferred embodiment, in the step (C2), the thickness of the other silicon carbide layer after the etching is ½ or less of the thickness of the metal film.

The metal film may be a Ni film.

In a preferred embodiment, the first and second silicon carbide layers are of a second conductivity type, and the first silicon carbide layer has a first conductivity between the step (A) and the step (B). The second silicon carbide layer between the step (G) of forming the body region of the mold and the source region of the second conductivity type in contact with the body region, and between the step (B) and the step (C). A step (H) of forming a gate insulating film and a gate electrode thereon, wherein the step (C) is performed on the source region of the surface of the second silicon carbide layer on the second silicon carbide layer. A step of forming an interlayer insulating film having an opening exposing a portion located at a portion, wherein the step (E) includes the metal film, a part of the second silicon carbide layer, and a part of the source region. React to form a metal silicide layer in contact with the source region It is a degree.

According to the present invention, in a semiconductor element using silicon carbide, it is possible to ensure good contact with the silicon carbide layer. In addition, since the margin for mask alignment can be reduced, the chip area can be reduced as compared with the prior art.

In particular, when the present invention is applied to a storage channel type MISFET, good ohmic contact is formed between the metal silicide layer serving as the source electrode and the source region while suppressing an increase in on-resistance due to the overetching of the source region. it can. Further, the chip area (unit cell area) can be reduced as compared with the conventional case.

(A) And (b) is a typical sectional view and a top view of a semiconductor device of a 1st embodiment by the present invention, respectively. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the semiconductor element of 1st Embodiment by this invention. It is typical sectional drawing of the other semiconductor element of 1st Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the other manufacturing method of the semiconductor element of 1st Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the conventional vertical MOSFET. (D)-(f) is process sectional drawing for demonstrating the manufacturing method of the conventional vertical MOSFET. (G)-(i) is process sectional drawing for demonstrating the manufacturing method of the conventional vertical MOSFET. It is process sectional drawing for demonstrating the manufacturing method of the conventional vertical MOSFET. FIGS. 7A and 7B are a cross-sectional view and a plan view, respectively, illustrating a conventional vertical MOSFET manufactured by the method of FIGS. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of the vertical MOSFET disclosed by patent document 2. FIG. It is sectional drawing which shows an example of the trench type MISFET of embodiment by this invention. (A) and (b) are schematic diagrams for explaining the concentration profiles in the depth direction of the cross section along the II ′ and II-II ′ lines of the metal silicide layer 11 shown in FIG. 1, respectively. is there. (A) and (b) are schematic diagrams for explaining the concentration profiles in the depth direction of the cross section along the II ′ and II-II ′ lines of the conventional metal silicide layer shown in FIG. 8, respectively. It is.

(First embodiment)
Hereinafter, a first embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The semiconductor element of this embodiment is a vertical MISFET using silicon carbide, and has a structure in which a plurality of unit cells are arranged.

FIG. 1A is a schematic cross-sectional view of a vertical MISFET using silicon carbide of the present embodiment, in which one unit cell among a plurality of unit cells and a part of a unit cell adjacent thereto are shown. A cross section is shown. FIG. 1B is a plan view showing the silicon carbide layer surface of one unit cell in the vertical MISFET.

Each unit cell of the vertical MISFET has a silicon carbide layer (also referred to as “first silicon carbide layer”) 2 formed by epitaxial growth on the main surface of a SiC substrate (here, n-type SiC substrate) 1 and silicon carbide. Channel layer 6 formed on layer 2, gate electrode 8 provided on channel layer 6 via gate insulating film 7, source electrode 11 in contact with the surface of silicon carbide layer 2, SiC substrate 1 And a drain electrode 14 provided on the back surface of the substrate. Channel layer (also referred to as “second silicon carbide layer”) 6 is an epitaxial layer containing, for example, n-type silicon carbide. The source electrode 11 is a layer containing metal silicide (here, Ni silicide layer).

In each unit cell, silicon carbide layer 2 is formed in the surface layer portion of silicon carbide layer 2 and has a body region (also referred to as a first region) 3 having a conductivity type (here, p-type) different from that of SiC substrate 1. And an n-type source region (also referred to as a second region) 4 in contact with the body region 3. The source region 4 contains an n-type impurity at a high concentration. In the present embodiment, body region 3 and source region 4 are arranged in the surface region of silicon carbide layer 2, and source region 4 is surrounded by body region 3 on the surface of silicon carbide layer 2. A p ⁺ contact region 5 containing a p-type impurity at a higher concentration than the body region 3 is formed inside the body region 3. A portion of silicon carbide layer 2 where none of body region 3, source region 4, and contact region 5 is formed includes drift region (also referred to as a third region) 2 d. Drift region 2d is, for example, an n ⁻ -type silicon carbide layer containing n-type impurities at a lower concentration than SiC substrate 1. Body region 3, source region 4 and contact region 5 are formed by a step of implanting impurities into silicon carbide layer 2 and a high-temperature heat treatment (activation annealing) step of activating the impurities implanted into silicon carbide layer 2. It is formed.

The source region 4 and the drift region 2d are connected via the channel layer 6. Channel layer 6 is, for example, a silicon carbide layer formed on silicon carbide layer 2 by epitaxial growth. Further, the contact region 5 and the source region 4 are in ohmic contact with the Ni silicide layer 11, respectively. Therefore, the body region 3 is electrically connected to the Ni silicide layer 11 through the contact region 5.

The gate insulating film 7 is a thermal oxide film (SiO ₂ film) formed by, for example, thermally oxidizing the surface of the channel layer 6. The gate electrode 8 is formed using, for example, conductive polysilicon.

The gate electrode 8 is covered with an interlayer insulating film 9. In the interlayer insulating film 9, an opening (contact hole) 10s for forming a source contact and an opening (contact hole) 10g for forming a gate contact are formed. A conductive layer (source wiring) 12 is provided in the contact hole 10 s and on the interlayer insulating film 9. The Ni silicide layers 11 in each unit cell are connected in parallel by a source wiring 12. Further, a conductive layer (gate wiring) 13 to be a gate wiring is provided in the contact hole 10g and on the interlayer insulating film 9. Thereby, the gate electrode 8 is electrically connected to the gate wiring 13.

In this embodiment, as described later, the Ni silicide layer 11 is formed by reacting the Ni film and the channel layer in the contact hole 10s. Therefore, the Ni silicide layer 11 is in contact with the inner wall of the contact hole 10 s and the channel layer 6. Further, the Ni silicide layer 11 contains carbon (C) contained in the silicon carbide layer 2 and the channel layer 6 in addition to Ni and Si. The Ni silicide layer 11 further includes second conductivity type impurities (for example, n-type impurities such as nitrogen and P) contained in the channel layer 6, and second conductivity type contained in the source region 4 of the silicon carbide layer 2. And a first conductivity type impurity (p-type impurity such as Al) contained in the contact region 5. The concentration profiles of these impurities in the depth direction reflect the concentration profiles of the channel layer 6 and the silicon carbide layer 2 before silicidation. A specific profile will be described later.

Hereinafter, a method for manufacturing a semiconductor device of this embodiment will be described with reference to the drawings.

2A to 2C are schematic process cross-sectional views showing a method for manufacturing a semiconductor device of this embodiment.

First, epitaxial growth is performed on the main surface of the low-resistance n-type SiC substrate 1 in the same manner as described above with reference to FIGS. 5 (a) to 5 (c) and FIGS. 6 (d) and (e). Silicon carbide layer 2 is formed, and p-type body region 3, source region 4 and p ⁺ contact region 5 are formed in silicon carbide layer 2. Next, annealing is performed at 1700 ° C. for about 30 minutes in an inert gas atmosphere, and the p-type body region 3, the source region 4 and the p ⁺ contact region 5 are electrically activated. Thereafter, channel layer 6 containing n-type silicon carbide is formed on silicon carbide layer 2 by epitaxial growth.

In the present embodiment, the thickness of the body region 3 (depth from the surface of the silicon carbide layer 2 to the lower end of the body region 3) is 500 to 2000 nm (for example, 1000 nm), and the thickness of the source region 4 is 150 to 600 nm (for example, 300 nm), and the thickness of the channel layer 6 is 10 to 200 nm (for example, 100 nm). Further, the average impurity concentration (for example, nitrogen concentration) in the channel layer 6 is adjusted to be in the range of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ . The channel layer 6 may be a single layer or may have a laminated structure.

Next, as shown in FIG. 2A, the gate insulating film 7 and the gate electrode 8 are formed on the channel layer 6 without processing the channel layer 6. Specifically, first, a thermal oxide film is formed by thermally oxidizing the surface of the channel layer 6 at a temperature of 1100 ° C. Instead, a single-layer or multilayer insulating film may be deposited on the channel layer 16. Next, a conductive film such as a low resistance polysilicon film or a metal film is formed on the thermal oxide film. A resist layer 42 is deposited on the conductive film, and the thermal oxide film and the conductive film are patterned by dry etching using the resist layer 42 as a mask. Thereby, the gate oxide film 7 is obtained from the thermal oxide film, and the gate electrode 8 is obtained from the conductive film.

After removing the resist layer 42, an interlayer insulating film 9 is deposited on the entire surface of the substrate 1 as shown in FIG. Next, a resist layer 43 having an opening is formed on the interlayer insulating film 9. Using the resist layer 43 as a mask, a contact hole 10 s exposing a part of the surface of the channel layer 6 on the surface of the channel layer 6 and a portion located on the contact region 5 is formed in the interlayer insulating film 9 by dry etching.

At this time, the surface portion of the channel layer 6 may be removed by overetching or the like, but it is preferable to adjust the etching conditions so that the source region 4 and the p ⁺ contact region 5 are not etched. This is because if the source region 4 is thin, the on-resistance of the MISFET may be high, and if the p ⁺ contact region 5 is thin, the switching speed may be low.

After removing the resist layer 43, a Ni (nickel) film 51 is deposited on the interlayer insulating film 9 and inside the contact hole 10s as shown in FIG. The thickness of the Ni film 51 is preferably 10 nm or more and 200 nm or less, for example, 100 nm.

Subsequently, annealing is performed for about 1 minute at a temperature of 950 ° C. in a nitrogen atmosphere. By this heat treatment, Ni contained in the Ni film 51 reacts with the silicon carbide in the channel layer 6 and the silicon carbide layer 2 therebelow to form the Ni silicide layer 11. The Ni silicide layer 11 is formed by diffusion of Ni into the channel layer 6. Therefore, the Ni silicide layer 11 is larger than the thickness of the reacted portion of the Ni film 51. Ni diffuses to the surface portions of the source region 4 and the p ⁺ contact region 5 under the channel layer 6 to be silicided. As a result, a good ohmic junction is formed between the Ni silicide layer 11 and the p ⁺ contact region 5 and the source region 4.

The upper part of the Ni silicide layer 11 in this embodiment is in contact with the inner wall of the contact hole 10s. The shape of the upper surface (the surface in contact with the source wiring) of the Ni silicide layer 11 can be adjusted by the shape of the contact hole 10 s formed in the interlayer insulating film 9. Further, the side wall (side surface) of the Ni silicide layer 11 is in contact with the channel layer 6 (here, the channel layer 6 and the source region 4). In the illustrated example, the side surface of the Ni silicide layer 11 is in contact with the channel layer 6, and the lower surface is not in contact with the channel layer 6. This is preferable because the entire lower surface of the Ni silicide layer 11 can be brought into contact with the silicon carbide layer 2. The Ni silicide layer 11 and the channel layer 6 may be in contact with each other only on the side surfaces.

In the heat treatment, Ni may diffuse not only in the silicon carbide layer 2 downward but also in the lateral direction. In that case, as shown in FIG. 3, the width w2 of the portion of the Ni silicide layer 11 surrounded by the channel layer 6 and the source region 4 in the cross section perpendicular to the main surface of the SiC substrate 1 is the contact hole. The width is greater than 10s (ie, the width of the upper surface of the Ni silicide layer 11) w1. In this specification, when the widths of the Ni silicide layer 11 that are in contact with the channel layer 6 and the silicon carbide layer 2 are different from each other, the larger one is defined as the width w2. The difference Δw (= w2−w1) between these widths is, for example, 200 nm or less. Note that when the lateral diffusion of Ni is extremely small, the width w2 and the width w1 are substantially equal (Δw = 0).

Thereafter, although not shown, the portion of the Ni film 51 that did not react with silicon carbide is removed. Next, the source wiring 12, the gate wiring 13, and the drain electrode 14 are formed by a known method to obtain the MISFET shown in FIG.

The annealing conditions (temperature and time) for forming the Ni silicide layer 11 are not limited to the above conditions, but the annealing temperature was deposited on the channel layer 6 in the contact hole 10s. It is preferable to raise to a temperature at which Ni completely reacts. If the thickness of the Ni film 51 is 10 nm or more and 200 nm or less, the annealing temperature is, for example, 850 ° C. or more and 1150 ° C. or less. When all of the deposited Ni reacts with silicon carbide, silicon carbide having substantially the same thickness as Ni is used for the reaction, so the Ni silicide layer 11 having a thickness approximately twice the thickness of the deposited Ni film 51. Is formed. Therefore, the thickness of the silicon carbide that reacts with Ni and the thickness of the Ni silicide layer 11 after the reaction are more easily controlled by selecting the heat treatment conditions (for example, temperature) so that all of the Ni reacts with silicon carbide. it can.

The thickness of the Ni film 51 is preferably larger than the thickness of the channel layer 6. For example, if the thickness of the channel layer 6 is 100 nm, the Ni film 51 is made thicker than 100 nm, the channel layer 6 is reacted with Ni in the thickness direction, and the source region 4 and the p ⁺ contact region 5 thereunder are reacted. The surface portion can be reacted with Ni more reliably. Thereby, an ohmic junction can be more reliably formed between the Ni silicide layer 11 and the source region 4 and the p ⁺ contact region 5.

When the Ni film 51 is made thicker than the channel layer 6, the source region 4 and the p ⁺ contact region 5 react with Ni by an amount corresponding to the difference ΔD between the thickness of the Ni film 51 and the thickness of the channel layer 6. It becomes a part of the silicide layer 11. As a result, the thickness of the source region 4 and the p ⁺ contact region 5 is reduced by the thickness corresponding to ΔD. Therefore, if the Ni film 51 is too thick, the source region 4 and the p ⁺ contact region 5 may be thinned to deteriorate the device characteristics. In the present embodiment, the thickness of the Ni film 51 is preferably less than or equal to twice the thickness of the channel layer 6. As a result, the thickness of the source region 4 and the p ⁺ contact region 5 that reacts with Ni can be suppressed, so that the thickness of the source region 4 and the p ⁺ contact region 5 can be sufficiently ensured. As a result, it is possible to suppress an increase in on-resistance due to the thinning of the source region 4 and a decrease in switching characteristics due to the thinning of the p ⁺ contact region 5.

In addition, the “thickness of the channel layer 6” here means the thickness of the channel layer 6 when deposited on the silicon carbide layer 2. For example, as described later, even when the surface portion of the channel layer 6 is etched (half-etched) when forming the contact hole 10s, the thickness of the Ni film 51 is the thickness of the channel layer 6 before being half-etched. It is preferable that it is larger than that and twice or less.

The thickness of the Ni silicide layer 11 obtained in this embodiment is approximately twice the thickness of the Ni film 51. As described above, if the thickness of the Ni film 51 is larger than the thickness of the channel layer 6 and not more than twice the thickness of the channel layer 6, the thickness of the Ni silicide layer 11 is the thickness of the channel layer 6. It is larger than 2 times and 4 times or less.

According to the above method, since it is not necessary to etch the channel layer 6, the source region 4 and the p ⁺ contact region 5 can be prevented from being thinned by overetching. In addition, a good ohmic junction can be formed between source region 4 and p ⁺ contact region 5 in silicon carbide layer 2 and Ni silicide layer 11.

Further, in the conventional method described above with reference to FIGS. 5 to 8, it is necessary to consider the alignment margin between the mask A and the mask B. According to the above method, the mask A for etching the channel layer 6 is used. Therefore, it is not necessary to consider the above alignment margin. Therefore, the area of the source region 4 can be made smaller than before, and the chip area can be reduced.

As described above, in the present embodiment, the channel layer 6 is silicided in the thickness direction. As a result, the obtained metal silicide layer 11 has the following concentration profile in the depth direction, reflecting the concentration profile before silicidation.

FIG. 12A shows Ni and p-type impurities (cross-section perpendicular to the substrate 1 in a portion of the metal silicide layer 11 located on the contact region 5) along the line II ′ shown in FIG. It is a figure which shows an example of the density | concentration profile of Al) typically. As shown in the figure, from the upper surface of the Ni silicide layer 11 to a predetermined depth dc, the impurity concentration of the channel layer 6 is reflected and the n-type impurity is contained at a low concentration and the p-type impurity is hardly contained. At a position deeper than the depth dc, p-type impurities are contained at a high concentration reflecting the impurity concentration of the contact region 5. The depth dc corresponds to the thickness of the channel layer 6.

FIG. 12B shows Ni and n-type cross sections taken along line II-II ′ shown in FIG. 1 (cross sections perpendicular to the substrate 1 in the portion of the metal silicide layer 11 located on the source region 4). It is a figure which shows typically an example of the density | concentration profile of an impurity (N). As shown in the figure, from the upper surface of the metal silicide layer 11 to a predetermined depth dc, n-type impurities are contained at a low concentration reflecting the impurity concentration of the channel layer 6. When the depth is greater than the depth dc, the concentration of the n-type impurity is significantly increased to reflect the impurity concentration of the source region 4. Therefore, the n-type impurity profile has a step near the depth dc.

On the other hand, in the conventional semiconductor element, after the channel layer is patterned to expose the surface of the silicon carbide layer, a Ni film is formed so as to be in contact with the surface of the silicon carbide layer to be silicided. Therefore, the concentration profile of the obtained metal silicide layer reflects the concentration profile of the surface portion of the silicon carbide layer.

In the case of the conventional semiconductor device shown in FIG. 8, in the cross section perpendicular to the substrate of the metal silicide layer located on the contact region (cross section taken along the line II ′ of FIG. 8), FIG. As shown in FIG. 4, the metal silicide layer contains p-type impurities at a concentration similar to the impurity concentration of the contact region from the upper surface to the lower surface. Almost no n-type impurities are contained. Further, in the cross section perpendicular to the substrate in the portion of the metal silicide layer located on the source region (the cross section taken along the line II-II ′ in FIG. 8), as shown in FIG. From the upper surface to the lower surface, an n-type impurity is contained at a concentration similar to the impurity concentration of the source region. A large step as shown in FIG. 12B does not occur in the concentration profile of the n-type impurity in the thickness direction.

12 and 13 are schematic diagrams for explaining the characteristics of the concentration profile of the metal silicide layer 11 in the present embodiment, and do not show a strict concentration profile.

The method of the present embodiment is not limited to the method described above with reference to FIG. 4A to 4C are process cross-sectional views for explaining another method of the present embodiment.

As shown in FIG. 4A, when the contact hole 10s is formed in the interlayer insulating film 9, the surface portion of the channel layer 6 may also be etched (half etching). The thickness of the channel layer 6 after being etched is, for example, 50 nm. However, as described above, it is preferable to control the etching conditions so as not to etch the silicon carbide layer 2.

Thereafter, as shown in FIG. 4B, a Ni (nickel) film 51 is deposited on the interlayer insulating film 9 and inside the contact hole 10s. The thickness of the Ni film 51 is, for example, 50 nm. In this state, annealing is performed for about 1 minute at a temperature of 950 ° C. in a nitrogen atmosphere. By this heat treatment, silicon carbide in the channel layer 6 reacts with Ni at the interface between the channel layer 6 and the Ni film 51 to form the Ni silicide layer 11. Here, the Ni film 51 is silicided almost completely, and the Ni silicide layer 11 having a thickness of, for example, 100 nm is formed. In this case, the thickness of the Ni film 51 is set to be larger than the thickness of the channel layer 6 that is thinned by the etching, so that not only the thinned portion of the channel layer 6 is used. Ni can be diffused to the surface portions of the source region 4 and the p ⁺ contact region 5. Therefore, a good ohmic junction is formed between the Ni silicide layer 11 and the p ⁺ contact region 5 and the source region 4. Further, the sidewall of the Ni silicide layer 11 is in contact with the channel layer 6.

Next, the portion of the Ni film 51 that has not reacted with silicon carbide is removed. Further, the source wiring 12, the gate wiring 13, and the drain electrode 14 are formed by a known method to obtain the MISFET shown in FIG.

In the step shown in FIG. 4A, it is preferable to adjust the etching conditions so that the thickness of the channel layer 6 after the surface portion is removed becomes 1/2 or less of the thickness of the Ni film 51. Thereafter, when the heat treatment conditions are adjusted so that substantially all of the deposited Ni is silicided, the Ni silicide layer 11 obtained by the heat treatment and the source region 4 and the p ⁺ contact region 5 are more reliably and reliably An ohmic junction can be formed.

According to the method shown in FIG. 4, the thickness of the Ni silicide layer 11 can be made smaller than the method described above with reference to FIG. The level of the upper surface of the Ni silicide layer 11 is lower than when the channel layer 6 is not half-etched. The upper surface of the Ni silicide layer 11 is lower than the upper surface of the channel layer 6 depending on the thickness of the Ni film 51 and the channel layer 6 and the etching amount of the silicon carbide layer 2 in the step shown in FIG. There is.

In this embodiment, the channel layer 6 and the Ni film 51 are reacted to form the Ni silicide layer 11, but instead, other metal materials that can form an ohmic junction with the silicon carbide layer 11 (for example, Ti, A film composed of Co) and the channel layer 6 may be reacted to form another metal silicide layer. Even in this case, the same effect as described above can be obtained.

In the above, in order to reduce the resistance between the body region 3 and the source wiring 12, the p ⁺ type contact region 5 having a carrier concentration higher than that of the body region 3 is provided, but the p ⁺ contact region 5 is formed. It does not have to be. For example, if the carrier concentration of the body region 3 is sufficiently high, the high concentration p ⁺ contact region 5 may not be formed.

Although a 4H-SiC substrate was used as the SiC substrate, other crystal planes or other polytype SiC substrates may be used. When a 4H—SiC substrate is used, the silicon carbide layer 2 may be formed on the Si surface, the drain electrode 14 may be formed on the C surface, the silicon carbide layer 2 on the C surface, and the drain electrode 14 on the Si surface. May be formed.

The semiconductor element of the above embodiment is an n-channel type, but may be a p-channel type. In a p-channel type semiconductor element (MISFET), the conductivity type of SiC substrate 1, drift region 2d, source region 4 and channel layer 6 is p-type, and the conductivity type of body region 3 and contact region 5 is n-type.

The semiconductor element of the present invention may be a trench type MISFET.

FIG. 11 is a cross-sectional view showing an example of a trench type MISFET according to the present invention. For the sake of simplicity, the same components as those in FIG.

In the MISFET shown in FIG. 11, the source region 4 is disposed in the surface region of the silicon carbide layer 2. The body region 3 is disposed below the source region 4 and in contact with the source region 4. Silicon carbide layer 2 has a trench 2t that penetrates source region 4 and body region 3 and reaches drift region 2d. In trench 2 t, channel layer 6 is formed so as to cover the side wall of source region 4 and the side wall of body region 3. A gate electrode 8 is provided on the channel layer 6 via a gate insulating film 7 in the trench 2t. Other configurations are the same as those shown in FIG.

Such a trench MISFET can also be formed by the same method as described above with reference to FIG. Specifically, trench 2t is formed in silicon carbide layer 2 in which body region 3, source region 4 and contact region 5 are formed. Next, the channel layer 6, the gate insulating film 7, and the gate electrode 8 are formed in this order in the trench 2t. Thereafter, the gate insulating film 7 and the gate electrode 8 are patterned without processing the channel layer 6. At this time, only the surface portion of the channel layer 6 may be etched. Subsequently, an interlayer insulating film 9 is formed on the channel layer 6 and the gate electrode 8. A contact hole that exposes a part of the surface of the channel layer 6 is formed in the interlayer insulating film 9. Thereafter, as in the step shown in FIG. 2C, a Ni film is deposited on the exposed surface of the channel layer 6 and annealed to form the metal silicide layer 11.

In the trench type MISFET shown in FIG. 11 as well, as in the above-described embodiment, it is possible to secure a good contact with the silicon carbide layer 2 and reduce the margin for mask alignment.

The semiconductor element of the present invention is not limited to a vertical MISFET, and may be a horizontal MISFET. Further, the semiconductor device may not be a MISFET, and may be various semiconductor devices having an electrode electrically connected to the silicon carbide layer. For example, in the above embodiment, the MISFET is manufactured using the SiC substrate 1 having the same conductivity type as that of the silicon carbide layer 2, but an insulated gate bipolar transistor (Insulated Gate Gate) is used using a SiC substrate having a conductivity type different from that of the silicon carbide layer 2. Bipolar Transistor (IGBT) can also be manufactured.

According to the present invention, the metal silicide layer is formed using the additional silicon carbide layer formed on the silicon carbide layer in the opening formed in the interlayer insulating film. As a result, a good contact can be ensured between a predetermined region in the silicon carbide layer and the metal silicide layer, and a margin in consideration of mask alignment can be reduced, so that an increase in chip area can be suppressed.

The present invention can be widely applied to a semiconductor element having an electrode on a silicon carbide layer and an apparatus including the same. The present invention can be suitably used particularly for a storage channel type MISFET. When applied to a storage channel type MISFET, an electrode (metal silicide layer) well bonded to the source region can be formed by reacting the metal deposited on the channel layer with the channel layer. In addition, since the thickness of the source region can be ensured, an increase in on-resistance can be suppressed. Further, since the margin for mask alignment can be reduced, the chip area can be reduced.

1 n-type SiC substrate 2 silicon carbide layer 2d n-type drift region 3 p-type body region 4 source region 5 p ⁺ contact region 6 channel layer 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10s contact hole for source contact formation 10g Contact hole for forming a gate contact 11 Metal silicide layer (Ni silicide, source electrode)
12 Source wiring 13 Gate electrode wiring 14 Back electrode (drain electrode)
31, 32, 33 Silicon oxide

film mask layer

41, 42, 43 Resist layer 51 Ni film

Claims

A silicon carbide substrate;
A first silicon carbide layer disposed on a surface of the silicon carbide substrate;
A second silicon carbide layer disposed on a partial region of the surface of the first silicon carbide layer;
A metal silicide layer provided on the first silicon carbide layer and in contact with the first silicon carbide layer;
An interlayer insulating film provided on the second silicon carbide layer and having an opening;
A conductive layer disposed in the opening,
The metal silicide layer is provided in contact with the inner wall of the opening;
The conductive layer is electrically connected to the first silicon carbide layer via the metal silicide layer;
The semiconductor element wherein the metal silicide layer is in contact with the second silicon carbide layer.
The first silicon carbide layer includes
A first region of a first conductivity type disposed in the first silicon carbide layer;
A second region of a second conductivity type disposed in contact with the first region in the first silicon carbide layer;
A region of the first silicon carbide layer in which neither the first region nor the second region is disposed includes a third region of a second conductivity type,
The semiconductor element according to claim 1, wherein the metal silicide layer is in contact with the second region.
A gate insulating film provided on the second silicon carbide layer;
The semiconductor element according to claim 1, further comprising a gate electrode disposed on the gate insulating film.
The semiconductor element according to any one of claims 1 to 3, wherein the thickness of the metal silicide layer is greater than twice the thickness of the second silicon carbide layer and less than or equal to four times.
5. The semiconductor element according to claim 1, wherein the metal silicide layer is a Ni silicide layer containing carbon.
When viewed from above the first silicon carbide layer, the width w2 of the metal silicide layer in contact with the first or second silicon carbide layer is not less than the width w1 of the opening, and the difference between these widths 6. The semiconductor element according to claim 1, wherein w2-w1 is 0 or more and 200 nm or less.
The semiconductor element according to claim 1, wherein a side surface of the metal silicide layer is in contact with the second silicon carbide layer, and a lower surface of the metal silicide layer is not in contact with the second silicon carbide layer.
The semiconductor element according to claim 7, wherein the metal silicide layer and the second silicon carbide layer are in contact with each other only on side surfaces.
The first and second regions are disposed on a surface region of the first silicon carbide layer, and the second region is disposed on the surface of the first silicon carbide layer so as to be surrounded by the first region. The semiconductor device according to claim 2.
The second region is disposed in a surface region of the first silicon carbide layer, the first region is disposed below the second region,
The semiconductor element according to claim 2, further comprising a trench that penetrates through the second region and the first region and reaches the third region.
A method for manufacturing a semiconductor element having a silicon carbide layer,
(A) preparing a silicon carbide substrate having a first silicon carbide layer formed on the surface;
(B) forming a second silicon carbide layer on the first silicon carbide layer;
(C) forming an interlayer insulating film having an opening exposing a part of the surface of the second silicon carbide layer on the second silicon carbide layer;
(D) forming a metal film on the exposed surface of the second silicon carbide layer in the opening of the interlayer insulating film;
(E) reacting the metal film with a part of the second silicon carbide layer and a part of the first silicon carbide layer to form a metal silicide layer in contact with the first silicon carbide layer;
(F) forming a conductive layer electrically connected to the first silicon carbide layer through the metal silicide layer in the opening of the interlayer insulating film.
12. The metal contained in the metal film in the step (E) is diffused and silicided into the second silicon carbide layer and the first silicon carbide layer, thereby forming the metal silicide layer. The manufacturing method of the semiconductor element of description.
The method of manufacturing a semiconductor element according to claim 11 or 12, wherein, in the step (D), the thickness of the metal film is larger than the thickness of the second silicon carbide layer and twice or less.
The step (C)
Forming the interlayer insulating film on the second silicon carbide layer (C1);
Forming the opening in the interlayer insulating film (C2),
The method of manufacturing a semiconductor element according to claim 11, wherein the second silicon carbide layer is not etched before the step (C2).
15. The method of manufacturing a semiconductor element according to claim 14, wherein the step (C2) includes a step of etching a surface portion of the second silicon carbide layer exposed by the opening.
The method of manufacturing a semiconductor element according to claim 15, wherein in the step (C2), the thickness of the other silicon carbide layer after the etching is ½ or less of the thickness of the metal film.
The method of manufacturing a semiconductor element according to claim 11, wherein the metal film is a Ni film.
The first and second silicon carbide layers are of a second conductivity type;
A step of forming a first conductivity type body region and a second conductivity type source region in contact with the body region in the first silicon carbide layer between the step (A) and the step (B). (G) and
A step (H) of forming a gate insulating film and a gate electrode on the second silicon carbide layer between the step (B) and the step (C);
The step (C) is a step of forming, on the second silicon carbide layer, an interlayer insulating film having an opening that exposes a portion of the surface of the second silicon carbide layer located on the source region. ,
The step (E) is a step of reacting the metal film with a part of the second silicon carbide layer and a part of the source region to form a metal silicide layer in contact with the source region. 18. A method for manufacturing a semiconductor device according to any one of items 1 to 17.