WO2011009344A1

WO2011009344A1 - Turbo encoding method and turbo encoding system based on long term evolution (lte)

Info

Publication number: WO2011009344A1
Application number: PCT/CN2010/073636
Authority: WO
Inventors: 刘合武
Original assignee: 中兴通讯股份有限公司
Priority date: 2009-07-21
Filing date: 2010-06-07
Publication date: 2011-01-27

Abstract

A TURBO encoding method and a TURBO encoding system based on Long Term Evolution (LTE) are disclosed. The TURBO encoding method includes: a master control unit triggers a storage unit to receive and store sequential data (201); the master control unit generates successively increasing addresses after triggering an inner interleaving unit to calculate interleaved addresses, and inputs the interleaved addresses and the successively increasing addresses to the storage unit, synchronously (202); a Recursive System Code (RSC) encoding unit reads interleaved data and the sequential data from the storage unit according to the interleaved addresses and the successively increasing addresses, then performs RSC encoding to the interleaved data and the sequential data (203).

Description

LTE-based TURBO coding method and system

The present invention relates to the field of communications, and in particular, to a TURBO coding method and system based on Long Term Evolution (LTE). Background technique

The 3rd Generation Partnership Project (3GPP) is a leading 3G technical specification organization that aims to develop and promote the 3G standard for the evolution-based core network of the Global System for Mobile Communications (GSM) system. . Among them, Long Term Evolution (LTE) is a 3G long-term evolution technology plan of 3GPP. The 3GPP LTE standard is a technological revolution in the communications industry. It provides good services for real-time services, high-reliability services and broadcasting services. Support, which can achieve low latency, full packet and high data rate targets. There is no doubt that LTE will become the most mainstream next-generation broadband mobile communication technology. The TURBO code has superior error and block error performance, and has been adopted by many communication standardization organizations and written into the relevant communication standards issued by it, no exception, 3GPP protocol (3GPP LTE TS 36.2132V8.5.0) The encoding method of TURBO code is adopted.

In the 3GPP LTE protocol, the TURBO encoder includes two 8-state member encoders and an inner interleaver. The LTE-based TURBO encoder's internal interleaver uses a special interleaving method different from other standards. The input/output relationship of the interleaver is:

c; = c _n(! ), (i = 0,L , ^ - l) Π( ) = mod( jx + / ₂ x ² , K)

Where ί. ,

Is the input data of the 1!11 80-coded interleaver, c„c[,..., c _K _ _x is the output data of the inner interleaver, 40 <^< 6144 , the value of the parameter / ^ port is based on the K value Variety. The existing TURBO encoder designs are mostly based on communication systems such as Wideband Code Division Multiple Access (WCDMA), and the internal interleaving method is different from the interleaving method based on LTE-based TURBO coding. For example: an existing WCDMA-based TURBO coding method and coding apparatus, the interleaver in the scheme is a memory in which an interleave address has been stored, that is, the scheme directly obtains the storage of the interleaved sequence by checking the interleaving table. Interleave address. However, if this scheme is applied to LTE-based TURBO coding, since LTE-based TURBO coding has relatively complicated internal interleaving, huge hardware internal storage overhead is required, so the cost is high and the data processing speed is slow. Summary of the invention

The technical problem to be solved by the present invention is that the LTE-based TURBO coding method is costly and slow, and proposes a LTE-based TURBO coding method and system with low cost and strong data processing.

In order to solve the above technical problem, the present invention provides an LTE-based TURBO coding method, which sets a main control unit, an inner interleaving unit, a storage unit, and a recursive system convolutional code (RSC) coding unit, and the method further includes:

The main control unit triggers the storage unit to receive and store sequential data;

After the main control unit triggers the inner interleaving unit to calculate the interleaving address, generates an sequential increasing address, and simultaneously inputs the interleaved address and the sequential incremental address into the storage unit;

The RSC encoding unit reads the interleaved data and the sequential data from the storage unit according to the interleaving address and the sequential incremental address, and then performs RSC encoding on the interleaved data and the sequential data.

Further, the main control unit triggers the storage unit to receive and store the sequence data, and specifically includes:

The main control unit receives the data block size K value, and starts receiving the sequence data; the main control unit triggers the storage unit to receive and store the sequence data, and simultaneously counts the received data by the counter; The main control unit generates the storage unit reception completion signal when the check counter is equal to K.

The method further includes:

The main control unit determines whether the K value is valid. When the judgment is invalid, the received sequence data is discarded, and the main control unit restarts receiving the sequence data.

Further, the main control unit determines whether the K value is valid, specifically: checking whether the data block size K value received by the main control unit is a specific value specified by the 3GPP LTE protocol.

Further, the main control unit triggers the inner interleaving unit to calculate an interleave address, which specifically includes:

The main control unit transmits a K value to the inner interleaving unit, and the inner interleaving unit calculates and stores an initial value of the interleaving address;

The inner interleaving unit recursively calculates all interleaving addresses according to the K value, the initial value of the interleaving address, and the interleaver input and output relation in the 3GPP LTE protocol.

Further, the RSC encoding unit performs RSC encoding on the interleaved data and the sequential data after the interleaving data and the sequential data are read from the storage unit according to the interleaving address and the sequential incremental address, and specifically includes:

The RSC encoding unit reads the interleaved data and the sequential data from the storage unit according to the interleaved address and the sequential incremental address;

The RSC encoding unit respectively performs RSC encoding on the interleaved data and the sequential data, and the main control unit counts the received interleaved data and the sequential data through a counter;

The main control unit checks whether the counter is equal to K, and if so, the main control unit generates a data read completion signal, and if not, the RSC encoding unit continues to read the interleaved data and the sequential data from the storage unit. Until the main control unit checks that the counter is equal to K.

Further, the storage unit includes two random access memories (RAMs), and the storage The unit performs data reception operation through any one of the RAMs while reading data operations through another RAM.

The present invention also provides an LTE-based TURBO coding system, where the system includes: a main control unit, an internal interleaving unit, a storage unit, and an RSC encoding unit;

The main control unit is configured to control the storage unit to receive and store sequence data, control the interleaving unit to calculate an interleave address, and control the RSC encoding unit to read interleave data and sequence data from the storage unit;

The inner interleaving unit is connected to the main control unit and the storage unit, and is used to calculate an interleaving address of the data;

The storage unit is connected to the main control unit, the inner interleaving unit and the RSC encoding unit, and configured to receive and store sequential data, output interleaved data and sequential data according to the interleaving address and the sequential incremental address;

The RSC coding unit is connected to the main control unit and the storage unit, and is configured to perform RSC coding on the interleaved data and the sequential data.

The main control unit further includes:

The K value valid judgment subunit is configured to determine whether the data block size K value is a specific value specified by the 3GPP LTE protocol;

a write control operation subunit for performing an operation of receiving data on the storage unit; and a read control operation subunit for performing an operation of reading data on the storage unit.

The inner interleaving unit further includes:

An initial value storage subunit, configured to store an initial value required by the inner interleaving unit to calculate an interleave address;

And a recursive calculation subunit, configured to recalculate all interleaved addresses according to a data block size K value and an initial value in the initial value storage subunit.

The storage unit further includes a first RAM subunit and a second RAM subunit, The first RAM sub-unit and the second RAM sub-unit are configured to perform a ping-pong operation, and receive and store the sequential data, and output the interleaved data and the sequential data according to the interleaved address and the sequential incremental address.

The RSC encoding unit further includes:

a first RSC coding subunit, configured to perform RSC coding on the received sequence data, and a second RSC coding subunit, configured to perform RSC coding on the received interleaved data;

The RSC coding control subunit is configured to connect the first RSC coding subunit and the second RSC coding subunit, and is configured to perform output control on the RSC encoded data of the first RSC coding subunit and the second RSC coding subunit.

The main control unit is further configured to send N sequential incremental addresses to the storage unit at each clock;

The inner interleaving unit is further configured to output N interleaving addresses in parallel to the storage unit at each clock;

The system includes at least N of the storage units, under the control of the main control unit, N storage units simultaneously perform a write operation, and each storage unit writes 1 bit of data at each clock; the storage unit Reading the locally saved data in parallel according to the received N sequential increment addresses and the N interleave addresses, and outputting the data to the RSC encoding unit correspondingly;

Correspondingly, the RSC encoder is further configured to perform RSC encoding on the N-bit uninterleaved data received at each clock, and perform RSC encoding on the N-bit interleaved data received at each clock; At the same time, an N-bit system code, an N-bit first check code, and an N-bit second check code are output.

In addition to the N storage units, the system further includes another N storage units, and the other N storage units perform ping-pong operations with the N storage units, and simultaneously read and write data in the storage unit.

When N=8, the initial value stored in the initial value storage unit is: moc J +

, mod(2/ ₂ , , moddSf^ 64 f ₂ ), K) , mod(16/ ₂ , and ηιο(1(128/ ₂ , ); where Κ is the code Block size, 40 ≤ ≤ 61 4 , the value of the parameter / ^ port varies according to the Κ value;

Correspondingly, the recursive calculation subunit is further used to: use a formula:

Π ' + 1) = ηιοά((Π( + modCCmodC^ + f ₂ , K) + mod(2i ₂ , ), ), successively calculate the value of the interleaved address Π(1) ~Π(7) by recursion;

According to the formula:

Π ' + 8) = mod((n( ) + modCCmodCS/! + 64 f ₂ , K) + mod(16if ₂ , Κ)), Κ)), Κ) Calculate the interleaved address by recursion Π (8 ) ~Π(15) value.

By adopting the method and system of the present invention, only the initial value of the data interleaving address is calculated and stored, the hardware memory is greatly saved, and the cost is reduced; in addition, the storage unit of the present invention is further provided with two RAMs for ping-pong operation. The data is received and read at the same time, so that it has strong data processing capability and improves the processing capability of the LTE data link.

In addition, the present invention is based on the 3GPP LTE protocol Turbo encoder parallel design scheme, which internally adopts the ping-pong operation and the parallel coding processing manner, which greatly shortens the processing time of the Turbo coding, improves the efficiency of the Turbo coding, and thus reduces the LTE. The processing delay of the link downlink improves the processing capability of the LTE data link. The system of the present invention has a clear structure and can be implemented by using a general low-cost circuit device to realize high-efficiency Turbo coding operation at low cost. DRAWINGS

1 is a schematic diagram of an LTE-based TURBO encoding system according to the present invention;

2 is a schematic flow chart of a TURBO encoding method based on LTE according to the present invention;

3a is a schematic flowchart of receiving sequence data in a preferred embodiment of the LTE-based TURBO encoding method according to the present invention;

FIG. 3b is a schematic flowchart of sending encoded data in a preferred embodiment of the LTE-based TURBO encoding method according to the present invention; FIG.

4 is an internal junction of an 8-bit parallel processing LTE Turbo coding system according to an embodiment of the present invention; Schematic diagram

5 is a schematic diagram of an interleaving address recursive generation in an inner interleaving module according to an embodiment of the present invention; FIG. 6 is a schematic structural diagram of an initial value storage subunit according to an embodiment of the present invention;

FIG. 7 is a block diagram of a single bit convolutional code encoding implementation in an LTE Turbo coding system according to an embodiment of the present invention. detailed description

The invention will now be further described with reference to the drawings and specific embodiments.

The core idea of the present invention is: the storage unit receives and stores the sequential data, and the inner interleaved unit counts the output unit to simultaneously output the interleaved data and the sequential data according to the interleaved address and the sequential incremental address, and sends the same to the recursive system convolutional code (RSC, Recursive Systematic Convolution code) The coding unit performs RSC coding. The sequence data refers to the uninterleaved original data sent by the external coding system, the interleaved data refers to the interleaved data, the sequential incremental address refers to the address corresponding to the sequential data received by the storage unit, and the interleaved address refers to the inner interleaved unit. The calculated 11() =

The value of ² , will be explained here by the following embodiments.

Referring to FIG. 1, the present invention further provides an LTE-based TURBO coding system 100, which is applied to a TURBO encoder. The system 100 includes a main control unit 102, an inner interleaving unit 104, a storage unit 106, and an RSC encoding unit 108. The main control unit 102 is configured to control the storage unit 106 to receive and store the sequential data, control the inner interleaving unit 104 to calculate the interleaving address, and the RSC encoding unit 108 reads the interleaved data and the sequential data from the storage unit 106;

The internal interleaving unit 104 is connected to the main control unit 102 and the storage unit 106 for calculating a data interleaving address. The storage unit 106 is connected to the main control unit 102, the inner interleaving unit 104, and the RSC encoding unit 108 for receiving and storing the interleaving. The data and sequence data; the RSC encoding unit 108 is connected to the main control unit 102 and the storage unit 106 for RSC encoding the interleaved data and the sequential data. The main control unit 102 further includes: a K value valid judgment subunit 102a, a write control operation subunit 102b, and a read control operation subunit 102c. The K value valid judgment subunit 102a is configured to determine whether the data block size K value is a specific value specified by the 3GPP LTE protocol; the write control operation subunit 102b is configured to perform an operation of receiving data on the storage unit 106; The subunit 102c is configured to perform an operation of reading data from the storage unit 106.

The inner interleaving unit 104 further includes: an initial value storage subunit 104a and a recursive calculation subunit 104b. The initial value storage subunit 104a is configured to store an initial value required for the inner interleaving unit 104 to calculate an interleave address; the recursive calculation subunit 104b is configured to initialize the subunit 104a according to the data block size and the initial value. The value is recursively calculated for all interleaved addresses.

The storage unit 106 further includes a first random access memory (RAM) subunit 106a and a second RAM subunit 106b. The first RAM sub-unit 106a and the second RAM sub-unit 106b are configured to perform ping-pong operations, and receive and store sequential data, and output interleaved data and sequential data according to the interleaved address and the sequential incremental address.

The RSC encoding unit 108 further includes: a first RSC encoding subunit 108a, a second RSC encoding subunit 108b, and an RSC encoding control subunit 108c. The first RSC encoding sub-unit 108a is configured to perform RSC encoding on the received sequence data; the second RSC encoding sub-unit 108b is configured to perform RSC encoding on the received interleaved data; and the RSC encoding control sub-unit 108c is connected to the first RSC. The coding sub-unit 108a and the second RSC coding sub-unit 108b are configured to implement data output control after processing by the first RSC coding sub-unit 108a and the second RSC coding sub-unit 108b.

Referring to FIG. 2, FIG. 2 is a schematic flowchart of a TURBO encoding method based on LTE according to the present invention, which includes the following steps:

Step 201: The main control unit triggers the storage unit to receive and store the sequence data. The main control unit actively triggers the storage unit to receive and store the sequential data.

Step 202: After the main control unit triggers the inner interleaving unit to calculate the interleave address, the main control unit generates a sequential increment address, and simultaneously inputs the interleave address and the sequential increment address into the storage unit. After the storage unit stores the sequence data, the main control unit triggers the inner interleaving unit to calculate the interleave address according to the output and the input relationship. According to the 3GPP LTE protocol, the input and output relationship of the interleaver is:

c; = c _n(! (i = 0,L , ^ - l)

Π( ) = modC^ xi + f ₂ xi ² , K)

Where ί.

For the output data of the internal interleaver, 40 < ^ < 6144, the value of the parameter / ^ port varies according to the value of K.

Step 203: The storage unit outputs the interleaved data and the sequential data according to the interleaving address and the sequential incremental address, and sends the interleaved data and the sequential data to the RSC encoding unit for RSC encoding. The RSC coding unit receives the interleaved data and the sequence data and RSC-encodes it under the direction of the main control unit, thereby completing the LTE-based TURBO coding.

The invention will now be described in further detail in connection with the preferred embodiments of the invention.

Referring to FIG. 3a, FIG. 3a is a schematic flowchart of receiving sequence data in a preferred embodiment of the LTE-based TURBO coding method according to the present invention. In a preferred embodiment of the present invention, the storage unit includes two identical RAMs for buffering, and both of the RAMs can be used to receive or read data, so that the storage unit can receive data operations through a RAM during TURBO encoding. At the same time, the data read operation is performed through another RAM, that is, the ping-pong operation is performed through two RAMs to realize simultaneous reception and reading of data.

The method for receiving sequential data in a preferred embodiment of the present invention includes the following steps:

Step 301: The main control unit receives the data block size K value from the outside and starts receiving the sequential data. This step further includes the external upstream unit detecting that the primary control unit is in an idle state, transmitting the first data indication signal thereto and simultaneously transmitting the data block size K value and the first sequential data.

Step 302: The main control unit checks whether the first RAM in the storage unit is in an idle state. If yes, step 306 is performed; otherwise, step 303 is performed. Step 303: The main control unit checks whether the second RAM in the storage unit is in an idle state, and if yes, performs step 304; if not, returns to step 302.

Step 304: The main control unit triggers the second RAM of the storage unit to receive and store the sequential data, and simultaneously counts the sequential data size received by the second RAM by the counter.

Step 305: The main control unit checks whether the counter is equal to K. If yes, the main control unit generates a second RAM reception completion signal; if not, step 304 is performed.

Step 306: The main control unit triggers the first RAM of the storage unit to receive and store the sequential data, and simultaneously counts the sequential data size received by the first RAM by the counter.

Step 307: The main control unit checks whether the counter is equal to K. If yes, the main control unit generates a first RAM reception completion signal; if not, step 306 is performed.

Before performing step 305 and step 307 respectively, the method further includes: the main control unit first determining whether the K value is valid, and if not, discarding the received data, and jumping back to step 302 to restart receiving data without performing steps. 305 or step 307; If the K value is valid, step 305 or step 307 is performed. According to the 3GPP LTE protocol, the K value in the input/output relationship of the interleaver is a specific value between 40 and 6144, so the method of determining whether the K value is valid is to check whether the data block size K value received by the main control unit is The specific value specified by the 3GPP LTE protocol, if not, indicates that the data received this time is invalid, and the storage unit needs to receive the data again.

Referring to FIG. 3b, FIG. 3b is a schematic flowchart of sending encoded data in a preferred embodiment of the LTE-based TURBO encoding method according to the present invention. After the first RAM or the second RAM in the storage unit receives the data, the main control unit starts triggering the storage unit to perform the operation of transmitting the encoded data.

The method for transmitting encoded data in the preferred embodiment of the present invention includes the following steps:

Step 311: The main control unit checks whether the received signal of the first RAM is valid. If it is invalid, step 312 is performed; if it is valid, step 316 is performed.

Step 312: The main control unit checks whether the reception completion signal of the second RAM is valid, if not If yes, go to step 311; if it is valid, go to step 313.

Step 313: The main control unit triggers the interleave unit to calculate the interleave address, and the main control unit generates a sequential increment address by reading the enable signal, and the interleave address and the sequential increment address are simultaneously input into the second RAM of the storage unit. The main control unit transmits the K value to the inner interleaving unit, and the inner interleaving unit first calculates and stores the initial value of the interleaving address according to the input and output relationship of the 3GPP LTE protocol interleaver and transmits it to the storage unit, and then according to the 3GPP LTE protocol. The middle interleaver input and output relations recursively calculate all interleaved addresses. In this way, the interleaving unit and the storage unit only need to store the initial value used for calculating the interleaving address, and the calculated interleaving address is continuously covered, and does not need to be saved all the time, thus avoiding the need for a large amount of memory to store all the interleaving. address.

Step 314: The RSC encoding unit reads the interleaved data and the sequential data from the second RAM of the storage unit according to the interleave address and the sequential increment address, and performs RSC encoding on the same, and the main control unit receives the interleaved data and the sequential data through the counter. Count.

Step 315: The main control unit checks whether the counter is equal to K. If yes, the main control unit generates a second RAM read completion signal; if not, step 314 is performed.

Step 316: The main control unit triggers the interleave unit to calculate the interleave address, and the main control unit generates a sequential increment address by reading the enable signal, and the interleave address and the sequential increment address are simultaneously input into the first RAM of the storage unit.

Step 317: The RSC encoding unit reads the interleaved data and the sequential data from the first RAM of the storage unit according to the interleave address and the sequential increment address, and performs RSC encoding on the same, and the main control unit reads the interleaved data and sequence through the counter pair. The data is counted.

Step 318: The main control unit checks whether the counter is equal to K. If yes, the main control unit generates a first RAM read completion signal; if not, step 317 is performed.

In addition, in the above-described scheme of the present invention, in a practical application, data blocks of a plurality of bits (up to 6144 bits) are included in one code block. According to the above-mentioned single-bit processing method, taking the maximum code block (6144 bits) as an example, only 6144 clock cycles are required to receive data, if interlaced is not considered. The address generation time and the RSC encoding time require 6144 clock cycles to read the data, so that the processing time of one code block is quite long. Even with ping-pong operation, simultaneous reading and writing of data requires more than 6144 clock cycles to process a maximum code block. Therefore, in the case of a large number of input bits, the delay of Turbo coding processing for one code block is relatively large, so that inevitably, a large delay is caused to the entire downlink processing, and a large delay is generated. At the same time, it will further cause the processing performance of the baseband to be low.

In order to overcome the problem that the downlink processing delay caused by the single-bit Turbo coding processing time is too long, the present invention implements multi-bit parallel processing on the basis of the system structure shown in FIG.

The main control unit 102 of FIG. 1 is connected to an inner interleaving unit 104, a storage unit 106 and an RSC encoding unit 108, respectively, which control the above-mentioned respective parts, which generate sequential incremental addresses and transmit N sequential incremental addresses at each clock. To the storage unit 106;

The inner interleaving unit 104 is connected to the storage unit 106 and the main control unit 102, which calculates the interlace address, and outputs N interleaving addresses in parallel to the storage unit 106 at each clock while the main control unit 102 transmits the sequential incrementing address;

The storage unit 106 is connected to the main control unit 102 and the internal interleaving unit 104, and has at least N storage units therein. Under the control of the main control unit 102, N storage units simultaneously perform a write operation, and each storage unit is at each clock. Writing 1-bit data; reading and locally outputting the locally saved data in parallel according to the received N sequential increment addresses and N interleave addresses generated by the main control unit 102 to the first RSC encoding unit in the RSC encoding unit 108 Unit 108a and second RSC encoding subunit 108b;

The RSC encoding unit 108 is connected to the storage unit 106 and the main control unit 102, and includes a first RSC encoding subunit 108a, a second RSC encoding subunit 108b, and an RSC encoding control subunit 108c, the first RSC encoding subunit 108a pair The N-bit uninterleaved data received by the clock is RSC-encoded and sent to the RSC encoding control sub-unit 108c. The second RSC encoding sub-unit 108b performs RSC encoding on the N-bit interleaved data received by each clock and sends the data to the N-bit interleaved data. The RSC encoding control sub-unit 108c, the RSC encoding control sub-unit 108c performs output control on the data sent from the first RSC encoding sub-unit 108a and the second RSC encoding sub-unit 108b, and simultaneously outputs an N-bit system code and N bits at each clock. The first check code and the N bit second check code.

In addition, when the storage unit 106 includes another N storage units in addition to the N storage units, the other N storage units perform ping-pong operation with the N storage units, and simultaneously read and write data in the storage unit 106. .

Further, a connected initial value storage subunit 104a and a recursive calculation subunit 104b may be included in the inner interleaving unit 104. The initial value storage subunit 104a stores an initial value required for calculating an interleave address; the recursive calculation subunit 104b is configured to calculate an interleave address according to the interleave address calculation formula and the initial value stored in the initial value storage subunit 104a, and It is output to the storage unit 106.

The 8-bit parallel processing is taken as an example to describe the multi-bit parallel processing scheme of the encoding system in detail. However, the present invention is not limited to the 8-bit parallel implementation, and is also applicable to 4-bit, 16-bit, 32-bit, etc. multi-bit parallelism. The implementation of the process.

Figure 4 shows the internal structure of an 8-bit parallel processing LTE Turbo coding system, which includes the following modules:

The main control unit 102: mainly implements overall control of the inner interleaving unit 104, the storage unit 106, and the RSC encoding unit 108. The internal main includes a K value valid judgment subunit 102a, a write operation control subunit 102b, a read operation control subunit 102c, and other control function subunits 102d. The K value valid judgment subunit 102a is configured to determine whether the code block size K value input by the upstream module is a specific value given in 5.1.3.2 of 3GPP LTE TS 36.212 V8.5.0, where the upstream module refers to the Turbo code a module directly connected to the system and serving as an output of data flowing into the interior of the Turbo coding system; a write operation control subunit 102b for generating a sequential write address to the memory unit 106 and performing selective write data control; the read operation control subunit 102c, The sequential increment address is generated for the storage unit 106 and the read data control is selected; the other control function sub-unit 102d mainly implements the handshake of the upstream and downstream modules and the inter-interleaving unit 104, the storage unit 106, and the RSC code list. The element 108 controls the signal and the like, wherein the downstream module refers to a module directly connected to the Turbo coding system and serves as an input terminal for data flowing out of the Turbo coding system;

The inner interleaving module 104: internally mainly includes an initial value storage subunit 104a and a recursive calculation subunit 104b. The initial value storage sub-unit 104a is configured to store the initial value of the interleaving address recursion; the recursive address, that is, the completion of the interleave address 11 ( ) = 1110 (1 ( + / _: ^ ^{2 )} , the 8-way parallel computing function, so that each Each clock can output 8 interleaved addresses at the same time, Π(8«), Π(8« + 1), Π(8« + 2), Π(8« + 3), Π(8« + 4), Π( 8« + 5), Π (8« + 6), Π (8« + 7);

The storage unit 106: internally includes two sets of dual-port RAM sub-units for storing data, that is, a first RAM sub-unit 106a and a second RAM sub-unit 106b. Each set of RAM sub-units includes 8 blocks of depth 768 and a width of lbit. Dual port RAM. The ping-pong operation is performed by two sets of dual-port RAM sub-units to realize simultaneous reading and writing of data. In the write data operation, 8 bits of data can be written at a time; during the read data operation, the sequential increment address input by the read operation control subunit 102c and the interleave address generated by the inner interleaving unit 104 can be simultaneously received, and the uninterleaved data can be output simultaneously. (8bits) and interleaved data (8bits);

The RSC encoder unit 108 is internally composed mainly of a first RSC encoding subunit 108a, a second RSC encoding subunit 108b, and an RSC control subunit 108c, and the first RSC encoding subunit 108a is responsible for performing parallel RSC on uninterleaved data (8 bits). Encoding; the second RSC encoding sub-unit 108b is responsible for parallel RSC encoding of the interleaved data (8 bits); the RSC control sub-unit 108c is responsible for outputting the RSC encoded data of the first RSC encoding sub-unit 108a and the second RSC encoding sub-unit 108b. Control, simultaneously output 8bits system code, 8bits first check code and 8bits second check code.

As shown in FIG. 5, it is a schematic diagram of the interleaving address recursive generation of the inner interleaving unit 104 of the present invention. The input of the internal interleaving unit 104 inside the Turbo coding system in LTE is c^c^c^c,,...^^, and the output is , ,...,4—i , where 40≤ ≤6144, input and Output The following algorithm relationships are satisfied:

_C ; = _Cn(i) , (i = 0, L, K_1)

Π(ϊ) = modC^ xi + f ₂ xi ² , K)

To complete the 8-way parallel calculation function of the interleave address n() = mod ; x + / ₂ x ² ,, each clock outputs 8 interleaved addresses simultaneously, ie Π(8«), Π(8« + 1), Π(8« + 2), Π(8« + 3), Π(8« + 4), Π(8« + 5), Π(8« + 6), Π(8« + 7), the invention Adopt parallel recursive implementation.

According to the internal interleaving address of the above LTE Turbo coding system, the formula n() = mod( ₁ x + ₂ x ² , K) is generated. For the code block value K of 40 ≤ ≤ 6144, it can be derived:

Π( + 1) = moddf, χ ( + 1) + / ₂ χ ( + 1) ² ), Κ)

= mod((n(i) + modCCmodC^ + f ₂ ,K) + mod(2if ₂ ,K)), K)), K) ( 1 )

U(i + 8) = mod((/; x (i + 8) + ₂ x (i + 8) ² ), K)

= mod((n() + moddmodiSf, + 64 f ₂ ,K) + mod(16if ₂ , K)), K)), K) ( 2 ) As can be seen from the above derivation, Π( + 1) The result can be obtained from the values of Π(0, Λ + Λ and 2. Among them, for a fixed block size Κ, Λ + Λ is fixed, 2^ can also be solved by accumulating, and the corresponding mo /; + / ₂ , and ηιοά(2/ ₂ , ) can be saved by pre-preserving the values of moc ^ + y^ Q and mod(2/ ₂ , iO in the initial value storage sub-unit 104a, and then querying according to the code block size K value The value in the corresponding address is recursively calculated to obtain Π( + 1).

Similarly, (+8) can save the values of mod((S f, + 64 f ₂ ), K) , mod(16/ ₂ , and ηιοά(128/ ₂ , ) in the initial value storage subunit 104a in advance. Then, according to the code block size 值 value query, the corresponding address saved is read and recursively calculated.

The 8-way parallel interleaved address can derive Π(1) from 推(0) = 0 according to the derivation relation (1), derive the output address Π(8) of the first way according to the derivation relation (2), and then utilize The address of the first way is used to derive the second output address, and the second output address is used to derive the third output address. The recursive process of the eight parallel interleaved addresses is as shown in FIG. 5. According to the above analysis and the derivation of FIG. 5, it can be seen that the inner interleaving unit 104 needs to store mo ^+y), raod(2f ₂ , K), mod((8/; +64/ ₂ ), mod( The initial value of 16/ ₂ , and ηιοά (128/ ₂ , ).

FIG. 6 is a schematic structural diagram of the initial value storage subunit 104a in the present invention. The subunit has a data bit width of 13 bits, a depth of 940, and an address width of 10. The data stored in addresses 0~187 is the initial value of modd^+f^K); the data stored in addresses 188~375 is the initial value of mod(2/ ₂₎ ; the data stored in addresses 376~563 is mod^ /; +64/ ₂ ), the initial value; the address 564~751 corresponds to the stored data is mod (16 / ₂ , iO initial value; address 752 ~ 939 corresponding stored data is mod (128 / ₂ , the initial value .

FIG. 7 is a block diagram of a single-bit convolutional code encoding implementation in a Turbo coding system. To implement 8-way parallel RSC coding, the present invention adopts the following parallel implementation scheme.

From Figure 7, there are:

(2-1) A hardware implementation of parallel RSC normal data processing can be derived from the above equation. The final output and shift register final values are as follows:

Z0=Dl ^A D0 ^A d0;

Zl=D2 ^A Dl ^A D0 ^A dl ^A d0;

z2-D2 ^A D0 ^A d2 ^A dl ^A d0;

Z5=D0M5M4M3M2;

Z6=D2 ^A Dl ^A d6 ^A d5 ^A d4 ^A d3 ^A d0;

Z7=Dl ^A D0 ^A d7 ^A d6 ^A d5 ^A d4 ^A dl; next_D0=D2 ^A D 1 M7M5M4M3M0;

next_D 1 =D0M6M4M3M2;

next_D2=DlM5M3M2Ml;

Where z0, zl, z2...z7 represent the value of the 8-channel RSC after output; DO, Dl, D2 represent the current value in the internal register of the RSC; next_D0, next_Dl, next_D2 represent the value of the next state in the above internal register ; d0, dl ...d7 represent 8 parallel inputs.

Compared with the prior art, the LTE-based TURBO coding method and system of the present invention calculates and stores the initial value of the data interleaving address by using the inner interleaving unit, and then recursively calculates all the interleaved addresses, thus avoiding the inner interleaving unit. Storing all the interleaved addresses greatly saves the hardware memory and reduces the cost. In addition, the memory unit of the present invention is further provided with two RAMs for ping-pong operation to realize simultaneous data reception and reading, thus having strong data processing capability. , improve the processing power of the LTE data link.

In addition, the present invention is based on the 3GPP LTE protocol Turbo encoder parallel design scheme, which internally adopts the ping-pong operation and the parallel coding processing manner, which greatly shortens the processing time of the Turbo coding, improves the efficiency of the Turbo coding, and thus reduces the LTE. The processing delay of the link downlink improves the processing capability of the LTE data link. The system of the present invention has a clear structure and can be implemented by using a general low-cost circuit device to realize high-efficiency Turbo coding operation at low cost.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A TURBO coding method based on Long Term Evolution (LTE), characterized in that: a main control unit, an inner interleaving unit, a storage unit, and a recursive system convolutional code (RSC) coding unit are provided, the method further comprising:

The LTE-based TURBO coding method according to claim 1, wherein the main control unit triggers the storage unit to receive and store the sequence data, which specifically includes:

The main control unit receives the data block size K value and starts receiving the sequence data; the main control unit triggers the storage unit to receive and store the sequence data, and simultaneously counts the received data by the counter;

The main control unit generates the storage unit reception completion signal when the check counter is equal to K.

The LTE-based TURBO coding method according to claim 2, wherein the method further includes:

The LTE-based TURBO coding method according to claim 3, wherein the main control unit determines whether the K value is valid, specifically: checking whether the data block size K value received by the main control unit is 3GPP LTE. The specific value specified in the agreement.

The LTE-based TURBO coding method according to claim 1 or 2, wherein the main control unit triggers the inner interleaving unit to calculate an interleave address, which specifically includes: The main control unit transmits a K value to the inner interleaving unit, and the inner interleaving unit calculates and stores an initial value of the interleaving address;

The LTE-based TURBO coding method according to claim 1 or 2, wherein the RSC coding unit reads the interleaved data and the sequential data from the storage unit according to the interleave address and the sequential incremental address, and then performs interleaved data and The sequential data is RSC encoded, and specifically includes:

The LTE-based TURBO encoding method according to claim 1, wherein the storage unit comprises two random access memories (RAMs), and the storage unit performs data receiving operations through any one of the RAMs, and simultaneously passes through Another RAM performs a read data operation.

8. An LTE-based TURBO coding system, the system comprising: a main control unit, an inner interleaving unit, a storage unit, and an RSC coding unit;

The inner interleaving unit is connected to the main control unit and the storage unit, and is used to calculate an interleaving address of data; The storage unit is connected to the main control unit, the inner interleaving unit, and the RSC encoding unit, and configured to receive and store sequential data, output interleaved data and sequential data according to the interleaved address and the sequential incremental address;

The LTE-based TURBO coding system according to claim 8, wherein the main control unit further comprises:

The LTE-based TURBO coding system according to claim 8, wherein the internal interleaving unit further comprises:

The LTE-based TURBO coding system according to claim 8, wherein the storage unit further comprises a first RAM sub-unit and a second RAM sub-unit, the first RAM sub-unit and the second RAM sub-unit For performing a ping-pong operation, while receiving and storing the sequential data, the interleaved data and the sequential data are output according to the interleaved address and the sequential increment address.

The LTE-based TURBO coding system according to claim 8, wherein the RSC coding unit further comprises:

a first RSC encoding subunit, configured to perform RSC encoding on the received sequence data, and a second RSC encoding subunit, configured to perform RSC encoding on the received interleaved data; The RSC coding control subunit is configured to connect the first RSC coding subunit and the second RSC coding subunit, and is configured to perform output control on the RSC encoded data of the first RSC coding subunit and the second RSC coding subunit.

The LTE-based TURBO coding system according to any one of claims 8 to 12, wherein the main control unit is further configured to: send N sequential incremental addresses to the storage unit at each clock;

The LTE-based TURBO coding system according to claim 13, wherein the system further includes another N storage units in addition to the N storage units, and the other N storage units and the N storage units. The unit performs a ping-pong operation and simultaneously reads and writes data in the storage unit.

The LTE-based TURBO coding system according to claim 13, wherein when N=8, the initial values stored in the initial value storage unit are: moc J + O , mod(2f ₂ , K) ,

Mod(12Sf ₂ , K); where K is the code block size, 40 ≤ ≤ 61 4 , the parameter; and the value of the sum varies according to the Κ value;

Correspondingly, the recursive calculation subunit is further used to: use a formula: Π '+ 1) = mod ( (n (/) + mod ((mod (/ + f 2, K) + mod (2if 2, K)),)), has passed the delivery body 4 calculates the interleave address [pi ( 1) the value of ~Π( ⁷ );

According to the formula:

Π( + 8) = ιηοά((Π() + moddmodiSf, + 6 f ₂ ,K) + mod(16if ₂ ,K)), K)), Κ) Calculate the interleaved address by recursion Π(8) ~Π(15) value.