WO2010136114A1

WO2010136114A1 - Digital predistorter for rf power amplifiers

Info

Publication number: WO2010136114A1
Application number: PCT/EP2010/002753
Authority: WO
Inventors: Anding Zhu; Lei GUAN
Original assignee: University College Dublin - National University Of Ireland, Dublin
Priority date: 2009-05-29
Filing date: 2010-05-05
Publication date: 2010-12-02

Abstract

A Volterra series-based digital pre-distorter for RF power amplifiers combines look-up-tables and multiplication, along with time division multiplexing to reduce the hardware resources required for implementation.

Description

Digital Predistorter for RF Power Amplifiers

Field of the Invention

The present invention relates to digital pre-distortion, and in particular, to compensate for nonlinear distortion by radio frequency (RF) power amplifiers (PAs).

Background of the Invention

RF power amplifiers are one of the most expensive and most power consuming components in wireless transmitters. To maintain optimum efficiency, PAs are normally operated near saturation, which generates inter-modulation products that interfere with adjacent channels. As wireless communication evolves towards high data-rate and broadband services, RF PAs also often exhibit frequency or history dependent behavior, namely, memory effects, which could sometimes severely degrade the system performance. To obtain high efficiency and simultaneously avoid severe distortion caused by PA nonlinearities, digital predistortion (DPD) techniques along with memory effect compensation methods have been proposed as in: J. Kim and K. Konstantinou, "Digital predistortion of wideband signals based on power amplifier model with memory," Electron. Lett., vol. 37, no. 23, pp. 1417-1418, Nov. 2001 ; M. C. Jeruchim, P. Balaban, and K. S. Shanmugan, Simulation of

Communication Systems, 2nd ed. Norwell, MA: Kluwer, 2000 which introduces Hammerstein and Wiener models; T. Liu, S. Boumaiza, and F. M. Ghannouchi, "Pre-compensation for the dynamic nonlinearity of wideband wireless transmitters using augmented Wiener predistorters," in Proc. Asia- Pacific Microw. Conf. Suzhou, China, Dec. 2005, vol.5, pp. 4-7; and G. Montoro, P. L. Gilabert, E. Bertran, A. Cesari.and D. D. Silveira, "A new digital predictive predistorter for behavioral power amplifier linearization," IEEE Microw. Wireless Compon. Lett., vol.17, no.6, pp.448-450, Jun. 2007 which discloses nonlinear auto-regressive moving average (NARMA) modelling.

The principle of DPD comprises building a nonlinear distortion function within the numerical or digital domain that is the inverse of the distortion function exhibited by the amplifier. A highly linear and low distortion system can be achieved when these two nonlinear functions are serially combined. An attraction of this approach is that the nonlinear PA can be linearized by a standalone add-on block, freeing vendors from the burden and complexity of manufacturing complex analog/RF circuits. However, it can be difficult to obtain an exact inverse function for a PA with memory.

C. Eun and E. J. Powers, "A new Volterra predistorter based on the indirect learning architecture," IEEE Trans. Signal Process., vol. 45, no. 1 , pp. 223-227, Jan. 1997; A. Zhu and T. J. Brazil, "An adaptive Volterra predistorter for the linearization of RF high power amplifiers," in IEEE MTT-S Int. Microw. Symp. Dig., pp. 461-464, May 2002; L. Ding, G. T. Zhou, D. R. Morgan, Z. Ma, J. S. Kenney, J. Kim, and C. R. Giardina, "A robust digital baseband predistorter constructed using memory polynomials," IEEE Trans. Commun., vol. 52, no. 1 , pp. 159-165, Jan. 2004; P. Jardin and G. Baudoin, "Filter lookup table method for power amplifier linearization," IEEE Trans. Veh. Tech., vol. 56, no. 3, pp. 1076- 1087, May 2007; and P. L. Gilabert, A. Cesari, G. Montoro, E. Bertran, and J.-M. Dilhac, "Multi-lookup table FPGA implementation of an adaptive digital predistorter for linearizing RF power amplifiers with memory effects," IEEE Trans. Microw. Theory Tech., vol.56, no.2, pp.372-384, Feb. 2008 disclose "memory" predistorters, which use a closed-loop configuration, e.g., an indirect learning structure or an iterative parameter adaptation mechanism, in which a full loop of up/down conversion and real-time digital signal processing are required. This significantly increases the implementation cost of the system.

A. Zhu, P. J. Draxler, JJ Yan, T. J. Brazil, D. F. Kinball, and P. M. Asbeck, "Open-loop digital predistorter for RF power amplifiers using dynamic deviation reduction-based Volterra series," IEEE Trans. Microwave Theory Tech., vol. 56, no. 7, pp. 1524-1534, July. 2008 (Zhu et al) discloses an open-loop digital predistorter for RF power amplifiers. This DPD approach is derived from the dynamic deviation reduction-based Volterra series disclosed in A. Zhu, J. C. Pedro, and T. J. Brazil, "Dynamic deviation reduction-based Volterra behavioral modeling of RF power amplifiers," IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4323-4332, Dec. 2006. This allows simultaneous compensation for nonlinear distortion and memory effects with a small number of parameters.

Based on the pth-order post-inverse theory, for example, as described in M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems, reprint ed. Malabar, FL: Krieger, 2006, the parameters of this digital predistorter can be directly estimated from the measured input and output of the PA with an offline characterization process. This eliminates the real-time closed-loop adaptation requirement, and removes the necessity to implement the parameter estimation algorithms in real digital circuits, which significantly reduces system complexity and implementation cost.

It is an object of the present invention to provide a low-complexity and low-cost hardware implementation for digital predistortion prior to power amplification.

Summary of the Present Invention

According to the present invention there is provided a digital pre-distorter for processing a baseband I/Q input signal x(«) prior to power amplification by a non-linear power amplifier, to produce a predistorted signal u («) according to the model: ύ{ή) = M₁ («) + U₂ (ή)

M M

= ∑C, (n)x(n - 0 + ∑ C,_,2 (n)x² (n)x (n - i) ι=0 1=1 where

and where P is an order of amplifier non-linearity modeled by said pre-distorter; M represents the extent of memory exhibited by said amplifier; x'(n) comprises a complex conjugate of said input signal jc(n) ; and g_{2k+] j}(.) are sequences of parameters calculated for each memory state and nonlinear order of said amplifier, said pre-distorter comprising: respective look-up tables storing values for components C₁ ,(«) and C_{1 2} («) for each memory state M of said amplifier, said tables being addressed according to at least a magnitude of said input signal x(n) , a multiplier for multiplying the values for each of the memory components, C₁. , (n) by said, input signal 3c(«) and an adder to sum said multiplied values to produce a signal «,(«) ; a multiplier for multiplying the values for each of the memory components! C_{1 2}(n) by said complex conjugate signal x («) and an adder to sum said multiplied values; a multiplier for multiplying said multiplied sum of components C_{1 2}{n) by a squared value of said input signal to produce a signal U₂ (n) ; and an adder to sum a delayed value of said signal «,(«) and said signal S₂ (n) to produce said predistorted signal u («) .

Embodiments of the invention provide a Volterra series-based digital predistorter for RF power amplifiers by combining look-up-tables and multiplication, along with time division multiplexing to reduce the hardware resources required for implementation.

Preferably, said pre-distorter is arranged to time division multiplex said input signal x(n) according to the number of memory states M modeled by said pre-distorter, and to sequentially select said look-up tables during each time divided sub-cycle of said input signal, said pre-distorter including a respective multiplexer operable with the look-up tables for each set of components C₁ , («) and C_{1 2} («) to conduct said multiplications for each memory component through a single multiplier during successive sub-cycles of said input signal and to sum said multiplications for a cycle of said input signal. Preferably, said pre-distorter can also be arranged to deal with an input signal x(«) over-sampled by a factor N and to interpolate said values for components C₁ ,(«) and C_{1 2}(n) from said look-up tables.

Since field programmable gate-array (FPGA) has many advantages in digital signal processing, including high density integration, parallel operation mechanism, high speed processing, and easy implementation, FPGA has become one of main choices for implementing baseband digital predistorters for RF power amplifiers. In preferred embodiments, the invention is implemented in an FPGA chip. However, the invention is not limited to FPGAs and the structure of the invention can also be readily implemented in other types of digital circuits, e.g., general digital signal processing chips.

Brief Description of the. Drawings

Embodiments of the. invention will now be described, by way of example, with reference to the accompanying drawin&o, ... which:

Fig.1 shows an example of LUT contents for a digital pre-distorter (DPD) according to an embodiment of the prqsent invention;

Fig. 2 shows a simple DPD implementation;

Fig. 3 shows time multiplexing for multiplication operations used within a DPD according to an embodiment of the present invention;

Fig. 4 shows a DPD implementation according to an embodiment of the present invention;

Fig. 5 shows two approaches to complex multiplication for use within a DPD of the present invention;

Fig. 6 shows an experimental test bench for obtaining model parameters for use within a DPD according to an embodiment of the present invention; and Fig. 7 shows spectra plots of a system with and without digital pre-distortion.

Description of the Preferred Embodiments

In Zhu et al referred to above, a DPD model was derived from the following dynamic deviation reduction-based Volterra series:

^•A_J,_i,(0^,-^,0^^,-^,i _r)π^jc(»-';)]}

J⁼^ Equation 1

where x(n) and y(n) are the input and the output, respectively of a power amplifier. P is the order of nonlinearity and M represents memory length. In this representation, the input elements are organized according to the order of dynamics involved in the model. A variable, r, is introduced to represent the order of the dynamics, and h_{p r}(0,...,0,i_},...,i_r) is the Volterra kernel with pth-order nonlinearity and rth-order dynamics. Because the effect of dynamics tends to fade with increasing order in many real power amplifiers, the high-order dynamics can be removed by setting the value of r to a small number, which leads to a significant simplification in model complexity.

This truncated model in the low-pass equivalent format can be directly adopted to represent the DPD function because digital predistorter often only needs to compensate static nonlinearities and low- order dynamics, which are the dominant distortion induced by the PA. For instance, the 1st-order dynamic truncation of the baseband Volterra model in the discrete time domain can be written as:

Equation 2

where x(«) and u («) are the input and the output I/Q envelopes, respectively of the DPD; iWi _j (•) '^s *^ne complex Volterra kernel of the DPD; (.)^* represents the complex conjugate operation; and |.| returns magnitude. Note that only odd order nonlinearities are included in the representation in equation (2), i.e., P is an odd number, since the effects from even order kernels can be omitted in a band-limited modulation system.

Direct implementation of the DPD function of equation (2) requires a large number of multipliers and adders to obtain the nonlinear and memory terms, for example, 60 multipliers are needed when P=5, M=3. This number increases significantly when P and M become larger. Since a multipliers is one of the most complex and expensive components in FPGA hardware, a large number of multipliers dramatically increases the complexity and the cost of the DPD.

In equation (2), multiplication operations are normally needed to produce the power terms of the signal, e.g.

■ One way to reduce the complexity for implementing the nonlinear terms is to use a LUT instead of using multiplication. Generally, in a LUT approach, a set of .values of the magnitude of x(n) and its. power terms, e.g. ,:..x(«)| , k = 0,1 ,... (P-1 )/2, can be calculated in advance and stored.in the table indexed by the magnitude \x(n)\ when the range of the signal values are known. For example, if the input magnitude is normalized to one and the LUT size is 1024, the interval value for the LUT, Δ, will

be 1/1024. A set of values of |3c(n)| can be calculated, e.g., 1 , 4Δ², 8Δ², ..., for

, and 1, 16Δ⁴,

64

value of these power terms can be retrieved quickly from the table later, without conducting complex computational operations, which significantly saves the hardware resources.

However, this LUT mapping method has two major disadvantages:

(1 ) a large memory is required to store sufficient data, e.g., separate tables are required to store different orders of power terms, and to maintain high precision signal processing, large tables are needed to cover wide ranges of high order nonlinear terms; and

(2) the memory terms and the coefficients of the DPD must be built in separately using multiplication.

In one embodiment of the present invention, LUTs are built by combining the power terms of the magnitude, 3c(«)j with the coefficients g_{2M y}(.) - So referring back to equation (2), since the g_{lk+λ J}{.) coefficients can be known in advance after the model extraction, if the terms of the DPD function are re-grouped, equation (2) can be re-cast as: u(n) = u_] (n) + ιι.,(n)

= C_{l 2}(n)x² (n)x (n -i)

Equation 3 where p-\

V"¹ ~ / -N I ~ / N |2A

C,,! (») = ∑ g2k₊i,i (0 |^(^w)|²* Equation 4

A=O

Q₂(O = ∑ #2A_÷i,2 (0 |^(«)r^(A~1} Equation 5

or Ci,₂(n) now only depends on the magnitude of x(ή) since

O^') or g_{2k+l 2}(j) can be considered as a constant to each power term of x(n)\ , when i is fixed and M represents 1he memory length. In other words, for a given i, C

i₁^n) and can be considered as a complex gain to 3c(« -/) and 3c^* (n - i) , respectively. Therefore,

and C,_;2(n) can be calculated for each x(n) value in advance and stored in look-up tables. These values can be retrieved directly from the tables and multiplied with x(n -i) and x^*(n - i) terms to produce the DPD output. For example, if the LUT size is 1024 and the input magnitude is normalized to 1 , for i=2, C_2;1(n), can be obtained as shown in Fig. 1.

In the same way, separate tables can be built for different memory terms for Ci₁₁ and Ci_>2, where i=0,

1 M. This LUT mapping approach is more efficient than the basic approach outlined in relation to equation (2), since it does not require multiplication of the coefficients and input data any more, and this structure also eliminates the requirement for building separate tables for each nonlinear power terms. As a result, hardware resources are significantly saved.

The values for the Cj₅J and C;_;2 can be calculated off-line to a required precision using a software simulation tool such as MATLAB. The final results of these values are lower in precision than required for the intermediate terms of equation (2), and can be scaled to suit a small LUT size. Therefore, significant memory storage can be saved.

It will be seen from equation (3), for u_λ(ή) , only the memory terms are separated out and all other terms are built into the LUT; while for u₂(ή) , x² (n) is left outside the table along with the conjugated memory terms. This is because, typically a LUT can only deal with one-to-one mapping, from address to location, but cannot handle one-to-multiple mapping. In other words, one input value only can be used to retrieve one output value, namely, one address should only be pointed at only one location. In this application, the input x(n) is a complex number including I and Q values, but the LUT address is generated from the magnitude only. With the same magnitude value, the power term x²(n) can have different values, which means that one address can correspond to multiple output values. To avoid this problem, x² (ή) is left outside the LUT, as shown in equation (3), although this requires two more multipliers to implement the system.

The next step of the implementation is to include the memory terms, i.e., 3c(« -/) and x^*(n - i) , and the term left outside the LUTs, x² (n) .

One solution is to multiply the values retrieved from the LUTs with these terms using multipliers. For example, an implementation of the first part of the output w, (n) is shown in Fig. 2, where it can be seen that with time delay units, multipliers and adders, M₁ (n) can be generated.

The implementation shown in Fig. 2 provides a dramatic reduction in complexity cost compared to normal analytical function based DPDs and conventional LUT approaches. However, this structure is not the simplest one because a number of multipliers are still involved, e.g., M+1 multipliers are required if the memory length is M.

To further reduce complexity, time-division multiplexing is used as described below.

As shown in Fig. 3, where TSi is the ith time slot, and Oi represents the ith multiplication operation, in Fig. 2, multipliers are operated in parallel and each operation occupies a whole time slot. However, by dividing a time slot into three sub-time slots and conducting the multiplication for each input within respective sub-time slots, the three multiplications can be conducted by using one multiplier.

Referring to Figure 4, in one implementation employing time-division multiplexing, the original data is up-sampled and a multiplexer is used to redistribute the data before conducting the multiplication operations serially. At the end of operations, the output data are recombined and down-sampled back to the original sample rate to produce the final output. So referring to the components in more detail:

Input Up-sampling 40 increases the operating frequency by (M+1 ) times with data repeating units, i.e., the input data are repeated (M+1) times at a higher sampling rate. Input Magnitude Calculation 42, 62: In one implementation, the CORDIC algorithm is used to calculate the magnitude of input complex I/Q data, and this is used in conjunction with a selection signal CS as the address for the LUTs 44,64.

LUT Mapping: separated LUTs are mapped into different parts of a standalone RAM so that indexing the contents is easier; the LUTs parts are indexed with the magnitude of respective input signals and the CS signal. This saves hardware cost for implementing addressing buses. Each LUT contains two parts, one for storing the real part of the coefficients and the other for the imaginary part. Nonetheless, it is appreciated that the addressing control buses for indexing the LUTs increase with memory length and this increases the hardware cost.

Data Multiplexing 46,66: in one implementation, these parts each contain a multiplexer with M delay units and each unit delays M+1 time cycles, and a selection signal CS. This structure converts parallel multiplications using multiple multipliers to serial operations sharing only one multiplier. For example, for M=2, the number of LUTs will be 3, and the number of delay blocks in the pipeline structure will be 2. Table 1 shows the data flow for'the structure shown in Fig. 4 for determining u_x(n) , where T represents the number of time cycles, x₀ (n) , x, (») and X₂ («) are the 3 up-sampled inputs sequences of the MUX, and x_out(n) is the output sequence of the MUX. Cj_)n represents the content¹. value stored in the LUTs Cy, i=0, 1 , 2, and C_out(n) is the pipelined output of the three LUTs, selected by the selection signal CS, which rotates as 0, 1 , 2, 0, 1 , 2,...; and z(n) is the output sequence obtained from multiplying x_ou/(«) and C_out(n) and corresponding with S₁ («) . (The structure for determining U₂ (n) can be implemented similarly.)

Table 1

As Table 1 shows, by using the MUX, the original low speed input sequence x(ri) is converted to the high speed sequence x_out (n) . In x_out(n) , samples in the original data x(n) appear sequentially every M+1 time cycles followed by M previous samples. With the common selection signal CS, synchronized values retrieved from LUTs are sent to C_out(n) and multiplied with x_out(n) to produce z(n). Since the inputs of multiplier include repeated pipeline elements, the output of multiplier, z(n), also has repeated pipeline elements.

Complex Multiplication: the ® in Fig. 4 represents complex multiplication (CM), which is used to conduct multiplication between x_mU(ri) and C_out(n). The complex multiplication operations can be carried out using real multiplications as: d = a ®b

= (a, + ja_q)(b, + jb_q) ÷ lafφ. -bj + b -a,)] *

where a, b and d are complex I/Q numbers, and i and q represent in-phase and quadrature parts, respectively. The operation in equation (6) can reduce by 25% the number of multipliers compared to normal CM operations, as illustrated in Fig. 5, where (a) is a normal structure; and (b) is the improved structure from equation (6). Since multipliers are much more complex and expensive than adders, the implementation of Fig. 5 (b) is simpler and cheaper than the one in Fig. 5(a).

Output Accumulation 48,68 is used to implement the accumulation (ACC) operation which is used to compensate for the memory effects distortion. The output of z<j(n) can be obtained from the following equation: z_d («) = z(n) + z(n - 1) + ... + z(n - M) Equation 7

Among the outputs of Z_d(n), there are two types of output values: one is the results directly used by u_λ {n) and M₂ (w) and the other is the intermediate results in process which are prepared for calculating u_x(n) and M₂ (H) for the next time cycle.

Output Down-sampling 70: not all the values of Z_d(n) are useful for producing the final output of the DPD; some values are just the intermediate processing results which can be discarded. The output M₁ (n) and M₂ (w) is only obtained from every M+1 time cycles in the serial data sequences. Thus, a down-sampling block 70 is employed to conduct such "selection". As illustrated in Table 2, for M₁ (H) , every M+1 time cycles, one value of za(n) is chosen as the output of M₁(H) , which is indicated by the time slots T_{r M} . A similar scheme can be employed for u₂(n) .

Table 2

With the above parts together, and with delays (to compensate processing delays between two branches), represented by Block z^:N1, the output can be produced as shown in Fig. 4. In this structure, only four complex multipliers are required. Unlike the structure in Fig. 2, the number of multipliers used does not increase with the memory length. This significantly reduces the cost of the system, especially for the systems with long term memory effects and with a large number of memory taps.

In order to further reduce the system complexity, under-sampling and interpolation can be used, as shown in Zhu et al. Here, the original input and output signals are sampled with a low sampling rate (much lower than the Nyquist rate) at the model extraction stage, while the input signal is then up- sampled and the parameters are interpolated by inserting zeros to avoid aliasing effects at the implementation stage. As such, the final DPD function becomes:

P-I

M κ (^Λ) = ∑ ∑ #2*₊i,i (0 |*(»)| x(n - ix N)

Ic=O J=O

Equation 8 (n)^jT (n-ix N)

where jc(rc) is the over-sampled input, and «(«) the new output of the DPD. N is the ratio of the sampling rate required for DPD output signal reconstruction versus that of the under-sampled model extraction data. Equation (8) can be implemented within the structure of Figure 4, where the multiplexing parts 46,66 are changed so that the number of delays is changed from M+1 to (M+1 )*N.

In order to validate the proposed DPD implementation, an experimental test bench as shown in Fig. 6 is used. The core digital predistortion algorithm is implemented in a Xilinx XC4VSX35 FPGA chip. The PC/MATLAB part generates the original WCDMA test data and receives the predistorted data generated by the FPGA. The model parameter extraction is also conducted in MATLAB. The RF chain set-up is the same as that presented by Zhu et al, where the baseband I/Q signal is first modulated to a digital intermediate frequency (IF) and fed to the Agilent Pattern Generator, and then converted to the analog domain and up-converted to the RF band, and finally sent to the power amplifier. To capture the output data, the output of the PA is first down-converted to the IF band, and then converted to the digital domain and captured by the Logic Analyzer, and finally demodulated to the baseband in MATLAB.

To evaluate the system performance, around 10,000 I/Q samples were recorded with a sampling rate at 15.36 MHz, i.e., four'samples per chip. After time alignment and normalization, 2,000 samples were used for parameter extraction, while the remaining 8,000 different samples were used for system performance evaluation in separated measurements. To avoid aliasing in the final system, the original input signal was over-sampled by a factor of seven, i.e., with a sampling rate at 107.52 MHz₁ or N=7 in Equation (8). The power amplifier under test was a high power Gallium Nitride (GaN) amplifier operated at 1.94 GHz, and excited by a WCDMA signal with a chip rate at 3.84 MHz and with 9.57 dB PAPR.

The nonlinearity order P was chosen as 7 and memory length M=4. There were 32 parameters in total. It required four complex multipliers (one for the first part and three for the second part) and nine LUTs (five for C_{1 1} and four for C_I>2) to implement the DPD function of equation (8). The size of the LUTs was 1024, and each LUT had 32-bit storage capacity, in which low 16-bit for the real part values and high 16-bit for the imaginary part. The import and export dual data port RAMs also were 32-bit in width and 8640 in size. For system validation, the data processed by FPGA was captured from the hardware platform and compared results calculated in an ideal software environment e.g. MATLAB. The normalized processing error is in the order of 10^" , which indicates the FPGA hardware implementation produces a very high precision for the signals. For example, Fig. 7 shows the frequency domain spectra of the PA output with and without DPD, where it can be seen that the nonlinear distortion is almost completed removed by employing the DPD. Other performance characteristics expected of the hardware implementation of the DPD can be seen in Zhu et al.

For comparison, two other DPD structures were also implemented: Scheme 1 (S1 ) is a direct structure, in which the DPD function is directly implemented by using the multipliers and adders. Scheme 2 (S2) is the structure as shown in Fig. 2, in which the coefficients and nonlinear power terms are built into LUTs while the memory terms are implemented by using multipliers. The structure in which the coefficients and nonlinear power terms are built into LUTs while the memory terms are implemented by using shared multipliers with time-division multiplexing according to the embodiment described above is referred to as Scheme 3 (S3).

P=5,M=2 P=7,M=2 P=7,M=4

LUT LUT LUT

S l 27 12 0 39 17 0 65 31 0

S2 8 8 14 8

S3 8

Table 3

The hardware utilization for different nonlinear order and memory lengths for three schemes are shown in Table 3, where <8> , θ and LUT means complex multipliers, two-input adders and look-up- tables, respectively. It can be clearly seen that the cost of Scheme 1 is highest and the complexity increases significantly with nonlinear order and memory length increase. The number of multipliers is reduced in Scheme 2, but it still increases with the memory length. Scheme 3 uses fewer resources and the number of multipliers is the same for all system with different nonlinear orders and memory length, which gain significant benefit when the nonlinear order and memory length increase.

The resource utilization difference between three schemes becomes more evident when implementing this DPD in an FPGA board. Table 4 shows the FPGA resource utilization in implementing the three schemes for the nonlinear order P=7 and memory length M=4.

Table 4

Claims

Claims:

1. A digital pre-distorter for processing a baseband I/Q input signal x(n) prior to power amplification by a non-linear power amplifier, to produce a predistorted signal ϋ(n) according to the model: ύ(n) = «,(«) + ύ₂ (n)

= C_{1 2} (n)x² (n)x (n - 1)

where

C_M(») =

and where

P is an order of amplifier non-linearity modeled by said pre-distorter; M represents the extent of memory exhibited by said amplifier; comprises a complex conjugate of said input signal x(n) ; and

§_{2k+\ j} (•) ^are sequences of parameters calculated for each memory state and nonlinear order of said amplifier, said pre-distorter comprising: respective look-up tables (44,64) storing values for components C₁ , («) and C_{1 2} (n) for each memory state M of said amplifier, said tables being addressed according to at least a magnitude of said input signal x(n) , a multiplier for multiplying the values for each of the memory components C₁ , («) by said input signal x(n) and an adder (48) to sum said multiplied values to produce a signal M, (H) ; a multiplier for multiplying the values for each of the memory components C_{1 2} (n) by said complex conjugate signal

and an adder (68) to sum said multiplied values; a multiplier for multiplying said multiplied sum of components C_{1 2} (n) by a squared value of said input signal to produce a signal U₂ (n) ; and an adder to sum a delayed value of said signal ύ_x {ή) and said signal ϊi₂(ή) to produce said predistorted signal M^H) .

2. A pre-distorter according to claim 1 arranged to time division multiplex (40) said input signal x(n) according to the number of memory states M modeled by said pre-distorter, and to sequentially select said look-up tables during each time divided sub-cycle of said input signal, said pre-distorter including a respective multiplexer (46,66) operable with the look-up tables for each set of components

C₁ ,(«) and C, ₂ {ή) to conduct said multiplications for each memory component through a single multiplier during successive sub-cycles of said input signal and to sum said multiplications for a cycle of said input signal.

3. A pre-distorter according to claim 1 arranged to receive an input signal x(n) over-sampled by a factor N and to interpolate said values for components C₁ , («) and C_{1 2} («) from said look-up tables.

4. A pre-distorter according to claim 1 implemented in one of an FPGA chip or a general purpose-digital signal processing chip.