WO2010131104A2

WO2010131104A2 - Method and device for controlling power-on of a processing circuit

Info

Publication number: WO2010131104A2
Application number: PCT/IB2010/001099
Authority: WO
Inventors: David Jacquet; Olivier Schneider
Original assignee: Stmicroelectronics (Grenoble 2) Sas
Priority date: 2009-05-15
Filing date: 2010-05-12
Publication date: 2010-11-18
Also published as: WO2010131104A3

Abstract

The present invention relates to a method for controlling the activation of a circuit (PRCU) clocked by a clock signal (CLK), the method comprising a phase of activating the circuit comprising simultaneous steps of increasing a supply voltage (Vs) of the circuit until a nominal supply voltage is reached, and of increasing a frequency of the clock signal until a nominal frequency is reached, the circuit being configured for operating within a certain range of supply voltage values and a certain range of clock signal frequencies below the nominal supply voltage and the nominal frequency.

Description

METHOD AND DEVICE FOR CONTROLLING POWER-ON OF A

PROCESSING CIRCUIT

The present invention relates to controlling power on of all or part of an integrated circuit. The present invention can be applied to any integrated circuit clocked by a clock signal, and particularly to microprocessors, microcontrollers or more specialized units such as memory or peripheral unit control units.

As a result, in particular, of the fact that such integrated circuits are integrated into increasingly miniaturized embedded systems, it has become essential to reduce the power consumption of these circuits. One technique for reducing the power consumption of an integrated circuit includes temporarily powering off all or some parts of the circuit that are temporarily not used, while the other parts of the system are active and therefore powered on. In classic integrated circuits, a circuit is only reactivated when the supply voltage of the circuit has reached its nominal value. It is indeed necessary to wait for the supply voltage of the circuit to stabilize before activating the circuit, i.e. applying a clock signal to it. The rise in the supply voltage generally causes an overvoltage followed by oscillations of decreasing amplitude. The faster the rise in the voltage, the higher the overvoltage. It is not therefore possible to reduce the time for reactivating a circuit, by reducing the supply voltage rising time. The time for reactivating a circuit is thus currently about one hundred microseconds. In a system clocked at 500 MHz, this reactivation time corresponds to 50,000 clock cycles, and therefore to as many instructions which could have been executed.

The deactivation of a circuit in an integrated circuit can therefore raise response time-related problems particularly in real-time systems. If the time required for the circuit reactivation is too long, it may then be impossible to. temporarily deactivate it. The longer the reactivation time, the less it is possible to deactivate a circuit in a system. Certain circuits must be reactivated when an event occurs, for example to receive data coming from a peripheral unit. If the circuit is not reactivated sufficiently quickly to empty a memory of the peripheral unit, it can be necessary to increase the memory capacity of the peripheral unit.

It can therefore be desirable to reduce the time for reactivating a circuit which has been deactivated to reduce the power consumption. One embodiment relates to a method for controlling the activation of a circuit clocked by a clock signal. According to one embodiment, the method comprises a phase of activating the circuit comprising simultaneous steps of increasing a supply voltage of the circuit until a nominal supply voltage is reached, and of increasing a frequency of the clock signal until a nominal frequency is reached, the circuit being configured for operating within a certain range of supply voltage values below the nominal supply voltage and a certain range of clock signal frequencies below the nominal frequency.

According to one embodiment, the supply voltage and the frequency of the clock signal are increased continuously or by successive stages. According to one embodiment, the method comprises a phase of deactivating the circuit comprising simultaneous steps of progressively decreasing the supply voltage of the circuit until a minimum supply voltage is reached, and of progressively decreasing a frequency of the clock signal until a zero frequency is reached. According to one embodiment, the supply voltage and the frequency of the clock signal are decreased continuously or by successive stages.

According to one embodiment, the minimum supply voltage is zero or equal to a retention voltage corresponding to a minimum value enabling the states of flip-flops and/or registers and/or memory cells of the circuit to be maintained.

According to one embodiment, the phase of activating and/or deactivating the circuit comprises steps of making the circuit go through different operating points, each operating point being defined by a supply voltage and a clock signal frequency of the circuit. According to one embodiment, the method comprises a step of selecting a set of operating points to activate and/or deactivate the circuit according to an operating parameter of the circuit resulting from a measurement taken during a test phase of the circuit or during normal use of the circuit. According to one embodiment, the phase of activating the circuit comprises a step of applying a bias voltage for biasing a substrate on which the circuit is formed.

Another embodiment relates to a device for controlling the activation of a circuit, configured for implementing the method as previously defined.

According to one embodiment, the device comprises a clock circuit supplying the circuit with the clock signal, the clock circuit being controlled to increase the frequency of the clock signal during a phase of activating the circuit, and/or decreasing the frequency of the clock signal during a phase of deactivating the circuit.

According to one embodiment, the clock circuit comprises a phase locked loop supplying a frequency divider supplying the clock signal with a constant frequency signal, the frequency divider being controlled to adjust the frequency of the clock signal successively to the frequency of operating points of the circuit during the phase of activating and/or the phase of deactivating the circuit.

According to one embodiment, the clock circuit comprises a fractional phase locked loop supplying the circuit with the clock signal, the fractional phase locked loop being controlled to adjust the frequency of the clock signal successively to the frequency of operating points of the circuit during the phase of activating the circuit and/or the phase of deactivating the circuit.

According to one embodiment, the device comprises a power supply circuit supplying the circuit with a supply voltage, the power supply circuit being controlled to increase a supply voltage of the circuit during a phase of activating the circuit, and/or to decrease the supply voltage of the circuit during a phase of deactivating the circuit.

According to one embodiment, the power supply circuit is configured for adjusting the supply voltage of the circuit successively to the voltage of operating points of the circuit during the phase of activating and/or the phase of deactivating the circuit.

Another embodiment relates to a portable item of equipment comprising a device as previously defined. Some examples of embodiments of the present invention will be described below in relation with, but not limited to, the following figures, in which:

- Figure 1 schematically represents a system comprising a control circuit for controlling supply and clock circuits in a processing circuit, according to one embodiment,

- Figure 2 schematically represents a system comprising a control circuit for controlling supply and clock circuits in a processing circuit, according to another embodiment, - Figures 3A to 3C represent timing diagrams of signals in the system in Figure 1 or 2.

Figure 1 represents a system comprising a circuit such as a processing circuit or data storage circuit PRCU, supply circuits SMPS and LDO and a clock circuit COSC. The circuit PRCU is powered by the supply circuits SMPS and LDO and clocked by a clock signal CLK supplied by the clock circuit. The circuit SMPS supplies the circuit PRCU with a supply voltage Vs. The circuit LDO supplies voltages Vbbp and Vbbn for biasing the substrate on which the circuit PRCU is formed. The voltages Vbbp and Vbbn are slightly positive or negative according to the performances of the circuit PRCU. The circuit SMPS can for example comprise a switched-mode power supply circuit. The circuit LDO can for example comprise a series regulator.

According to one embodiment, the clock circuit COSC and the supply circuits SMPS and LDO are controlled by a circuit RMPGEN to increase the frequency of the clock signal CLK and simultaneously the supply voltage Vs when the circuit PRCU is activated, from a minimum voltage and a zero frequency, until a nominal voltage and a nominal clock signal frequency are reached.

Therefore, upon a reactivation, the circuit PRCU can instantly start to execute instructions, before the voltage reaches its nominal value, even if all the processing power of the circuit is not immediately available.

According to one embodiment, the clock circuit COSC and the supply circuits SMPS and LDO are controlled by the circuit RMPGEN to also decrease the frequency of the clock signal CLK and simultaneously the supply voltage Vs when the circuit PRCU is deactivated, until a zero clock signal frequency and a minimum supply voltage are reached.

Therefore, upon a deactivation, the circuit PRCU can continue to execute instructions for a certain time until the frequency of the signal CLK changes to 0, without consuming any additional energy. Indeed, in the event that the power supply is cut off, the power supply circuit disperses the energy accumulated particularly in the stray capacitances of the circuit PRCU.

The circuit RMPGEN receives an activation or deactivation control signal SL and is configured for activating or deactivating the circuit PRCU by controlling the circuits COSC, SMPS and LDO further to a change of state of the signal SL. The voltages Vbbp and Vbbn may be applied to the circuit PRCU only during the periods when the latter must be active.

The minimum supply voltage of the circuit PRCU can be zero or chosen equal to a retention voltage enabling the states of flip-flops, and of any registers and memory cells of the circuit PRCU, to be maintained. The increase and decrease in the frequency of the clock signal CLK and in the supply voltage Vs can be performed gradually and continuously or by stages.

Figure 2 represents a system that differs from the one represented in

Figure 1 in that the clock circuit COSC comprises a phase locked loop circuit PLL generating a clock signal at the frequency F and a frequency divider DIVN, the division ratio N of which is controlled by the circuit RMPGEN. The frequency of the clock signal supplied to the circuit PRCU is equal to F/N. The circuit RMPGEN also controls switches INT to increase or decrease, by stages, the supply voltage Vs supplied by the power supply circuit SMPS. The clock circuit COSC can also be produced by a fractional phase locked loop (fractional PLL) classically comprising a frequency divider, and a sigma-delta modulator integrated into a return loop of the frequency divider. Such an oscillator can generate different frequencies spaced out from one another by a very fine pitch. Figures 3A to 3C represent timing diagrams of the activation/deactivation control signal SL of the circuit PRCU, of the clock signal CLK, and of the supply voltage Vs. In Figure 3A, the signal SL changes, for example, to an active state at an instant t1 , to deactivate the circuit PRCU, and changes to an inactive state at an instant t6 to reactivate the circuit PRCU. In Figure 3B, the frequency of the clock signal CLK decreases during a deactivation phase as from the instant t1 , to change from a nominal frequency F5 to a zero frequency, by passing through successive intermediate stages F4 at the instant t2, F3 at the instant t3, F2 at the instant t4, then F1 at the instant t5.

During an activation phase as from the instant t6, the frequency of the signal CLK increases to change from a zero frequency to the nominal frequency F5, by passing through the successive intermediate stages F1 at the instant t7, F2 at the instant t8, F3 at the instant t9, then F4 at the instant t10.

In Figure 3C, the supply voltage Vs of the circuit PRCU (curve C1 ) changes from a nominal voltage V5 to a voltage V4 at the instant t1 , then successively to voltages V3 at the instant t2, V2 at the instant t3 and V1 at the instant t4 to reach a zero voltage at the instant t5. At the instant t6 when the circuit PRCU is reactivated, the supply voltage Vs changes from a zero voltage to the voltage V1 , then successively to voltages V2 at the instant t7, V3 at the instant tδ and V4 at the instant t9, to reach the nominal voltage V5 at the instant t10.

Before the instant t1 , the circuit PRCU operates at rated capacity. Between the instants t1 and t5, the current consumption of the circuit PRCU is reduced insofar as the latter essentially consumes the energy that is usually dispersed in the supply circuits when the electrical power supply is cut off. During the period when the frequency of the signal CLK is zero between the instants t5 and t6, the circuit PRCU is inactive and consumes no current. The circuit PRCU starts to be active, for example it executes instructions, from the instant t6, and reaches its rated capacity at the instant t10.

During the activation (between the instants t1 and t5) and deactivation (between the instants t6 and t10) phases, the circuit PRCU successively goes through operating points (V1 , F1 ), (V2, F2), (V3, F3), (V4, F4) and (V5, F5), each being defined by a pair (voltage, frequency). The number of operating points through which the circuit PRCU goes during an activation or deactivation phase can be in the order of about ten or twenty, for example 16. It will be understood that the circuit PRCU must be configured for operating correctly in the vicinity of each of these operating points. The circuit PRCU can also be configured for operating correctly between the voltage values V1 and V5 and between the frequencies F1 and F5. For this purpose, buffers can be added in the circuit to ensure that a signal is maintained long enough at the input of each flip-flop of the circuit to be taken into account by the flip-flop.

Figure 3C also represents a curve C2 of the variation of the voltage Vs when the latter suddenly changes from 0 to the nominal voltage V5. The curve C2 shows that the voltage Vs has an overvoltage extending after the voltage V5, followed by dampened oscillations which substantially disappear as from the instant t10, i.e. at the same time as the circuit PRCU is fully operational.

It should be noted that if a reactivation event of the circuit PRCU occurs between the instants t1 and t5, the circuit PRCU can be immediately reactivated, which is not possible if the supply voltage Vs suddenly increases to the nominal supply voltage V5 (curve C2).

The operating points (V1 , F1 ), (V2, F2), (V3, F3), (V4, F4) and (V5, F5) - referred to below as (Vi, Fi) - can vary from one circuit to another due to variations in conditions during the manufacturing of integrated circuits, and the circuit RMPGEN can access a table storing several sets of operating point values for circuits of different qualities. By giving a quality level to each circuit during a test phase, the circuit RMPGEN can select a set of operating points in the table. The circuit RMPGEN can be configured for reading the values of a set of operating points corresponding to the quality level of the circuit PRCU and for controlling the circuits SMPS and COSC to successively apply to the circuit PRCU the voltage and frequency values read in the table. In this way, the different operating points through which the circuit PRCU goes can be adjusted to the quality thereof. The circuit LDO can be configured for maintaining the bias voltages

Vbbn and Vbbp applied to the substrate of the circuit PRCU so that the differences Vs-Vbbp and GND-Vbbn are constant (GND being the voltage of the circuit ground). Therefore, a pair of values of the differences Vs-Vbbp and GND-Vbbn can be provided when the circuit is inactive -i.e. when the frequency of the clock signal CIk is zero- to minimize leakage currents in the circuit and a pair of values of these differences can be provided as soon as the frequency of the clock signal CIk received by the circuit PRCU is nonzero. A pair of values of the differences Vs-Vbbp and GND-Vbbn can also be provided during the transient phases in which the frequency of the clock signal CIk changes from 0 to its nominal value, and/or from its nominal value to 0, to maximize the frequency of the clock signal at each operating point (Vi, Fi) of the circuit, possibly at the expense of significant leakage currents. Indeed, significant leakage currents during the transient phases only do not greatly penalize the current consumption of the circuit. The bias voltages Vbbn and Vbbp for biasing the substrate, applied to the circuit PRCU can also be defined depending on the quality of the integrated circuit. Out of a production of integrated circuits, certain integrated circuits are more efficient insofar as they can operate with a high clock frequency, but their leakage currents are generally high as well. However, the least efficient circuits (which are capable of operating only with a lower clock frequency) have fewer leakage currents. The bias of the substrate enables an efficient circuit to be brought down to an average level and therefore its leakage currents to be reduced by applying a slightly positive or negative bias voltage to the substrate of the circuit. The quality of a circuit can also vary with time particularly depending on the ambient temperature or the ageing of the circuit. The integrated circuit can comprise operation monitoring cells produced with transistors identical to those of the integrated circuit to age in the same way as the other circuits of the integrated circuit. For example, these monitoring cells perform functions of oscillators the oscillation frequency of which varies as the cells age. The quality of the integrated circuit can thus result from a measurement of the drift in the oscillation frequency of these cells, taken during the normal use of the circuit.

It will be understood by those skilled in the art that various alternative embodiments and various applications of the present invention are possible. In particular, the present invention is not limited to the embodiments described and extends to all the embodiments enabling a circuit to be supplied with a voltage and a clock signal, with an increasing supply voltage and an increasing frequency signal during the activation of the circuit, and possibly a decreasing supply voltage and a decreasing frequency signal during the deactivation of the circuit. The present invention is not limited either to the embodiments in which the supply voltage and the frequency of the clock signal decrease gradually or by successive stages during a phase of deactivating the circuit. Indeed, the frequency of the clock signal and the supply voltage of the circuit can be put to 0 suddenly, without this penalizing the current consumption, or being detrimental to the circuit.

The present invention is not limited either to circuits requiring the substrate to be biased. The power supply circuit LDO supplying the bias voltages for biasing the substrate is then not necessary. Depending on the case, and particularly depending on the manufacturing technology and the integration level, all or part of the circuits LDO, SMPS, RMPGEN, COSC and PRCU can be produced or not in a same integrated circuit.

Claims

1. A method for controlling the activation of a circuit (PRCU) clocked by a clock signal (CLK), characterized in that it comprises a phase of activating the circuit

(PRCU) comprising simultaneous steps of increasing a supply voltage (Vs) of the circuit until a nominal supply voltage (V5) is reached, and of increasing a frequency of the clock signal (CLK) until a nominal frequency (F5) is reached, the circuit being configured for operating within a certain range of supply voltage values (V1-V5) below the nominal supply voltage and a certain range of clock signal frequencies (F1-F5) below the nominal frequency.

2. Method according to claim 1 , wherein the supply voltage (Vs) and the frequency of the clock signal (CLK) are increased continuously or by successive stages.

3. Method according to claim 1 or 2, comprising a phase of deactivating the circuit (PRCU) comprising simultaneous steps of progressively decreasing the supply voltage (Vs) of the circuit until a minimum supply voltage is reached, and of progressively decreasing a frequency of the clock signal (CLK) until a zero frequency is reached.

4. Method according to claim 3, wherein the supply voltage and the frequency of the clock signal are decreased continuously or by successive stages.

5. Method according to claim 3 or 4, wherein the minimum supply voltage is zero or equal to a retention voltage corresponding to a minimum value enabling the states of flip-flops and/or registers and/or memory cells of the circuit (PRCU) to be maintained.

6. Method according to one of claims 1 to 5, wherein the phase of activating and/or deactivating the circuit (PRCU) comprises steps of making the circuit go through different operating points (V1.F1 ; V2.F2; V3.F3; V4.F4), each operating point being defined by a supply voltage and a clock signal frequency of the circuit.

7. Method according to claim 6, comprising a step of selecting a set of operating points to activate and/or deactivate the circuit (PRCU) according to an operating parameter of the circuit resulting from a measurement taken during a test phase of the circuit or during normal use of the circuit.

8. Method according to one of claims 1 to 7, wherein the phase of activating the circuit (PRCU) comprises a step of applying a bias voltage

(Vbbp, Vbbn) for biasing a substrate on which the circuit is formed.

9. A device for controlling the activation of a circuit, characterized in that it is configured for implementing the method according to one of claims 1 to 8.

10. Device according to claim 9, comprising a clock circuit (COSC) supplying the circuit (PRCU) with the clock signal (CLK), the clock circuit being controlled to increase the frequency of the clock signal during a phase of activating the circuit, and/or decreasing the frequency of the clock signal during a phase of deactivating the circuit.

11. Device according to claim 10, wherein the clock circuit comprises a phase locked loop (PLL) supplying a frequency divider (DIVN) supplying the clock signal (CLK) with a constant frequency signal, the frequency divider being controlled to adjust the frequency of the clock signal successively to the frequency of operating points of the circuit (PRCU) during the phase of activating and/or the phase of deactivating the circuit.

12. Device according to claim 10, wherein the clock circuit (COSC) comprises a fractional phase locked loop supplying the circuit (PRCU) with the clock signal (CLK)₁ the fractional phase locked loop being controlled to adjust the frequency of the clock signal successively to the frequency of operating points of the circuit during the phase of activating the circuit and/or the phase of deactivating the circuit.

13. Device according to one of claims 9 to 12, comprising a power supply circuit (SMPS) supplying the circuit with a supply voltage, the power supply circuit being controlled to increase a supply voltage of the circuit during a phase of activating the circuit, and/or to decrease the supply voltage of the circuit during a phase of deactivating the circuit.

14. Device according to claim 13, wherein the power supply circuit (SMPS) is configured for adjusting the supply voltage of the circuit successively to the voltage (V1 , V2, V3, V4, V5) of operating points of the circuit (PRCU) during the phase of activating and/or the phase of deactivating the circuit.

15. A portable item of equipment, characterized in that it comprises a device according to one of claims 9 to 14.