WO2010110289A1

WO2010110289A1 - Router apparatus, semiconductor integrated circuit device, routing method, and program

Info

Publication number: WO2010110289A1
Application number: PCT/JP2010/055032
Authority: WO
Inventors: 淳鳥居
Original assignee: 日本電気株式会社
Priority date: 2009-03-24
Filing date: 2010-03-24
Publication date: 2010-09-30
Also published as: JP5488589B2; JPWO2010110289A1

Abstract

A router apparatus which forwards packets with a short delay time. The router apparatus comprises: a reception unit which receives a first packet as well as receives a second packet which includes the destination address and arrival timing of the first packet; a routing unit which routes the first packet, referring to the destination address of the first packet included in the second packet; an arbiter unit which performs arbitration with respect to the first packet, referring to the destination address and arrival timing of the first packet included in the second packet; and a forwarding unit which forwards the first packet in accordance with the routing by the routing unit and arbitration by the arbiter unit.

Description

Router device, semiconductor integrated circuit device, routing method and program

[Description of related applications]
The present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2009-072507 (filed on Mar. 24, 2009), the entire contents of which are incorporated herein by reference. Shall.
The present invention relates to a router device, a semiconductor integrated circuit device, a routing method, and a program, and in particular, a router device for communication between IP cores provided in a semiconductor integrated circuit device, a semiconductor integrated circuit device having the router device, and a routing The present invention relates to a method and a program.

SoC (System On a Chip) refers to a semiconductor integrated circuit device in which a plurality of IP (Intellectual Property) cores are integrated. Conventionally, communication between IP cores mounted on the SoC has been performed via a bus. For example, AMBA (Advanced Microcontroller Bus Architecture) proposed by ARM Inc. is a standard for buses between IP cores. In response to the increase in the number of IP cores and the complexity of SoC, AHB (Advanced High- performance Bus), multi-layer AHB, AXI (Advanced eXtensible Interface).

However, according to the bus configuration, the wiring length becomes long and it is difficult to cope with the improvement of the frequency. In addition, according to the bus configuration, it is necessary to concentrate on arbitration for access competition from a plurality of IP cores, so that it is necessary to recreate the bus as the number of IP cores increases. At present, for this problem, a method of securing communication locality (locality) by hierarchically connecting buses is used.

On the other hand, Non-Patent Document 1 describes NoC (Network on Chip) that ensures scalability by distributing arbitration to each router while effectively utilizing communication locality by sending data in packets. Yes.

Examples of chips adopting NoC include TILE64 manufactured by Tilera, 80 core chip manufactured by Intel, FAUST chip manufactured by CEA-LETI, and STNoC manufactured by STMicroelectronics.

FIG. 3 is a block diagram showing the configuration of the SoC that employs NoC. FIG. 5 is a diagram illustrating a flit configuration of a normal packet. Referring to FIG. 5, a normal packet is composed of a plurality of flits. Referring to FIGS. 3 and 5, in SoC 21, a network is configured by router devices R0 to R15 and communication channel 25. Communication between the IP cores IP0 to IP15 is realized by flowing the normal packet shown in FIG. 5 through this network.

However, when the NoC configuration is adopted, the number of cycles (that is, delay time (latency)) for delivering data from the data transmission IP core to the reception IP core is longer than the delay time in the bus configuration. . When the bus configuration is adopted, a channel from the transmission IP core to the reception IP core is established when arbitration is completed, so that the data transfer speed and latency satisfy the bus operating frequency and the frequency. Therefore, it is determined by the number of stages of pipeline registers inserted every fixed wiring length.

On the other hand, when the NoC configuration is adopted, after the first flit of the packet arrives, calculation of the destination of the packet, arbitration of the output switch and channel based on the destination, and latch to the output buffer are performed in a plurality of cycles. It is necessary to do it. Although depending on the distance between IP cores that perform communication, when a plurality of router devices are used, the NoC configuration may cause a large delay compared to the bus configuration.

In response to this problem, NRC (Next Routing Computation) has been proposed in which routing is performed by a router device immediately before. Referring to FIG. 3, in NRC, when transmitting a packet from router device R0 to router device R5 via router device R1, router device R0 performs routing of router device R1, and router device R1 is a router device. R5 routing is performed.

Non-Patent Document 2 describes EVC (Express Virtual Channel). FIG. 12 is a diagram for explaining the EVC described in Non-Patent Document 2. Referring to FIG. 12, the number of pipeline stages required in a relay router device is reduced by providing an EVC 204 that bypasses routing and arbitration by several relay router devices. During bypass, the packet passes through the router device in two cycles.

Referring to FIG. 12, router devices R0 to R15 are connected by a bidirectional communication channel 202. When there are many communications from the router apparatus R1 to the router apparatus R15, the EVC 204 is defined. The router devices R2, R7, and R11 omit the routing and switch arbitration of packets that arrive at the EVC 204. Accordingly, the delay time from the router device R1 to the router device R3 and the delay time from the router device R3 to R15 are shortened.

Non-Patent Document 3 describes predictive routing. That is, in parallel with the routing for the arrived packet, the output direction of the packet is speculatively predicted based on a predetermined prediction rule, and the packet is output by performing switch arbitration and switch passage in that direction. If the speculation is successful, the delay time is shortened according to the routing cycle. If the speculation fails as a result of the routing calculation, the output latch and the flit of the packet stored in the input latch and input data FIFO in the router device in the speculative output direction are canceled and the correct output direction Redo switch arbitration and switch passage for.

The entire disclosures of Non-Patent Documents 1 to 3 are incorporated herein by reference.
The following analysis was made by the present inventors. According to the above NRC, it is necessary to transmit the result of the routing calculation together with the packet to the next router device, so that the amount of wiring increases. In addition, each router device needs to route a plurality of router devices connected to itself, which complicates the routing.

Further, according to the EVC described in Non-Patent Document 2, the delay between adjacent nodes cannot be reduced, and arbitration and flow control between channels connecting a plurality of relay router apparatuses to be bypassed, and each relay router Arbitration for securing channels in the apparatus is required, and the effect of reducing the delay time is poor. In order to realize EVC, it is necessary to increase the number of buffers of the router device.

Furthermore, the prediction router described in Non-Patent Document 3 requires a recovery process when the speculation is lost. Therefore, it is necessary to hold the packet in the buffer from the top data until speculation is confirmed. In addition, when speculation fails, extra power is consumed.

Further, although these systems can reduce the routing delay time, the switch arbitration time cannot be shortened. Therefore, the delay time that can be shortened is limited although the configuration is complicated.

Therefore, it becomes a problem to transfer packets with a short delay time in the router device. An object of the present invention is to provide a router device, a semiconductor integrated circuit device, a routing method, and a program for solving such a problem.

A router device according to a first aspect of the present invention includes a receiving unit that receives a first packet and receives a second packet including a destination address and arrival timing of the first packet, and the second packet includes A routing unit that performs routing of the first packet with reference to a destination address of the first packet, and a destination address and arrival timing of the first packet included in the second packet with respect to the first packet. An arbiter unit that performs arbitration, and a transfer unit that transfers the first packet in accordance with routing by the routing unit and arbitration by the arbiter unit.

A semiconductor integrated circuit device according to a second aspect of the present invention includes a plurality of IP cores and the router device that transfers packets between the plurality of IP cores.

In the routing method according to the third aspect of the present invention, the router device receives the second packet including the destination address and arrival timing of the first packet before receiving the first packet; A step of routing the first packet with reference to the destination address of the first packet included in the first packet, and a first address with reference to the destination address and arrival timing of the first packet included in the second packet. Performing an arbitration on the packet and forwarding the first packet according to the routing and the arbitration.

According to a fourth aspect of the present invention, there is provided a program for receiving a second packet including a destination address and arrival timing of the first packet before receiving the first packet; A process of routing the first packet with reference to a destination address of the included first packet, and a destination address and arrival timing of the first packet included in the second packet A computer executes a process of performing arbitration on the first packet and a process of transferring the first packet according to the routing and the arbitration. Note that the program may be a configuration file for a reconfigurable device.

According to the router device, the semiconductor integrated circuit, the routing method, and the program according to the present invention, the router device can transfer a packet with a short delay time.

It is a block diagram which shows the structure of the router apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the router apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the arbiter part in the 2nd Embodiment of this invention. It is a figure which shows the flit structure of the normal packet transferred by the router apparatus which concerns on the 2nd Embodiment of this invention. It is a figure which shows the flit structure of the reservation request packet transferred by the router apparatus which concerns on the 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the router apparatus which concerns on the 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the router apparatus which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the reservation table in the 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the reservation table in the 2nd Embodiment of this invention. It is a figure which shows the structure of the semiconductor integrated circuit device which concerns on the 3rd Embodiment of this invention. It is a figure for demonstrating EVC described in the nonpatent literature 2. FIG.

The router device according to the first development form is preferably the router device according to the first aspect.

The router device of the second development form includes the number of preceding cycles that is the number of cycles from when the second packet is received as the arrival timing until the first packet is received. It is preferable that the arbiter unit performs the arbitration based on the number of preceding cycles and the flit length.

In the router device according to the third development form, the transfer unit updates the number of preceding cycles included in the second packet, and transfers the second packet to the subsequent router device according to the routing by the routing unit. preferable.

In the router device of the fourth expansion form, it is preferable that the second packet includes the priority of the first packet, and the arbiter unit performs the arbitration according to the priority.

In the router device of the fifth form of deployment, when the arbiter unit performs arbitration according to the priority and cancels the preceding arbitration, it notifies the subsequent router to which the second packet has been transferred. It is preferable to do.

The semiconductor integrated circuit device according to the sixth development is preferably the semiconductor integrated circuit device according to the second aspect.

A semiconductor integrated circuit device according to a seventh development form is the same as the semiconductor integrated circuit device according to the fourth development form, in which a first communication channel that connects a plurality of IP cores and transfers a first packet, and a plurality of IP It is preferable to further include a second communication channel for connecting the cores and transferring the second packet.

The routing method according to the eighth development form is preferably the routing method according to the third aspect.

The routing method of the ninth development form includes the number of preceding cycles that is the number of cycles from when the second packet is received as the arrival timing until the first packet is received. The router apparatus preferably performs arbitration based on the number of preceding cycles and the flit length.

In the routing method of the tenth development form, it is preferable that the second packet includes the priority of the first packet, and the router device performs arbitration according to the priority.

(Embodiment 1)
A router device according to a first embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1, the router device 30 includes a receiving unit 31, a routing unit 32, an arbiter unit 33, and a transfer unit 34.

The receiving unit 31 receives the first packet and receives the second packet including the destination address and arrival time of the first packet.

The routing unit 32 refers to the destination address of the first packet included in the second packet and routes the first packet.

The arbiter unit 33 performs arbitration for the first packet with reference to the destination address and arrival time of the first packet included in the second packet.

The transfer unit 34 transfers the first packet according to the routing by the routing unit 32 and the arbitration by the arbiter unit 33.

At this time, since the router device 30 does not need to perform routing and arbitration for the first packet after receiving the first packet, it can transfer the first packet with a short delay time.

(Embodiment 2)
A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram illustrating a configuration of the router device 20 according to the present embodiment. Each component in FIG. 2 performs the same operation on a packet input from the input channel 1 of the N direction, S direction, E direction, W direction, and IP core. Are suffixed with n, e, s, w, and i, respectively. In the following description, subscripts are omitted for convenience.

Referring to FIG. 2, the router device 20 includes an input channel 1, an input FIFO buffer 2, a through line 3, an input FIFO buffer output channel 4, a

selector

6, 12, an output latch 7, an output channel 8, an arbiter unit 9, and an input latch. 10, a routing unit 11, and a reservation packet generation unit 13.

FIG. 3 is a block diagram showing a configuration of a system on chip (semiconductor integrated circuit device) using a network on chip (NoC). Referring to FIG. 3, the semiconductor integrated circuit device 21 includes IP cores IP0 to IP15, a network interface NIF, routers R0 to R15, and a communication channel 25.

The IP cores IP0 to IP15 are each connected to the communication channel 25 via the network interface NIF. The routers R0 to R15 route the packet passing through the communication channel 25, and the packet is transmitted to the communication channel 25 in a desired direction. As the router devices R0 to R15, the router device 20 shown in FIG. 2 is provided.

2 receives a packet from the input channel 1 in five directions of N direction, E direction, S direction, W direction and I direction. The input latch 10 once latches the received packet. The routing unit 11 calculates (routes) the packet transfer destination. The routing unit 11 makes a reservation request to the arbiter unit 9 when making a reservation for packet transmission. The input FIFO buffer 2 stores flit data after the reservation request. The input FIFO buffer output channel 4 is connected to the crossbar 5. The through line 3 outputs the reserved packet to the crossbar 5 with a short delay time without going through the input FIFO buffer 2. The selector 12 delivers flit data from the through line 3 to the input FIFO buffer 2.

The selector 6 receives eight input signals in the same direction as the output out of the ten inputs, and outputs one of the received input signals as an output signal in accordance with an instruction from the arbiter unit 9. The output signal that has been output is output to the output channel 8 via the output latch 7 that aligns the timing of data output from the router device 20.

The reservation request packet generator 13 generates a reservation request packet. The reservation request packet generation unit 13 receives information from the arbiter unit 9 as to whether or not a reservation has been made in the router device 20, and when a reservation is made, the next request packet is sent at a timing when no other packet is transmitted. A reservation request packet is transmitted to the stage router. The selector 14 is a selector provided for this purpose.

FIG. 4 is a block diagram showing a configuration of the arbiter unit 9 in the present embodiment. Referring to FIG. 4, the arbiter unit 9 includes a selector arbiter 51, a reservation arbiter 52, a reservation table 53, and a remaining counter 56.

The selector arbiter 51 receives the normal packet arbitration request 61 from the input FIFO buffer 2 and the reservation information 62 from the reservation table 53, and arbitrates so that the reservation information 62 can be preferentially selected and the signal of the selector 6 can be selected. The arbitration result signal 63 is output to the selector 6.

The reservation arbiter 52 receives the reservation request 64 included in the reservation request packet from the routing unit 11, refers to the attribute entry 54 of the reservation table 53, and determines whether or not the router device 20 is free at the arrival timing of the normal packet. Determine. When the router device 20 is free, the reservation arbiter 52 sets (sets) the attribute entry 54 effectively and writes the input channel 1 that receives the normal packet to the input channel entry 55.

The reservation arbiter 52 writes an appropriate value to the remaining number register 58 of the remaining counter 56 when the entry of the reservation table 53 overflows. When the reservation is made, the reservation arbiter 52 transmits a reservation result notification signal 66 notifying that the reservation has been made to the reservation request packet generator 13. When the reservation request packet generator 13 receives the reservation result notification signal 66, the reservation request packet generator 13 transmits a reservation request packet to the router device at the next stage.

5 and 6 are diagrams showing a format (frit configuration) of a packet transferred by the router device 20 according to the present embodiment. FIG. 5 shows a normal packet flit configuration. On the other hand, FIG. 6 shows a flit configuration of the reservation request packet. Referring to FIG. 5 or FIG. 6, the normal packet or the reservation request packet includes a packet body signal 81 or 91 and a sideband signal 82 or 92. The sideband signal 82 or 92 indicates an attribute of the packet body signal 81 or 91, and is encoded by the following format as an example.

Attribute Packet body meaning 0b000 Invalid state 0b001 Reservation request packet 0b010 Reservation cancellation packet 0b011 Undefined 0b100 Normal packet control information head 0b101 Normal packet address 0b110 Normal packet data end 0b111 Normal packet data middle

Referring to FIG. 6, a normal packet is composed of a plurality of flits 0 to n and is transferred over a plurality of cycles. The flit whose sideband signal 82 is 0b100 is the head flit of a normal packet, and includes a destination address 83, a flit length 84, and control information 85. A flit whose sideband signal 82 is 0b101 includes an access address 86 and an access attribute 87. In the flit in which the sideband signal 82 is 0b110 or 0b111, the packet includes data 88. The flit whose sideband signal 82 is 0b110 includes data at the end of the packet.

Referring to FIG. 6, the sideband signal 92 of the flit corresponding to the reservation request packet is 0b001, and the flit includes a destination address 93, a flit length 94, and a preceding cycle number 95. The preceding cycle number 95 indicates the number of cycles between the arrival of the reservation request packet and the arrival of the normal packet.

Next, the operation of the router device 20 according to the present embodiment will be described with reference to a timing chart. FIG. 7 shows a packet routing operation of the router device 20 when there is no reservation request. On the other hand, FIG. 8 shows a packet routing operation of the router device 20 when a reservation request is made.

The operation of the router device 20 shown in FIG. 7 is the same as the operation of the conventional router device. First, the head flit arrives at the input channel 1 in the T1 cycle. Next, in the T2 cycle, the input latch 10 latches the flit, and the routing unit 11 performs routing based on the destination address 83 of the head flit to determine in which direction the packet should be transferred. .

Next, the head flit is stored in the input FIFO buffer 2 in the T3 cycle. Here, the arbiter unit 9 determines whether or not the output channel 8 to which this packet is to be output is free, and if it is free, assigns the selector 6 corresponding to the output destination.

Next, in the T4 cycle, the head frit actually passes through the selector 6 and is latched in the output latch 7. Furthermore, the head flit is output in the T5 cycle. Subsequent flits are input, routed, and output at the same timing as the leading flits. Referring to FIG. 7, a delay of 4 cycles occurs because the packet passes through the router device 20.

Next, with reference to FIG. 8, packet routing of the router device 20 when a reservation request by a reservation request packet is made will be described. In the T1 cycle, a reservation request packet arrives. The reservation request packet is latched by the input latch 10 in the T2 cycle in the same manner as when the leading flit of the normal packet arrives. The routing unit 11 performs routing with reference to the destination address 93 of the head flit (that is, the reservation request packet), and determines in which direction the packet should be transferred.

Next, in the T3 cycle, the reservation arbiter 52 refers to the number of preceding cycles 95 and the flit length 94 included in the reservation request packet, and the reservation table 53, and at the timing when the normal packet arrives, the output channel 8 is free. It is determined whether or not there is. If there is a vacancy, the reservation arbiter 52 changes the attribute entry 54 of the cycle from the vacant state 00 to the reserved states 01 (first), 11 (intermediate), 10 (end), and inputs to the input channel entry 55 Fill in channel 1. When the reservation is made, the reservation arbiter 52 transmits a reservation result notification signal 66 indicating that the reservation has been made and an arbitration result notification signal 65 indicating the current selector arbiter state to the reservation request packet generator 13. . The reservation request packet generator 13 generates a reservation request packet for the next router based on the reservation result notification signal 66. The generated reservation request packet is latched by the output latch 7 via the selector 14.

Next, in the T4 cycle, the reservation request packet is transmitted to the router at the next stage.

Next, in the T5 cycle, the leading flit of the normal packet arrives. Since the reservation for the router device 20 is established, the head flit passes directly through the selector 6 without going through the input latch 10 and the input FIFO buffer 2. Therefore, the head flit is latched in the output latch 7 in the T6 cycle and is output to the output channel 8 in the T7 cycle.

Referring to FIG. 8, when a normal packet passes through the router device 20, a two-cycle delay occurs. Therefore, according to the router device 20 of the present embodiment, when the reservation is made, the delay time can be shortened by two cycles compared to the case where the reservation is not made. In the example shown in FIG. 8, the interval between the reservation request packet and the normal packet before passing through the router device 20 is 3 cycles, and the interval after passing through the router device 20 is 2 cycles. The number of cycles to be shortened is determined when a reservation is made in the T3 cycle. Therefore, the number of preceding cycles 95 included in the reservation request packet transmitted to the next router in the T4 cycle is reduced by 1 and transmitted as 2 cycles. When the preceding cycle number 95 becomes 1 cycle or less, the reservation request packet is not transmitted to the subsequent router. This is because a normal packet arrives at the subsequent router before reservation is made based on the reservation request packet.

In the T3 cycle, when another normal packet transfer has already been reserved for the router device 20, the router device 20 performs one of the following processes based on the priority of the packet.

The router device 20 invalidates the newly arrived reservation request packet, and performs normal scheduling for the normal packet corresponding to the newly arrived reservation request packet (first process). At this time, the router device 20 does not issue a reservation request packet to the next-stage router device.

The router device 20 invalidates the schedule that has already been reserved, treats the normal packet that has already been reserved as a normal packet, and makes a new reservation based on the newly arrived reservation request packet (second processing) ). At this time, the router device 20 issues a reservation request packet to the next-stage router.

When the router device 20 performs the second process, the next-stage router device performs the same process. In addition, when the destination address (target IP core) is different between the packet that has been reserved earlier and the packet that has been reserved later, the route of the packet that has been reserved earlier and the packet that has been reserved later The route is different from the middle. The router device 20 provided at a location where the route for these packets branches from the same route to a different route indicates that the reservation for the same reservation cycle and the same input channel 1 has already been made. A reservation cancellation packet is issued as necessary to the output channel 8 that has been recognized by reference and has been previously reserved.

Next, the operation of the router device 20 according to the present embodiment will be described based on a specific example. Here, as an example, in the semiconductor integrated circuit device 21 shown in FIG. 3, a reservation request packet for communication from the IP core IP0 to the IP core IP9 is issued, and a reservation request for communication from the IP core IP4 to the IP core IP13. Consider a case where a packet is also issued and a regular packet reservation conflicts.

It is assumed that a packet from IP core IP0 to IP core IP9 passes through a route of IP core IP0 → router R0 → router R4 → router R8 → router R9 → IP core IP9. On the other hand, a packet from the IP core IP4 to the IP core IP13 passes through a route of IP core IP4 → router R4 → router R8 → router R12 → router R13 → IP core IP13. At this time, packet reservation may compete between the routers R4 and R8.

FIG. 9 is a diagram for explaining the operation of the reservation table 53 of the router apparatus R4. FIG. 9 shows the operation of the reservation table 53 when the previous reservation is canceled in the router apparatus R4.

In the T1 cycle, the reservation request packet from the IP core IP0 arrives at the router R4 via the router R0. When information indicating that a normal packet having a flit length of 6 arrives in the T1 + 7 cycle is included in the reservation packet, the reservation arbiter 52 of the router apparatus R4 refers to the entry of the reservation table 53 at that timing.

The reservation arbiter 52 determines that the reservation is possible, and in the T2 cycle that is one cycle after the T1 cycle, validates the attribute entry 101 corresponding to +6 to +11 cycles, and at the same time, makes a reservation request from the router apparatus R0. Therefore, the input channel entry 102 is set to N. At the same time, the router device R4 issues a reservation request packet to the next-stage router device R8.

Next, in the T3 cycle, one cycle is advanced, and the range reserved for input from the input channel 1n in the N direction shifts to +5 to +10 cycles. At this point, the reservation request packet from the IP core IP4 arrives at the router device R4. When the router apparatus R4 tries to reserve a normal packet in the +9 to +14 cycles from the T3 cycle, it competes with the reservation for the input channel 1n in the N direction previously reserved in the T3 cycle +9 and the 10th cycle.

Here, when the priority of the reservation request issued by the IP core IP4 is higher than the priority of the previous reservation request, the router apparatus R4 receives the input from the N direction in T3 + 5 to +10 cycles. The reservation is canceled and a new reservation is made from the IP core IP4.

In the T4 cycle, the input from the input channel 1i in the I direction is newly reserved for the T4 + 8 to +13 cycles. For example, the priority may be held in the reservation request packet or the reservation table 53, or the priority of IP4 may always be set higher in the router device.

FIG. 10 is a diagram for explaining the operation of the reservation table 53 of the router apparatus R8. FIG. 10 is a diagram for explaining a reservation canceling operation in another direction accompanying cancellation of a previous reservation in the router apparatus R8.

Referring to FIG. 10, in the T4 cycle, the reservation request packet from the IP core IP0 arrives at the router device R8, and in the T5 cycle, the reservation for the reservation table 53 in the E direction (R9 direction) of the router device R8 is established.

However, since the reservation request packets from the IP core IP4 arrive at the router apparatus R8 in the T6 cycle, these reservation request packets compete in the T6 + 7 and +8 cycles, and the router apparatus R8 receives the request from the IP core IP0. Recognize that it was canceled. Therefore, in the T7 cycle, the reservation from the IP core IP0 output in the E direction is cancelled. At the same time, the router apparatus R8 sends a reservation cancellation packet in the E direction (R9 direction). As a result, the reservation in the router apparatus R9 is also cancelled.

Through the above operation, normal packets from the IP core IP0 flow through the network according to a sequence not accompanied by a reservation. When it is not permitted to insert flits constituting other packets between a plurality of flits constituting a normal packet, the packet from the IP core IP0 does not pass the normal packet reserved by the IP core IP4. It remains in the input FIFO buffer 2 of the router device R4 until completion.

Since the number of entries in the reservation table 53 is limited, it is preferable to provide a remaining counter 56 as shown in FIG. When making a reservation exceeding the upper limit of the number of entries, the number exceeding the upper limit of the number of entries is recorded in the remaining number register 58 of the remaining counter 56. FIG. 4 shows, as an example, a case where the same packet continues for four cycles exceeding the upper limit (+16) of the number of entries. At this time, the reservation arbiter 52 sets 4 to the remaining number register 58 and sets the same input channel (S) as the input channel entry 55 of the maximum upper limit entry + 16 to the input channel entry 59. For each cycle, the remaining counter 56 is counted down and the contents of the reservation table 53 are shifted. At this time, the value of the input channel entry 59 is set for the maximum upper limit entry +16 together with the attribute generated by the attribute generation unit 57. As a result, routing reservation exceeding the upper limit of the number of entries can be made.

(Third embodiment)
A semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to the drawings.

In the semiconductor integrated circuit device 21 according to the second embodiment, there is only one network. That is, not only a normal packet but also a reservation request packet and a reservation cancellation packet are transmitted / received through this one system network. However, according to such a configuration, it is conceivable that the packet transfer efficiency is lowered due to the competition between the reservation request packet and the normal packet. Therefore, the reservation request packet may be transmitted / received via a network different from the normal packet.

FIG. 11 is a diagram showing a configuration of the semiconductor integrated circuit device 121 according to the present embodiment. The semiconductor integrated circuit device 121 is a system on chip (SoC) in which a network on chip (NoC) is duplicated. In the semiconductor integrated circuit device 121, a normal network and a control network are separated.

Referring to FIG. 11, the semiconductor integrated circuit device 121 includes IP cores IP0 to IP15, a network interface NIF, main router devices MR0 to MR15, control router devices CR0 to CR15, a main communication channel 125, and a control communication channel 127. .

The IP cores IP0 to IP15 are connected to the main communication channel 125 via the network interface NIF. The main router devices MR0 to MR15 route packets passing through the main communication channel 125, and send the packets to the main communication channel 125 in a desired direction.

The network interface NIF and the control router devices CR0 to CR15 are connected via a control communication channel 127. The main router devices MR0 to MR15 are connected to the control router devices CR0 to CR15, respectively. The control router devices CR0 to CR15 perform routing of packets passing through the control communication channel 127. By sending a reservation request packet and a reservation cancellation packet to the control network, the packet scheduling of the main router devices MR0 to MR15 is reserved or canceled.

Since the control network does not need to flow packets with a long flit length, the number of entries in the input FIFO buffer (not shown) can be reduced. Also, by reducing the bit width for the control communication channel 127 compared to the bit width for the main communication channel 125, the control communication channel 127 can be realized at a lower cost than a normal network. Further, network traffic can be optimized by sending an access request packet such as a read request to a memory without a data flit to the control network.

In the above embodiment, it is necessary to issue a reservation request packet before issuing a normal packet storing data. However, when the IP core is connected to an external memory or an internal memory (for example, SDRAM), a period of several cycles may be required until data is output after an access request is made to these devices. . The network interface NIF connected to these devices preferably issues a memory access request and simultaneously issues a reservation request packet to the network. This is because network routing and switch reservation can be completed before data is available. At this time, the delay time of the network can be concealed.

Although the above description has been made based on the embodiment, the present invention is not limited to the above embodiment.
It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

In addition, although a part or all of the said embodiment can be described as the following additional remarks, it is not limited to these.

(Supplementary Note 1) A receiving unit that receives the first packet and receives the second packet including the destination address and arrival timing of the first packet;
A routing unit for routing the first packet with reference to a destination address of the first packet included in the second packet;
An arbiter unit that performs arbitration for the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
And a transfer unit that transfers the first packet in accordance with routing by the routing unit and arbitration by the arbiter unit.

(Supplementary Note 2) The second packet includes a preceding cycle number that is a cycle number from the reception of the second packet to the reception of the first packet as the arrival timing, and the first packet Including the flit length of the packet,
The router apparatus according to appendix 1, wherein the arbiter unit performs the arbitration based on the number of preceding cycles and the flit length.

(Supplementary Note 3) The transfer unit updates the number of preceding cycles included in the second packet, and transfers the second packet to a subsequent router device according to the routing by the routing unit. The router device according to attachment 2.

(Supplementary Note 4) The second packet includes the priority of the first packet,
The router device according to any one of appendices 1 to 3, wherein the arbiter unit performs arbitration according to the priority.

(Supplementary Note 5) When the arbitration unit performs arbitration according to the priority, and cancels the preceding arbitration, the arbiter unit notifies the subsequent router to which the second packet has been transferred. The router device according to attachment 4, wherein the router device is characterized.

(Appendix 6) A plurality of IP cores;
A semiconductor integrated circuit device comprising: the router device according to any one of appendices 1 to 5 that transfers packets between the plurality of IP cores.

(Supplementary note 7) a first communication channel for connecting the plurality of IP cores and transferring the first packet;
The semiconductor integrated circuit device according to appendix 6, further comprising a second communication channel for connecting the plurality of IP cores and transferring a second packet.

(Supplementary Note 8) The router device receives a second packet including a destination address and arrival timing of the first packet before receiving the first packet;
Routing the first packet with reference to a destination address of the first packet included in the second packet;
Performing arbitration on the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
Forwarding the first packet according to the routing and the arbitration.

(Supplementary Note 9) The second packet includes a preceding cycle number which is a cycle number from the reception of the second packet to the reception of the first packet as the arrival timing, and the first packet Including the flit length of the packet,
9. The routing method according to appendix 8, wherein the router device performs the arbitration based on the number of preceding cycles and the flit length.

(Supplementary Note 10) The second packet includes the priority of the first packet,
10. The routing method according to

appendix

8 or 9, wherein the router device performs the arbitration according to the priority.

(Supplementary Note 11) A process of receiving a second packet including a destination address and arrival timing of the first packet before receiving the first packet;
A process of routing the first packet with reference to a destination address of the first packet included in the second packet;
A process of performing arbitration on the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
A program for causing a computer to execute the process of transferring the first packet according to the routing and the arbitration.

(Supplementary Note 12) The second packet includes a preceding cycle number which is a cycle number from the reception of the second packet to the reception of the first packet as the arrival timing, and the first packet Including the flit length of the packet,
The program according to appendix 11, wherein the computer executes the process of performing the arbitration based on the preceding cycle number and the flit length.

(Supplementary note 13) The second packet includes the priority of the first packet,
The program according to

appendix

11 or 12, which causes a computer to execute a process of performing the arbitration according to the priority.

(Supplementary note 14) A computer-readable recording medium on which the program according to any one of supplementary notes 11 to 13 is recorded.

1, 1n, 1e, 1s, 1w, 1i input channel 2, 2n, 2e, 2s, 2w, 2i input FIFO buffer 3, 3n, 3e, 3s, 3w, 3i through line 4, 4n, 4e, 4s, 4w, 4i input FIFO buffer output channel 5 crossbar 6, 6n, 6e, 6s, 6w, 6i, 12, 12n, 12e, 12s, 12w, 12i, 14 selector 7, 7n, 7e, 7s, 7w, 7i output latch 8, 8n, 8e, 8s, 8w, 8i Output channels 9, 9n, 9e, 9s, 9w, 9i, 33, 50 Arbiter units 10, 10n, 10e, 10s, 10w, 10i Input latches 11, 11n, 11e, 11s, 11w , 11i, 32 Routing units 13, 13n, 13e, 13s, 13w, 13i Reservation request packet generators 20, 30, R0 to R15 Data device 21, 121 Semiconductor integrated circuit device 25, 202 Communication channel 31 Receiving unit 34 Transfer unit 51 Selector arbiter 52 Reservation arbiter 53 Reservation table 54, 101 Attribute entry 55, 59, 102 Input channel entry 56 Remaining counter 57 Attribute generation unit 58 Remaining number register 60 Subtraction unit 61 Arbitration request 62 from input FIFO buffer Reservation information 63 Arbitration result signal 64 Reservation request 65 Arbitration result notification signal 66 Reservation result notification signal 81, 91 Packet body signals 82, 92 Sideband signals 83, 93 Destination address 84, 94 Flit length 85 Control information 86 Access address 87 Access attribute 88 Data 89 Write buffer 95 Number of preceding cycles 125 Main communication channel 127 Control communication channel 204 EVC (Express Vir ual Channel)
CR0 to CR15 Control router IP0 to IP15 IP (Intellectual Property) core MR0 to MR15 Main router NIF network interface

Claims

A receiving unit that receives the first packet and receives the second packet including the destination address and arrival timing of the first packet;
A routing unit for routing the first packet with reference to a destination address of the first packet included in the second packet;
An arbiter unit that performs arbitration for the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
And a transfer unit that transfers the first packet in accordance with routing by the routing unit and arbitration by the arbiter unit.
The second packet includes, as the arrival timing, a preceding cycle number that is a cycle number from the reception of the second packet to the reception of the first packet, and the flit length of the first packet. Including
The router apparatus according to claim 1, wherein the arbiter unit performs the arbitration based on the number of preceding cycles and the flit length.
The transfer unit updates the number of preceding cycles included in the second packet, and transfers the second packet to a subsequent router device according to the routing by the routing unit. The router device described in 1.
The second packet includes the priority of the first packet;
The router device according to claim 1, wherein the arbiter unit performs arbitration according to the priority.
In the case where arbitration is performed according to the priority, the arbiter unit notifies the subsequent router to which the second packet has been transferred when canceling the preceding arbitration, The router device according to claim 4.
Multiple IP cores;
6. A semiconductor integrated circuit device comprising: the router device according to claim 1 that transfers packets between the plurality of IP cores.
A first communication channel for connecting the plurality of IP cores and transferring the first packet;
The semiconductor integrated circuit device according to claim 6, further comprising a second communication channel for connecting the plurality of IP cores and transferring a second packet.
The router device receiving a second packet including a destination address and arrival timing of the first packet before receiving the first packet;
Routing the first packet with reference to a destination address of the first packet included in the second packet;
Performing arbitration on the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
Forwarding the first packet according to the routing and the arbitration.
The second packet includes, as the arrival timing, a preceding cycle number that is a cycle number from the reception of the second packet to the reception of the first packet, and the flit length of the first packet. Including
The routing method according to claim 8, wherein the router device performs the arbitration based on the number of preceding cycles and the flit length.
The second packet includes the priority of the first packet;
The routing method according to claim 8 or 9, wherein the router device performs the arbitration according to the priority.
Processing to receive a second packet including a destination address and arrival timing of the first packet before receiving the first packet;
A process of routing the first packet with reference to a destination address of the first packet included in the second packet;
A process of performing arbitration on the first packet with reference to a destination address and arrival timing of the first packet included in the second packet;
A program for causing a computer to execute the process of transferring the first packet according to the routing and the arbitration.
The second packet includes, as the arrival timing, a preceding cycle number that is a cycle number from the reception of the second packet to the reception of the first packet, and the flit length of the first packet. Including
The program according to claim 11, wherein the computer executes the process of performing the arbitration based on the number of preceding cycles and the flit length.
The second packet includes the priority of the first packet;
The program according to claim 11 or 12, wherein the program executes a process of performing the arbitration according to the priority.