WO2010067143A1

WO2010067143A1 - Method, apparatus and computer program product for facilitating a full-rate cooperative relay system

Info

Publication number: WO2010067143A1
Application number: PCT/IB2008/055174
Authority: WO
Inventors: Kyeong Jin Kim; Shu-Shaw Wang
Original assignee: Nokia Corporation
Priority date: 2008-12-09
Filing date: 2008-12-09
Publication date: 2010-06-17

Abstract

A method, apparatus and computer program product are provided for facilitating data transmission, such as full-rate data transmission, via a cooperative relay system. During a first time slot, a first source transmission may be received from a source node that includes data and associated parity check bits and a first relay transmission may be received from a first relay node that includes parity check bits associated with data from a prior source transmission. In a second time slot, a second source transmission may be received from the source node that includes data and associated parity check bits and a second relay transmission may be received from a second relay node that includes parity check bits associated with the data from the first source transmission. The data from the first source transmission may then be decoded at least partially based on the first source transmission and the second relay transmission.

Description

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR FACILITATING A FULL-RATE COOPERATIVE RELAY SYSTEM

TECHNOLOGICAL FIELD

Embodiments of the present invention relate generally to wireless communications and, more particularly, to cooperative relay systems for facilitating wireless communications.

BACKGROUND

A wireless distribution system (WDS) enables the wireless interconnection of access points (AP) such as in an IEEE 802.11 network. A WDS allows a wireless network to be expanded using multiple access points without the need for a wired backbone to link the access points. A WDS also preserves the medium access control (MAC) addresses of client packets across links between access points. As such, connections between clients may be made using MAC addresses rather than by specifying Internet Protocol (IP) assignments. An access point can be either a main, relay or remote base station. A main base station is typically connected to a wired network, such as the Ethernet. A relay base station relays data between remote base stations, wireless clients or other relay stations to either a main or another relay base station. A remote base station accepts connections from wireless clients and passes them to relay or main stations.

In addition to transmitting data via a WDS or otherwise, error correction information, such as error correction codes, may be provided to permit at least some of the errors that may occur to the data to be corrected by the recipient without requiring retransmission of the data. One error correction code that may be utilized is a zig-zag code. With respect to data in the form of an information block M that is arranged in matrix form, such as d(i,j), a parity bit p(i) may represent the modulo two addition of j data bits and the prior parity bit. For example, for data having an (i, j) matrix form, the parity bits may be determined as follows: p(\)=∑d(l,j) mod 2,...,

7-1

P(i)=∑d(i,j)+p(i-l) mod 2

7-1

wherein N is the number of rows of the matrix. A corresponding graphical representation of zig-zag coding is depicted in Figure 1.

An extension of zig-zag coding is concatenated zig-zag coding in which a data block is repeatedly subjected to interleaving with parity bits being determined for each different interleaved version of the data block. As such, a concatenated zig-zag code may be described by a triplet (I, J, K) wherein the data block is of dimension (I x J) and K is the number of constituent encoders in concatenation. In order to generate a concatenated zigzag code, the data block is first interleaved, such as by being subjected to random interleaving, and initial vector of parity bits p(i) for the block of interleaved data is then determined. The original data block is then differently interleaved and a second vector of parity bits P₂ is then determined for the interleaved data. As shown in Figure 2, the process of interleaving the original data block and then determining the resultant vector of parity bits may be repeated M times. Following the repeated interleaving and determination of the respective vectors of parity bits, an encoded representation of the original data block and a concatenation of the vectors of parity bits may be transmitted as shown in Figure 2. In this instance, the number of total transmitted bits is I*(J+K) where (I * J) is the number of information bits and (PK) is the number of parity bits. From this fact, the code rate for such a transmission is J/(J+K).

While concatenated zig-zag coding may offer advantages in terms of error correction performance, the inclusion of concatenated zig-zag coding in a single relay cooperative system may cause a single relay cooperative system to become a half-rate data transmission scheme. As shown in Figure 3, for example, a source node S may desire to transmit data to a destination node D with the assistance of a single relay node R. As shown in both Figure 3 and the timeline depicted in Figure 4, the source node S initially transmits xi to both the destination node D and the relay node R, wherein Xi=(Di, i,Pi,i) for a first set of information data D_1, i and a first vector of parity bits Py. After receiving X₁, the relay node decodes X₁ and then repeatedly and randomly interleaves the data block to generate a plurality of vectors of parity bits P₂,i,P₃,i,...,Pκ,i, one of which is associated with each differently interleaved version of the data block. In the second time slot t₂, the relay node then forwards either x₂p = P_2, i or x₂p = {P2,_hP3,i,- • -,Pκ,i } to the destination node. As shown in Figure 4, the source node does not transmit any additional data to the destination during this second time slot t₂. If the relay node transmits x₂p = P₂, i to the destination node, the relay node applies the maximum transmission power to P₂,i. However, if the relay node transmits x₂p ={P₂,i,P₃,i ...,P_{K1 !} } to the destination node, the relay node equally distributes the maximum transmission power between P₂₁I₅P₃₁I₁... ,PK, i- Upon receipt of the additional plurality of vectors of parity bits from the relay node, the destination node attempts to decode the original information data utilizing not only the vector of parity bits provided by the source node, but also P₂ i provided by the relay node. If the destination node is able to decode the information data, the destination node will cease further processing and discard the additional, unused vectors of parity bits provided by the relay node. However, if the destination node is still unable to decode the information data, the destination node will utilize the next vector of parity bits, that is, P_3ii, in the decoding process. This process will continue until the destination node has either successfully decoded the information data or has used all of the additional plurality of vectors of parity bits provided by the relay node including P_κ>1. If the additional plurality of vectors of parity bits provided by the relay node are insufficient to permit the destination node to successfully decode the information data, the destination node may request a re-transmission.

As shown in Figure 4, while the destination node is attempting to decode the first set of information data, the source node may transmit a second set of information data and parity bits, x₃ ⁼{D_1]2,P_lj2} to both the destination node and the relay node during the third time slot t₃. Upon receipt of X₃, the relay node again decodes the second set of information data and then repeatedly interleaves the data block to generate a plurality of vectors of parity bits, that is, P₂,₂,P₃,₂,...,Pκ,2 for the differently interleaved versions of the data block. During the fourth time slot t₄, the relay node forwards either

or x_4p

■ -,Pκ,2} to the destination node. As with the second time slot t₂, the source node does not transmit any data to the destination node during the fourth time slot t₄. As illustrated in Figure 4 and described above, two sets of information data are therefore transmitted between the source and destination nodes during four times slots in accordance with the foregoing time division multiplex (TDM) scheme. As such, this cooperative relay system may support half-rate data transmission. As before, the code rate will be J/(J+K).

As an alternative to zig-zag coding, distributed turbo coding has been proposed in conjunction with a single relay cooperative system in which two versions of the same code word are available at the destination node for its detection. Since a relay node is required to send a single code word or several code words to the destination, the bandwidth requirements for such a system disadvantageously increase linearly with the number of code words and may limit the transmission time of the system.

As such, it may be advantageous to provide a cooperative relay system that could provide improved data throughput with a reduced bandwidth requirement. For example, it may be desirable to provide a cooperative relay system capable of supporting full-rate data symbol transmission.

BRIEF SUMMARY OF THE INVENTION

A method, apparatus and computer program product are therefore provided for facilitating data transmission via a cooperative relay system that is capable of providing improved data throughput with a reduced bandwidth requirement. In one embodiment, the method, apparatus and computer program product are configured to provide full-rate data transmission between the source and destination nodes of a dual-relay cooperative system. As such, methods, apparatus and computer products of embodiments to the present invention permit the advantages of a WDS to be enjoyed while expediting communications between the various nodes.

In one embodiment, a method is provided that receives, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission. For example, the first relay transmission may include only parity check bits. The method of this embodiment also receives, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission. Like the first relay transmission, the second relay transmission in one example may include only parity check bits. The method of this embodiment further includes decoding, at a destination node, the data from a first source transmission at least partially based on the first source transmission and the second relay transmission. In another embodiment, an apparatus is provided that includes a processor configured to receive, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission. For example, the first relay transmission may include only parity check bits. The processor of this embodiment is also configured to receive, in a second time slot, a second source transmission from the source node, comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission. The second relay transmission may also, in one example, include only parity check bits. The processor of this embodiment is further configured to decode the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

In yet another embodiment, an apparatus is provided that includes means for receiving, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission. For example, the first relay transmission may include only parity check bits. The apparatus of this embodiment also includes means for receiving, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission. The second relay transmission may also, in one example, include only parity check bits. The apparatus of this embodiment further includes means for decoding the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

In a further embodiment, a computer program product is provided that comprises a computer-readable storage medium having computer-executable program code instructions stored therein. The computer executable program code instructions of this embodiment include program code instructions for receiving, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission. For example, the first relay transmission may include only parity check bits. The computer executable program code instructions to this embodiment also include program code instructions for receiving, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission. The second relay transmission may also, in one example, include only parity check bits. Further, the computer executable program code instructions of this embodiment include program code instructions for decoding the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

Having thus described the invention in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

Figure 1 is a graphical representation of zig-zag coding;

Figure 2 is a graphical representation of the generation of a concatenated zig-zag code;

Figure 3 is a depiction of a single relay cooperative system;

Figure 4 depicts half-rate data symbol transmission by the single-relay cooperative system of Figure 3 over four time slots Ti, T₂, T₃ and T₄;

Figure 5 is a graphical representation of a dual-relay cooperative system in accordance with one embodiment to the present invention;

Figure 6 is a block diagram of a source node in accordance with one embodiment to the present invention;

Figure 7 is a graphical representation of the signal flow between the source, first and second relay and destination nodes over four time slots, that is, ti, t₂, t₃ and t₄ in accordance with one embodiment of the present invention;

Figure 8 depicts the signaling between the source node, the first and second relay nodes and the destination node for odd time slots, such as tj,t₃... in accordance with one embodiment of the present invention;

Figure 9 is a block diagram of a relay node in accordance with one embodiment of the present invention;

Figure 10 depicts the signaling between the source node, the first and second relay nodes and the destination node for even time slots, such as t₂,t₄... in accordance with one embodiment of the present invention;

Figure 11 is a flow chart of the operations of a destination node in accordance with one embodiment to the present invention;

Figure 12 is a block diagram of a destination node in accordance with one embodiment to the present invention; Figure 13 is a graph of the bit error rate for data transmissions between the source node and the destination node utilizing different numbers of vectors of parity bits in accordance with one embodiment of the present invention; and

Figure 14 is a graph of the packet error rate for data transmissions between the source node and the destination node utilizing different numbers of vectors of parity bits in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Some embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout. As used herein, the terms "data," "content," "information" and similar terms may be used interchangeably to refer to data capable of being transmitted, received and/or stored in accordance with embodiments of the present invention. Moreover, the term "exemplary", as used herein, is not provided to convey any qualitative assessment, but instead merely to convey an illustration of an example. Thus, use of any such terms should not be taken to limit the spirit and scope of embodiments of the present invention.

As shown in Figure 5, a dual relay cooperative system is provided in accordance with one embodiment of the present invention. The dual relay cooperative system includes a source node S, a destination node D and first and second relay nodes Rj and R₂. By cooperatively utilizing the first and second relay nodes, increased rates of data transmission, such as full-rate data transmission, may be provided between the source and destination nodes, as described below.

Prior to transmitting data to the destination node, the source node S may initially determine error correcting information, such as parity bits, for the data. In one embodiment, the source node determines a vector of parity bits P^ for the data Di₁) utilizing zig-zag coding. The source node may be configured in a variety of manners, but, in one embodiment, may be configured as shown in Figure 6. In this regard, the source node may include a processor 10, a memory device 12, a receiver 14, a transmitter 16, a priority bit generator 18 and an encoder 20. The processor may be embodied in a number of different ways. For example, the processor may be embodied as various processing means such as a processing element, a co-processor, a controller or various other processing devices including integrated circuits such as, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), a hardware accelerator or the like. In an exemplary embodiment, the processor may be configured to execute instructions stored in the memory device or otherwise accessible to the processor. As such, whether configured by hardware or software or a combination thereof, the processor may represent an entity capable of performing operations according to embodiments of the present invention while configured accordingly.

The receiver 14 and transmitter 16 may be combined as a transceiver or may be separately provided for receiving and transmitting signals, respectively. The memory device 12 may include, for example, volatile and/or non-volatile memory. The memory device may be configured to store information, data, applications, instructions or the like for enabling the source node S to carry out the various functions in accordance with exemplary embodiments of the present invention. For example, the memory device could be configured to buffer input data for processing by the processor 10. Additionally or alternatively, the memory device could be configured to store instructions for execution by the processor.

In an exemplary embodiment, the processor 10 may be embodied as, include or otherwise control the parity bit generator 18 and/or the encoder 20. However, the parity bit generator and the encoder may each be any means such as a device or circuitry embodied in hardware, software, or a combination of hardware and software (e.g., the processor operating under software control, the processor embodied as an ASIC or FPGA specifically configured to perform the operations described herein, or a combination thereof) that is configured to perform the corresponding functions of the parity bit generator and the encoder, as described herein. For example, the parity bit generator of this embodiment may be configured to generate the parity bits associated with the data, such as in accordance with zig-zag coding, as noted above. In an exemplary embodiment, any or all of the parity bit generator and the encoder may include instructions, code, modules, applications, and/or circuitry for providing respective portions of the pixel bit generation and encoding functions, respectively. However, it should be noted that the code, circuitry and/or instructions associated with the parity bit generator and the encoder may not necessarily be modular. After generation of a vector of parity bits Py, such as by the parity bit generator 18, the source node S and, in one embodiment, the encoder 20 of the source node may encode the data and, in one embodiment, both the data and the vector of parity bits. In order to facilitate data transmission via a dual-relay cooperative system, such as shown in Figure 5, a code division multiplexing (CDM) scheme may be employed. As such, the source node, such as the processor 10, may mask the encoded data and the vector of parity bits with a first mask and the transmitter 16 may then transmit a first source transmission including the masked, encoded data and the vector of parity bits designated at X₁ = (Di_1I5Pi_1I) to both the destination node D and the first relay node Rl during a first time slot ti. A transmission of xi to the destination node and the first relay node during the first time slot is also depicted in the timeline of Figure 7 and the signal flow of Figure 8, which depicts the data and the vectors of parity bits that flow between the source, relay and destination nodes during odd numbered time slots (that is, n=l, 3, ...), such as ti, t₃,.... The source node S may mask the encoded data and the vector of parity bits in a variety of manners. In one embodiment, however, the source node, such as the processor, masks the encoded data and the vector of parity bits with a first pseudorandom number sequence PNi.

As shown in Figures 7 and 8, the second relay node R2 also provides a first relay transmission to the destination node D during the first time slot ti concurrent with the first source transmission from the source node S. As explained further below, the first relay transmission may include an additional plurality of vectors of parity bits x_Op for data that was the subject of a prior source transmission, such as the source transmission during the immediately preceding time slot to, with the plurality of vectors of parity bits being generated for differently interleaved versions of the data.

Upon receipt of the first source transmission, the first relay node Rl may be configured to unmask the transmission and then decode the data. The first relay node may then repeatedly randomly interleave the data and generate a respective vector of parity bits xip ⁼ {P2,i, P2,i_{v >}Pκ,i} for each differently interleaved version of the data. The first relay node, as well as the second relay node R2, may be configured in a variety of manners, but, in one embodiment, may be configured as shown in Figure 9. In this regard, the relay node may include a processor 30, a memory device 32, a receiver 34, a transmitter 36, a decoder 38, an interleaver 40 and a priority bit generator 42. The processor may be embodied in a number of different ways. For example, the processor may be embodied as various processing means such as a processing element, a co-processor, a controller or various other processing devices including integrated circuits such as, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), a hardware accelerator or the like. In an exemplary embodiment, the processor may be configured to execute instructions stored in the memory device or otherwise accessible to the processor. As such, whether configured by hardware or software or a combination thereof, the processor may represent an entity capable of performing operations according to embodiments of the present invention while configured accordingly.

The receiver 34 and transmitter 36 may be combined as a transceiver or may be separately provided for receiving and transmitting signals, respectively. The memory device 32 may include, for example, volatile and/or non-volatile memory. The memory device may be configured to store information, data, applications, instructions or the like for enabling the relay node to carry out the various functions in accordance with exemplary embodiments of the present invention. For example, the memory device could be configured to buffer input data for processing by the processor 30. Additionally or alternatively, the memory device could be configured to store instructions for execution by the processor.

In an exemplary embodiment, the processor 30 may be embodied as, include or otherwise control the decoder 38, the interleaver 40 and/or the parity bit generator 42. However, the decoder, interleaver and parity bit generator may each be any means such as a device or circuitry embodied in hardware, software, or a combination of hardware and software (e.g., the processor operating under software control, the processor embodied as an ASIC or FPGA specifically configured to perform the operations described herein, or a combination thereof) that is configured to perform the corresponding functions of the decoder, interleaver and parity bit generator, as described herein. In an exemplary embodiment, any or all of the decoder, interleaver and parity bit generator may include instructions, code, modules, applications, and/or circuitry for providing respective portions of the decoding, interleaving and pixel bit generation functions, respectively. However, it should be noted that the code, circuitry and/or instructions associated with the decoder, interleaver and parity bit generator may not necessarily be modular.

In this regard, the processor 30 of the first relay node Rl may unmask the first source transmission and the decoder 38 may then decode the data. Thereafter, the interleaver 40 may interleave the data, such as by random interleaving, and the parity bit generator 42 may then determine the respective vector of parity bits P_2, i for the interleaved data. The interleaver may then again interleave the original data and the parity bit generator may again determine the respective vector of parity bits P₃, i for the newly interleaved version of the data. The repeated interleaving and parity bit generation may be repeated a pre-determined number of times until K vectors of parity bits have been generated.

During the second time slot t₂, the source node S may transmit a second source transmission x₂ = {Di_j2,Pi_j2} to both the destination node D and the second relay node R2. See, for example, the second time period t₂ in the time line of Figure 7 and the signal flow of Figure 10, which depicts the data and the vectors of parity bits that flow between the source, relay and destination nodes during even numbered time slots (that is, n=2, 4, ...), such as t₂, t₄,... Like the first source transmission, the second source transmission comprises a masked, encoded representation of the data and the associated vector of parity bits generated by the source node, such as in accordance with zig-zag coding. During this second time slot t₂, the first relay node Rl may also transmit the additional vectors of parity bits xip = {P₂,i, P₂,i,...,Pκ,i} that have been generated based upon the data of the first source transmission, that is, the source transmission from the prior time slot, to the destination node via a second relay transmission. As before, the second source transmission may be masked by a first mask, such as a first pseudorandom number sequence PNi. However, the second relay transmission of the additional plurality of vectors of parity bits may be masked by the first relay node, such as the processor 30 of the first relay node, by a second mask, such as a second pseudorandom number sequence PN₂. In one embodiment, the first and second masks, such as the PN] and PN₂ sequences, are orthogonal to one another. By utilizing two different masks, the destination node D can concurrently receive and decode transmissions received from both the source node and a relay node utilizing a CDM scheme.

As described above in conjunction with the first relay node Rl, the second relay node R2 may receive the second source transmission and following unmasking and decoding of the data, the second relay node may repeatedly interleave the data and generate an additional vector of parity bits for each differently interleaved version of the data, thereby generating x₂p = {P₂₎₂,P₃,₂,...,Pκ;_}- Thereafter, in the third time slot t₃ as shown in Figures 7 and 8, the source node S may provide a third source transmission to both the first relay node and the destination node D including an encoded representation of additional data and the associated vector of parity bits x₃ = {Di ₃,Pi_j3}, while the second relay node may provides a third relay transmission including the additional plurality of vectors of parity bits generated by the second relay node based upon the data included in the second source transmission. As with the prior relay transmissions, the third relay transmission may be masked with the second mask, such as a second pseudorandom number sequence PN₂.

This process of the source node S transmitting a new source transmission to the destination node D and to alternating ones of the relay nodes, while permitting the other relay node to transmit an additional plurality of vectors of parity bits for the data that was transmitted by the source node during the immediately preceding time period may be repeated during successive time slots as shown in Figure 7. Since a new set of information data is transmitted in each time slot, the method, apparatus and computer program products of one embodiment of the present invention provide for full-rate data transmission utilizing the cooperative relay system. As such, the resulting coding rate may be J/(J+K).

As described above and as shown in operation 50 of Figure 11, during the first time slot ti, the destination node D may include means for receiving the first source transmission and the first relay transmission. The destination node may be configured in a variety of manners, but, in one embodiment, may be configured as shown in Figure 12. In this regard, the destination node may include a processor 60, a memory device 62, a receiver 64, a transmitter 66 and a decoder 68. The processor may be embodied in a number of different ways. For example, the processor may be embodied as various processing means such as a processing element, a co-processor, a controller or various other processing devices including integrated circuits such as, for example, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), a hardware accelerator or the like. In an exemplary embodiment, the processor may be configured to execute instructions stored in the memory device or otherwise accessible to the processor. As such, whether configured by hardware or software or a combination thereof, the processor may represent an entity capable of performing operations according to embodiments of the present invention while configured accordingly.

The receiver 64 and transmitter 66 may be combined as a transceiver or may be separately provided for receiving and transmitting signals, respectively. The memory device 62 may include, for example, volatile and/or non-volatile memory. The memory device may be configured to store information, data, applications, instructions or the like for enabling the destination node D to carry out the various functions in accordance with exemplary embodiments of the present invention. For example, the memory device could be configured to buffer input data for processing by the processor 60. Additionally or alternatively, the memory device could be configured to store instructions for execution by the processor.

In an exemplary embodiment, the processor 60 may be embodied as, include or otherwise control the decoder 68. However, the decoder may each be any means such as a device or circuitry embodied in hardware, software, or a combination of hardware and software (e.g., the processor operating under software control, the processor embodied as an ASIC or FPGA specifically configured to perform the operations described herein, or a combination thereof) that is configured to perform the functions of the decoder, as described herein. In an exemplary embodiment, the decoder may include instructions, code, modules, applications, and/or circuitry for providing the decoding function.

As such, the means for receiving the first source transmission and the first relay transmission may be embodied by the processor 60 and/or the receiver 64 in accordance with the illustrated embodiment. Additionally, the processor 60 of the destination node D may unmask the first source transmission, such as with a first mask, e.g., PNl, and may unmask the first relay transmission, such as with a second mask, e.g., PN2. As shown at operation 52 of Figure 11, the destination node may include means, such as the processor and/or the decoder 68, for beginning to decode the data of the first source transmission, such as by means of an iterative decoding process. In this regard, the first source transmission may be represented as y_s._D = h_s._Dx + n_S-_D wherein x is the coded bit stream including both the data and the parity bits, n_s._D is the added Gaussian noise and h_s._D is the channel coefficient for the direct path between the source and destination nodes as shown in Figure 5. The destination node, such as the decoder, initially decodes the signal y_s._D received from the direct path from the source node. During this initial decoding process, the decoder may utilize equal a priori bit information such that the external extrinsic information becomes zero. Concurrent with the initial decoding of the data from the first source transmission, the destination node, such as the decoder, may complete the decoding of the data from the prior source transmission (such as from time slot to) using additional parity bits from the first relay transmission x_Op from the second relay node R2.

The source transmission received by the first relay node Rl from the source node S during the same time period ti may be represented as y_s._R = h_s._Rx + n_SRD wherein Π_S._R is the added Gaussian noise and h_s._R is the channel coefficient between the source and relay nodes, as also shown in Figure 5. As described above, at the first relay node, the coded bit stream is decoded and a plurality of vectors of parity bits {P_2;i,P_3;i ...,Pκ_,i } are generated for the differently interleaved versions of the same data. During the second time slot t₂, the first relay node transmits the vectors of parity bits to the destination node D. As indicated at operation 54 of Figure 11 , during the second time slot t₂, the destination node may include means, such as the processor 60 and/or the receiver 64, for receiving a second source transmission from the source node as well as the second relay transmission from the first relay node containing the additional vectors of parity bits associated with the data from the first source transmission. As such, the composite signal received by the destination node relating to the data from the first source transmission includes both the first source transmission and the additional vectors of parity bits provided via the second

relay transmission and may be represented as yr_j = ys -D , i

+ ⁿb wherein

YR-D yR_D = h^pP¹ + IIR__D with P¹ being the i-th parity (i=2, 3, ..., K) for the original data and hk__D,nR_D being the corresponding channel coefficients and the added Gaussian noise during transmission of the i-th parity bits.

Upon receipt, from the first relay node Rl, of the additional vectors of parity bits for the data originally provided via the first source transmission, the destination node D, such as the decoder 68, may complete the decoding of the data from the first source transmission, as shown at operation 56 of Figure 1 1 , by using the additional vectors of parity bits to enhance the decoding performance in an iterative manner. In this regard, at iteration i + 1 , the soft-bit information that is used by the decoder becomes a function of the Log Likelihood Ratio (LLR) as given by:

wherein λ^ι~ (x) is the extrinsic information used in the i-th iteration by the decoder. In addition to completing the decoding of the data from the first source transmission, the destination node, such as the decoder, may also begin to decode the data from the second source transmission utilizing the vector of parity bits provided with the second source transmission. The process depicted in Figure 11 may then be repeated for additional source and relay transmissions.

It may be noted that the use of more additional vectors of parity bits may improve the performance without changing the coding rate. For example, Figures 13 and 14 depict the bit error rate (BER) and the packet error rate (PER), respectively, as a function of the signal to noise ratio (Eb/No) at the receiver front end for the transmission of data from a source node S to a destination node D utilizing a pair of cooperative relay nodes configured to provide different numbers N_p of parity bit vectors. In the example depicted in Figures 13 and 14, the data block length is 996 bits, zig-zag coding was employed having I = 83, J = 12 and K = 3, a coding rate of 0.8 was utilized, and random interleaving was employed along with Binary Phase Shift Keying (BPSK) modulation. As illustrated in Figures 13 and 14, as the number of vectors of parity bits increases from 1 to 10, both the bit error rate and the packet error rate decrease.

As such, the methods, apparatus and computer program products of an exemplary embodiment of the present invention provides for full-rate data transmission utilizing a cooperative relay system. The methods, apparatus and computer program products of the present invention may also provide additional advantages with one exemplary embodiment permitting the transmit power from the source node to the destination node to be reduced by using the zig-zag parity check bits obtained from the relay nodes. Additionally, the methods, apparatus and computer program products of an exemplary embodiment of the present invention reduces the time and bandwidth requirements for the relay nodes to communicate with the destination node since the relay nodes merely transmit parity bits as opposed to different versions of the code word. Methods, apparatus and computer program products of an exemplary embodiment of the present invention also reduce the retransmission frequencies with a reasonable number of parity bits.

Figure 11 is a flowchart of operations performed by the destination node D according to some exemplary embodiments of the invention. As with the operations of the source and relay nodes described above, it will be understood that each block or step of the flowchart, and combinations of blocks in the flowchart, can be implemented by various means, such as hardware, firmware, and/or software including one or more computer program instructions. For example, one or more of the procedures described above may be embodied by computer program instructions. In this regard, the computer program instructions which embody the procedures described above may be stored by a memory device of the respective node employing embodiments of the present invention and executed by a processor of the respective node. As will be appreciated, any such computer program instructions may be loaded onto a computer or other programmable apparatus (i.e., hardware) to produce a machine, such that the instructions which execute on the computer (e.g., via a processor) or other programmable apparatus create means for implementing the above-described functions, such as those specified in the flowchart block(s) or step(s). These computer program instructions may also be stored in a computer-readable memory that can direct a computer (e.g., a processor or another computing device) or other programmable apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the above-described functions, such as those specified in the flowchart block(s) or step(s). The computer program instructions may also be loaded onto a computer or other programmable apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block(s) or step(s).

Accordingly, blocks or steps of the flowchart support combinations of means for performing the specified functions, combinations of steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that one or more blocks or steps of the flowchart, and combinations of blocks or steps in the flowchart, can be implemented by special purpose hardware-based computer systems which perform the specified functions or steps, or combinations of special purpose hardware and computer instructions.

In an exemplary embodiment, an apparatus for performing the method of Figure 11 above may comprise a processor (e.g., the processor 60) configured to perform some or each of the operations (50-56) described above. The processor may, for example, be configured to perform the operations (50-56) by performing hardware implemented logical functions, executing stored instructions, or executing algorithms for performing each of the operations. Alternatively, the apparatus may comprise means for performing each of the operations described above. In this regard, according to an example embodiment, examples of means for performing operations 50-56 may comprise, for example, the processor 60 and/or the decoder 68, as described above.

Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these inventions pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. For example, while the cooperative relay system was described above to have first and second relay nodes, the cooperative relay system of other embodiments may include additional relay nodes. In addition, the zig-zag coding schem may also be extended to other coding schemes, such as turbo coding, etc. Moreover, although the foregoing descriptions and the associated drawings describe exemplary embodiments in the context of certain exemplary combinations of elements and/or functions, it should be appreciated that different combinations of elements and/or functions may be provided by alternative embodiments without departing from the scope of the appended claims. In this regard, for example, different combinations of elements and/or functions than those explicitly described above are also contemplated as may be set forth in some of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

THAT WHICH IS CLAIMED:

1. A method comprising: receiving, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission; receiving, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission; and decoding, at a destination node, the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

2. A method according to Claim 1 further comprising: receiving, in a third time slot, a third source transmission from a source node comprising data and associated parity check bits and a third relay transmission from the first relay node comprising parity check bits associated with data from a second source transmission; and decoding the data from the second source transmission at least partially based on the second source transmission and the third relay transmission.

3. A method according to Claim 1 wherein receiving the first source transmission comprises receiving the first source transmission masked with a first mask and receiving the first relay transmission comprises receiving the first relay transmission masked with a second mask, wherein receiving the second source transmission comprises receiving the second source transmission masked with the first mask and receiving the second relay transmission comprises receiving the first relay transmission masked with the second mask, and wherein the method further comprises unmasking the first and second source transmissions in accordance with the first mask and desmasking the first and second relay transmissions in accordance with the second mask prior to decoding the data.

4. A method according to Claim 1 wherein receiving the first and second relay transmissions comprises receiving parity check bits without any associated data.

5. A method according to Claim 1 wherein decoding the data comprises iteratively decoding the data initially at least partially based on the first source transmission and subsequently at least partially based on both the first source transmission and the second relay transmission.

6. A method according to Claim 1 wherein receiving the first relay transmission comprises receiving a plurality of parity check bits associated with differently interleaved representations of the data from the prior source transmission, and wherein receiving the second relay transmission comprises receiving a plurality of parity check bits associated with differently interleaved representations of the data from the first source transmission.

7. An apparatus comprising a processor configured to: receive, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission; receive, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission; and decode the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

8. An apparatus according to Claim 7 wherein the processor is further configured to: receive, in a third time slot, a third source transmission from a source node comprising data and associated parity check bits and a third relay transmission from the first relay node comprising parity check bits associated with data from a second source transmission; and decode the data from the second source transmission at least partially based on the second source transmission and the third relay transmission.

9. A apparatus according to Claim 7 wherein the processor is configured to receive the first source transmission by receiving the first source transmission masked with a first mask and to receive the first relay transmission by receiving the first relay transmission masked with a second mask, wherein the processor is configured to receive the second source transmission by receiving the second source transmission masked with the first mask and to receive the second relay transmission by receiving the first relay transmission masked with the second mask, and wherein the processor is further configured to unmask the first and second source transmissions in accordance with the first mask and to desmask the first and second relay transmissions in accordance with the second mask prior to decoding the data.

10. An apparatus according to Claim 7 wherein the processor is configured to receive the first and second relay transmissions by receiving parity check bits without any associated data.

11. An apparatus according to Claim 7 wherein the processor is configured to decode the data by iteratively decoding the data initially at least partially based on the first source transmission and subsequently at least partially based on both the first source transmission and the second relay transmission.

12. An apparatus according to Claim 7 wherein the processor is configured to receive the first relay transmission by receiving a plurality of parity check bits associated with differently interleaved representations of the data from the prior source transmission, and wherein the processor is configured to receive the second relay transmission by receiving a plurality of parity check bits associated with differently interleaved representations of the data from the first source transmission.

13. An apparatus according to Claim 7 wherein the processor is configured to receive the first and second relay transmissions by the receiving parity check bits generated by zig-zag coding of the associated data.

14. A computer program product comprising a computer-readable storage medium having computer-executable program code instructions stored therein, the computer executable program code instructions comprising: program code instructions for receiving, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission; program code instructions for receiving, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission; and program code instructions for decoding the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.

15. A computer program product according to Claim 14 further comprising: program code instructions for receiving, in a third time slot, a third source transmission from a source node comprising data and associated parity check bits and a third relay transmission from the first relay node comprising parity check bits associated with data from a second source transmission; and program code instructions for decoding the data from the second source transmission at least partially based on the second source transmission and the third relay transmission.

16. A computer program product according to Claim 14 wherein the program code instructions for receiving the first source transmission comprise program code instructions for receiving the first source transmission masked with a first mask and the program code instructions for receiving the first relay transmission comprise program code instructions for receiving the first relay transmission masked with a second mask, wherein the program code instructions for receiving the second source transmission comprise program code instructions for receiving the second source transmission masked with the first mask and the program code instructions for receiving the second relay transmission comprise program code instructions for receiving the first relay transmission masked with the second mask, and wherein the method further comprises program code instructions for unmasking the first and second source transmissions in accordance with the first mask and desmasking the first and second relay transmissions in accordance with the second mask prior to decoding the data.

17. A computer program product according to Claim 14 wherein the program code instructions for receiving the first and second relay transmissions comprise program code instructions for receiving parity check bits without any associated data.

18. A computer program product according to Claim 14 wherein the program code instructions for decoding the data comprise program code instructions for iteratively decoding the data initially at least partially based on the first source transmission and subsequently at least partially based on both the first source transmission and the second relay transmission.

19. A computer program product according to Claim 14 wherein the program code instructions for receiving the first relay transmission comprise program code instructions for receiving a plurality of parity check bits associated with differently interleaved representations of the data from the prior source transmission, and wherein the program code instructions for receiving the second relay transmission comprise program code instructions for receiving a plurality of parity check bits associated with differently interleaved representations of the data from the first source transmission.

20. An apparatus comprising: means for receiving, in a first time slot, a first source transmission from a source node comprising data and associated parity check bits and a first relay transmission from a first relay node comprising parity check bits associated with data from a prior source transmission; means for receiving, in a second time slot, a second source transmission from the source node comprising data and associated parity check bits and a second relay transmission from a second relay node comprising parity check bits associated with the data from the first source transmission; and means for decoding the data from the first source transmission at least partially based on the first source transmission and the second relay transmission.