WO2010064362A1 - Field effect transistor - Google Patents

Field effect transistor Download PDF

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Publication number
WO2010064362A1
WO2010064362A1 PCT/JP2009/006038 JP2009006038W WO2010064362A1 WO 2010064362 A1 WO2010064362 A1 WO 2010064362A1 JP 2009006038 W JP2009006038 W JP 2009006038W WO 2010064362 A1 WO2010064362 A1 WO 2010064362A1
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Prior art keywords
semiconductor layer
nitride semiconductor
fet
field effect
effect transistor
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PCT/JP2009/006038
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French (fr)
Japanese (ja)
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按田義治
石田秀俊
上田哲三
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パナソニック株式会社
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Priority to CN200980148577.4A priority Critical patent/CN102239550A/en
Publication of WO2010064362A1 publication Critical patent/WO2010064362A1/en
Priority to US13/118,945 priority patent/US20110227132A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a field effect transistor, and more particularly to a field effect transistor composed of a group III nitride semiconductor.
  • Group III nitride semiconductors typified by gallium nitride (GaN) have a large band gap, a high breakdown electric field, and a high saturation electron velocity that surpass silicon and gallium arsenide. Because of this physical advantage, field effect transistors (FETs) using group III nitride semiconductors are promising as next-generation high-frequency devices and high-power switching devices, and are actively researched and developed.
  • GaN gallium nitride
  • the above-mentioned FET is required to achieve both a high breakdown voltage and a high on-resistance, but generally both are in a trade-off relationship with the same material. Further, normally-off FETs are required for high power switching devices, and the parasitic resistance between the gate and the source and between the gate and the drain tends to be further increased. It is also known that a high density trap level exists on the surface of the group III nitride semiconductor, and the trap level trapped during high-speed switching operation cannot follow switching, resulting in a current collapse in which the drain current decreases. It has been.
  • FIG. 8 is a cross-sectional view showing the structure of the FET described in Patent Document 1.
  • FIG. 8 is a cross-sectional view showing the structure of the FET described in Patent Document 1.
  • a carrier traveling layer 802 and a carrier supply layer 803 are provided on a substrate 801, and a GaN-based protective layer 804 is provided on the upper surface of the carrier supply layer 803. .
  • the surface of the GaN-based protective layer 804 is covered with a protective layer 805 made of silicon nitride (SiN) between the gate electrode 806 and the source electrode 808 and between the gate electrode 806 and the drain electrode 807. .
  • SiN silicon nitride
  • the on-resistance cannot be said to be sufficiently low, and further reduction of the on-resistance is required.
  • the breakdown voltage of the element is determined by the distance between the gate electrode and the drain electrode. Increasing the distance improves the breakdown voltage, but increases the parasitic resistance between the gate and the drain and increases the on-resistance.
  • the on-resistance is sufficiently low as a power loss in both the high-frequency device and the high-power switching device. In the future, it will be necessary to further reduce the on-resistance for higher performance FETs. An improvement in the device structure is effective in reducing the on-resistance.
  • normally-off type FETs tend to increase the parasitic resistance between the gate and the source and between the gate and the drain.
  • the influence of the surface state is suppressed and consideration is given to an increase in the parasitic resistance.
  • further resistance reduction is necessary.
  • the present invention has been made to solve the above problems, and an object thereof is to provide a field effect transistor having a low on-resistance.
  • a field effect transistor according to the present invention is formed on a first nitride semiconductor layer and the first nitride semiconductor layer, and more than the first nitride semiconductor layer.
  • a fourth nitride semiconductor layer having a band gap energy larger than that of the third nitride semiconductor layer, and a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.
  • a channel is formed.
  • the heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer but also between the third nitride semiconductor layer and the fourth nitride semiconductor layer.
  • a channel is also formed at the heterojunction interface. That is, in addition to the conventional two-dimensional electron gas forming the channel, a two-dimensional electron gas is further formed on the surface side. Therefore, sheet resistance can be reduced and on-resistance can be reduced.
  • the channel is moved away from the semiconductor layer on the outermost surface side of the FET as compared with the conventional FET, the influence of the surface level on the channel can be reduced. As a result, current collapse due to the surface state can be suppressed.
  • the two heterojunction interfaces are formed of a nitride semiconductor, a two-dimensional electron gas is generated at the heterojunction interface due to piezo polarization and spontaneous polarization resulting from lattice mismatch. Therefore, since it is not necessary to add impurities for forming the channel, a high breakdown voltage FET can be realized.
  • the gate electrode of the field effect transistor is formed in a recess provided in the fourth nitride semiconductor layer.
  • the channel can be brought close to the gate electrode while keeping the channel away from the semiconductor layer on the outermost surface side of the FET. As a result, it is possible to easily control the threshold voltage of the gate while suppressing current collapse.
  • the recess penetrates a heterojunction interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer.
  • the recess penetrates through the third nitride semiconductor layer and the fourth nitride semiconductor layer to reach the surface of the second nitride semiconductor layer, and the second as the bottom surface of the recess.
  • the surface of the nitride semiconductor layer is preferably flush with the interface between the second nitride semiconductor layer and the third nitride semiconductor layer.
  • the gate threshold voltage is determined by the film thickness and Al composition ratio of the second nitride semiconductor layer, the gate threshold voltage can be easily controlled. Therefore, an FET having a uniform gate threshold voltage in the wafer surface can be realized.
  • the field effect transistor preferably further includes an insulating film formed on the bottom surface of the recess.
  • the FET is made into a MIS (Metal Insulator Semiconductor) structure, the current flowing into the gate can be suppressed and a positive bias can be applied to the gate electrode, so that an effective structure as a normally-off type FET can be realized.
  • MIS Metal Insulator Semiconductor
  • the field effect transistor further includes a fifth nitride semiconductor layer formed on a bottom surface of the recess, and an insulating film formed between the gate electrode and the fifth nitride semiconductor layer. It is preferable to provide.
  • the insulating film can be formed continuously with the epitaxial growth of the fifth nitride semiconductor layer in the recess, an insulating film having good insulating characteristics can be realized.
  • the insulating film is preferably made of a laminated structure of silicon nitride and aluminum nitride.
  • the insulating film contains AlN excellent in heat conduction, an FET that is particularly effective for a device that drives a large power can be realized.
  • the insulating film is preferably formed by an atomic layer deposition apparatus.
  • the film thickness of the second nitride semiconductor layer is preferably smaller than the film thickness of the fourth nitride semiconductor layer.
  • the electrons in the channel at the heterojunction interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer are converted into the first nitride semiconductor layer and the second nitride semiconductor layer.
  • the channel resistance can be further reduced, and the on-resistance can be reduced.
  • the thickness of the second nitride semiconductor layer directly under the gate electrode can be reduced, a configuration effective for a normally-off type FET can be realized.
  • the source electrode and the drain electrode of the field effect transistor respectively include a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer. It is preferable to contact the heterojunction interface of the nitride semiconductor layer.
  • the contact resistance of the source electrode and the drain electrode can be reduced.
  • a low on-resistance can be realized in an FET composed of a nitride semiconductor.
  • FIG. 1 is a cross-sectional view showing the configuration of the FET according to the first embodiment of the present invention.
  • FIG. 2 is an energy band diagram of the FET according to the embodiment.
  • FIG. 3A is a diagram showing an FET having a single channel structure.
  • FIG. 3B is a diagram showing a FET having a double channel structure.
  • FIG. 3C is a diagram illustrating experimental results of the relationship between the breakdown voltage and the on-resistance in the diode characteristics of the gate electrode and the drain electrode.
  • FIG. 4 is a cross-sectional view showing the configuration of the FET according to the second exemplary embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing the configuration of the FET according to the third exemplary embodiment of the present invention.
  • FIG. 6 is a cross-sectional view showing the configuration of the FET according to the fourth exemplary embodiment of the present invention.
  • FIG. 7 is a sectional view showing the structure of an FET according to the fifth embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing the structure of a conventional FET.
  • FIG. 1 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
  • This FET includes a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 105, and a fourth nitride semiconductor layer.
  • 106 an insulating film 107, a drain electrode 108, a source electrode 109, a gate electrode 110, and an element isolation layer 111.
  • the substrate 101 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, or a GaN substrate having a thickness (film thickness) of 10 ⁇ m or more and 1000 ⁇ m or less.
  • the buffer layer 102 is made of AlN having a thickness corresponding to the substrate 101, for example, 100 nm, and is formed on the substrate 101.
  • the first nitride semiconductor layer 103 is made of undoped GaN having a thickness of 2 ⁇ m, for example, and is formed on the buffer layer 102.
  • “undoped” means that impurities are not intentionally introduced.
  • the second nitride semiconductor layer 104 is formed on the first nitride semiconductor layer 103 and has a larger band gap energy than the first nitride semiconductor layer 103.
  • the second nitride semiconductor layer 104 is made of, for example, undoped Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the second nitride semiconductor layer 104 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 20 nm.
  • the third nitride semiconductor layer 105 is formed on the second nitride semiconductor layer 104 and has a lower band gap energy than the second nitride semiconductor layer 104.
  • the third nitride semiconductor layer 105 is made of undoped GaN having a thickness of 20 nm, for example.
  • the fourth nitride semiconductor layer 106 is formed on the third nitride semiconductor layer 105 and has a larger band gap energy than the third nitride semiconductor layer 105.
  • the fourth nitride semiconductor layer 106 is made of, for example, undoped Al y Ga 1-y N (0 ⁇ y ⁇ 1).
  • the fourth nitride semiconductor layer 106 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
  • Spontaneous polarization occurs between the heterojunction interface of the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 and the heterojunction interface of the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106.
  • electric charges of, for example, about 1 ⁇ 10 13 cm ⁇ 2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
  • the drain electrode 108 and the source electrode 109 are formed in regions on both sides of the gate electrode 110, and the heterojunction interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 and the third nitride, respectively. It is in contact with the heterojunction interface between the semiconductor layer 105 and the fourth nitride semiconductor layer 106 and is electrically connected to the electron transit region (channel) generated in the interface region.
  • the drain electrode 108 and the source electrode 109 are in contact with the first nitride semiconductor layer 103.
  • the drain electrode 108 and the source electrode 109 are composed of, for example, a laminated structure of Ti and Al.
  • a recess 120 is formed in the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106.
  • the recess 120 penetrates the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106. And reaches the surface of the second nitride semiconductor layer 104.
  • a gate electrode 110 is formed in the recess 120.
  • the gate electrode 110 is made of, for example, palladium (Pd), nickel (Ni), platinum (Pt), or the like. Note that the gate electrode 110 may be made of Ti when the material constituting the gate electrode 110 is not diffused into the nitride semiconductor layer by the insulating film 107.
  • the insulating film 107 is formed on the bottom and side surfaces of the recess 120 and the surface of the fourth nitride semiconductor layer 106.
  • the insulating film 107 formed on the bottom and side surfaces of the recess 120 is sandwiched between the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, the fourth nitride semiconductor layer 106, and the gate electrode 110. Yes.
  • the insulating film 107 includes, for example, silicon nitride (SiN), silicon oxide (SiO), aluminum nitride (AlN), aluminum oxide (AlO), a stacked structure of SiN and AlN, a stacked structure of SiN and AlO, and the like.
  • SiN silicon nitride
  • SiO silicon oxide
  • AlN aluminum nitride
  • AlO aluminum oxide
  • a stacked structure of SiN and AlN a stacked structure of SiN and AlO, and the like.
  • the insulating film 107 is made of SiN or SiO
  • the insulating film 107 is formed by, for example, a plasma chemical vapor deposition (CVD) method or a low pressure CVD method.
  • CVD plasma chemical vapor deposition
  • the insulating film 107 is made of AlN or AlO
  • the insulating film 107 is formed by, for example, a sputtering method or an atomic layer deposition method (atomic layer deposition: ALD method) using an atomic layer deposition apparatus.
  • the element isolation layer 111 is formed by ion-implanting impurities such as boron (B) into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
  • impurities such as boron (B)
  • FIG. 2 is an energy band diagram of the FET according to the present embodiment.
  • a two-dimensional electron gas is generated at the heterojunction interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, and a channel (referred to as a bulk side channel) is formed.
  • a two-dimensional electron gas is generated at the heterojunction interface between the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106, whereby a channel (referred to as a surface side channel) is also formed on the surface side. ing.
  • a channel referred to as a surface side channel
  • the on-resistance can be reduced by the reduced channel resistance.
  • the bulk side channel is away from the semiconductor layer (the surface of the fourth nitride semiconductor layer 106) on the outermost surface side of the FET, the influence of the surface level on the channel is not increased. Reduced. As a result, current collapse due to the surface state can be suppressed.
  • the Al composition ratio of the fourth nitride semiconductor layer 106 is higher than the Al composition ratio of the second nitride semiconductor layer 104 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel.
  • the larger one is desirable, and the thickness of the fourth nitride semiconductor layer 106 is desirably larger than the thickness of the second nitride semiconductor layer 104.
  • the thickness of the second nitride semiconductor layer 104 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 106.
  • two heterojunction interfaces are formed by a laminated structure of, for example, GaN / AlGaN / GaN / AlGaN.
  • a two-dimensional electron gas is generated at the interface between the two heterojunctions due to piezoelectric polarization caused by lattice mismatch between AlGaN and GaN and spontaneous polarization caused by the GaN-based layer itself. Accordingly, since a plurality of electron transit layers (channels) formed at the AlGaN / GaN heterojunction interface are provided, the on-resistance between the gate electrode 110 and the source electrode 109 and between the gate electrode 110 and the drain electrode 108 is provided. Can be reduced.
  • 3C shows the breakdown voltage and on-resistance in the diode characteristics of the gate electrode 110 and the drain electrode 108 for the single channel structure having one electron transit layer of FIG. 3A and the double channel structure having two electron transit layers of FIG. 3B. It shows the experimental result of the relationship.
  • FIG. 3C shows that the on-resistance can be reduced to about half in the double channel structure when the breakdown voltage is almost the same in both cases. Therefore, for example, by using a laminated structure of GaN / AlGaN / GaN / AlGaN, the amount of electrons traveling with respect to a conventional FET having only one heterojunction interface of GaN / AlGaN is increased, and the on-resistance is reduced. Is possible. By providing this double channel structure on both sides of the gate electrode 110, the parasitic resistance of the source and drain of the FET can be suppressed to about half while maintaining the same breakdown voltage.
  • the drain side is usually a portion where the electric field is concentrated, but even if a multi-layer electron transit layer is provided, the breakdown voltage is not lowered.
  • the longitudinal resistance of the laminated structure of GaN / AlGaN / GaN / AlGaN can be reduced by designing the film thickness and composition of each nitride semiconductor layer.
  • the insulating film 107 is provided under the gate electrode 110 and the MIS structure is adopted. Therefore, the current flowing into the gate electrode 110 can be suppressed, a positive bias can be applied to the gate electrode 110, and an effective structure as a normally-off type FET can be realized.
  • the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106 contain In. May be.
  • the first nitride semiconductor layer 103 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
  • another semiconductor layer may be disposed on the fourth nitride semiconductor layer 106.
  • the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106 include, for example, Si.
  • N-type impurities such as n-type impurities may be doped.
  • the depth of the recess 120 is a depth that penetrates the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106. If the distance to the channel can be shortened, the depth is not limited to this.
  • the depth of the recess 120 is a depth that stops in the middle of the fourth nitride semiconductor layer 106 without reaching the third nitride semiconductor layer 105, or penetrates the fourth nitride semiconductor layer 106, 3 may be a depth that stops halfway through the nitride semiconductor layer 105.
  • FIG. 4 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
  • the FET includes a substrate 201, a buffer layer 202, a first nitride semiconductor layer 203, a second nitride semiconductor layer 204, a third nitride semiconductor layer 205, and a fourth nitride semiconductor layer. 206, an insulating film 207, a drain electrode 208, a source electrode 209, a gate electrode 210, and an element isolation layer 211.
  • the substrate 201 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, or a GaN substrate having a thickness of 10 ⁇ m or more and 1000 ⁇ m or less.
  • the buffer layer 202 is made of AlN having a thickness corresponding to the substrate 201, for example, 100 nm, and is formed on the substrate 201.
  • the first nitride semiconductor layer 203 is made of undoped GaN having a thickness of 2 ⁇ m, for example, and is formed on the buffer layer 202.
  • the second nitride semiconductor layer 204 is formed on the first nitride semiconductor layer 203 and has a larger band gap energy than the first nitride semiconductor layer 203.
  • the second nitride semiconductor layer 204 is made of, for example, undoped Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the second nitride semiconductor layer 204 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 20 nm.
  • the third nitride semiconductor layer 205 is formed on the second nitride semiconductor layer 204 and has a lower band gap energy than the second nitride semiconductor layer 204.
  • the third nitride semiconductor layer 205 is made of undoped GaN having a thickness of 20 nm, for example.
  • the fourth nitride semiconductor layer 206 is formed on the third nitride semiconductor layer 205 and has a larger band gap energy than the third nitride semiconductor layer 205.
  • the fourth nitride semiconductor layer 206 is made of, for example, undoped Al y Ga 1-y N (0 ⁇ y ⁇ 1).
  • the fourth nitride semiconductor layer 206 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
  • Spontaneous polarization occurs between the heterojunction interface of the first nitride semiconductor layer 203 and the second nitride semiconductor layer 204 and the heterojunction interface of the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206.
  • electric charges of, for example, about 1 ⁇ 10 13 cm ⁇ 2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
  • the Al composition ratio of the fourth nitride semiconductor layer 206 is higher than the Al composition ratio of the second nitride semiconductor layer 204 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel.
  • the larger one is desirable, and the thickness of the fourth nitride semiconductor layer 206 is desirably larger than the thickness of the second nitride semiconductor layer 204.
  • the thickness of the second nitride semiconductor layer 204 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 206.
  • the drain electrode 208 and the source electrode 209 are formed in regions on both sides of the gate electrode 210, and the heterojunction interface between the first nitride semiconductor layer 203 and the second nitride semiconductor layer 204 and the third nitride, respectively. It contacts the heterojunction interface between the semiconductor layer 205 and the fourth nitride semiconductor layer 206 and is electrically connected to the electron transit region generated in the interface region.
  • the drain electrode 208 and the source electrode 209 are in contact with the first nitride semiconductor layer 203.
  • the drain electrode 208 and the source electrode 209 are made of, for example, a laminated structure of Ti and Al.
  • a recess 220 is formed in the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206.
  • the recess 220 penetrates the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206. And reaches the surface of the second nitride semiconductor layer 204.
  • a gate electrode 210 is formed in the recess 220.
  • the recess 220 is formed by selectively etching the third nitride semiconductor layer 205 with respect to the second nitride semiconductor layer 204 in particular.
  • the concave portion 220 is not formed in the second nitride semiconductor layer 204, and the surface of the second nitride semiconductor layer 204 serving as the bottom surface of the concave portion 220 is the second nitride semiconductor layer 204 and the second nitride semiconductor layer 204. 3 is flush with the interface of the nitride semiconductor layer 205.
  • the gate electrode 210 is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 210 may be made of Ti when the material constituting the gate electrode 210 is not diffused into the nitride semiconductor layer by the insulating film 207.
  • the insulating film 207 is formed on the bottom and side surfaces of the recess 220 and the surface of the fourth nitride semiconductor layer 206.
  • the insulating film 207 formed on the bottom and side surfaces of the recess 220 is sandwiched between the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, the fourth nitride semiconductor layer 206, and the gate electrode 210. Yes.
  • the insulating film 207 includes, for example, a stacked structure of SiN, SiO, AlN, AlO, SiN, and AlN, a stacked structure of SiN and AlO, and the like.
  • the insulating film 207 is formed by, for example, a CVD method or a low pressure CVD method.
  • the insulating film 207 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
  • the element isolation layer 211 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
  • the on-resistance can be reduced for the same reason as the FET of the first embodiment.
  • an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
  • the recess 220 is formed by selective etching, and the thickness of the second nitride semiconductor layer 204 immediately below the gate electrode 210 can be accurately controlled. Therefore, it becomes easy to adjust the threshold voltage of the gate.
  • the first nitride semiconductor layer 203, the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, and the fourth nitride semiconductor layer 206 contain In. May be.
  • the first nitride semiconductor layer 203 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
  • another semiconductor layer may be disposed on the fourth nitride semiconductor layer 206.
  • the first nitride semiconductor layer 203, the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, and the fourth nitride semiconductor layer 206 include, for example, Si.
  • N-type impurities such as n-type impurities may be doped.
  • FIG. 5 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
  • the FET includes a substrate 301, a buffer layer 302, a first nitride semiconductor layer 303, a second nitride semiconductor layer 304, a third nitride semiconductor layer 305, and a fourth nitride semiconductor layer.
  • 306 an insulating film 307, a drain electrode 308, a source electrode 309, a gate electrode 310, an element isolation layer 311, and a fifth nitride semiconductor layer 312.
  • the substrate 301 is, for example, a sapphire substrate having a thickness of 10 ⁇ m or more and 1000 ⁇ m or less, a SiC substrate, a Si substrate, a GaN substrate, or the like.
  • the buffer layer 302 is made of AlN having a thickness corresponding to the substrate 301, for example, 100 nm, and is formed on the substrate 301.
  • the first nitride semiconductor layer 303 is made of undoped GaN having a thickness of 2 ⁇ m, for example, and is formed on the buffer layer 302.
  • the second nitride semiconductor layer 304 is formed on the first nitride semiconductor layer 303 and has a larger band gap energy than the first nitride semiconductor layer 303.
  • the second nitride semiconductor layer 304 is made of, for example, undoped Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the second nitride semiconductor layer 304 is composed of 20 nm thick undoped Al 0.25 Ga 0.75 N.
  • the third nitride semiconductor layer 305 is formed on the second nitride semiconductor layer 304 and has a lower band gap energy than the second nitride semiconductor layer 304.
  • the third nitride semiconductor layer 305 is made of undoped GaN having a thickness of 20 nm, for example.
  • the fourth nitride semiconductor layer 306 is formed on the third nitride semiconductor layer 305 and has a larger band gap energy than the third nitride semiconductor layer 305.
  • the fourth nitride semiconductor layer 306 is made of, for example, undoped Al y Ga 1-y N (0 ⁇ y ⁇ 1).
  • the fourth nitride semiconductor layer 306 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
  • Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 and the heterojunction interface between the third nitride semiconductor layer 305 and the fourth nitride semiconductor layer 306.
  • electric charges of, for example, about 1 ⁇ 10 13 cm ⁇ 2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
  • the Al composition ratio of the fourth nitride semiconductor layer 306 is set so that the electrons in the surface side channel are guided to the bulk side channel more effectively.
  • the Al composition ratio of the semiconductor layer 312 is desirably larger, and the thickness of the fourth nitride semiconductor layer 306 is more than the thickness of the second nitride semiconductor layer 304 and the fifth nitride semiconductor layer 312. The larger one is desirable.
  • the thickness of the fifth nitride semiconductor layer 312 is It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 306.
  • the drain electrode 308 and the source electrode 309 are formed in regions on both sides of the gate electrode 310, and the heterojunction interface between the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 and the third nitride, respectively. It is in contact with the heterojunction interface between the semiconductor layer 305 and the fourth nitride semiconductor layer 306, and is electrically connected to the electron transit region generated in the interface region.
  • the drain electrode 308 and the source electrode 309 are in contact with the first nitride semiconductor layer 303.
  • the drain electrode 308 and the source electrode 309 are composed of a laminated structure of Ti and Al, for example.
  • a recess 320 is formed in the first nitride semiconductor layer 303, the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306.
  • the recess 320 penetrates through the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306, that is, the third nitride semiconductor layer 305 and the fourth nitride semiconductor.
  • the heterojunction interface of the layer 306 and the heterojunction interfaces of the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 penetrate to the surface of the first nitride semiconductor layer 303.
  • a gate electrode 310 is formed in the recess 320.
  • the gate electrode 310 is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 310 may be made of Ti when the material constituting the gate electrode 310 is not diffused into the nitride semiconductor layer by the insulating film 307.
  • the fifth nitride semiconductor layer 312 is formed on the bottom and side surfaces of the recess 320 and the surface of the fourth nitride semiconductor layer 306, and is made of, for example, undoped Al z Ga 1 -z N (0 ⁇ z ⁇ 1). .
  • the fifth nitride semiconductor layer 312 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 10 nm.
  • the fifth nitride semiconductor layer 312 is formed by epitaxially growing a nitride semiconductor layer in the recess 320 by, for example, metal-organic chemical vapor deposition (MOCVD).
  • MOCVD metal-organic chemical vapor deposition
  • the insulating film 307 is formed continuously in this epitaxial growth without being exposed to the atmosphere (in-situ).
  • the gate electrode 310 is in contact with the insulating film 307 in the recess 320.
  • the presence of the fifth nitride semiconductor layer 312 can increase the crystallinity of the insulating film 307 and can be formed with good reproducibility. Rather than directly growing the insulating film 307 on the nitride semiconductor on the bottom surface of the recess 320, the fifth nitride semiconductor layer 312 that is the same nitride semiconductor layer is formed and then the insulating film 307 is formed by continuous growth. However, the crystallinity and reproducibility of the insulating film 307 can be improved.
  • the fifth nitride semiconductor layer 312 is, for example, an undoped Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer, and the layer in contact with the bottom surface of the recess 320 is, for example, a GaN layer.
  • a channel layer is formed under the fifth nitride semiconductor layer 312 when the Al composition X of the fifth nitride semiconductor layer 312 is larger than the Al composition at the bottom of the recess 320.
  • the amount of charge induced at that time is determined by the film thickness and composition of the fifth nitride semiconductor layer 312 formed by epitaxial growth with high controllability, so that reproducibility can be enhanced.
  • the insulating film 307 is formed on the fifth nitride semiconductor layer 312.
  • the insulating film 307 in the recess 320 is formed and sandwiched between the fifth nitride semiconductor layer 312 and the gate electrode 310.
  • the insulating film 307 is composed of, for example, a laminated structure of SiN, SiO, AlN, AlO, SiN and AlN having a thickness of 1 to 5 nm, a laminated structure of SiN and AlO, and the like.
  • the insulating film 307 is made of SiN or SiO
  • the insulating film 307 is formed by, for example, a CVD method or a low pressure CVD method.
  • the insulating film 307 is made of AlN or AlO
  • the insulating film 307 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
  • the element isolation layer 311 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
  • the on-resistance can be reduced for the same reason as the FET of the first embodiment.
  • an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
  • the insulating film 307 can be formed continuously with the epitaxial growth of the fifth nitride semiconductor layer 312 in the recess 320, the insulating film 307 having good insulating characteristics can be formed. realizable.
  • the first nitride semiconductor layer 303, the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306 contain In. May be.
  • the first nitride semiconductor layer 303 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
  • another semiconductor layer may be disposed on the fourth nitride semiconductor layer 306.
  • the physical semiconductor layer 312 may be doped with an n-type impurity such as Si.
  • the depth of the recess 320 is a depth penetrating the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306.
  • the depth is not limited as long as the distance between the gate electrode 310 and the bulk side channel can be shortened.
  • the depth of the recess 320 is deep enough to stop in the middle of the fourth nitride semiconductor layer 306 without reaching the third nitride semiconductor layer 305, penetrate through the fourth nitride semiconductor layer 306, The depth that stops in the middle of the nitride semiconductor layer 305, or the depth that passes through the fourth nitride semiconductor layer 306 and the third nitride semiconductor layer 305 and stops in the middle of the second nitride semiconductor layer 304. There may be.
  • FIG. 6 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
  • This FET includes a substrate 401, a buffer layer 402, a first nitride semiconductor layer 403, a second nitride semiconductor layer 404, a third nitride semiconductor layer 405, and a fourth nitride semiconductor layer.
  • a drain electrode 408, a source electrode 409, a gate electrode 410, and an element isolation layer 411 are provided.
  • the substrate 401 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, or the like having a thickness of 10 ⁇ m to 1000 ⁇ m.
  • the buffer layer 402 is made of AlN having a thickness corresponding to the substrate 401, for example, 100 nm, and is formed on the substrate 401.
  • the first nitride semiconductor layer 403 is made of undoped GaN having a thickness of 2 ⁇ m, for example, and is formed on the buffer layer 402.
  • the second nitride semiconductor layer 404 is formed on the first nitride semiconductor layer 403 and has a larger band gap energy than the first nitride semiconductor layer 403.
  • the second nitride semiconductor layer 404 is made of, for example, undoped Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the second nitride semiconductor layer 404 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 30 nm.
  • the third nitride semiconductor layer 405 is formed on the second nitride semiconductor layer 404 and has a lower band gap energy than the second nitride semiconductor layer 404.
  • the third nitride semiconductor layer 405 is made of undoped GaN having a thickness of 30 nm, for example.
  • the fourth nitride semiconductor layer 406 is formed on the third nitride semiconductor layer 405 and has a larger band gap energy than the third nitride semiconductor layer 405.
  • the fourth nitride semiconductor layer 406 is made of, for example, undoped Al y Ga 1-y N (0 ⁇ y ⁇ 1).
  • the fourth nitride semiconductor layer 406 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 30 nm.
  • Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 403 and the second nitride semiconductor layer 404 and the heterojunction interface between the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406.
  • electric charges of, for example, about 1 ⁇ 10 13 cm ⁇ 2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
  • the Al composition ratio of the fourth nitride semiconductor layer 406 is higher than the Al composition ratio of the second nitride semiconductor layer 404 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel.
  • the larger one is desirable, and the thickness of the fourth nitride semiconductor layer 406 is desirably larger than the thickness of the second nitride semiconductor layer 404.
  • the drain electrode 408 and the source electrode 409 are formed in the regions on both sides of the gate electrode 410, and the heterojunction interface between the first nitride semiconductor layer 403 and the second nitride semiconductor layer 404 and the third nitride, respectively. It contacts the heterojunction interface between the semiconductor layer 405 and the fourth nitride semiconductor layer 406 and is electrically connected to the electron transit region generated in the interface region.
  • the drain electrode 408 and the source electrode 409 are in contact with the first nitride semiconductor layer 403.
  • the drain electrode 408 and the source electrode 409 are made of a laminated structure of Ti and Al, for example.
  • a recess 420 is formed in the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406.
  • the recess 420 penetrates the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. And reaches the surface of the second nitride semiconductor layer 404.
  • a gate electrode 410 is formed in the recess 420 so as to cover the bottom and side surfaces of the recess 420.
  • the gate electrode 410 in the recess 420 is in direct contact with the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 without an insulating film interposed therebetween.
  • the recess 420 is formed by selectively etching the third nitride semiconductor layer 405 with respect to the second nitride semiconductor layer 404 in particular.
  • the concave portion 420 is not formed in the second nitride semiconductor layer 404, and the surface of the second nitride semiconductor layer 404 serving as the bottom surface of the concave portion 420 is the second nitride semiconductor layer 404 and the second nitride semiconductor layer 404. 3 is flush with the interface of the nitride semiconductor layer 405.
  • the gate electrode 410 is in Schottky junction with the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406, and is made of, for example, Pd, Ni, Pt, or the like.
  • the element isolation layer 411 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
  • the on-resistance can be reduced for the same reason as the FET of the first embodiment.
  • the first nitride semiconductor layer 403, the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 contain In. May be.
  • the first nitride semiconductor layer 403 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
  • another semiconductor layer may be disposed on the fourth nitride semiconductor layer 406.
  • the first nitride semiconductor layer 403, the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 include, for example, Si.
  • N-type impurities such as n-type impurities may be doped.
  • the depth of the recess 420 is a depth that penetrates the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. If the distance to the channel can be shortened, the depth is not limited to this.
  • the depth of the recess 420 is a depth that stops in the middle of the fourth nitride semiconductor layer 406 without reaching the third nitride semiconductor layer 405, or penetrates the fourth nitride semiconductor layer 406, 3 may be a depth that stops halfway through the nitride semiconductor layer 405.
  • FIG. 7 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
  • This FET includes a substrate 501, a buffer layer 502, a first nitride semiconductor layer 503, a second nitride semiconductor layer 504, a third nitride semiconductor layer 505, and a fourth nitride semiconductor layer. 506, an insulating film 507, a drain electrode 508, a source electrode 509, a gate electrode 510, and an element isolation layer 511 are provided.
  • the substrate 501 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, or the like having a thickness of 10 ⁇ m or more and 1000 ⁇ m or less.
  • the buffer layer 502 is made of AlN having a thickness corresponding to the substrate 501, for example, 100 nm, and is formed on the substrate 501.
  • the first nitride semiconductor layer 503 is made of undoped GaN having a thickness of 2 ⁇ m, for example, and is formed on the buffer layer 502.
  • the second nitride semiconductor layer 504 is formed on the first nitride semiconductor layer 503 and has a larger band gap energy than the first nitride semiconductor layer 503.
  • the second nitride semiconductor layer 504 is made of, for example, undoped Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • the second nitride semiconductor layer 504 is composed of 20 nm thick undoped Al 0.25 Ga 0.75 N.
  • the third nitride semiconductor layer 505 is formed on the second nitride semiconductor layer 504 and has a smaller band gap energy than the second nitride semiconductor layer 504.
  • the third nitride semiconductor layer 505 is made of undoped GaN having a thickness of 20 nm, for example.
  • the fourth nitride semiconductor layer 506 is formed on the third nitride semiconductor layer 505 and has a larger band gap energy than the third nitride semiconductor layer 505.
  • the fourth nitride semiconductor layer 506 is made of, for example, undoped Al y Ga 1-y N (0 ⁇ y ⁇ 1).
  • the fourth nitride semiconductor layer 506 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
  • Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 503 and the second nitride semiconductor layer 504 and the heterojunction interface between the third nitride semiconductor layer 505 and the fourth nitride semiconductor layer 506.
  • electric charges of, for example, about 1 ⁇ 10 13 cm ⁇ 2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
  • the Al composition ratio of the fourth nitride semiconductor layer 506 is higher than the Al composition ratio of the second nitride semiconductor layer 504 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel.
  • the larger one is desirable, and the thickness of the fourth nitride semiconductor layer 506 is desirably larger than the thickness of the second nitride semiconductor layer 504.
  • the thickness of the second nitride semiconductor layer 504 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 506.
  • the drain electrode 508 and the source electrode 509 are formed in regions on both sides of the gate electrode 510, and the heterojunction interface between the first nitride semiconductor layer 503 and the second nitride semiconductor layer 504 and the third nitride, respectively.
  • the semiconductor layer 505 and the fourth nitride semiconductor layer 506 are in contact with the heterojunction interface and are electrically connected to the electron transit region generated in the interface region.
  • the drain electrode 508 and the source electrode 509 are in contact with the first nitride semiconductor layer 503.
  • the drain electrode 508 and the source electrode 509 are composed of a laminated structure of Ti and Al, for example.
  • the insulating film 507 is formed on the surface of the fourth nitride semiconductor layer 506 and includes, for example, a stacked structure of SiN, SiO, AlN, AlO, SiN, and AlN, a stacked structure of SiN and AlO, and the like.
  • the insulating film 507 is made of SiN or SiO
  • the insulating film 507 is formed by, for example, a CVD method or a low pressure CVD method.
  • the insulating film 507 is made of AlN or AlO
  • the insulating film 507 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
  • the gate electrode 510 is formed on the insulating film 507 and is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 510 may be made of Ti when the material constituting the gate electrode 510 is not diffused into the nitride semiconductor layer by the insulating film 507.
  • the element isolation layer 511 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
  • the on-resistance can be reduced for the same reason as the FET of the first embodiment.
  • an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
  • the first nitride semiconductor layer 503, the second nitride semiconductor layer 504, the third nitride semiconductor layer 505, and the fourth nitride semiconductor layer 506 contain In. May be.
  • the first nitride semiconductor layer 503 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
  • another semiconductor layer may be disposed on the fourth nitride semiconductor layer 506.
  • the first nitride semiconductor layer 503, the second nitride semiconductor layer 504, the third nitride semiconductor layer 505, and the fourth nitride semiconductor layer 506 include, for example, Si.
  • N-type impurities such as n-type impurities may be doped.
  • the FET of the above embodiment may take the form of a Schottky junction type FET in which the insulating film 507 is not provided as in the FET of the third embodiment.
  • the FET of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment.
  • the present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
  • the present invention can be applied to FETs, and in particular to high power high frequency devices such as mobile phone base stations, high power switching devices such as inverters, and the like.

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Abstract

Disclosed is an FET having a low on-resistance.  The FET comprises: a first nitride semiconductor layer (103); a second nitride semiconductor layer (104) which is formed on the first nitride semiconductor layer (103) and has a larger band gap energy than the first nitride semiconductor layer (103); a third nitride semiconductor layer (105) which is formed on the second nitride semiconductor layer (104); and a fourth nitride semiconductor layer (106) which is formed on the third nitride semiconductor layer (105) and has a larger band gap energy than the third nitride semiconductor layer (105).  In the FET, a channel is formed at the heterojunction interface between the first nitride semiconductor layer (103) and the second nitride semiconductor layer (104).

Description

電界効果トランジスタField effect transistor
　本発明は、電界効果トランジスタに関し、特に、ＩＩＩ族窒化物半導体から構成される電界効果トランジスタに関するものである。 The present invention relates to a field effect transistor, and more particularly to a field effect transistor composed of a group III nitride semiconductor.
　窒化ガリウム（ＧａＮ）に代表されるＩＩＩ族窒化物半導体はシリコンやガリウム砒素を凌ぐ、大きなバンドギャップ、高い破壊電界、及び高い飽和電子速度を有する。この物性的な優位性からＩＩＩ族窒化物半導体を用いた電界効果トランジスタ（ＦＥＴ）は次世代の高周波デバイスやハイパワースイッチングデバイスとして有望であり、盛んに研究開発されている。 Group III nitride semiconductors typified by gallium nitride (GaN) have a large band gap, a high breakdown electric field, and a high saturation electron velocity that surpass silicon and gallium arsenide. Because of this physical advantage, field effect transistors (FETs) using group III nitride semiconductors are promising as next-generation high-frequency devices and high-power switching devices, and are actively researched and developed.
　上記のＦＥＴでは、高い耐圧と高いオン抵抗とを両立することが求められるが、一般的には同一材料において両者はトレードオフの関係にある。さらにハイパワースイッチングデバイスではノーマリーオフ型のＦＥＴが求められ、ゲート・ソース間、及びゲート・ドレイン間の寄生抵抗は更に大きくなる傾向である。また、ＩＩＩ族窒化物半導体の表面には高密度のトラップ準位が存在し、高速スイッチング動作時には捕獲されたトラップ準位がスイッチングに追随できず、ドレイン電流が減少する電流コラプスが生じることが知られている。 The above-mentioned FET is required to achieve both a high breakdown voltage and a high on-resistance, but generally both are in a trade-off relationship with the same material. Further, normally-off FETs are required for high power switching devices, and the parasitic resistance between the gate and the source and between the gate and the drain tends to be further increased. It is also known that a high density trap level exists on the surface of the group III nitride semiconductor, and the trap level trapped during high-speed switching operation cannot follow switching, resulting in a current collapse in which the drain current decreases. It has been.
　従来の窒化物半導体を用いたＦＥＴとしては、例えば、特許文献１及び２に記載のものが知られている。図８は特許文献１に記載のＦＥＴの構造を示す断面図である。 As FETs using conventional nitride semiconductors, for example, those described in Patent Documents 1 and 2 are known. FIG. 8 is a cross-sectional view showing the structure of the FET described in Patent Document 1. In FIG.
　図８に示すように、特許文献１のＦＥＴでは、基板８０１上にキャリア走行層８０２及びキャリア供給層８０３が設けられ、さらにキャリア供給層８０３の上面にはＧａＮ系保護層８０４が設けられている。そして、ＧａＮ系保護層８０４の表面のうちゲート電極８０６とソース電極８０８との間、及びゲート電極８０６とドレイン電極８０７との間は、窒化シリコン（ＳｉＮ）からなる保護層８０５で被覆されている。これにより、ＩＩＩ族窒化物半導体の表面準位を低減することができ、ゲート電極８０６脇の表面トラップ準位による電流コラプスを低減することができる。 As shown in FIG. 8, in the FET of Patent Document 1, a carrier traveling layer 802 and a carrier supply layer 803 are provided on a substrate 801, and a GaN-based protective layer 804 is provided on the upper surface of the carrier supply layer 803. . The surface of the GaN-based protective layer 804 is covered with a protective layer 805 made of silicon nitride (SiN) between the gate electrode 806 and the source electrode 808 and between the gate electrode 806 and the drain electrode 807. . Thereby, the surface level of the group III nitride semiconductor can be reduced, and current collapse due to the surface trap level beside the gate electrode 806 can be reduced.
特開２００２－３５９２５６号公報JP 2002-359256 A 特開２００８－２１１１７２号公報JP 2008-2111172 A
　しかしながら、従来のＩＩＩ族窒化物半導体を用いたＦＥＴでは、オン抵抗が十分低いとは言えず、更なるオン抵抗の低減が求められている。また、素子の耐圧はゲート電極とドレイン電極との距離により決定され、その距離を大きくすることで耐圧は向上するがゲート・ドレイン間の寄生抵抗は増大し、オン抵抗が増大してしまう。 However, in a conventional FET using a group III nitride semiconductor, the on-resistance cannot be said to be sufficiently low, and further reduction of the on-resistance is required. The breakdown voltage of the element is determined by the distance between the gate electrode and the drain electrode. Increasing the distance improves the breakdown voltage, but increases the parasitic resistance between the gate and the drain and increases the on-resistance.
　ここで、オン抵抗は高周波デバイスとハイパワースイッチングデバイスとのいずれにおいても電力ロスとなり十分低いことが望まれる。今後、ＦＥＴの高性能化に向けて、さらなるオン抵抗の低減が必要である。そして、オン抵抗の低減にはデバイス構造の改善が効果的である。 Here, it is desirable that the on-resistance is sufficiently low as a power loss in both the high-frequency device and the high-power switching device. In the future, it will be necessary to further reduce the on-resistance for higher performance FETs. An improvement in the device structure is effective in reducing the on-resistance.
　また、ノーマリーオフ型のＦＥＴでは、ゲート・ソース間、及びゲート・ドレイン間の寄生抵抗は大きくなる傾向であり、特許文献１のＦＥＴでは表面準位の影響を抑え、寄生抵抗の増大に配慮しているものの、一層の抵抗の低減が必要である。 Further, normally-off type FETs tend to increase the parasitic resistance between the gate and the source and between the gate and the drain. In the FET of Patent Document 1, the influence of the surface state is suppressed and consideration is given to an increase in the parasitic resistance. However, further resistance reduction is necessary.
　そこで、本発明は、上記課題を解決するためになされたもので、低オン抵抗の電界効果トランジスタを提供することを目的とする。 Therefore, the present invention has been made to solve the above problems, and an object thereof is to provide a field effect transistor having a low on-resistance.
　上記目的を達成するために、本発明に係る電界効果トランジスタは、第１の窒化物半導体層と、前記第１の窒化物半導体層の上に形成され、前記第１の窒化物半導体層よりもバンドギャップエネルギーが大きい第２の窒化物半導体層と、前記第２の窒化物半導体層の上に形成された第３の窒化物半導体層と、前記第３の窒化物半導体層の上に形成され、前記第３の窒化物半導体層よりもバンドギャップエネルギーが大きい第４の窒化物半導体層とを備え、前記第１の窒化物半導体層及び前記第２の窒化物半導体層のヘテロ接合界面には、チャネルが形成されることを特徴とする。 In order to achieve the above object, a field effect transistor according to the present invention is formed on a first nitride semiconductor layer and the first nitride semiconductor layer, and more than the first nitride semiconductor layer. A second nitride semiconductor layer having a large band gap energy; a third nitride semiconductor layer formed on the second nitride semiconductor layer; and a third nitride semiconductor layer formed on the third nitride semiconductor layer. A fourth nitride semiconductor layer having a band gap energy larger than that of the third nitride semiconductor layer, and a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A channel is formed.
　この構成によれば、第１の窒化物半導体層と第２の窒化物半導体層との間のヘテロ接合界面だけでなく、第３の窒化物半導体層と第４の窒化物半導体層との間のヘテロ接合界面にもチャネルが形成される。すなわち、従来のチャネルを形成する２次元電子ガスに加えて表面側にさらに２次元電子ガスが形成される。従って、シート抵抗を低減することができ、オン抵抗を低減することができる。 According to this configuration, not only the heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer but also between the third nitride semiconductor layer and the fourth nitride semiconductor layer. A channel is also formed at the heterojunction interface. That is, in addition to the conventional two-dimensional electron gas forming the channel, a two-dimensional electron gas is further formed on the surface side. Therefore, sheet resistance can be reduced and on-resistance can be reduced.
　また、従来のＦＥＴと比較して、ＦＥＴの最表面側にある半導体層からチャネルが遠ざけられるため、チャネルへの表面準位による影響を低減できる。その結果、表面準位に起因した電流コラプスを抑制することができる。 Moreover, since the channel is moved away from the semiconductor layer on the outermost surface side of the FET as compared with the conventional FET, the influence of the surface level on the channel can be reduced. As a result, current collapse due to the surface state can be suppressed.
　また、２つのヘテロ接合界面は窒化物半導体により形成されるため、ヘテロ接合界面には格子不整合から生じるピエゾ分極と自発分極とにより２次元電子ガスが生成される。従って、チャネルの形成に不純物の添加が必要ないので、高耐圧のＦＥＴを実現できる。 Also, since the two heterojunction interfaces are formed of a nitride semiconductor, a two-dimensional electron gas is generated at the heterojunction interface due to piezo polarization and spontaneous polarization resulting from lattice mismatch. Therefore, since it is not necessary to add impurities for forming the channel, a high breakdown voltage FET can be realized.
　ここで、前記電界効果トランジスタのゲート電極は、前記第４の窒化物半導体層に設けられた凹部内に形成されることが好ましい。 Here, it is preferable that the gate electrode of the field effect transistor is formed in a recess provided in the fourth nitride semiconductor layer.
　この構成によれば、ＦＥＴの最表面側にある半導体層からチャネルを遠ざけつつ、ゲート電極にチャネルを近付けることができる。その結果、電流コラプスを抑制しつつ、ゲートの閾値電圧の制御を容易にすることができる。 According to this configuration, the channel can be brought close to the gate electrode while keeping the channel away from the semiconductor layer on the outermost surface side of the FET. As a result, it is possible to easily control the threshold voltage of the gate while suppressing current collapse.
　ここで、前記凹部は、前記第３の窒化物半導体層及び前記第４の窒化物半導体層のヘテロ接合界面を貫通していることが好ましい。特に、前記凹部は、前記第３の窒化物半導体層及び前記第４の窒化物半導体層を貫通して前記第２の窒化物半導体層の表面まで達し、前記凹部の底面としての前記第２の窒化物半導体層の表面は、前記第２の窒化物半導体層及び前記第３の窒化物半導体層の界面と面一であることが好ましい。 Here, it is preferable that the recess penetrates a heterojunction interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer. In particular, the recess penetrates through the third nitride semiconductor layer and the fourth nitride semiconductor layer to reach the surface of the second nitride semiconductor layer, and the second as the bottom surface of the recess. The surface of the nitride semiconductor layer is preferably flush with the interface between the second nitride semiconductor layer and the third nitride semiconductor layer.
　この構成によれば、第２の窒化物半導体層の膜厚及びＡｌ組成比によりゲートの閾値電圧が決定されるので、ゲートの閾値電圧の制御を容易にすることができる。従って、ウェハ面内で均一なゲートの閾値電圧を有するＦＥＴを実現できる。 According to this configuration, since the gate threshold voltage is determined by the film thickness and Al composition ratio of the second nitride semiconductor layer, the gate threshold voltage can be easily controlled. Therefore, an FET having a uniform gate threshold voltage in the wafer surface can be realized.
　また、前記電界効果トランジスタは、さらに、前記凹部の底面に形成された絶縁膜を備えることが好ましい。 The field effect transistor preferably further includes an insulating film formed on the bottom surface of the recess.
　この構成によれば、ＦＥＴをＭＩＳ（Metal Insulator Semiconductor）構造にしてゲートに流れ込む電流を抑制し、ゲート電極に正バイアスを印加できるので、ノーマリーオフ型ＦＥＴとして効果的な構造を実現できる。 According to this configuration, since the FET is made into a MIS (Metal Insulator Semiconductor) structure, the current flowing into the gate can be suppressed and a positive bias can be applied to the gate electrode, so that an effective structure as a normally-off type FET can be realized.
　また、前記電界効果トランジスタは、さらに、前記凹部の底面に形成された第５の窒化物半導体層と、前記ゲート電極と前記第５の窒化物半導体層との間に形成された絶縁膜とを備えることが好ましい。 The field effect transistor further includes a fifth nitride semiconductor layer formed on a bottom surface of the recess, and an insulating film formed between the gate electrode and the fifth nitride semiconductor layer. It is preferable to provide.
　この構成によれば、凹部内における第５の窒化物半導体層のエピタキシャル成長と連続して絶縁膜を形成することができるので、良好な絶縁特性の絶縁膜を実現できる。 According to this configuration, since the insulating film can be formed continuously with the epitaxial growth of the fifth nitride semiconductor layer in the recess, an insulating film having good insulating characteristics can be realized.
　また、前記絶縁膜は、窒化シリコン及び窒化アルミニウムの積層構造体からなることが好ましい。 The insulating film is preferably made of a laminated structure of silicon nitride and aluminum nitride.
　この構成によれば、絶縁膜は熱伝導に優れたＡｌＮを含むため、特に大電力を駆動するデバイスに対して特に有効なＦＥＴを実現できる。 According to this configuration, since the insulating film contains AlN excellent in heat conduction, an FET that is particularly effective for a device that drives a large power can be realized.
　また、前記絶縁膜は、原子層堆積装置により形成されることが好ましい。 The insulating film is preferably formed by an atomic layer deposition apparatus.
　この構成によれば、絶縁膜の膜質の向上と、優れた膜厚の制御とが可能となる。 According to this configuration, it is possible to improve the quality of the insulating film and to control the film thickness.
　また、前記第２の窒化物半導体層の膜厚は、前記第４の窒化物半導体層の膜厚よりも小さいことが好ましい。 The film thickness of the second nitride semiconductor layer is preferably smaller than the film thickness of the fourth nitride semiconductor layer.
　この構成によれば、第３の窒化物半導体層と第４の窒化物半導体層との間のヘテロ接合界面のチャネルの電子を、第１の窒化物半導体層と第２の窒化物半導体層との間のヘテロ接合界面のチャネルに効果的に導くことができる。その結果、さらにチャネル抵抗を低減することができ、オン抵抗を低減することができる。また、ゲート電極直下の第２の窒化物半導体層の膜厚を薄くすることができるので、ノーマリーオフ型のＦＥＴに対して有効な構成を実現できる。 According to this configuration, the electrons in the channel at the heterojunction interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer are converted into the first nitride semiconductor layer and the second nitride semiconductor layer. Can effectively lead to the channel of the heterojunction interface between. As a result, the channel resistance can be further reduced, and the on-resistance can be reduced. In addition, since the thickness of the second nitride semiconductor layer directly under the gate electrode can be reduced, a configuration effective for a normally-off type FET can be realized.
　また、前記電界効果トランジスタのソース電極及びドレイン電極は、それぞれ前記第１の窒化物半導体層及び前記第２の窒化物半導体層のヘテロ接合界面と、前記第３の窒化物半導体層及び前記第４の窒化物半導体層のヘテロ接合界面とに接触することが好ましい。 In addition, the source electrode and the drain electrode of the field effect transistor respectively include a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer. It is preferable to contact the heterojunction interface of the nitride semiconductor layer.
　この構成によれば、ソース電極及びドレイン電極のコンタクト抵抗を低減することができる。 According to this configuration, the contact resistance of the source electrode and the drain electrode can be reduced.
　本発明によれば、窒化物半導体から構成されるＦＥＴにおいて低オン抵抗を実現することができる。 According to the present invention, a low on-resistance can be realized in an FET composed of a nitride semiconductor.
図１は、本発明の第１の実施の形態に係るＦＥＴの構成を示す断面図である。FIG. 1 is a cross-sectional view showing the configuration of the FET according to the first embodiment of the present invention. 図２は、同実施の形態に係るＦＥＴのエネルギーバンド図である。FIG. 2 is an energy band diagram of the FET according to the embodiment. 図３Ａは、シングルチャネル構造のＦＥＴを示す図である。FIG. 3A is a diagram showing an FET having a single channel structure. 図３Ｂは、ダブルチャネル構造のＦＥＴを示す図である。FIG. 3B is a diagram showing a FET having a double channel structure. 図３Ｃは、ゲート電極及びドレイン電極のダイオード特性における耐圧及びオン抵抗の関係の実験結果を示す図である。FIG. 3C is a diagram illustrating experimental results of the relationship between the breakdown voltage and the on-resistance in the diode characteristics of the gate electrode and the drain electrode. 図４は、本発明の第２の実施の形態に係るＦＥＴの構成を示す断面図である。FIG. 4 is a cross-sectional view showing the configuration of the FET according to the second exemplary embodiment of the present invention. 図５は、本発明の第３の実施の形態に係るＦＥＴの構成を示す断面図である。FIG. 5 is a cross-sectional view showing the configuration of the FET according to the third exemplary embodiment of the present invention. 図６は、本発明の第４の実施の形態に係るＦＥＴの構成を示す断面図である。FIG. 6 is a cross-sectional view showing the configuration of the FET according to the fourth exemplary embodiment of the present invention. 図７は、本発明の第５の実施の形態に係るＦＥＴの構成を示す断面図である。FIG. 7 is a sectional view showing the structure of an FET according to the fifth embodiment of the present invention. 図８は、従来のＦＥＴの構造を示す断面図である。FIG. 8 is a cross-sectional view showing the structure of a conventional FET.
　以下、本発明の実施の形態におけるＦＥＴについて、図面を参照しながら説明する。 Hereinafter, FETs according to embodiments of the present invention will be described with reference to the drawings.
　（第１の実施の形態）
　以下、本発明の第１の実施の形態におけるＦＥＴの構成及びその製造方法を説明する。 (First embodiment)
Hereinafter, the configuration of the FET and the manufacturing method thereof according to the first embodiment of the present invention will be described.
　図１は、本実施の形態に係るＦＥＴの構成を示す断面図である。 FIG. 1 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
　このＦＥＴは、基板１０１と、バッファ層１０２と、第１の窒化物半導体層１０３と、第２の窒化物半導体層１０４と、第３の窒化物半導体層１０５と、第４の窒化物半導体層１０６と、絶縁膜１０７と、ドレイン電極１０８と、ソース電極１０９と、ゲート電極１１０と、素子分離層１１１とを備えている。 This FET includes a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 105, and a fourth nitride semiconductor layer. 106, an insulating film 107, a drain electrode 108, a source electrode 109, a gate electrode 110, and an element isolation layer 111.
　基板１０１は、例えば１０μｍ以上１０００μｍ以下の厚み（膜厚）のサファイア基板、ＳｉＣ基板、Ｓｉ基板、及びＧａＮ基板等である。 The substrate 101 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, or a GaN substrate having a thickness (film thickness) of 10 μm or more and 1000 μm or less.
　バッファ層１０２は、基板１０１に応じた厚み、例えば１００ｎｍのＡｌＮから構成され、基板１０１の上に形成される。 The buffer layer 102 is made of AlN having a thickness corresponding to the substrate 101, for example, 100 nm, and is formed on the substrate 101.
　第１の窒化物半導体層１０３は、例えば２μｍの厚みのアンドープＧａＮから構成され、バッファ層１０２の上に形成される。ここで、「アンドープ」とは、不純物が意図的に導入されていないことを意味するものとする。 The first nitride semiconductor layer 103 is made of undoped GaN having a thickness of 2 μm, for example, and is formed on the buffer layer 102. Here, “undoped” means that impurities are not intentionally introduced.
　第２の窒化物半導体層１０４は、第１の窒化物半導体層１０３の上に形成され、第１の窒化物半導体層１０３よりもバンドギャップエネルギーが大きい。第２の窒化物半導体層１０４は、例えばアンドープＡｌxＧａ1-xＮ（０＜ｘ≦１）から構成される。例えば、第２の窒化物半導体層１０４は、２０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The second nitride semiconductor layer 104 is formed on the first nitride semiconductor layer 103 and has a larger band gap energy than the first nitride semiconductor layer 103. The second nitride semiconductor layer 104 is made of, for example, undoped Al x Ga 1-x N (0 <x ≦ 1). For example, the second nitride semiconductor layer 104 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 20 nm.
　第３の窒化物半導体層１０５は、第２の窒化物半導体層１０４の上に形成され、第２の窒化物半導体層１０４よりもバンドギャップエネルギーが小さい。第３の窒化物半導体層１０５は、例えば２０ｎｍの厚みのアンドープＧａＮから構成される。 The third nitride semiconductor layer 105 is formed on the second nitride semiconductor layer 104 and has a lower band gap energy than the second nitride semiconductor layer 104. The third nitride semiconductor layer 105 is made of undoped GaN having a thickness of 20 nm, for example.
　第４の窒化物半導体層１０６は、第３の窒化物半導体層１０５の上に形成され、第３の窒化物半導体層１０５よりもバンドギャップエネルギーが大きい。第４の窒化物半導体層１０６は、例えばアンドープＡｌyＧａ1-yＮ（０＜ｙ≦１）から構成される。例えば、第４の窒化物半導体層１０６は、２５ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The fourth nitride semiconductor layer 106 is formed on the third nitride semiconductor layer 105 and has a larger band gap energy than the third nitride semiconductor layer 105. The fourth nitride semiconductor layer 106 is made of, for example, undoped Al y Ga 1-y N (0 <y ≦ 1). For example, the fourth nitride semiconductor layer 106 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
　第１の窒化物半導体層１０３及び第２の窒化物半導体層１０４のヘテロ接合界面と、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６のヘテロ接合界面とには、自発分極及びピエゾ分極により例えば１×１０13ｃｍ-2程度の電荷が生じており、ゲートがオンの状態ではヘテロ接合界面を電子が走行し、特にＦＥＴにおいて横方向の抵抗を大きく下げることができる。 Spontaneous polarization occurs between the heterojunction interface of the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 and the heterojunction interface of the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106. In addition, electric charges of, for example, about 1 × 10 13 cm −2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
　ドレイン電極１０８及びソース電極１０９は、ゲート電極１１０の両側方の領域に形成され、それぞれ第１の窒化物半導体層１０３及び第２の窒化物半導体層１０４のヘテロ接合界面と、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６のヘテロ接合界面とに接触し、該界面領域に生成された電子走行領域（チャネル）と電気的に接続されている。ドレイン電極１０８及びソース電極１０９は、第１の窒化物半導体層１０３に接触している。 The drain electrode 108 and the source electrode 109 are formed in regions on both sides of the gate electrode 110, and the heterojunction interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104 and the third nitride, respectively. It is in contact with the heterojunction interface between the semiconductor layer 105 and the fourth nitride semiconductor layer 106 and is electrically connected to the electron transit region (channel) generated in the interface region. The drain electrode 108 and the source electrode 109 are in contact with the first nitride semiconductor layer 103.
　ドレイン電極１０８及びソース電極１０９は、例えばＴｉ及びＡｌの積層構造体から構成される。 The drain electrode 108 and the source electrode 109 are composed of, for example, a laminated structure of Ti and Al.
　第２の窒化物半導体層１０４、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６には、凹部１２０が形成されている。この凹部１２０は、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６を貫通、つまり第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６のヘテロ接合界面を貫通して第２の窒化物半導体層１０４の表面まで達している。そして、凹部１２０内には、ゲート電極１１０が形成されている。 A recess 120 is formed in the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106. The recess 120 penetrates the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106. And reaches the surface of the second nitride semiconductor layer 104. A gate electrode 110 is formed in the recess 120.
　ゲート電極１１０は、例えばパラジウム（Ｐｄ）、ニッケル（Ｎｉ）及び白金（Ｐｔ）等から構成される。なお、ゲート電極１１０は、ゲート電極１１０を構成する材料が絶縁膜１０７により窒化物半導体層に拡散しない場合にはＴｉから構成されてもよい。 The gate electrode 110 is made of, for example, palladium (Pd), nickel (Ni), platinum (Pt), or the like. Note that the gate electrode 110 may be made of Ti when the material constituting the gate electrode 110 is not diffused into the nitride semiconductor layer by the insulating film 107.
　絶縁膜１０７は、凹部１２０の底面及び側面並びに第４の窒化物半導体層１０６表面に形成されている。凹部１２０の底面及び側面に形成された絶縁膜１０７は、第２の窒化物半導体層１０４、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６とゲート電極１１０とに挟み込まれている。 The insulating film 107 is formed on the bottom and side surfaces of the recess 120 and the surface of the fourth nitride semiconductor layer 106. The insulating film 107 formed on the bottom and side surfaces of the recess 120 is sandwiched between the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, the fourth nitride semiconductor layer 106, and the gate electrode 110. Yes.
　絶縁膜１０７は、例えば窒化シリコン（ＳｉＮ）、酸化シリコン（ＳｉＯ）、窒化アルミニウム（ＡｌＮ）、酸化アルミ（ＡｌＯ）、ＳｉＮ及びＡｌＮの積層構造体、並びにＳｉＮ及びＡｌＯの積層構造体等から構成される。絶縁膜１０７がＳｉＮ又はＳｉＯから構成される場合、絶縁膜１０７は例えばプラズマ化学気相成長（ＣＶＤ）法や減圧ＣＶＤ法により成膜される。一方、絶縁膜１０７がＡｌＮ又はＡｌＯにより構成される場合、絶縁膜１０７は例えばスパッタ法や原子層堆積装置を用いた原子層堆積法（アトミックレイヤーデポジション：ＡＬＤ法）により成膜される。 The insulating film 107 includes, for example, silicon nitride (SiN), silicon oxide (SiO), aluminum nitride (AlN), aluminum oxide (AlO), a stacked structure of SiN and AlN, a stacked structure of SiN and AlO, and the like. The When the insulating film 107 is made of SiN or SiO, the insulating film 107 is formed by, for example, a plasma chemical vapor deposition (CVD) method or a low pressure CVD method. On the other hand, when the insulating film 107 is made of AlN or AlO, the insulating film 107 is formed by, for example, a sputtering method or an atomic layer deposition method (atomic layer deposition: ALD method) using an atomic layer deposition apparatus.
　素子分離層１１１は、例えば窒化物半導体層にホウ素（Ｂ）等の不純物をイオン注入することにより形成され、ＦＥＴを他の素子と電気的に分離する。 The element isolation layer 111 is formed by ion-implanting impurities such as boron (B) into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
　図２は本実施の形態に係るＦＥＴのエネルギーバンド図である。 FIG. 2 is an energy band diagram of the FET according to the present embodiment.
　ゲートバイアスがゼロの場合において、第１の窒化物半導体層１０３及び第２の窒化物半導体層１０４のヘテロ接合界面には２次元電子ガスが発生し、チャネル（バルク側チャネルと呼ぶ）が形成されると共に、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６のヘテロ接合界面にも２次元電子ガスが発生することにより表面側にもチャネル（表面側チャネルと呼ぶ）が形成されている。このようにバルク側チャネルと表面側チャネルの２つのチャネルが形成されるため、トータルのチャネル抵抗は低減される。この２つのチャネル間にはポテンシャル障壁が存在するが、トンネリングにより電子の移動が可能であるため、表面側チャネルの電子もドレイン電流として寄与する。そのため、低減されたチャネル抵抗分だけオン抵抗を低減することができる。また、従来のＦＥＴと比較して、バルク側チャネルがＦＥＴの最表面側にある半導体層（第４の窒化物半導体層１０６表面）から遠ざけられているため、表面準位によるチャネルへの影響が低減される。その結果、表面準位に起因した電流コラプスを抑制することができる。 When the gate bias is zero, a two-dimensional electron gas is generated at the heterojunction interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, and a channel (referred to as a bulk side channel) is formed. In addition, a two-dimensional electron gas is generated at the heterojunction interface between the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106, whereby a channel (referred to as a surface side channel) is also formed on the surface side. ing. Thus, since two channels of the bulk side channel and the surface side channel are formed, the total channel resistance is reduced. Although there is a potential barrier between the two channels, electrons can move by tunneling, and thus electrons in the surface side channel also contribute as drain currents. Therefore, the on-resistance can be reduced by the reduced channel resistance. Further, as compared with the conventional FET, since the bulk side channel is away from the semiconductor layer (the surface of the fourth nitride semiconductor layer 106) on the outermost surface side of the FET, the influence of the surface level on the channel is not increased. Reduced. As a result, current collapse due to the surface state can be suppressed.
　ここで、より効果的に表面側チャネルの電子がバルク側チャネルに導かれるように、第４の窒化物半導体層１０６のＡｌ組成比は、第２の窒化物半導体層１０４のＡｌ組成比よりも大きい方が望ましく、さらに、第４の窒化物半導体層１０６の厚さは、第２の窒化物半導体層１０４の厚さよりも大きい方が望ましい。また、ゲート電極１１０直下の第２の窒化物半導体層１０４の膜厚を薄くし、ノーマリーオフ型のＦＥＴを実現するために、第２の窒化物半導体層１０４の厚さは、第４の窒化物半導体層１０６の厚さよりも小さい方が望ましい。 Here, the Al composition ratio of the fourth nitride semiconductor layer 106 is higher than the Al composition ratio of the second nitride semiconductor layer 104 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel. The larger one is desirable, and the thickness of the fourth nitride semiconductor layer 106 is desirably larger than the thickness of the second nitride semiconductor layer 104. In addition, in order to reduce the thickness of the second nitride semiconductor layer 104 immediately below the gate electrode 110 and realize a normally-off FET, the thickness of the second nitride semiconductor layer 104 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 106.
　以上のように、本実施の形態のＦＥＴによれば、例えばＧａＮ／ＡｌＧａＮ／ＧａＮ／ＡｌＧａＮの積層構造により２つのヘテロ接合界面が形成される。そして、２つのヘテロ接合界面には、ＡｌＧａＮとＧａＮとの間での格子不整合から生じるピエゾ分極とＧａＮ系層自体から生じる自発分極とにより２次元電子ガスが生成される。従って、ＡｌＧａＮ／ＧａＮのヘテロ接合界面で形成される電子走行層（チャネル）が複数備えられるため、ゲート電極１１０とソース電極１０９との間、及びゲート電極１１０とドレイン電極１０８との間のオン抵抗を低減することができる。 As described above, according to the FET of the present embodiment, two heterojunction interfaces are formed by a laminated structure of, for example, GaN / AlGaN / GaN / AlGaN. A two-dimensional electron gas is generated at the interface between the two heterojunctions due to piezoelectric polarization caused by lattice mismatch between AlGaN and GaN and spontaneous polarization caused by the GaN-based layer itself. Accordingly, since a plurality of electron transit layers (channels) formed at the AlGaN / GaN heterojunction interface are provided, the on-resistance between the gate electrode 110 and the source electrode 109 and between the gate electrode 110 and the drain electrode 108 is provided. Can be reduced.
　図３Ｃは、図３Ａの１つの電子走行層を有するシングルチャネル構造と、図３Ｂの２つの電子走行層を有するダブルチャネル構造とについて、ゲート電極１１０及びドレイン電極１０８のダイオード特性における耐圧及びオン抵抗の関係の実験結果を示したものである。 3C shows the breakdown voltage and on-resistance in the diode characteristics of the gate electrode 110 and the drain electrode 108 for the single channel structure having one electron transit layer of FIG. 3A and the double channel structure having two electron transit layers of FIG. 3B. It shows the experimental result of the relationship.
　図３Ｃから、耐圧が両者でほぼ同等の場合、ダブルチャネル構造ではオン抵抗は約半分に低減可能であることがわかる。従って、例えばＧａＮ／ＡｌＧａＮ／ＧａＮ／ＡｌＧａＮの積層構造を用いることで、ＧａＮ／ＡｌＧａＮの１つのヘテロ接合界面のみを備える従来のＦＥＴに対して走行する電子の量を増し、オン抵抗を低減することが可能である。このダブルチャネル構造をゲート電極１１０の両脇に設けることで、同一の耐圧を維持したまま、ＦＥＴのソース及びドレインの寄生抵抗を約半分に抑制することができる。特に、ドレイン側は通常電界が集中する箇所であるが、多層の電子走行層を備えても耐圧を低下させることはない。このとき、ＧａＮ／ＡｌＧａＮ／ＧａＮ／ＡｌＧａＮの積層構造の縦方向抵抗は各窒化物半導体層の膜厚や組成を設計することで低減することが可能である。 FIG. 3C shows that the on-resistance can be reduced to about half in the double channel structure when the breakdown voltage is almost the same in both cases. Therefore, for example, by using a laminated structure of GaN / AlGaN / GaN / AlGaN, the amount of electrons traveling with respect to a conventional FET having only one heterojunction interface of GaN / AlGaN is increased, and the on-resistance is reduced. Is possible. By providing this double channel structure on both sides of the gate electrode 110, the parasitic resistance of the source and drain of the FET can be suppressed to about half while maintaining the same breakdown voltage. In particular, the drain side is usually a portion where the electric field is concentrated, but even if a multi-layer electron transit layer is provided, the breakdown voltage is not lowered. At this time, the longitudinal resistance of the laminated structure of GaN / AlGaN / GaN / AlGaN can be reduced by designing the film thickness and composition of each nitride semiconductor layer.
　また、本実施の形態のＦＥＴによれば、ゲート電極１１０の下に絶縁膜１０７が設けられ、ＭＩＳ構造が採用されている。従って、ゲート電極１１０に流れ込む電流を抑制し、ゲート電極１１０に正バイアスを印加でき、ノーマリーオフ型ＦＥＴとして効果的な構造を実現できる。 Further, according to the FET of the present embodiment, the insulating film 107 is provided under the gate electrode 110 and the MIS structure is adopted. Therefore, the current flowing into the gate electrode 110 can be suppressed, a positive bias can be applied to the gate electrode 110, and an effective structure as a normally-off type FET can be realized.
　なお、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層１０３、第２の窒化物半導体層１０４、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６はＩｎを含んでいてもよい。 In the FET of the above embodiment, the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106 contain In. May be.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層１０３は、一部にドーピング層を備えていてもよい。この構造により、窒化物半導体層内での電荷量を制御し、ゲートの閾値電圧を調整することが容易となる。 Further, in the FET of the above embodiment, the first nitride semiconductor layer 103 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
　また、上記実施の形態のＦＥＴにおいて、第４の窒化物半導体層１０６の上には、さらに別の半導体層が配置されてもよい。 In the FET of the above embodiment, another semiconductor layer may be disposed on the fourth nitride semiconductor layer 106.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層１０３、第２の窒化物半導体層１０４、第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６には、例えばＳｉ等のｎ型不純物のドーピングが施されていてもよい。 In the FET of the above-described embodiment, the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the third nitride semiconductor layer 105, and the fourth nitride semiconductor layer 106 include, for example, Si. N-type impurities such as n-type impurities may be doped.
　また、上記実施の形態のＦＥＴにおいて、凹部１２０の深さは第３の窒化物半導体層１０５及び第４の窒化物半導体層１０６を貫通する深さであるとしたが、ゲート電極１１０とバルク側チャネルとの距離を短くすることができれば、この深さに限られない。例えば、凹部１２０の深さは、第３の窒化物半導体層１０５に達することなく第４の窒化物半導体層１０６の途中で止まる深さ、又は第４の窒化物半導体層１０６を貫通し、第３の窒化物半導体層１０５の途中で止まる深さであってもよい。 In the FET of the above-described embodiment, the depth of the recess 120 is a depth that penetrates the third nitride semiconductor layer 105 and the fourth nitride semiconductor layer 106. If the distance to the channel can be shortened, the depth is not limited to this. For example, the depth of the recess 120 is a depth that stops in the middle of the fourth nitride semiconductor layer 106 without reaching the third nitride semiconductor layer 105, or penetrates the fourth nitride semiconductor layer 106, 3 may be a depth that stops halfway through the nitride semiconductor layer 105.
　（第２の実施の形態）
　以下、本発明の第２の実施の形態におけるＦＥＴの構成及びその製造方法を説明する。 (Second Embodiment)
Hereinafter, the configuration of the FET and the manufacturing method thereof according to the second embodiment of the present invention will be described.
　図４は、本実施の形態に係るＦＥＴの構成を示す断面図である。 FIG. 4 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
　このＦＥＴは、基板２０１と、バッファ層２０２と、第１の窒化物半導体層２０３と、第２の窒化物半導体層２０４と、第３の窒化物半導体層２０５と、第４の窒化物半導体層２０６と、絶縁膜２０７と、ドレイン電極２０８と、ソース電極２０９と、ゲート電極２１０と、素子分離層２１１とを備えている。 The FET includes a substrate 201, a buffer layer 202, a first nitride semiconductor layer 203, a second nitride semiconductor layer 204, a third nitride semiconductor layer 205, and a fourth nitride semiconductor layer. 206, an insulating film 207, a drain electrode 208, a source electrode 209, a gate electrode 210, and an element isolation layer 211.
　基板２０１は、例えば１０μｍ以上１０００μｍ以下の厚みのサファイア基板、ＳｉＣ基板、Ｓｉ基板、及びＧａＮ基板等である。 The substrate 201 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, or a GaN substrate having a thickness of 10 μm or more and 1000 μm or less.
　バッファ層２０２は、基板２０１に応じた厚み、例えば１００ｎｍのＡｌＮから構成され、基板２０１の上に形成される。 The buffer layer 202 is made of AlN having a thickness corresponding to the substrate 201, for example, 100 nm, and is formed on the substrate 201.
　第１の窒化物半導体層２０３は、例えば２μｍの厚みのアンドープＧａＮから構成され、バッファ層２０２の上に形成される。 The first nitride semiconductor layer 203 is made of undoped GaN having a thickness of 2 μm, for example, and is formed on the buffer layer 202.
　第２の窒化物半導体層２０４は、第１の窒化物半導体層２０３の上に形成され、第１の窒化物半導体層２０３よりもバンドギャップエネルギーが大きい。第２の窒化物半導体層２０４は、例えばアンドープＡｌxＧａ1-xＮ（０＜ｘ≦１）から構成される。例えば、第２の窒化物半導体層２０４は、２０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The second nitride semiconductor layer 204 is formed on the first nitride semiconductor layer 203 and has a larger band gap energy than the first nitride semiconductor layer 203. The second nitride semiconductor layer 204 is made of, for example, undoped Al x Ga 1-x N (0 <x ≦ 1). For example, the second nitride semiconductor layer 204 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 20 nm.
　第３の窒化物半導体層２０５は、第２の窒化物半導体層２０４の上に形成され、第２の窒化物半導体層２０４よりもバンドギャップエネルギーが小さい。第３の窒化物半導体層２０５は、例えば２０ｎｍの厚みのアンドープＧａＮから構成される。 The third nitride semiconductor layer 205 is formed on the second nitride semiconductor layer 204 and has a lower band gap energy than the second nitride semiconductor layer 204. The third nitride semiconductor layer 205 is made of undoped GaN having a thickness of 20 nm, for example.
　第４の窒化物半導体層２０６は、第３の窒化物半導体層２０５の上に形成され、第３の窒化物半導体層２０５よりもバンドギャップエネルギーが大きい。第４の窒化物半導体層２０６は、例えばアンドープＡｌyＧａ1-yＮ（０＜ｙ≦１）から構成される。例えば、第４の窒化物半導体層２０６は、２５ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The fourth nitride semiconductor layer 206 is formed on the third nitride semiconductor layer 205 and has a larger band gap energy than the third nitride semiconductor layer 205. The fourth nitride semiconductor layer 206 is made of, for example, undoped Al y Ga 1-y N (0 <y ≦ 1). For example, the fourth nitride semiconductor layer 206 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
　第１の窒化物半導体層２０３及び第２の窒化物半導体層２０４のヘテロ接合界面と、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６のヘテロ接合界面とには、自発分極及びピエゾ分極により例えば１×１０13ｃｍ-2程度の電荷が生じており、ゲートがオンの状態ではヘテロ接合界面を電子が走行し、特にＦＥＴにおいて横方向の抵抗を大きく下げることができる。 Spontaneous polarization occurs between the heterojunction interface of the first nitride semiconductor layer 203 and the second nitride semiconductor layer 204 and the heterojunction interface of the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206. In addition, electric charges of, for example, about 1 × 10 13 cm −2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
　ここで、より効果的に表面側チャネルの電子がバルク側チャネルに導かれるように、第４の窒化物半導体層２０６のＡｌ組成比は、第２の窒化物半導体層２０４のＡｌ組成比よりも大きい方が望ましく、さらに、第４の窒化物半導体層２０６の厚さは、第２の窒化物半導体層２０４の厚さよりも大きい方が望ましい。また、ゲート電極２１０直下の第２の窒化物半導体層２０４の膜厚を薄くし、ノーマリーオフ型のＦＥＴを実現するために、第２の窒化物半導体層２０４の厚さは、第４の窒化物半導体層２０６の厚さよりも小さい方が望ましい。 Here, the Al composition ratio of the fourth nitride semiconductor layer 206 is higher than the Al composition ratio of the second nitride semiconductor layer 204 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel. The larger one is desirable, and the thickness of the fourth nitride semiconductor layer 206 is desirably larger than the thickness of the second nitride semiconductor layer 204. Further, in order to reduce the thickness of the second nitride semiconductor layer 204 immediately below the gate electrode 210 and realize a normally-off type FET, the thickness of the second nitride semiconductor layer 204 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 206.
　ドレイン電極２０８及びソース電極２０９は、ゲート電極２１０の両側方の領域に形成され、それぞれ第１の窒化物半導体層２０３及び第２の窒化物半導体層２０４のヘテロ接合界面と、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６のヘテロ接合界面とに接触し、該界面領域に生成された電子走行領域と電気的に接続されている。ドレイン電極２０８及びソース電極２０９は、第１の窒化物半導体層２０３に接触している。 The drain electrode 208 and the source electrode 209 are formed in regions on both sides of the gate electrode 210, and the heterojunction interface between the first nitride semiconductor layer 203 and the second nitride semiconductor layer 204 and the third nitride, respectively. It contacts the heterojunction interface between the semiconductor layer 205 and the fourth nitride semiconductor layer 206 and is electrically connected to the electron transit region generated in the interface region. The drain electrode 208 and the source electrode 209 are in contact with the first nitride semiconductor layer 203.
　ドレイン電極２０８及びソース電極２０９は、例えばＴｉ及びＡｌの積層構造体から構成される。 The drain electrode 208 and the source electrode 209 are made of, for example, a laminated structure of Ti and Al.
　第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６には、凹部２２０が形成されている。この凹部２２０は、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６を貫通、つまり第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６のヘテロ接合界面を貫通して第２の窒化物半導体層２０４の表面まで達している。そして、凹部２２０内には、ゲート電極２１０が形成されている。凹部２２０は、特に第２の窒化物半導体層２０４に対して第３の窒化物半導体層２０５を選択的にエッチングすることにより形成されている。 A recess 220 is formed in the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206. The recess 220 penetrates the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 205 and the fourth nitride semiconductor layer 206. And reaches the surface of the second nitride semiconductor layer 204. A gate electrode 210 is formed in the recess 220. The recess 220 is formed by selectively etching the third nitride semiconductor layer 205 with respect to the second nitride semiconductor layer 204 in particular.
　ここで、第２の窒化物半導体層２０４には凹部２２０は形成されておらず、凹部２２０の底面としての第２の窒化物半導体層２０４の表面は、第２の窒化物半導体層２０４及び第３の窒化物半導体層２０５の界面と面一である。ここでの面一とは、第２の窒化物半導体層２０４の表面に対するエッチングの精度による、数ｎｍ程度のずれがあっても良い。 Here, the concave portion 220 is not formed in the second nitride semiconductor layer 204, and the surface of the second nitride semiconductor layer 204 serving as the bottom surface of the concave portion 220 is the second nitride semiconductor layer 204 and the second nitride semiconductor layer 204. 3 is flush with the interface of the nitride semiconductor layer 205. Here, there may be a deviation of about several nanometers depending on the etching accuracy with respect to the surface of the second nitride semiconductor layer 204.
　ゲート電極２１０は、例えばＰｄ、Ｎｉ及びＰｔ等から構成される。なお、ゲート電極２１０は、ゲート電極２１０を構成する材料が絶縁膜２０７により窒化物半導体層に拡散しない場合にはＴｉから構成されてもよい。 The gate electrode 210 is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 210 may be made of Ti when the material constituting the gate electrode 210 is not diffused into the nitride semiconductor layer by the insulating film 207.
　絶縁膜２０７は、凹部２２０の底面及び側面並びに第４の窒化物半導体層２０６表面に形成されている。凹部２２０の底面及び側面に形成された絶縁膜２０７は、第２の窒化物半導体層２０４、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６とゲート電極２１０とに挟み込まれている。 The insulating film 207 is formed on the bottom and side surfaces of the recess 220 and the surface of the fourth nitride semiconductor layer 206. The insulating film 207 formed on the bottom and side surfaces of the recess 220 is sandwiched between the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, the fourth nitride semiconductor layer 206, and the gate electrode 210. Yes.
　絶縁膜２０７は、例えばＳｉＮ、ＳｉＯ、ＡｌＮ、ＡｌＯ、ＳｉＮ及びＡｌＮの積層構造体、並びにＳｉＮ及びＡｌＯの積層構造体等から構成される。絶縁膜２０７がＳｉＮ又はＳｉＯから構成される場合、絶縁膜２０７は例えばＣＶＤ法や減圧ＣＶＤ法により成膜される。一方、絶縁膜２０７がＡｌＮ又はＡｌＯから構成される場合、絶縁膜２０７は例えばスパッタ法や原子層堆積装置を用いたＡＬＤ法により成膜される。 The insulating film 207 includes, for example, a stacked structure of SiN, SiO, AlN, AlO, SiN, and AlN, a stacked structure of SiN and AlO, and the like. When the insulating film 207 is made of SiN or SiO, the insulating film 207 is formed by, for example, a CVD method or a low pressure CVD method. On the other hand, when the insulating film 207 is made of AlN or AlO, the insulating film 207 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
　素子分離層２１１は、例えば窒化物半導体層にＢ等の不純物をイオン注入することにより形成され、ＦＥＴを他の素子と電気的に分離する。 The element isolation layer 211 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
　以上のように、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、オン抵抗を低減することができる。 As described above, according to the FET of the present embodiment, the on-resistance can be reduced for the same reason as the FET of the first embodiment.
　また、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、ノーマリーオフ型ＦＥＴとして効果的な構造を実現できる。 Further, according to the FET of the present embodiment, an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
　また、本実施の形態のＦＥＴによれば、選択エッチングにより凹部２２０が形成され、ゲート電極２１０直下の第２の窒化物半導体層２０４の膜厚を正確に制御することができる。従って、ゲートの閾値電圧を調整することが容易となる。 Further, according to the FET of the present embodiment, the recess 220 is formed by selective etching, and the thickness of the second nitride semiconductor layer 204 immediately below the gate electrode 210 can be accurately controlled. Therefore, it becomes easy to adjust the threshold voltage of the gate.
　なお、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層２０３、第２の窒化物半導体層２０４、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６はＩｎを含んでいてもよい。 In the FET of the above embodiment, the first nitride semiconductor layer 203, the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, and the fourth nitride semiconductor layer 206 contain In. May be.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層２０３は、一部にドーピング層を備えていてもよい。この構造により、窒化物半導体層内での電荷量を制御し、ゲートの閾値電圧を調整することが容易となる。 Further, in the FET of the above embodiment, the first nitride semiconductor layer 203 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
　また、上記実施の形態のＦＥＴにおいて、第４の窒化物半導体層２０６の上には、さらに別の半導体層が配置されてもよい。 In the FET of the above embodiment, another semiconductor layer may be disposed on the fourth nitride semiconductor layer 206.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層２０３、第２の窒化物半導体層２０４、第３の窒化物半導体層２０５及び第４の窒化物半導体層２０６には、例えばＳｉ等のｎ型不純物のドーピングが施されていてもよい。 In the FET of the above-described embodiment, the first nitride semiconductor layer 203, the second nitride semiconductor layer 204, the third nitride semiconductor layer 205, and the fourth nitride semiconductor layer 206 include, for example, Si. N-type impurities such as n-type impurities may be doped.
　（第３の実施の形態）
　以下、本発明の第３の実施の形態におけるＦＥＴの構成及びその製造方法を説明する。 (Third embodiment)
Hereinafter, the configuration of the FET and the manufacturing method thereof according to the third embodiment of the present invention will be described.
　図５は、本実施の形態に係るＦＥＴの構成を示す断面図である。 FIG. 5 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
　このＦＥＴは、基板３０１と、バッファ層３０２と、第１の窒化物半導体層３０３と、第２の窒化物半導体層３０４と、第３の窒化物半導体層３０５と、第４の窒化物半導体層３０６と、絶縁膜３０７と、ドレイン電極３０８と、ソース電極３０９と、ゲート電極３１０と、素子分離層３１１と、第５の窒化物半導体層３１２とを備えている。 The FET includes a substrate 301, a buffer layer 302, a first nitride semiconductor layer 303, a second nitride semiconductor layer 304, a third nitride semiconductor layer 305, and a fourth nitride semiconductor layer. 306, an insulating film 307, a drain electrode 308, a source electrode 309, a gate electrode 310, an element isolation layer 311, and a fifth nitride semiconductor layer 312.
　基板３０１は、例えば１０μｍ以上１０００μｍ以下の厚みのサファイア基板、ＳｉＣ基板、Ｓｉ基板、及びＧａＮ基板等である。 The substrate 301 is, for example, a sapphire substrate having a thickness of 10 μm or more and 1000 μm or less, a SiC substrate, a Si substrate, a GaN substrate, or the like.
　バッファ層３０２は、基板３０１に応じた厚み、例えば１００ｎｍのＡｌＮから構成され、基板３０１の上に形成される。 The buffer layer 302 is made of AlN having a thickness corresponding to the substrate 301, for example, 100 nm, and is formed on the substrate 301.
　第１の窒化物半導体層３０３は、例えば２μｍの厚みのアンドープＧａＮから構成され、バッファ層３０２の上に形成される。 The first nitride semiconductor layer 303 is made of undoped GaN having a thickness of 2 μm, for example, and is formed on the buffer layer 302.
　第２の窒化物半導体層３０４は、第１の窒化物半導体層３０３の上に形成され、第１の窒化物半導体層３０３よりもバンドギャップエネルギーが大きい。第２の窒化物半導体層３０４は、例えばアンドープＡｌxＧａ1-xＮ（０＜ｘ≦１）から構成される。例えば、第２の窒化物半導体層３０４は、２０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The second nitride semiconductor layer 304 is formed on the first nitride semiconductor layer 303 and has a larger band gap energy than the first nitride semiconductor layer 303. The second nitride semiconductor layer 304 is made of, for example, undoped Al x Ga 1-x N (0 <x ≦ 1). For example, the second nitride semiconductor layer 304 is composed of 20 nm thick undoped Al 0.25 Ga 0.75 N.
　第３の窒化物半導体層３０５は、第２の窒化物半導体層３０４の上に形成され、第２の窒化物半導体層３０４よりもバンドギャップエネルギーが小さい。第３の窒化物半導体層３０５は、例えば２０ｎｍの厚みのアンドープＧａＮから構成される。 The third nitride semiconductor layer 305 is formed on the second nitride semiconductor layer 304 and has a lower band gap energy than the second nitride semiconductor layer 304. The third nitride semiconductor layer 305 is made of undoped GaN having a thickness of 20 nm, for example.
　第４の窒化物半導体層３０６は、第３の窒化物半導体層３０５の上に形成され、第３の窒化物半導体層３０５よりもバンドギャップエネルギーが大きい。第４の窒化物半導体層３０６は、例えばアンドープＡｌyＧａ1-yＮ（０＜ｙ≦１）から構成される。例えば、第４の窒化物半導体層３０６は、２５ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The fourth nitride semiconductor layer 306 is formed on the third nitride semiconductor layer 305 and has a larger band gap energy than the third nitride semiconductor layer 305. The fourth nitride semiconductor layer 306 is made of, for example, undoped Al y Ga 1-y N (0 <y ≦ 1). For example, the fourth nitride semiconductor layer 306 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
　第１の窒化物半導体層３０３及び第２の窒化物半導体層３０４のヘテロ接合界面と、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６のヘテロ接合界面とには、自発分極及びピエゾ分極により例えば１×１０13ｃｍ-2程度の電荷が生じており、ゲートがオンの状態ではヘテロ接合界面を電子が走行し、特にＦＥＴにおいて横方向の抵抗を大きく下げることができる。 Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 and the heterojunction interface between the third nitride semiconductor layer 305 and the fourth nitride semiconductor layer 306. In addition, electric charges of, for example, about 1 × 10 13 cm −2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
　ここで、より効果的に表面側チャネルの電子がバルク側チャネルに導かれるように、第４の窒化物半導体層３０６のＡｌ組成比は、第２の窒化物半導体層３０４及び第５の窒化物半導体層３１２のＡｌ組成比よりも大きい方が望ましく、さらに、第４の窒化物半導体層３０６の厚さは、第２の窒化物半導体層３０４及び第５の窒化物半導体層３１２の厚さよりも大きい方が望ましい。また、ゲート電極３１０直下の第５の窒化物半導体層３１２の膜厚を薄くし、ノーマリーオフ型のＦＥＴを実現するために、第５の窒化物半導体層３１２の厚さは、第４の窒化物半導体層３０６の厚さよりも小さい方が望ましい。 Here, the Al composition ratio of the fourth nitride semiconductor layer 306 is set so that the electrons in the surface side channel are guided to the bulk side channel more effectively. The Al composition ratio of the semiconductor layer 312 is desirably larger, and the thickness of the fourth nitride semiconductor layer 306 is more than the thickness of the second nitride semiconductor layer 304 and the fifth nitride semiconductor layer 312. The larger one is desirable. In addition, in order to reduce the thickness of the fifth nitride semiconductor layer 312 immediately below the gate electrode 310 and realize a normally-off FET, the thickness of the fifth nitride semiconductor layer 312 is It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 306.
　ドレイン電極３０８及びソース電極３０９は、ゲート電極３１０の両側方の領域に形成され、それぞれ第１の窒化物半導体層３０３及び第２の窒化物半導体層３０４のヘテロ接合界面と、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６のヘテロ接合界面とに接触し、該界面領域に生成された電子走行領域と電気的に接続されている。ドレイン電極３０８及びソース電極３０９は、第１の窒化物半導体層３０３に接触している。 The drain electrode 308 and the source electrode 309 are formed in regions on both sides of the gate electrode 310, and the heterojunction interface between the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 and the third nitride, respectively. It is in contact with the heterojunction interface between the semiconductor layer 305 and the fourth nitride semiconductor layer 306, and is electrically connected to the electron transit region generated in the interface region. The drain electrode 308 and the source electrode 309 are in contact with the first nitride semiconductor layer 303.
　ドレイン電極３０８及びソース電極３０９は、例えばＴｉ及びＡｌの積層構造体から構成される。 The drain electrode 308 and the source electrode 309 are composed of a laminated structure of Ti and Al, for example.
　第１の窒化物半導体層３０３、第２の窒化物半導体層３０４、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６には、凹部３２０が形成されている。この凹部３２０は、第２の窒化物半導体層３０４、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６を貫通、つまり第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６のヘテロ接合界面と第１の窒化物半導体層３０３及び第２の窒化物半導体層３０４のヘテロ接合界面とを貫通して第１の窒化物半導体層３０３表面まで達している。そして、凹部３２０内には、ゲート電極３１０が形成されている。 A recess 320 is formed in the first nitride semiconductor layer 303, the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306. The recess 320 penetrates through the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306, that is, the third nitride semiconductor layer 305 and the fourth nitride semiconductor. The heterojunction interface of the layer 306 and the heterojunction interfaces of the first nitride semiconductor layer 303 and the second nitride semiconductor layer 304 penetrate to the surface of the first nitride semiconductor layer 303. A gate electrode 310 is formed in the recess 320.
　ゲート電極３１０は、例えばＰｄ、Ｎｉ及びＰｔ等から構成される。なお、ゲート電極３１０は、ゲート電極３１０を構成する材料が絶縁膜３０７により窒化物半導体層に拡散しない場合にはＴｉから構成されてもよい。 The gate electrode 310 is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 310 may be made of Ti when the material constituting the gate electrode 310 is not diffused into the nitride semiconductor layer by the insulating film 307.
　第５の窒化物半導体層３１２は、凹部３２０の底面及び側面並びに第４の窒化物半導体層３０６表面に形成され、例えばアンドープＡｌzＧａ1-zＮ（０＜ｚ≦１）から構成される。例えば、第５の窒化物半導体層３１２は、１０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。第５の窒化物半導体層３１２は、例えば有機金属化学気相蒸着法（Metal-Organic Chemical Vapor Deposition：ＭＯＣＶＤ法）により凹部３２０内で窒化物半導体層をエピタキシャル成長させることにより形成される。絶縁膜３０７は、このエピタキシャル成長に連続して大気にさらすことなく（ｉｎ－ｓｉｔｕで）形成される。ゲート電極３１０は凹部３２０内で絶縁膜３０７に接している。 The fifth nitride semiconductor layer 312 is formed on the bottom and side surfaces of the recess 320 and the surface of the fourth nitride semiconductor layer 306, and is made of, for example, undoped Al z Ga 1 -z N (0 <z ≦ 1). . For example, the fifth nitride semiconductor layer 312 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 10 nm. The fifth nitride semiconductor layer 312 is formed by epitaxially growing a nitride semiconductor layer in the recess 320 by, for example, metal-organic chemical vapor deposition (MOCVD). The insulating film 307 is formed continuously in this epitaxial growth without being exposed to the atmosphere (in-situ). The gate electrode 310 is in contact with the insulating film 307 in the recess 320.
　第５の窒化物半導体層３１２が存在することにより、絶縁膜３０７の結晶性を高め、また再現性よく形成することができる。凹部３２０の底面の窒化物半導体上に直接絶縁膜３０７を成長させるよりも、同じ窒化物半導体層である第５の窒化物半導体層３１２を形成してから連続成長により絶縁膜３０７を形成した方が、絶縁膜３０７の結晶性および再現性を向上できる。また、第５の窒化物半導体層３１２が例えばアンドープＡｌzＧａ1-zＮ（０＜ｚ≦１）層であり、凹部３２０の底面で接する層が例えばＧａＮ層である構成のように、第５の窒化物半導体層３１２のＡｌ組成Ｘが凹部３２０底面のＡｌ組成と比較して大きい場合に、第５の窒化物半導体層３１２下にチャネル層が形成される。その際に誘起される電荷量は、制御性の高いエピタキシャル成長で形成される第５の窒化物半導体層３１２の膜厚や組成で決定されることから、再現性を高くすることが可能となる。 The presence of the fifth nitride semiconductor layer 312 can increase the crystallinity of the insulating film 307 and can be formed with good reproducibility. Rather than directly growing the insulating film 307 on the nitride semiconductor on the bottom surface of the recess 320, the fifth nitride semiconductor layer 312 that is the same nitride semiconductor layer is formed and then the insulating film 307 is formed by continuous growth. However, the crystallinity and reproducibility of the insulating film 307 can be improved. Further, the fifth nitride semiconductor layer 312 is, for example, an undoped Al z Ga 1-z N (0 <z ≦ 1) layer, and the layer in contact with the bottom surface of the recess 320 is, for example, a GaN layer. A channel layer is formed under the fifth nitride semiconductor layer 312 when the Al composition X of the fifth nitride semiconductor layer 312 is larger than the Al composition at the bottom of the recess 320. The amount of charge induced at that time is determined by the film thickness and composition of the fifth nitride semiconductor layer 312 formed by epitaxial growth with high controllability, so that reproducibility can be enhanced.
　絶縁膜３０７は、第５の窒化物半導体層３１２の上に形成されている。凹部３２０内の絶縁膜３０７は、第５の窒化物半導体層３１２とゲート電極３１０との間に形成され、挟み込まれている。 The insulating film 307 is formed on the fifth nitride semiconductor layer 312. The insulating film 307 in the recess 320 is formed and sandwiched between the fifth nitride semiconductor layer 312 and the gate electrode 310.
　絶縁膜３０７は、例えば１～５ｎｍの厚みのＳｉＮ、ＳｉＯ、ＡｌＮ、ＡｌＯ、ＳｉＮ及びＡｌＮの積層構造体、並びにＳｉＮ及びＡｌＯの積層構造体等から構成される。絶縁膜３０７がＳｉＮ又はＳｉＯから構成される場合、絶縁膜３０７は例えばＣＶＤ法や減圧ＣＶＤ法により成膜される。一方、絶縁膜３０７がＡｌＮ又はＡｌＯから構成される場合、絶縁膜３０７は例えばスパッタ法や原子層堆積装置を用いたＡＬＤ法により成膜される。 The insulating film 307 is composed of, for example, a laminated structure of SiN, SiO, AlN, AlO, SiN and AlN having a thickness of 1 to 5 nm, a laminated structure of SiN and AlO, and the like. When the insulating film 307 is made of SiN or SiO, the insulating film 307 is formed by, for example, a CVD method or a low pressure CVD method. On the other hand, when the insulating film 307 is made of AlN or AlO, the insulating film 307 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
　素子分離層３１１は、例えば窒化物半導体層にＢ等の不純物をイオン注入することにより形成され、ＦＥＴを他の素子と電気的に分離する。 The element isolation layer 311 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
　以上のように、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、オン抵抗を低減することができる。 As described above, according to the FET of the present embodiment, the on-resistance can be reduced for the same reason as the FET of the first embodiment.
　また、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、ノーマリーオフ型ＦＥＴとして効果的な構造を実現できる。 Further, according to the FET of the present embodiment, an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
　また、本実施の形態のＦＥＴによれば、凹部３２０内における第５の窒化物半導体層３１２のエピタキシャル成長と連続して絶縁膜３０７を形成することができるので、良好な絶縁特性の絶縁膜３０７を実現できる。 Further, according to the FET of the present embodiment, since the insulating film 307 can be formed continuously with the epitaxial growth of the fifth nitride semiconductor layer 312 in the recess 320, the insulating film 307 having good insulating characteristics can be formed. realizable.
　なお、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層３０３、第２の窒化物半導体層３０４、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６はＩｎを含んでいてもよい。 Note that in the FET of the above embodiment, the first nitride semiconductor layer 303, the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306 contain In. May be.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層３０３は、一部にドーピング層を備えていてもよい。この構造により、窒化物半導体層内での電荷量を制御し、ゲートの閾値電圧を調整することが容易となる。 In the FET of the above embodiment, the first nitride semiconductor layer 303 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
　また、上記実施の形態のＦＥＴにおいて、第４の窒化物半導体層３０６の上には、さらに別の半導体層が配置されてもよい。 Further, in the FET of the above embodiment, another semiconductor layer may be disposed on the fourth nitride semiconductor layer 306.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層３０３、第２の窒化物半導体層３０４、第３の窒化物半導体層３０５、第４の窒化物半導体層３０６及び第５の窒化物半導体層３１２には、例えばＳｉ等のｎ型不純物のドーピングが施されていてもよい。 In the FET of the above embodiment, the first nitride semiconductor layer 303, the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, the fourth nitride semiconductor layer 306, and the fifth nitride The physical semiconductor layer 312 may be doped with an n-type impurity such as Si.
　また、上記実施の形態のＦＥＴにおいて、凹部３２０の深さは第２の窒化物半導体層３０４、第３の窒化物半導体層３０５及び第４の窒化物半導体層３０６を貫通する深さであるとしたが、ゲート電極３１０とバルク側チャネルとの距離を短くすることができれば、この深さに限られない。例えば、凹部３２０の深さは、第３の窒化物半導体層３０５に達することなく第４の窒化物半導体層３０６の途中で止まる深さ、第４の窒化物半導体層３０６を貫通し、第３の窒化物半導体層３０５の途中で止まる深さ、又は第４の窒化物半導体層３０６及び第３の窒化物半導体層３０５を貫通し、第２の窒化物半導体層３０４の途中で止まる深さであってもよい。 Further, in the FET of the above embodiment, the depth of the recess 320 is a depth penetrating the second nitride semiconductor layer 304, the third nitride semiconductor layer 305, and the fourth nitride semiconductor layer 306. However, the depth is not limited as long as the distance between the gate electrode 310 and the bulk side channel can be shortened. For example, the depth of the recess 320 is deep enough to stop in the middle of the fourth nitride semiconductor layer 306 without reaching the third nitride semiconductor layer 305, penetrate through the fourth nitride semiconductor layer 306, The depth that stops in the middle of the nitride semiconductor layer 305, or the depth that passes through the fourth nitride semiconductor layer 306 and the third nitride semiconductor layer 305 and stops in the middle of the second nitride semiconductor layer 304. There may be.
　（第４の実施の形態）
　以下、本発明の第４の実施の形態におけるＦＥＴの構成及びその製造方法を説明する。 (Fourth embodiment)
Hereinafter, the configuration of the FET and the manufacturing method thereof according to the fourth embodiment of the present invention will be described.
　図６は、本実施の形態に係るＦＥＴの構成を示す断面図である。 FIG. 6 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
　このＦＥＴは、基板４０１と、バッファ層４０２と、第１の窒化物半導体層４０３と、第２の窒化物半導体層４０４と、第３の窒化物半導体層４０５と、第４の窒化物半導体層４０６と、ドレイン電極４０８と、ソース電極４０９と、ゲート電極４１０と、素子分離層４１１とを備えている。 This FET includes a substrate 401, a buffer layer 402, a first nitride semiconductor layer 403, a second nitride semiconductor layer 404, a third nitride semiconductor layer 405, and a fourth nitride semiconductor layer. 406, a drain electrode 408, a source electrode 409, a gate electrode 410, and an element isolation layer 411 are provided.
　基板４０１は、例えば１０μｍ以上１０００μｍ以下の厚みのサファイア基板、ＳｉＣ基板、Ｓｉ基板、及びＧａＮ基板等である。 The substrate 401 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, or the like having a thickness of 10 μm to 1000 μm.
　バッファ層４０２は、基板４０１に応じた厚み、例えば１００ｎｍのＡｌＮから構成され、基板４０１の上に形成される。 The buffer layer 402 is made of AlN having a thickness corresponding to the substrate 401, for example, 100 nm, and is formed on the substrate 401.
　第１の窒化物半導体層４０３は、例えば２μｍの厚みのアンドープＧａＮから構成され、バッファ層４０２の上に形成される。 The first nitride semiconductor layer 403 is made of undoped GaN having a thickness of 2 μm, for example, and is formed on the buffer layer 402.
　第２の窒化物半導体層４０４は、第１の窒化物半導体層４０３の上に形成され、第１の窒化物半導体層４０３よりもバンドギャップエネルギーが大きい。第２の窒化物半導体層４０４は、例えばアンドープＡｌxＧａ1-xＮ（０＜ｘ≦１）から構成される。例えば、第２の窒化物半導体層４０４は、３０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The second nitride semiconductor layer 404 is formed on the first nitride semiconductor layer 403 and has a larger band gap energy than the first nitride semiconductor layer 403. The second nitride semiconductor layer 404 is made of, for example, undoped Al x Ga 1-x N (0 <x ≦ 1). For example, the second nitride semiconductor layer 404 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 30 nm.
　第３の窒化物半導体層４０５は、第２の窒化物半導体層４０４の上に形成され、第２の窒化物半導体層４０４よりもバンドギャップエネルギーが小さい。第３の窒化物半導体層４０５は、例えば３０ｎｍの厚みのアンドープＧａＮから構成される。 The third nitride semiconductor layer 405 is formed on the second nitride semiconductor layer 404 and has a lower band gap energy than the second nitride semiconductor layer 404. The third nitride semiconductor layer 405 is made of undoped GaN having a thickness of 30 nm, for example.
　第４の窒化物半導体層４０６は、第３の窒化物半導体層４０５の上に形成され、第３の窒化物半導体層４０５よりもバンドギャップエネルギーが大きい。第４の窒化物半導体層４０６は、例えばアンドープＡｌyＧａ1-yＮ（０＜ｙ≦１）から構成される。例えば、第４の窒化物半導体層４０６は、３０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The fourth nitride semiconductor layer 406 is formed on the third nitride semiconductor layer 405 and has a larger band gap energy than the third nitride semiconductor layer 405. The fourth nitride semiconductor layer 406 is made of, for example, undoped Al y Ga 1-y N (0 <y ≦ 1). For example, the fourth nitride semiconductor layer 406 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 30 nm.
　第１の窒化物半導体層４０３及び第２の窒化物半導体層４０４のヘテロ接合界面と、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６のヘテロ接合界面とには、自発分極及びピエゾ分極により例えば１×１０13ｃｍ-2程度の電荷が生じており、ゲートがオンの状態ではヘテロ接合界面を電子が走行し、特にＦＥＴにおいて横方向の抵抗を大きく下げることができる。 Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 403 and the second nitride semiconductor layer 404 and the heterojunction interface between the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. In addition, electric charges of, for example, about 1 × 10 13 cm −2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
　ここで、より効果的に表面側チャネルの電子がバルク側チャネルに導かれるように、第４の窒化物半導体層４０６のＡｌ組成比は、第２の窒化物半導体層４０４のＡｌ組成比よりも大きい方が望ましく、さらに、第４の窒化物半導体層４０６の厚さは、第２の窒化物半導体層４０４の厚さよりも大きい方が望ましい。 Here, the Al composition ratio of the fourth nitride semiconductor layer 406 is higher than the Al composition ratio of the second nitride semiconductor layer 404 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel. The larger one is desirable, and the thickness of the fourth nitride semiconductor layer 406 is desirably larger than the thickness of the second nitride semiconductor layer 404.
　ドレイン電極４０８及びソース電極４０９は、ゲート電極４１０の両側方の領域に形成され、それぞれ第１の窒化物半導体層４０３及び第２の窒化物半導体層４０４のヘテロ接合界面と、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６のヘテロ接合界面とに接触し、該界面領域に生成された電子走行領域と電気的に接続されている。ドレイン電極４０８及びソース電極４０９は、第１の窒化物半導体層４０３に接触している。 The drain electrode 408 and the source electrode 409 are formed in the regions on both sides of the gate electrode 410, and the heterojunction interface between the first nitride semiconductor layer 403 and the second nitride semiconductor layer 404 and the third nitride, respectively. It contacts the heterojunction interface between the semiconductor layer 405 and the fourth nitride semiconductor layer 406 and is electrically connected to the electron transit region generated in the interface region. The drain electrode 408 and the source electrode 409 are in contact with the first nitride semiconductor layer 403.
　ドレイン電極４０８及びソース電極４０９は、例えばＴｉ及びＡｌの積層構造体から構成される。 The drain electrode 408 and the source electrode 409 are made of a laminated structure of Ti and Al, for example.
　第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６には凹部４２０が形成されている。この凹部４２０は、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６を貫通、つまり第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６のヘテロ接合界面を貫通して第２の窒化物半導体層４０４の表面まで達している。そして、凹部４２０内には、凹部４２０の底面及び側面を覆うようにゲート電極４１０が形成されている。従って、凹部４２０内のゲート電極４１０は、絶縁膜を介することなく、第２の窒化物半導体層４０４、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６に直接接している。凹部４２０は、特に第２の窒化物半導体層４０４に対して第３の窒化物半導体層４０５を選択的にエッチングすることにより形成されている。 A recess 420 is formed in the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. The recess 420 penetrates the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406, that is, penetrates the heterojunction interface between the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. And reaches the surface of the second nitride semiconductor layer 404. A gate electrode 410 is formed in the recess 420 so as to cover the bottom and side surfaces of the recess 420. Therefore, the gate electrode 410 in the recess 420 is in direct contact with the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 without an insulating film interposed therebetween. The recess 420 is formed by selectively etching the third nitride semiconductor layer 405 with respect to the second nitride semiconductor layer 404 in particular.
　ここで、第２の窒化物半導体層４０４には凹部４２０は形成されておらず、凹部４２０の底面としての第２の窒化物半導体層４０４の表面は、第２の窒化物半導体層４０４及び第３の窒化物半導体層４０５の界面と面一である。 Here, the concave portion 420 is not formed in the second nitride semiconductor layer 404, and the surface of the second nitride semiconductor layer 404 serving as the bottom surface of the concave portion 420 is the second nitride semiconductor layer 404 and the second nitride semiconductor layer 404. 3 is flush with the interface of the nitride semiconductor layer 405.
　ゲート電極４１０は、第２の窒化物半導体層４０４、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６とショットキー接合し、例えばＰｄ、Ｎｉ及びＰｔ等から構成される。 The gate electrode 410 is in Schottky junction with the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406, and is made of, for example, Pd, Ni, Pt, or the like.
　素子分離層４１１は、例えば窒化物半導体層にＢ等の不純物をイオン注入することにより形成され、ＦＥＴを他の素子と電気的に分離する。 The element isolation layer 411 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
　以上のように、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、オン抵抗を低減することができる。 As described above, according to the FET of the present embodiment, the on-resistance can be reduced for the same reason as the FET of the first embodiment.
　なお、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層４０３、第２の窒化物半導体層４０４、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６はＩｎを含んでいてもよい。 Note that in the FET of the above embodiment, the first nitride semiconductor layer 403, the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 contain In. May be.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層４０３は、一部にドーピング層を備えていてもよい。この構造により、窒化物半導体層内での電荷量を制御し、ゲートの閾値電圧を調整することが容易となる。 In the FET of the above embodiment, the first nitride semiconductor layer 403 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
　また、上記実施の形態のＦＥＴにおいて、第４の窒化物半導体層４０６の上には、さらに別の半導体層が配置されてもよい。 In the FET of the above embodiment, another semiconductor layer may be disposed on the fourth nitride semiconductor layer 406.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層４０３、第２の窒化物半導体層４０４、第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６には、例えばＳｉ等のｎ型不純物のドーピングが施されていてもよい。 In the FET of the above embodiment, the first nitride semiconductor layer 403, the second nitride semiconductor layer 404, the third nitride semiconductor layer 405, and the fourth nitride semiconductor layer 406 include, for example, Si. N-type impurities such as n-type impurities may be doped.
　また、上記実施の形態のＦＥＴにおいて、凹部４２０の深さは第３の窒化物半導体層４０５及び第４の窒化物半導体層４０６を貫通する深さであるとしたが、ゲート電極４１０とバルク側チャネルとの距離を短くすることができれば、この深さに限られない。例えば、凹部４２０の深さは、第３の窒化物半導体層４０５に達することなく第４の窒化物半導体層４０６の途中で止まる深さ、又は第４の窒化物半導体層４０６を貫通し、第３の窒化物半導体層４０５の途中で止まる深さであってもよい。 In the FET of the above embodiment, the depth of the recess 420 is a depth that penetrates the third nitride semiconductor layer 405 and the fourth nitride semiconductor layer 406. If the distance to the channel can be shortened, the depth is not limited to this. For example, the depth of the recess 420 is a depth that stops in the middle of the fourth nitride semiconductor layer 406 without reaching the third nitride semiconductor layer 405, or penetrates the fourth nitride semiconductor layer 406, 3 may be a depth that stops halfway through the nitride semiconductor layer 405.
　（第５の実施の形態）
　以下、本発明の第５の実施の形態におけるＦＥＴの構成及びその製造方法を説明する。 (Fifth embodiment)
Hereinafter, the configuration of the FET and the manufacturing method thereof according to the fifth embodiment of the present invention will be described.
　図７は、本実施の形態に係るＦＥＴの構成を示す断面図である。 FIG. 7 is a cross-sectional view showing the configuration of the FET according to the present embodiment.
　このＦＥＴは、基板５０１と、バッファ層５０２と、第１の窒化物半導体層５０３と、第２の窒化物半導体層５０４と、第３の窒化物半導体層５０５と、第４の窒化物半導体層５０６と、絶縁膜５０７と、ドレイン電極５０８と、ソース電極５０９と、ゲート電極５１０と、素子分離層５１１とを備えている。 This FET includes a substrate 501, a buffer layer 502, a first nitride semiconductor layer 503, a second nitride semiconductor layer 504, a third nitride semiconductor layer 505, and a fourth nitride semiconductor layer. 506, an insulating film 507, a drain electrode 508, a source electrode 509, a gate electrode 510, and an element isolation layer 511 are provided.
　基板５０１は、例えば１０μｍ以上１０００μｍ以下の厚みのサファイア基板、ＳｉＣ基板、Ｓｉ基板、及びＧａＮ基板等である。 The substrate 501 is, for example, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, or the like having a thickness of 10 μm or more and 1000 μm or less.
　バッファ層５０２は、基板５０１に応じた厚み、厚さ例えば１００ｎｍのＡｌＮから構成され、基板５０１の上に形成される。 The buffer layer 502 is made of AlN having a thickness corresponding to the substrate 501, for example, 100 nm, and is formed on the substrate 501.
　第１の窒化物半導体層５０３は、例えば２μｍの厚みのアンドープＧａＮから構成され、バッファ層５０２の上に形成される。 The first nitride semiconductor layer 503 is made of undoped GaN having a thickness of 2 μm, for example, and is formed on the buffer layer 502.
　第２の窒化物半導体層５０４は、第１の窒化物半導体層５０３の上に形成され、第１の窒化物半導体層５０３よりもバンドギャップエネルギーが大きい。第２の窒化物半導体層５０４は、例えばアンドープＡｌxＧａ1-xＮ（０＜ｘ≦１）から構成される。例えば、第２の窒化物半導体層５０４は、２０ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The second nitride semiconductor layer 504 is formed on the first nitride semiconductor layer 503 and has a larger band gap energy than the first nitride semiconductor layer 503. The second nitride semiconductor layer 504 is made of, for example, undoped Al x Ga 1-x N (0 <x ≦ 1). For example, the second nitride semiconductor layer 504 is composed of 20 nm thick undoped Al 0.25 Ga 0.75 N.
　第３の窒化物半導体層５０５は、第２の窒化物半導体層５０４の上に形成され、第２の窒化物半導体層５０４よりもバンドギャップエネルギーが小さい。第３の窒化物半導体層５０５は、例えば２０ｎｍの厚みのアンドープＧａＮから構成される。 The third nitride semiconductor layer 505 is formed on the second nitride semiconductor layer 504 and has a smaller band gap energy than the second nitride semiconductor layer 504. The third nitride semiconductor layer 505 is made of undoped GaN having a thickness of 20 nm, for example.
　第４の窒化物半導体層５０６は、第３の窒化物半導体層５０５の上に形成され、第３の窒化物半導体層５０５よりもバンドギャップエネルギーが大きい。第４の窒化物半導体層５０６は、例えばアンドープＡｌyＧａ1-yＮ（０＜ｙ≦１）から構成される。例えば、第４の窒化物半導体層５０６は、２５ｎｍの厚みのアンドープＡｌ0.25Ｇａ0.75Ｎから構成される。 The fourth nitride semiconductor layer 506 is formed on the third nitride semiconductor layer 505 and has a larger band gap energy than the third nitride semiconductor layer 505. The fourth nitride semiconductor layer 506 is made of, for example, undoped Al y Ga 1-y N (0 <y ≦ 1). For example, the fourth nitride semiconductor layer 506 is made of undoped Al 0.25 Ga 0.75 N having a thickness of 25 nm.
　第１の窒化物半導体層５０３及び第２の窒化物半導体層５０４のヘテロ接合界面と、第３の窒化物半導体層５０５及び第４の窒化物半導体層５０６のヘテロ接合界面とには、自発分極及びピエゾ分極により例えば１×１０13ｃｍ-2程度の電荷が生じており、ゲートがオンの状態ではヘテロ接合界面を電子が走行し、特にＦＥＴにおいて横方向の抵抗を大きく下げることができる。 Spontaneous polarization occurs between the heterojunction interface between the first nitride semiconductor layer 503 and the second nitride semiconductor layer 504 and the heterojunction interface between the third nitride semiconductor layer 505 and the fourth nitride semiconductor layer 506. In addition, electric charges of, for example, about 1 × 10 13 cm −2 are generated by piezo polarization, and electrons run through the heterojunction interface when the gate is on, and the lateral resistance can be greatly reduced particularly in FETs.
　ここで、より効果的に表面側チャネルの電子がバルク側チャネルに導かれるように、第４の窒化物半導体層５０６のＡｌ組成比は、第２の窒化物半導体層５０４のＡｌ組成比よりも大きい方が望ましく、さらに、第４の窒化物半導体層５０６の厚さは、第２の窒化物半導体層５０４の厚さよりも大きい方が望ましい。また、ゲート電極５１０直下の第２の窒化物半導体層５０４の膜厚を薄くし、ノーマリーオフ型のＦＥＴを実現するために、第２の窒化物半導体層５０４の厚さは、第４の窒化物半導体層５０６の厚さよりも小さい方が望ましい。 Here, the Al composition ratio of the fourth nitride semiconductor layer 506 is higher than the Al composition ratio of the second nitride semiconductor layer 504 so that electrons in the surface-side channel are more effectively guided to the bulk-side channel. The larger one is desirable, and the thickness of the fourth nitride semiconductor layer 506 is desirably larger than the thickness of the second nitride semiconductor layer 504. In addition, in order to reduce the thickness of the second nitride semiconductor layer 504 immediately below the gate electrode 510 and realize a normally-off FET, the thickness of the second nitride semiconductor layer 504 is set to It is desirable that the thickness is smaller than the thickness of the nitride semiconductor layer 506.
　ドレイン電極５０８及びソース電極５０９は、ゲート電極５１０の両側方の領域に形成され、それぞれ第１の窒化物半導体層５０３及び第２の窒化物半導体層５０４のヘテロ接合界面と、第３の窒化物半導体層５０５及び第４の窒化物半導体層５０６のヘテロ接合界面とに接触し、該界面領域に生成された電子走行領域と電気的に接続されている。ドレイン電極５０８及びソース電極５０９は、第１の窒化物半導体層５０３に接触している。 The drain electrode 508 and the source electrode 509 are formed in regions on both sides of the gate electrode 510, and the heterojunction interface between the first nitride semiconductor layer 503 and the second nitride semiconductor layer 504 and the third nitride, respectively. The semiconductor layer 505 and the fourth nitride semiconductor layer 506 are in contact with the heterojunction interface and are electrically connected to the electron transit region generated in the interface region. The drain electrode 508 and the source electrode 509 are in contact with the first nitride semiconductor layer 503.
　ドレイン電極５０８及びソース電極５０９は、例えばＴｉ及びＡｌの積層構造体から構成される。 The drain electrode 508 and the source electrode 509 are composed of a laminated structure of Ti and Al, for example.
　絶縁膜５０７は、第４の窒化物半導体層５０６表面に形成され、例えばＳｉＮ、ＳｉＯ、ＡｌＮ、ＡｌＯ、ＳｉＮ及びＡｌＮの積層構造体、並びにＳｉＮ及びＡｌＯの積層構造体等から構成される。絶縁膜５０７がＳｉＮ又はＳｉＯから構成される場合、絶縁膜５０７は例えばＣＶＤ法や減圧ＣＶＤ法により成膜される。一方、絶縁膜５０７がＡｌＮ又はＡｌＯから構成される場合、絶縁膜５０７は例えばスパッタ法や原子層堆積装置を用いたＡＬＤ法により成膜される。 The insulating film 507 is formed on the surface of the fourth nitride semiconductor layer 506 and includes, for example, a stacked structure of SiN, SiO, AlN, AlO, SiN, and AlN, a stacked structure of SiN and AlO, and the like. When the insulating film 507 is made of SiN or SiO, the insulating film 507 is formed by, for example, a CVD method or a low pressure CVD method. On the other hand, when the insulating film 507 is made of AlN or AlO, the insulating film 507 is formed by, for example, a sputtering method or an ALD method using an atomic layer deposition apparatus.
　ゲート電極５１０は、絶縁膜５０７の上に形成され、例えばＰｄ、Ｎｉ及びＰｔ等から構成される。なお、ゲート電極５１０は、ゲート電極５１０を構成する材料が絶縁膜５０７により窒化物半導体層に拡散しない場合にはＴｉから構成されてもよい。 The gate electrode 510 is formed on the insulating film 507 and is made of, for example, Pd, Ni, Pt, or the like. Note that the gate electrode 510 may be made of Ti when the material constituting the gate electrode 510 is not diffused into the nitride semiconductor layer by the insulating film 507.
　素子分離層５１１は、例えば窒化物半導体層にＢ等の不純物をイオン注入することにより形成され、ＦＥＴを他の素子と電気的に分離する。 The element isolation layer 511 is formed by ion-implanting impurities such as B into the nitride semiconductor layer, for example, and electrically isolates the FET from other elements.
　以上のように、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、オン抵抗を低減することができる。 As described above, according to the FET of the present embodiment, the on-resistance can be reduced for the same reason as the FET of the first embodiment.
　また、本実施の形態のＦＥＴによれば、第１の実施の形態のＦＥＴと同様の理由により、ノーマリーオフ型ＦＥＴとして効果的な構造を実現できる。 Further, according to the FET of the present embodiment, an effective structure as a normally-off type FET can be realized for the same reason as the FET of the first embodiment.
　なお、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層５０３、第２の窒化物半導体層５０４、第３の窒化物半導体層５０５及び第４の窒化物半導体層５０６はＩｎを含んでいてもよい。 Note that in the FET of the above embodiment, the first nitride semiconductor layer 503, the second nitride semiconductor layer 504, the third nitride semiconductor layer 505, and the fourth nitride semiconductor layer 506 contain In. May be.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層５０３は、一部にドーピング層を備えていてもよい。この構造により、窒化物半導体層内での電荷量を制御し、ゲートの閾値電圧を調整することが容易となる。 In the FET of the above embodiment, the first nitride semiconductor layer 503 may partially include a doping layer. This structure makes it easy to control the amount of charge in the nitride semiconductor layer and adjust the threshold voltage of the gate.
　また、上記実施の形態のＦＥＴにおいて、第４の窒化物半導体層５０６の上には、さらに別の半導体層が配置されてもよい。 Further, in the FET of the above embodiment, another semiconductor layer may be disposed on the fourth nitride semiconductor layer 506.
　また、上記実施の形態のＦＥＴにおいて、第１の窒化物半導体層５０３、第２の窒化物半導体層５０４、第３の窒化物半導体層５０５及び第４の窒化物半導体層５０６には、例えばＳｉ等のｎ型不純物のドーピングが施されていてもよい。 In the FET of the above embodiment, the first nitride semiconductor layer 503, the second nitride semiconductor layer 504, the third nitride semiconductor layer 505, and the fourth nitride semiconductor layer 506 include, for example, Si. N-type impurities such as n-type impurities may be doped.
　また、上記実施の形態のＦＥＴにおいて、第３の実施の形態のＦＥＴと同様に絶縁膜５０７が設けられないショットキー接合型のＦＥＴの形態がとられてもよい。 Further, the FET of the above embodiment may take the form of a Schottky junction type FET in which the insulating film 507 is not provided as in the FET of the third embodiment.
　以上、本発明のＦＥＴについて、実施の形態に基づいて説明したが、本発明は、この実施の形態に限定されるものではない。本発明の要旨を逸脱しない範囲内で当業者が思いつく各種変形を施したものも本発明の範囲内に含まれる。 As mentioned above, although the FET of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention.
　本発明は、ＦＥＴに適用でき、特に携帯電話基地局等のハイパワー高周波装置やインバーター等のハイパワースイッチング装置等に適用できる。 The present invention can be applied to FETs, and in particular to high power high frequency devices such as mobile phone base stations, high power switching devices such as inverters, and the like.
　　１０１、２０１、３０１、４０１、５０１、８０１　　基板
　　１０２、２０２、３０２、４０２、５０２　　バッファ層
　　１０３、２０３、３０３、４０３、５０３　　第１の窒化物半導体層
　　１０４、２０４、３０４、４０４、５０４　　第２の窒化物半導体層
　　１０５、２０５、３０５、４０５、５０５　　第３の窒化物半導体層
　　１０６、２０６、３０６、４０６、５０６　　第４の窒化物半導体層
　　１０７、２０７、３０７、５０７　　絶縁膜
　　１０８、２０８、３０８、４０８、５０８、８０７　　ドレイン電極
　　１０９、２０９、３０９、４０９、５０９、８０８　　ソース電極
　　１１０、２１０、３１０、４１０、５１０、８０６　　ゲート電極
　　１１１、２１１、３１１、４１１、５１１　　素子分離層
　　１２０、２２０、３２０、４２０　　凹部
　　３１２　　第５の窒化物半導体層
　　８０２　　キャリア走行層
　　８０３　　キャリア供給層
　　８０４　　ＧａＮ系保護層
　　８０５　　保護層
  101, 201, 301, 401, 501, 801 Substrate 102, 202, 302, 402, 502 Buffer layer 103, 203, 303, 403, 503 First nitride semiconductor layer 104, 204, 304, 404, 504 Second Nitride semiconductor layer 105, 205, 305, 405, 505 Third nitride semiconductor layer 106, 206, 306, 406, 506 Fourth nitride semiconductor layer 107, 207, 307, 507 Insulating film 108, 208, 308, 408, 508, 807 Drain electrode 109, 209, 309, 409, 509, 808 Source electrode 110, 210, 310, 410, 510, 806 Gate electrode 111, 211, 311, 411, 511 Element isolation layer 120, 220 320, 420 Recess 312 Fifth nitrogen SEMICONDUCTOR layer 802 carrier transit layer 803 carrier supply layer 804 GaN-based protective layer 805 protective layer

Claims (14)

  1. 　第１の窒化物半導体層と、
    　前記第１の窒化物半導体層の上に形成され、前記第１の窒化物半導体層よりもバンドギャップエネルギーが大きい第２の窒化物半導体層と、
    　前記第２の窒化物半導体層の上に形成された第３の窒化物半導体層と、
    　前記第３の窒化物半導体層の上に形成され、前記第３の窒化物半導体層よりもバンドギャップエネルギーが大きい第４の窒化物半導体層とを備え、
    　前記第１の窒化物半導体層及び前記第２の窒化物半導体層のヘテロ接合界面には、チャネルが形成される
    　電界効果トランジスタ。     A first nitride semiconductor layer;
    A second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap energy larger than that of the first nitride semiconductor layer;
    A third nitride semiconductor layer formed on the second nitride semiconductor layer;
    A fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having a band gap energy larger than that of the third nitride semiconductor layer;
    A field effect transistor, wherein a channel is formed at a heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer.
  2. 　前記電界効果トランジスタのゲート電極は、前記第４の窒化物半導体層に設けられた凹部内に形成される
    　請求項１に記載の電界効果トランジスタ。     The field effect transistor according to claim 1, wherein a gate electrode of the field effect transistor is formed in a recess provided in the fourth nitride semiconductor layer.
  3. 　前記凹部は、前記第３の窒化物半導体層及び前記第４の窒化物半導体層のヘテロ接合界面を貫通している
    　請求項２に記載の電界効果トランジスタ。     The field effect transistor according to claim 2, wherein the recess penetrates a heterojunction interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer.
  4. 　前記凹部は、前記第３の窒化物半導体層及び前記第４の窒化物半導体層を貫通して前記第２の窒化物半導体層の表面まで達し、
    　前記凹部の底面としての前記第２の窒化物半導体層の表面は、前記第２の窒化物半導体層及び前記第３の窒化物半導体層の界面と面一である
    　請求項３に記載の電界効果トランジスタ。     The recess penetrates the third nitride semiconductor layer and the fourth nitride semiconductor layer and reaches the surface of the second nitride semiconductor layer,
    The field effect according to claim 3, wherein a surface of the second nitride semiconductor layer as a bottom surface of the recess is flush with an interface between the second nitride semiconductor layer and the third nitride semiconductor layer. Transistor.
  5. 　前記凹部は、前記第２の窒化物半導体層、前記第３の窒化物半導体層及び前記第４の窒化物半導体層を貫通して前記第１の窒化物半導体層まで達する
    　請求項４に記載の電界効果トランジスタ。     5. The concave portion reaches the first nitride semiconductor layer through the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride semiconductor layer. Field effect transistor.
  6. 　前記電界効果トランジスタは、さらに、前記凹部の底面に形成された絶縁膜を備える
    　請求項２～５のいずれか１項に記載の電界効果トランジスタ。     6. The field effect transistor according to claim 2, further comprising an insulating film formed on a bottom surface of the concave portion.
  7. 　前記電界効果トランジスタは、さらに、
    　前記凹部の底面に形成された第５の窒化物半導体層と、
    　前記ゲート電極と前記第５の窒化物半導体層との間に形成された絶縁膜とを備える
    　請求項２～５のいずれか１項に記載の電界効果トランジスタ。     The field effect transistor further comprises:
    A fifth nitride semiconductor layer formed on the bottom surface of the recess;
    6. The field effect transistor according to claim 2, further comprising an insulating film formed between the gate electrode and the fifth nitride semiconductor layer.
  8. 　前記第５の窒化物半導体層は、ＡｌzＧａ1-zＮ（０＜ｚ≦１）からなる
    　請求項７に記載の電界効果トランジスタ。     The field effect transistor according to claim 7, wherein the fifth nitride semiconductor layer is made of Al z Ga 1-z N (0 <z ≦ 1).
  9. 　前記絶縁膜は、窒化シリコンからなる
    　請求項６～８のいずれか１項に記載の電界効果トランジスタ。     The field effect transistor according to any one of claims 6 to 8, wherein the insulating film is made of silicon nitride.
  10. 　前記絶縁膜は、窒化シリコン及び窒化アルミニウムの積層構造体からなる
    　請求項６～８のいずれか１項に記載の電界効果トランジスタ。     The field effect transistor according to any one of claims 6 to 8, wherein the insulating film is formed of a laminated structure of silicon nitride and aluminum nitride.
  11. 　前記絶縁膜は、原子層堆積装置により形成される
    　請求項６～８のいずれか１項に記載の電界効果トランジスタ。     The field effect transistor according to any one of claims 6 to 8, wherein the insulating film is formed by an atomic layer deposition apparatus.
  12. 前記第２の窒化物半導体層の膜厚は、前記第４の窒化物半導体層の膜厚よりも小さい
    　請求項１～１１のいずれか１項に記載の電界効果トランジスタ。     The field effect transistor according to any one of claims 1 to 11, wherein a film thickness of the second nitride semiconductor layer is smaller than a film thickness of the fourth nitride semiconductor layer.
  13. 　前記電界効果トランジスタのソース電極及びドレイン電極は、それぞれ前記第１の窒化物半導体層及び前記第２の窒化物半導体層のヘテロ接合界面と、前記第３の窒化物半導体層及び前記第４の窒化物半導体層のヘテロ接合界面とに接触する
    　請求項１～１２のいずれか１項に記載の電界効果トランジスタ。     The source electrode and the drain electrode of the field effect transistor are respectively heterojunction interfaces of the first nitride semiconductor layer and the second nitride semiconductor layer, the third nitride semiconductor layer, and the fourth nitride. The field effect transistor according to any one of claims 1 to 12, which is in contact with a heterojunction interface of a physical semiconductor layer.
  14. 　前記第１の窒化物半導体層は、ＧａＮからなり、
    　前記第２の窒化物半導体層は、ＡｌxＧａ1-xＮ（０＜ｘ≦１）からなり、
    　前記第３の窒化物半導体層は、ＧａＮからなり、
    　前記第４の窒化物半導体層は、ＡｌyＧａ1-yＮ（０＜ｙ≦１）からなる
    　請求項１～１３のいずれか１項に記載の電界効果トランジスタ。     The first nitride semiconductor layer is made of GaN,
    The second nitride semiconductor layer is made of Al x Ga 1-x N (0 <x ≦ 1),
    The third nitride semiconductor layer is made of GaN,
    The field effect transistor according to any one of claims 1 to 13, wherein the fourth nitride semiconductor layer is made of Al y Ga 1-y N (0 <y ≦ 1).
PCT/JP2009/006038 2008-12-05 2009-11-12 Field effect transistor WO2010064362A1 (en)

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