WO2010061455A1

WO2010061455A1 - Plasma display panel driving method, and plasma display device

Info

Publication number: WO2010061455A1
Application number: PCT/JP2008/071551
Authority: WO
Inventors: 熊谷　純一; 佐々木　孝; 信義近藤
Original assignee: 日立プラズマディスプレイ株式会社
Priority date: 2008-11-27
Filing date: 2008-11-27
Publication date: 2010-06-03

Abstract

Disclosed is a driving method for driving a plasma display panel comprising scanning electrodes and maintaining electrodes extending in a first direction and arranged alternately in a second direction, and a plurality of address electrodes arranged to intersect the scanning electrodes and the maintaining electrodes. The driving method is characterized in that one frame or one field is constituted of a plurality of subfields, in that the subfields include an address period, for which a pulse voltage is applied to the scanning electrodes and the address electrodes to generate an address discharge thereby to select a cell to be turned on, and a maintaining period, for which a voltage is applied to the scanning electrode and the maintaining electrode selected for the address period, to generate a maintaining discharge thereby to express a gradation, in that the maintaining discharge is not performed when the minimum of the gradation is expressed, and in that the subfields, in which a voltage waveform change is made such that one pulse voltage to be applied to the scanning electrode or the address electrode is made so obtuse that the voltage changes with the lapse of time, are provided in the address discharge.

Description

Plasma display panel driving method and plasma display apparatus

The present invention relates to a plasma display panel driving method and a plasma display device.

Conventionally, an X electrode group and a Y electrode group arranged in parallel on the first substrate, and a second substrate facing the first substrate so as to intersect the X electrode group and the Y electrode group. In a plasma display apparatus for driving a plasma display panel having address electrode groups arranged by a subfield method in which one frame is composed of a plurality of subfields, the plurality of subfields select cells to be lit. A first subfield including an address period in which address discharge is performed, a sustain period in which sustain discharge is performed in a cell selected in the address period, and a second subfield including an address period without the sustain period. And in the address period in the first subfield, following the Y electrode group and the address electrode group, Address discharge is performed between the electrode group and the Y electrode group. In the address period in the second subfield, the Y electrode group and the address are not transferred to the discharge between the X electrode group and the Y electrode group. An address electrode is provided between the electrode group and a subfield in which the voltage of the address pulse applied to the address electrode is set lower than a normal value is further provided in the second subfield. Is known in which two sub-fields are provided (see, for example, Patent Document 1).

According to such a plasma display device, when expressing a low luminance gradation in which the sustain discharge does not continue, the address voltage value is set to two levels to thereby reduce the intensity of the address discharge to two levels. Improve expression ability.
Japanese Patent Laying-Open No. 2005-157064

However, in the configuration described in Patent Document 1 described above, the value of the address voltage is changed depending on the subfield, so that there is a problem that the circuit configuration of the address driver is complicated and the cost is increased.

In recent years, the concentration of Xe gas sealed in the plasma display panel tends to increase. However, when the concentration of Xe gas is increased, it becomes difficult for discharge to occur, and the address voltage described in Patent Document 1 is set higher than usual. With the lowered address pulse, there is a problem that address discharge does not occur, and consequently the lowest gradation cannot be expressed.

Therefore, an object of the present invention is to provide a plasma display panel driving method and a plasma display device capable of expressing low luminance gradation with high definition with a simple configuration.

In order to achieve the above object, a driving method of a plasma display panel according to a first aspect of the present invention includes scan electrodes and sustain electrodes extending in a first direction and alternately arranged in a second direction, A driving method of a plasma display panel, comprising a plurality of address electrodes arranged so as to cross the scan electrodes and sustain electrodes, wherein cells that emit light by discharge are formed at intersections of the scan electrodes, sustain electrodes, and address electrodes Because
One frame or one field is composed of a plurality of subfields, and the subfields generate an address discharge by applying a pulse voltage to the scan electrodes and the address electrodes, and an address period for selecting the cells to be lit. A sustain period in which a voltage is applied between the scan electrode and the sustain electrode selected in the address period to generate a sustain discharge and express gray levels,
When expressing the lowest gradation of the gradation, the sustain discharge is not performed, and in the address discharge, one of the pulse voltages applied to the scan electrode or the address electrode is set to a voltage over time. A subfield is provided for switching the voltage waveform to an obtuse wave in which the voltage changes.

Thereby, the magnitude of the voltage applied at the time of address discharge itself is not changed, and the discharge can be weakened by applying a blunt wave, so that the address discharge can be reliably generated and the discharge intensity is weakened, The lowest gradation can be expressed with high definition. Further, since the magnitude of the applied voltage is not changed, a configuration for controlling the magnitude of the voltage itself is unnecessary, and a low luminance gradation can be expressed with a simple configuration.

A second invention is a method for driving a plasma display panel according to the first invention, wherein:
The obtuse wave is generated by switching the connection of a resistor to a circuit that outputs the pulse voltage.

This makes it possible to switch the voltage waveform reliably with a simple configuration, and to express low luminance gradation easily and with high definition.

A third invention is a method of driving a plasma display panel according to the second invention, wherein
Whether or not to provide the obtuse wave subfield is determined based on a ratio of the cells displaying the lowest gradation to the total number of cells.

This makes it possible to determine whether or not to provide such an obtuse wave subfield for expressing the lowest gradation based on the proportion of cells displaying the lowest gradation, and only when necessary. The low luminance gradation can be expressed with high definition.

A fourth invention is a method of driving a plasma display panel according to the third invention,
When outputting the obtuse wave, the pulse width of the pulse voltage is widened.

This makes it possible to reliably generate and output a blunt wave, and to appropriately express a low luminance gradation.

A fifth invention is a method of driving a plasma display panel according to the fourth invention,
When expressing a gradation that is one step larger than the lowest gradation, the sustain discharge is not performed, and in the address discharge, both of the pulse voltages applied to the scan electrode or the address electrode are fixed potentials. A subfield is provided.

Thus, even a gradation that is one step larger than the lowest gradation can be expressed without providing a large gradation difference from the lowest gradation, and a low-luminance gradation can be expressed with high definition.

A sixth aspect of the invention is a plasma display panel driving method according to the fifth aspect of the invention,
When expressing a gradation that is two steps higher than the lowest gradation, the sustain discharge is not performed, and the pulse voltage applied to the scan electrode and the address electrode in the address discharge is both set to a fixed potential. And a subfield for applying a voltage to the sustain electrode so that a discharge is generated between the scan electrode and the sustain electrode after the discharge is generated between the scan electrode and the address electrode. It is characterized by that.

Thereby, when low gradation expression is performed without performing sustain discharge, more low gradations can be expressed, and high-definition low luminance gradation expression can be performed.

A plasma display device according to a seventh aspect of the present invention is arranged to extend in the first direction and to be arranged so as to intersect the scan electrodes and sustain electrodes alternately arranged in the second direction and the scan electrodes and sustain electrodes. A plurality of address electrodes, a plasma display panel in which cells that emit light by discharge are formed at intersections of the scan electrodes, the sustain electrodes, and the address electrodes;
A scan driver for driving the scan electrode by applying a pulse voltage to the scan electrode;
An address driver for driving the address electrode by applying a pulse voltage to the address electrode;
A voltage waveform switching circuit connected to the scan driver or the address driver and configured to make the pulse voltage an obtuse wave whose voltage changes with time.

Thereby, the generation of the blunt wave can be easily generated by the voltage switching circuit, and the low luminance can be expressed with high definition with a simple configuration.

An eighth invention is the plasma display device according to the seventh invention, wherein
The voltage waveform switching circuit is a circuit that switches a resistance value connected to the scan driver or the address driver by a switch.

This makes it possible to simply configure a voltage waveform switching circuit with resistors and switches, and to accurately generate a blunt wave.

A ninth invention is the plasma display device according to the eighth invention,
A scan driving circuit for inputting an image signal to be displayed on the plasma display, converting one frame or one field of the image signal into a plurality of subfields, and driving the scan driver using the subfields, and the address driver A control circuit for controlling an address drive circuit for driving
When the ratio of the number of cells including the luminance signal of the lowest gradation included in the subfield to the total number of cells is equal to or greater than a predetermined value, the control circuit sets the voltage switching circuit to the obtuse wave output side. It has the voltage switching control means to switch to.

This makes it possible to generate a dull wave only at a timing when low luminance expression is necessary, and to appropriately expand the expression of target luminance.

The tenth invention is the plasma display device according to the ninth invention,
The voltage switching control unit is configured to increase a pulse width of the voltage pulse output from the scan driver or the address driver to which the voltage switching circuit is connected when switching the voltage switching circuit to an obtuse wave output side. It is characterized by performing.

As a result, blunt waves can be generated reliably, and voltage waveforms can be switched reliably when low luminance representation is required.

An eleventh invention is the plasma display device according to the tenth invention, wherein
The scan electrode, the sustain electrode, and the address electrode are provided on opposing surfaces of the cell.

This makes it possible to express low luminance gradation with high precision in a counter-type plasma display.

According to the present invention, low luminance gradation can be expressed with high definition with a simple configuration.

1 is an overall configuration diagram of a plasma display device according to an embodiment. 1 is an exploded perspective view of an example of a plasma display panel 10. FIG. It is the figure which showed an example of the voltage waveform of 1st subfield SF1, 2nd subfield SF2, and 3rd subfield SF3. It is the figure which showed an example of the voltage waveform of 4th subfield SF4 and 5th subfield SF5. It is the figure which showed the voltage waveform of 1st subfield SF1 which displays the minimum gradation of the drive method of the plasma display panel 10 concerning a present Example. It is the figure shown about an example of the structure of the scanning drive circuit of the plasma display apparatus which concerns on a present Example. It is the figure which showed an example of the scan pulse and address pulse in the address discharge expressing the lowest gradation. FIG. 8 is a diagram showing an example of a configuration of an address driving circuit 20 for generating an address pulse blunt wave Vad shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plasma display panel 11 Front substrate 12

Front glass substrate

13, 17 Dielectric layer 14 Protective film 15 Back substrate 16 Rear glass substrate 18

Bulkheads

19, 19R, 19G, 19B Phosphor 20 Address drive circuit 21

Address drivers

22, 44 Voltage waveform Switching circuit 30 Sustain drive circuit 40 Scan drive circuit 41 Scan driver 42 Sustain driver 43 Reset circuit 50 Drive control circuit 51 Subfield conversion circuit 52 Address data generation circuit 53 Scan data generation circuit 54 Voltage waveform switching control means 55 Maintenance data generation means

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

FIG. 1 is an overall configuration diagram of a plasma display device according to an embodiment to which the present invention is applied. In FIG. 1, the plasma display apparatus according to the present embodiment includes a plasma display panel 10, an address driving circuit 20, a sustain driving circuit 30, a scan driving circuit 40, and a drive control circuit 50.

The plasma display panel 10 is a display panel for displaying an image. The plasma display panel 10 includes a plurality of sustain electrodes X1, X2, X3,... And a plurality of scan electrodes Y1, Y2, Y3,. Hereinafter, each of the sustain electrodes X1, X2, X3,... Or their generic name is referred to as a sustain electrode Xi, and each of the scan electrodes Y1, Y2, Y3,. It is called Yi. i means a subscript. The plasma display panel 10 includes a plurality of address electrodes A1, A2, A3,... Extending in the vertical direction. Hereinafter, each of the address electrodes A1, A2, A3,... Or their generic name is referred to as an address electrode Aj, and j means a subscript. The sustain electrodes Xi and the scan electrodes Yi extending in the horizontal direction are alternately arranged in the vertical direction. The sustain electrode Xi may be called the X electrode Xi, and the scan electrode Yi may be called the Y electrode Yi. In a plan view, a cell Cij is formed at a position where the sustain electrode Xi, the scan electrode Yi, and the address electrode Aj intersect. The discharge cells Cij correspond to pixels, and the plasma display panel 10 can display a two-dimensional image. The sustain electrode Xi and the scan electrode Yi in the cell Cij have a space therebetween, and constitute a capacitive load.

The address drive circuit 20 is a circuit for driving the address electrode Aj, and supplies an address pulse having a predetermined voltage value to the address electrode Aj in the address period to generate an address discharge. The address drive circuit 20 may include a plurality of address drivers 21 configured as an IC (Integrated Circuit, integrated circuit device). Each address driver 21 may be configured as an IC having a plurality of outputs, and by providing a plurality of address drivers 21, all the address electrodes Aj may be driven.

Further, in the plasma display device according to the present embodiment, the address driving circuit 20 may include a voltage waveform switching circuit 22. The voltage waveform switching circuit 21 is means for switching the address pulse output from the address driver 21 to a square wave or an obtuse wave. The address pulse output from the address driver 21 is usually a square wave whose voltage is constant between cycles. However, in the plasma display device according to the present embodiment, time elapses when expressing the lowest gradation. At the same time, an obtuse wave whose voltage changes is applied as a voltage pulse to weaken the discharge intensity. At this time, as for the voltage pulse, the address pulse applied to the address electrode Aj may be a blunt wave, and the scan pulse applied to the scan electrode Yi may be a blunt wave. Provides a voltage waveform switching circuit 22 in the address drive circuit 20 to generate blunt waves. Details of the specific configuration and function of the voltage waveform switching circuit 22 will be described later.

The scan drive circuit 40 is a circuit for driving the scan electrode Yi, and includes a scan driver 41, a sustain driver 42, a reset circuit 43, and a voltage waveform switching circuit 44.

The scan driver 41 supplies a scan pulse having a predetermined voltage value to the scan electrode Yi according to the control of the drive control circuit 50 and the sustain driver 42, and generates an address discharge. Similarly to the address driver 21, the scan driver 41 may be configured as an IC having a plurality of outputs, and further provided with a plurality of scan drivers 41, so that all the scan electrodes Yi can be driven. Also in the scan driver 41, the scan pulse that is normally output may be a square wave having a constant voltage value between cycles.

The sustain driver 42 is a circuit that supplies a sustain pulse having the same voltage to the scan electrodes Yi to generate a sustain discharge.

The reset circuit 43 is a circuit that supplies a reset pulse having a predetermined voltage value to the scan electrode Yi according to the control of the drive control circuit 50, generates a reset discharge, and initializes and arranges the wall charge of the discharge cell Cij. is there. The reset discharge may be performed as an all-cell reset that discharges all the cells Cij and an on-cell reset that resets only the cells Cij that have undergone the sustain discharge.

The voltage waveform switching circuit 44 switches the pulse voltage waveform of the scan pulse applied from the address driver 41 to the scan electrode Yi to an obtuse wave whose voltage changes over time when generating an address discharge in the address period. Circuit. The voltage waveform switching circuit 44 has a function similar to that of the voltage waveform switching circuit 22 described in the address driving circuit 20 and is a circuit having a function of switching a square wave to an obtuse wave when expressing the lowest gradation. When the scan pulse is a dull wave and the address pulse is a square wave, a voltage waveform switching circuit 44 is provided on the scan drive circuit 40. Details of the specific configuration and function of the voltage waveform switching circuit 44 will be described later.

The sustain drive circuit 30 is a circuit for driving the sustain electrode Xi, and supplies a sustain pulse having the same voltage to the sustain electrode Xi to generate a sustain discharge. Each sustain electrode Xi is interconnected and has the same voltage level.

The drive control circuit 50 is a circuit that drives and controls the address drive circuit 20, the sustain drive circuit 30, and the scan drive circuit 40. The drive control circuit 50 includes a subfield conversion circuit 51, an address data generation circuit 52, a scan data generation circuit 53, and a maintenance data generation circuit 55.

Further, the drive control circuit 50 may include voltage waveform switching control means 54 as necessary. The voltage waveform switching control means 54 does not cause the plasma display apparatus according to the present embodiment to generate a blunt wave at the time of address discharge for all the lowest gradations, but to display the lowest among the image signals to be displayed. Only when the ratio of the pixels occupied by the gradation is high, when performing such a low gradation expression using blunt waves, whether to perform voltage waveform switching control and control based on the determination result are performed. And may be provided as necessary.

When one frame or one field input signal S, which is a general image signal, is input to the drive control circuit 50, the subfield conversion circuit 51 subdivides one frame or one field image into a plurality of subfields. Perform conversion. Based on the converted subfield, the address data generation circuit 52 and the scan data generation circuit 53 generate address data and scan data necessary to drive the scan driver 41 of the address drive circuit 20 and the scan drive circuit 40. The sustain data generation circuit 55 generates sustain data necessary for driving the sustain driver 42 of the sustain drive circuit 30 and the scan drive circuit 40.

Based on the conversion result of the subfield conversion circuit 51 or the input signal S, the voltage waveform switching control means 54 includes the cell Cij that expresses the lowest gradation at a ratio of the entire cell Cij. Is calculated.

Specifically, for example, when an image signal is expressed with 256 levels of gradation, the image signal is scaled up so that it is multiplied by 4 and expressed with 1024 levels of gradation. The lowest gradation expressed by the plasma display apparatus according to the present embodiment is lower in luminance, such as 0.5, 0.25, and 0.125, when the conventional lowest gradation is 1. This is the gradation to be expressed. Therefore, for example, by expressing 256 levels of gradation in 1024 levels, the above-mentioned levels of 0.5, 0.25, and 0.125 can be expressed. A gradation of 1 indicates 0.125 of 256 gradations, a gradation of 2 indicates 0.25 of 256 gradations, and a gradation of 3 indicates 0.5 of 256 gradations. . For example, by performing such conversion, it is possible to calculate the ratio of the number of cells Cij that express the lowest gradation to the total cells Cij in the image signal. For example, a predetermined threshold is provided for this ratio, and when the cell Cij displaying the minimum luminance is 10% or more with respect to the total number of cells, for example, address discharge is performed using blunt waves. Thus, voltage waveform switching control can be performed according to the display ratio.

As described above, the voltage waveform switching control unit 54 performs the voltage waveform switching control based on the pixel ratio of the lowest luminance included in the image signal to be displayed based on the input signal S or the subfield conversion result of the SF conversion circuit 51. be able to.

When the voltage waveform switching control based on the display ratio of the lowest luminance is not performed, the voltage waveform switching circuit 44 or the address driving circuit in the scan driving circuit 40 is based on the scan data generating circuit 53 and the address data generating circuit 54. The voltage waveform switching circuit 22 in 20 may switch the voltage waveform.

Further, the voltage waveform switching control means 54 expands the pulse width of the voltage pulse to which the blunt wave is applied when the voltage waveform switching control in which the scan pulse or the address pulse is a blunt wave is executed in the address discharge. Further, control for extending the pulse application time may be performed. For example, if the display image itself is a dark image and an overall low-brightness image is displayed, the number of subfields can be reduced, and even if the pulse width is increased to express low-brightness gradations. In many cases, it does not affect the whole. In such a case, control may be performed so that the pulse width is widened and the voltage

waveform switching circuits

22 and 44 reliably generate an obtuse wave. For example, when generating a normal blunt wave, the pulse width is set to about twice as wide, and when there is a margin in the time of the subfield, it is expanded to a level of 5 times or 10 times. Also good. The degree of expansion of the pulse width when outputting blunt waves can be controlled in various ways as long as the total time of the subfields is within the range of one frame or one field. Depending on the application, various settings may be made.

FIG. 2 is a diagram showing an example of an exploded perspective view of the plasma display panel 10. In FIG. 2, the plasma display panel 10 includes a front substrate 11 and a rear substrate 15 and is configured by bonding them facing each other.

The front substrate 11 includes a front glass substrate 12, and a plurality of sustain electrodes Xi and scan electrodes Yi extend on the inner surface of the front substrate 11 in the horizontal direction (horizontal direction) of the screen and are alternately arranged in the vertical direction (vertical direction). It is formed so that. Then, the dielectric layer 13 and the protective film 14 cover the sustain electrodes Xi and the scan electrodes Yi, and the upper surface substrate 11 is configured.

The back substrate 15 has a back glass substrate 16 on the outside, and a plurality of address electrodes Aj are formed on the surface of the back glass substrate 16 so as to extend in the vertical direction of the screen, and the dielectric layer 17 is formed thereon. Covered. A raised partition wall (rib) 18 is formed on the dielectric layer 17. A partition 18 forms a partition on the opposing surface of the front substrate 11 and the back substrate 15, thereby dividing and forming a plurality of cells Cij. A region in the partition where the sustain electrode Xi and the scan electrode Yi of the front substrate 11 intersect with the address electrode Aj of the rear substrate 15 forms one cell Cij. As described above, in the plasma display device according to the present embodiment, the sustain electrode Xi, the scan electrode Yi, and the address electrode Aj may be provided on the opposing

substrates

11 and 15 to constitute the cell Cij. Further, a phosphor 19 is formed on the surface of the cell Cij, that is, between the adjacent partition walls 18. There are three types of phosphor 19, red phosphor 19R, green phosphor 19G, and blue phosphor 19B, and these three colors form one pixel.

The discharge space between the front substrate 11 and the back substrate 15 is filled with a discharge gas such as Ne—Xe, and excites the red phosphor 19R, the green phosphor 19G, and the blue phosphor 19B by ultraviolet rays generated by the discharge. Each color emits light.

In recent years, the discharge gas tends to be high concentration Xe in order to improve the luminous efficiency of the plasma display panel 10. However, when the concentration of Xe gas is increased, the light emission efficiency is improved, but the drive voltage is increased, and unless the high voltage is applied, the discharge itself is difficult to occur. According to the driving method of the plasma display apparatus according to the present embodiment, the magnitude of the maximum value of the driving voltage itself is not changed, and the discharge intensity is controlled by controlling the time when the maximum value is reached using an obtuse wave. Since it is weakened, it is possible to weaken only the discharge intensity of the plasma display panel 10 having a high concentration of Xe while reliably generating the address discharge itself.

In the discharge of the cells Cij, when the reset pulse is applied to all the scan electrodes Yi, the reset discharge is generated, and the wall charges for control are uniformly accumulated in all the cells Cij. Resetting all cells Cij in this way is called all cell reset. The reset discharge also includes a reset discharge called an on-cell reset that selects and discharges a cell Cij that has emitted light in the previous subfield.

Next, when a pulse is applied to the address electrode Aj and the scan electrode Yi, an address discharge is generated, and wall charges due to the address discharge are accumulated in the cell Cij. At the time of address discharge, an ON signal of an address pulse is applied to a cell Cij that emits light, and an OFF signal of an address pulse is applied to a non-light emitting cell Cij that does not emit light, and all address electrodes A1 to Aj Address pulses corresponding to light emission / non-light emission are applied simultaneously. A scan pulse is sequentially applied from Y1 to Yi to the line of the scan electrode Yi for performing address selection, and an address discharge is generated in the cell Cij to which the on signal is applied in response to the on / off signal of the address electrode Aj. The address discharge is not generated in the cell Cij generated and applied with the off signal. A period in which the address discharge is generated and the cell Cij to emit light is selected is called an address period.

In the driving method of the plasma display panel 10 and the plasma display apparatus according to the present embodiment, at the time of address discharge, one of the address pulse and the scan pulse is not a square wave that keeps the maximum voltage during pulse application, but changes with time. An obtuse wave having a slope and reaching a maximum value is applied. As a result, the address discharge can be made weaker than the address discharge caused by the square waves, and a low luminance gradation can be expressed.

Next, a sustain pulse is applied to each of the sustain electrodes Xi and the scan electrodes Yi, and the discharge cells Cij that have undergone address discharge store sufficient wall charges, so that sustain discharge occurs and light is emitted. The discharge cell Cij that has not occurred does not emit sustain discharge and does not emit light. Note that a period during which the sustain discharge occurs is called a sustain period.

For example, the plasma display panel 10 having the configuration shown in FIG. 2 may be applied to the plasma display device according to the present embodiment. The plasma display panel 10 driving method and the plasma display apparatus according to the present embodiment can be applied to various plasma display panels 10 that perform address discharge. Therefore, the plasma display panel 10 is not limited to the plasma display panel 10 shown in FIG. However, as long as the plasma display panel 10 performs address discharge, the plasma display panel 10 of various modes can be applied.

Next, a method for driving the plasma display panel 10 according to the present embodiment and an example of a subfield waveform of the plasma display device will be described with reference to FIGS.

FIG. 3 is a diagram illustrating an example of voltage waveforms applied to the address electrodes Aj, the scan electrodes Yi, and the sustain electrodes Xi in the first subfield SF1, the second subfield SF2, and the third subfield SF3. In FIG. 3, the voltage waveform applied to the address electrode Aj is indicated by ADD, the voltage waveform applied to the scan electrode Yi is indicated by Y, and the voltage waveform applied to the sustain electrode Xi is indicated by X.

In FIG. 3, a first subfield SF1 indicates a subfield expressing the lowest gradation. In the first subfield SF1, only the reset period Ta and the address period Ta are provided, and no sustain period is provided. In this way, in the first subfield SF1, the sustain discharge is not performed in order to express a gradation that is lower than the first stage gradation in which the normal sustain discharge is performed.

In the reset period Tr, no voltage is applied to the address electrode Aj, and a reset voltage is applied only to the scan electrode Yi. As the reset voltage, the voltage Vs is first applied, but then the voltage rises and the highest voltage (Vs + Vw) is applied. At this time, reset discharge occurs in all the cells Cij, and wall charges are accumulated in the cells Cij. Thereafter, the reset voltage decreases with time, the polarity becomes negative, and the voltage (−Vy + Vα) takes the minimum value. While the voltage changes from the maximum value to the minimum value, a small discharge is generated, and the wall charge in the cell Cij is adjusted to an appropriate amount. Note that Vs, (Vs + Vw), and (−Vy + Vα) shown in FIG. 3 can be set to various values depending on the panel characteristics and the application, for example, Vs = 200 [V], (Vs + Vw). ) = 400 [V], (−Vy + Vα) = − 150 [V].

At this time, the sustain electrode Xi is maintained in the high impedance state of the float state, and the cell Cij is a load having capacitive coupling. Therefore, the sustain electrode Xi is affected by the voltage application of the scan electrode Yi. The voltage increases slightly and reaches HiZ.

Next, in the address period of the first subfield SF1, an address pulse Va is applied to the address electrode Aj, and a blunt wave (-Vyd) is applied to the scan electrode Yi. The address pulse Va is a positive square wave whose voltage is Va during the pulse application period, but the obtuse wave (-Vyd) applied to the scan electrode Yi falls from the potential 0 [V] as time passes. Finally, the voltage (−Vy) is reached. Usually, a square wave of voltage (−Vy) is applied to the scan electrode Yi. In this case, the potential difference between the two electrodes is always (Va−Vy) during the pulse application period, but in the driving method of the plasma display panel 10 according to the present embodiment, an obtuse wave having such an inclination is applied to the scanning electrode Yi. Apply. As a result, a period in which the applied voltage difference between the address electrode Aj and the scan electrode Yi is smaller than (Va−Vy) can be made longer than when a square wave is applied, and the address discharge can be reduced. At this time, no voltage is applied to the sustain electrode Xi, the voltage is maintained at the ground potential, and no discharge is generated at the sustain electrode Xi.

Thus, in the first subfield SF1, not only the sustain period is provided, but also the subfield is provided so that the address discharge in the address period Ta has a lower luminance than usual and the low luminance gradation can be appropriately expressed. ing.

The second subfield SF2 is a subfield that represents a gradation that is one step higher than the first subfield that represents the lowest gradation. In the second subfield SF2, the reset period Tr applies the same voltage waveform as that of the first subfield SF1 to the electrodes Aj, Yi, Yj, and thus the description thereof is omitted. Similar to the first subfield SF1, the state of the wall charges of all the cells Cij is appropriately adjusted by the reset period Tr.

In the address period Ta, a square wave address pulse Va is applied to the address electrode Aj. On the other hand, a square-wave scan pulse (−Vy) is also applied to the scan electrode Yi. Thereby, in the address period Ta, a potential difference (Va−Vy) is applied between the address electrode Aj and the scan electrode Yi, thereby generating an address discharge. Since the address pulse Va and the scan pulse (−Vy) are applied at the same timing and with the same pulse width, there is no decrease in the potential difference between the electrodes Aj and Yi during the application of the address pulse Va and the scan pulse (−Vy). A discharge stronger than that of the first subfield SF1 occurs. As described above, in the second subfield SF2, a gradation with higher luminance than the first subfield SF1 can be expressed, and an area having a luminance lower than that of the normal gradation expression is further divided into two stages. The gradation expression can be performed separately. In the meantime, the sustain electrode Xi is adjusted to be kept at the ground potential and no discharge is generated in the sustain electrode Xi, similarly to the first subfield SF1.

The third subfield SF3 is a subfield that expresses a gradation that is two steps higher than the first subfield SF1 showing the lowest gradation and one step higher than the second subfield SF2.

The third subfield SF3 is the same as the first subfield SF1 and the second subfield SF2 in that the third subfield SF3 does not include the sustain period and includes only the reset period Tr and the address period Ta.

In the reset period Tr, the address electrode Aj is kept at the ground potential, and the reset pulse is applied to the scan electrode Yi, as in the first subfield SF1 and the second subfield SF2. Further, the reset pulse applied to the scan electrode Yi has the same voltage waveform as that of the first subfield SF1 and the second subfield SF2, and therefore the description thereof is omitted.

On the other hand, the point that the pulse of the voltage Vx1 is applied to the sustain electrode Xi first and last in the reset period Tr is different from the first subfield SF1 and the second subfield SF2. This is because the reset pulse applied to the scan electrode Yi applies the decreasing voltage waveform for adjusting the wall charge of the cell Cij after applying the maximum voltage (Vs + Vw) and scans with the sustain electrode Xi. This is to generate a slightly stronger discharge between the electrodes Yi.

In the address period Ta, as in the second subfield SF2, a positive square wave address pulse Va is applied to the address electrode Aj, and a negative square wave scan pulse (−Vy is applied to the scan electrode Yi. ) Is applied. As a result, an address discharge stronger than that of the first subfield SF1 is generated between the address electrode Aj and the scan electrode Yi, similarly to the second subfield SF2.

Further, in the address period Ta, a constant voltage Vx2 having a positive potential is applied to the sustain electrode Xi. This point is different from the second subfield SF2. After a discharge is generated between the address electrode Aj and the scan electrode Yi by the voltage Vx2 applied to the sustain electrode Xi, a discharge is continuously generated between the scan electrode Yi and the sustain electrode Xi using this as a trigger. . This is also a kind of address discharge that occurs during the address period Ta, and is a second stage address discharge. In this way, in the third subfield SF3, not only the address discharge between the scan electrode Yi and the address electrode Aj but also the address discharge is generated between the scan electrode Yi and the sustain electrode Xi in the address period. Accordingly, a gradation with higher luminance than that of the second subfield SF2 can be expressed, and a gradation with a luminance lower than that of the subfield having the sustain period can be expressed.

As described above, according to the driving method of the plasma display panel 10 according to the present embodiment, the three-stage low luminance gradation is obtained by using the subfield including only the reset period Tr and the address period Ta without including the sustain period. Can be expressed. Thereby, the low luminance gradation can be expressed with high definition.

Note that the luminance difference between the first subfield SF1, the second subfield SF2, and the third subfield is a setting of the blunt wave (-Vyd), the scan pulse (-Vy), and the voltage Vx2 applied to the sustain electrode Xi. However, for example, the luminance of the first subfield SF1 is half the luminance of the second subfield SF2, and the luminance of the second subfield SF2 is the third luminance. The luminance may be set to be half the luminance of the subfield SF3. In this case, for example, if the third subfield SF3 expresses a gradation of 0.5, the second subfield SF2 can express a gradation of 0.25, and the first subfield SF1 becomes 0 .125 gradations can be expressed, and low luminance gradations can be expressed with high definition.

Next, an example of voltage waveforms after the fourth subfield SF4 will be described with reference to FIG. FIG. 4 shows voltage waveforms applied to the address electrodes Aj, the scan electrodes Yi, and the sustain electrodes Xi in the fourth subfield SF4 and the fifth subfield SF5 in the driving method of the plasma display panel 10 according to the present embodiment. It is the figure which showed an example.

In the fourth subfield SF4, a sustain period Ts is provided after the reset period Tr and the address period Ta.

In the reset period Tr and the address period Ta, the voltage waveform is the same as that of the third subfield SF3, and thus the description thereof is omitted.

Note that in the fourth subfield SF4 having the sustain period Ts and performing the sustain discharge after the address discharge, the address discharge is not terminated by the discharge between the address electrode Aj and the scan electrode Yi, and then the scan is performed. Address discharge is continuously generated between the electrode Yi and the sustain electrode Xi. Thereby, during the subsequent sustain discharge, the wall charges in the cell Cij are sufficiently present, and the sustain discharge is reliably and appropriately performed.

In the sustain period Ts, the sustain pulse Vs is alternately applied to the sustain electrode Xi and the scan electrode Yi, and the sustain discharge is continuously performed alternately while changing the polarity. Then, a high luminance gradation is expressed in proportion to the length of the sustain period Ts, that is, the number of sustain pulses Vs.

As described above, in the fourth subfield SF4, the subfield in which the sustain period Ts is provided after the address period Ta and the sustain discharge is performed after the address discharge is shown. Usually, a subfield having such a sustain period Ts in one field or one frame including a plurality of subfields is more general. By further providing the subfield SF1, the second subfield SF2, and the third subfield SF3, it is possible to expand the low gradation expression area.

The fifth subfield SF5 is a diagram showing the voltage waveform of the subfield including the on-cell reset. The fifth subfield SF5 is a subfield that is selectively performed only for the cell Cij in which the cell Cij is turned on. That is, the fifth subfield SF5 is a subfield performed only for the cell Cij in which the fourth subfield SF4 is executed, and the first subfield SF1, the second subfield SF2, or the second subfield SF5 It is not performed immediately following the third subfield.

In the fifth subfield SF5, only the reset period Tr is different from the fourth subfield SF4, and the voltage waveforms in the address period Ta and the sustain period Ts are the same as those in the fourth subfield SF4. In the reset period Tr, the positive reset pulse is not applied in the reset period Tr of the fourth subfield SF4, and the negative reset pulse is applied to the scan electrode Yi. Such a reset discharge is called an on-cell reset. For the cell Cij in which the sustain discharge has been performed, the wall charge at the time of the sustain discharge remains in the cell Cij. Reset discharge can be completed simply by applying voltage pulses to be adjusted. Note that the address period Ta and the sustain period Ts are the same as those in the fourth subfield SF4, and thus description thereof is omitted.

Next, the voltage waveform in the address period Ta of the first subfield SF of the driving method of the plasma display panel 10 according to the present embodiment will be described in detail with reference to FIG. FIG. 5 is a diagram illustrating a voltage waveform of the first subfield SF1 that displays the lowest gradation of the driving method of the plasma display panel 10 according to the present embodiment. In FIG. 5, A indicates a voltage waveform applied to the address electrode Aj, and Y indicates a voltage waveform applied to the scan electrode Yi.

In FIG. 5, the pulse voltage (address pulse) applied to the address electrode Aj is a pulse voltage close to a constant square wave with the positive voltage Va, but the pulse voltage (scan pulse) applied to the scan electrode Yi. This waveform shows an obtuse wave that gradually decreases with time from the ground potential. That is, in FIG. 5, an example in which the address pulse is a fixed potential and the scan pulse is an obtuse wave will be described. The lowest potential of the scan pulse is (−Vy). If the voltage between the scan electrode Yi and the address electrode Aj reaches the discharge start voltage before reaching the lowest potential (−Vy), the address discharge is generated. . As described in FIG. 3, the voltage between the electrodes (Va−Vy) is a value that surely exceeds the discharge start voltage, and therefore, in the blunt wave (−Vyd), the address is at the timing when the potential is decreasing. A discharge is generated, and a weaker discharge is generated than when the scan pulse is close to a square wave of (−Vy).

Thus, by making the pulse voltage applied to the scan electrode Yi a blunt wave, a weak address discharge can be easily generated without changing the set voltage of the scan driver 41 itself. In addition, since the blunt wave (-Vyd) is a pulse voltage that eventually reaches (-Vy), the address discharge itself can be reliably performed even in the plasma display panel 10 in which high-concentration xenon is sealed. Can be generated.

Next, the configuration of the scan driving circuit 40 for generating the blunt wave (-Vyd) scan pulse shown in FIG. 5 will be described with reference to FIG. FIG. 6 is a diagram showing an example of the configuration of the scan drive circuit of the plasma display apparatus according to the present embodiment. In FIG. 6, a scan driver 40 including a scan driver 40 connected to the discharge cell Cij, a voltage waveform switching circuit 44, and a sustain driver 42 is shown.

The scan driver 41 includes a high potential side MOS transistor My1 and a low potential side MOS transistor My2. The high potential side MOS transistor My1 is connected to the ground potential. Therefore, when the high potential side MOS transistor My1 is turned on, the ground potential is supplied to the scan electrode Yi.

The low potential side MOS transistor My2 is connected to the voltage waveform switching circuit 44. The voltage waveform switching circuit 44 is constituted by a parallel connection of a resistor R1 and a switch SW1. The opposite side of the voltage waveform switching circuit 44 is connected to the low potential supply MOS transistor My5 and to the sustain driver 42.

The voltage waveform switching circuit 44 is a circuit for switching between supplying a scan pulse (−Vy) or a blunt wave (−Vyd) of a fixed potential to the low potential side MOS transistor My2 of the scan driver 41. When supplying a fixed potential scan pulse (-Vy), the low potential connection MOS transistor My5 is turned on and the switch SW1 is turned on. As a result, the resistor R1 is short-circuited, so that the fixed voltage (−Vy) is supplied to the low potential side MOS transistor My2.

On the other hand, when a blunt wave (-Vyd) is applied to the scan electrode Yi, that is, when the lowest luminance gradation is expressed, the low potential connection MOS transistor My5 is turned on and the switch SW1 is turned off. In this case, since the resistor R1 is connected in series, the fixed potential (−Vy) becomes an obtuse wave (−Vyd) and is supplied to the low potential side MOS transistor My2.

Thus, in the plasma display device according to the present embodiment, a voltage pulse of a fixed potential (−Vy) is applied to the scan electrode Yi by switching the switch SW1 on or off, or a voltage of a blunt wave (−Vyd) is applied. Whether to apply a pulse can be easily switched, and there is no need to perform complicated control to change the voltage value.

For example, the switch SW1 may be controlled to be turned on in a subfield representing the lowest gradation based on the scan data generated by the scan data generation circuit 53 of the drive control circuit 50, or may be the lowest of the display image. On / off may be controlled in accordance with the ratio of signals indicating gradation. In this case, for example, on / off switching of the switch SW1 may be controlled by the voltage waveform switching control means 54 of the drive control circuit 54. At this time, the voltage waveform switching control means 54 may also control the time during which the low potential side MOS transistor My2 and the low potential connection MOS transistor My5 of the scan driver 41 are turned on, that is, the pulse width of the blunt wave. The voltage waveform switching control means 54 may be configured as an arithmetic processing means for performing such arithmetic processing, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory) or a ROM (Read Only Memory). It may be configured as a microcomputer provided with storage means such as, or may be configured as a predetermined electronic circuit.

In FIG. 6, the sustain driver 42 functions as a potential supply means for supplying the sustain pulse Vs or the ground potential. When Vs is supplied to the scan electrode Yi, the MOS transistor My3 is turned on and the ground potential is set. In the case of supply, the MOS transistor My4 is turned on.

Next, an address discharge for supplying a fixed potential to the scan electrode Yi and supplying an obtuse wave to the address electrode Aj will be described with reference to FIG. FIG. 7 is a diagram showing an example of a scan pulse and an address pulse in the address discharge for displaying the lowest gradation. In FIG. 7, the voltage pulse applied to the scan electrode Yi is indicated by Y, and the voltage pulse applied to the address electrode Aj is indicated by A.

As shown in FIG. 7, a voltage pulse (scan pulse) of a fixed potential (−Vy) is applied to the scan electrode Yi, and the obtuse wave Vad whose voltage gradually increases with time changes is applied to the address electrode Aj. Is supplied. The obtuse wave Vad eventually reaches the voltage value Va, and the discharge start voltage is set lower than (Va−Vy). Therefore, the address discharge is also generated while the voltage of the obtuse wave Vad is rising. appear. The discharge intensity is smaller than that when a potential difference of (Va−Vy) is applied between the scan electrode Yi and the address electrode Aj at the same timing. Therefore, similarly to the case shown in FIG. 5, it is possible to generate a discharge that is weaker than the address discharge by applying a square wave, and appropriately express the minimum gradation.

As described above, the obtuse wave voltage pulse may be applied to the address electrode Aj, and the substantially square wave fixed voltage Va may be applied to the scan electrode Yi. Also by this, a weak address discharge can be generated, so that the lowest gradation can be expressed appropriately.

FIG. 8 is a diagram showing an example of the configuration of the address drive circuit 20 for generating the blunt wave Vad of the address pulse shown in FIG.

The address driving circuit 20 of the plasma display device according to the present embodiment includes an address driver 21 and a voltage waveform switching circuit 22. The address driver 21 includes a high potential side switching element Ma1 and a low potential side switching element Ma2. In FIG. 8, the high-potential side switching element Ma1 and the low-potential side switching element Ma2 are indicated by switch symbols. However, for example, a switching element such as a MOS transistor may be applied.

The voltage waveform switching circuit 22 is configured by a parallel connection circuit of a resistor R2 and a switch SW1, one end is connected to the high potential side switching element Ma1, and the other end is connected to the fixed potential Va. When the voltage pulse of the fixed potential Va is supplied to the address electrode Aj of the cell Cij, the switching element Ma1 and the switch SW1 of the voltage waveform switching circuit 22 are turned on, the resistor R2 is short-circuited, and directly to the switching element Ma1. Is supplied with a fixed potential Va. On the other hand, when applying an obtuse wave to the address electrode Aj, the switch SW1 of the voltage waveform switching circuit 22 is turned off to switch to a circuit in which the resistor R2 is connected in series. As described above, the blunt wave Vad can be easily generated for the voltage pulse applied to the address electrode Aj by switching the switch SW1.

Further, the switching control of the switch SW1 may be performed directly based on the address data generated by the address data generation circuit 52, or the voltage waveform switching control means in consideration of the pulse width, the display rate, etc. 54 may be controlled.

Note that when the ground potential is supplied to the address electrode Aj, the low potential side switching element Ma2 may be turned on and the high potential side switching element Ma1 may be turned off.

The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

The present invention can be applied to a plasma display device that displays a moving image with high definition.

Claims

A plurality of scan electrodes and sustain electrodes extending in a first direction and alternately arranged in a second direction; and a plurality of address electrodes arranged to intersect the scan electrodes and the sustain electrodes, A plasma display panel driving method in which cells that emit light by discharge are formed at intersections between sustain electrodes and the address electrodes,
One frame or one field is composed of a plurality of subfields, and the plurality of subfields generate an address discharge by applying a pulse voltage to the scan electrodes and the address electrodes to select the cells to be lit. And a subfield having a sustain period for generating a sustain discharge by applying a voltage between the scan electrode and the sustain electrode selected in the address period and expressing a gray level,
When expressing the lowest gradation of the gradation, the sustain discharge is not performed, and in the address discharge, one of the pulse voltages applied to the scan electrode or the address electrode is set to a voltage over time. A driving method of a plasma display panel, characterized in that an obtuse wave subfield having an obtuse wave with a change is provided.
The method of driving a plasma display panel according to claim 1, wherein the obtuse wave is generated by switching connection of a resistor to a circuit that outputs the pulse voltage.
3. The plasma display panel driving method according to claim 2, wherein whether or not the obtuse wave subfield is provided is determined based on a ratio of the cells displaying the lowest gradation to the total number of cells.
4. The method of driving a plasma display panel according to claim 3, wherein when outputting the obtuse wave, a pulse width of the pulse voltage is widened.
When expressing a gradation that is one step higher than the lowest gradation, the sustain discharge is not performed, and the pulse voltage applied to the scan electrode and the address electrode in the address discharge is both set to a fixed potential. 5. The method of driving a plasma display panel according to claim 4, wherein a subfield is provided.
When expressing a gradation that is two steps higher than the lowest gradation, the sustain discharge is not performed, and the pulse voltage applied to the scan electrode and the address electrode in the address discharge is both set to a fixed potential. And a subfield for applying a voltage to the sustain electrode so that a discharge is generated between the scan electrode and the sustain electrode after the discharge is generated between the scan electrode and the address electrode. The method of driving a plasma display panel according to claim 5.
A plurality of scan electrodes and sustain electrodes extending in a first direction and alternately arranged in a second direction; and a plurality of address electrodes arranged to intersect the scan electrodes and the sustain electrodes, A plasma display panel in which cells that emit light by discharge are formed at intersections of the sustain electrodes and the address electrodes;
A scan driver for driving the scan electrode by applying a pulse voltage to the scan electrode;
An address driver for driving the address electrode by applying a pulse voltage to the address electrode;
A plasma display device comprising: a voltage waveform switching circuit connected to the scan driver or the address driver and configured to make the pulse voltage an obtuse wave whose voltage changes over time.
The plasma display device according to claim 7, wherein the voltage waveform switching circuit is a circuit that switches a resistance value connected to the scan driver or the address driver by a switch.
A scan driving circuit for inputting an image signal to be displayed on the plasma display, converting one frame or one field of the image signal into a plurality of subfields, and driving the scan driver using the subfields, and the address driver A control circuit for controlling an address drive circuit for driving
When the ratio of the number of cells including the luminance signal of the lowest gradation included in the subfield to the total number of cells is equal to or greater than a predetermined value, the control circuit sets the voltage switching circuit to the obtuse wave output side. 9. The plasma display device according to claim 8, further comprising voltage switching control means for switching between the two.
The voltage switching control unit is configured to increase a pulse width of the voltage pulse output from the scan driver or the address driver to which the voltage switching circuit is connected when switching the voltage switching circuit to an obtuse wave output side. The plasma display device according to claim 9, wherein:
11. The plasma display apparatus according to claim 10, wherein the scan electrode, the sustain electrode, and the address electrode are provided on opposing surfaces of the cell.