WO2010024506A1

WO2010024506A1 - Flash based storage device using page buffer as write cache and method of using the same

Info

Publication number: WO2010024506A1
Application number: PCT/KR2008/007648
Authority: WO
Inventors: Jeong Su Park; Sang Lyul Min
Original assignee: Snu R & Db Foundation
Priority date: 2008-08-29
Filing date: 2008-12-24
Publication date: 2010-03-04
Also published as: KR20100026227A; KR101030146B1

Abstract

A method of using a page buffer of a flash memory based storage device as a write cache is disclosed. The flash memory device may include a page buffer to temporarily store data when a read and a write are requested. A programming operation corresponding to a first write command programs data stored in a page buffer to a memory cell array. When the programming operation fails, the flash memory device receives a second write command, and a programming operation corresponding to the second write command programs the data stored in the page buffer to the memory cell array. The second write command and the first write command are write commands with respect to the same data. Accordingly, when the flash memory device uses the data stored in the page buffer, there is no need to receive additional data.

Description

FLASH BASED STORAGE DEVICE USING PAGE BUFFERAS WRITE CACHE AND METHOD OF USING THE SAME

Technical Field The present invention relates to a method of storing data to a flash memory device. This work was supported by the IT R&D program of MIC/IITA [2006-S-040- 03, Development of Flash Memory-based Embedded Multimedia Software].

Background Art A flash memory is a non- volatile memory which maintains stored data even when power is cut off and provides a function of electrically erasing a whole or part of a chip and rewriting the same.

The flash memory is classified into various types such as NAND, NOR, and the like depending on a configuration of a memory cell array. Here, the memory cell is a minimum unit to store one bit data.

The NAND flash memory is able to have high integration and high capacity, thereby attracting attention as a substitute device for a hard disk. Currently, NAND flash memory has been widely utilized as a storage media of a portable mobile device, such as a portable phone, a digital camera, an MP3 player, a camcorder, a PDA, and the like.

However, the flash memory takes a longer time to read and write data compared with a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM). Erasing data stored in the flash memory and storing data in the flash memory takes longer time than reading the data stored in the flash memory. Due to the described asymmetric characteristic of the flash memory, the flash memory device may read and write data by a unit (usually 512B, 2KB, 4KB) called as a page. The flash memory device may simultaneously store data corresponding to a single page. In this instance, the flash memory device may include a page buffer, may store a data page in the page buffer, and simultaneously store the data page in memory cells.

Disclosure of Invention Technical Goals An aspect of the present invention provides a method of using a page buffer as a write cache to reduce a number of data transmissions between a flash memory device and an external host.

An aspect of the present invention provides a flash memory device, that may use data stored in a page buffer, to a plurality of programming operations.

An aspect of the present invention provides a method of using data stored in a page buffer to reduce a penalty caused by failure of programming of the flash memory device.

Technical solutions

According to an aspect of the present invention, there is provided a flash memory device, including a memory cell array including a plurality of memory cells, a page buffer to store data received from an external host as a data page, and a controller unit to control the page buffer to program the stored data page to a first address in the memory cell array, wherein the controller unit controls the page buffer to program the stored data page to a second address in the memory cell array based on a predetermined condition.

According to an aspect of the present invention, there is provided a method of using flash memory, the method including receiving data from an external host and storing the data in a page buffer, programming the data stored in the page buffer to a first address in a memory cell array in response to a program command received from the external host, determining whether the programming corresponding to the first address is successful, and programming the data stored in the page buffer to a second address in the memory cell array when the programming corresponding to the first address fails.

According to an aspect of the present invention, there is provided a method of using a flash memory, the method including receiving data from an external host and storing the data in a page buffer, programming the data stored in the page buffer to a first address in a memory cell array in response to a first program command received from the external host, the first address corresponding to the first program command, and programming the data stored in the page buffer to a second address in the memory cell array in response to a second program command received from the external host, the second address corresponding to the second program command.

According to an aspect of the present invention, there is provided a method of using a flash memory, the method including storing data to a page buffer, programming the data stored in the page buffer to a first address in a memory cell array in response to a first program command, the first address corresponding to the first program command, determining whether a second program command is a command that uses the data stored in the page buffer, and programming the data stored in the page buffer to a second address in the memory cell array in response to the second program command, when the second program command uses the data stored in the page buffer, the second address corresponding to the second program command.

Advantageous Effect

According to an aspect of the present invention, a page buffer of a flash memory device may be used as a write cache, and thereby may reduce a number of data transmission between a flash memory device and an external host.

According to an aspect of the present invention, a flash memory device may use data stored in a page buffer for a plurality of programming operations.

According to an aspect of the present invention, a flash memory device may use a page buffer as a write cache, and thereby may reduce a penalty caused by failure of programming of the flash memory device.

Brief Description of Drawings

FIG. 1 illustrates a flash memory device according to an example embodiment of the present invention; FIG. 2 illustrates a controller module and NAND flash chip according to an example embodiment of the present invention;

FIG. 3 illustrates a flowchart of a method of using a flash memory according to an example embodiment of the present invention; and

FIG. 4 illustrates a flash memory device according to an example embodiment of the present invention.

Best Mode for Carrying Out the Invention Although a few example embodiments of the present invention will be shown and described, the present invention is not limited to the described example embodiments, wherein like reference numerals refer to the like elements throughout.

FIG. 1 illustrates a flash memory device 100 according to an example embodiment of the present invention.

The flash memory device 100 includes a memory cell array 110, a page buffer 120, and a controller unit 130.

The memory cell array 110 may include a plurality of memory cells.

The plurality of memory cells may be Single Bit Cells (SBC) that store one bit per cell or Multi-Bit Cells (MBC) that store more than two bits per cell. SBC is referred to as a Single Level Cell (SLC) and MBC is referred to as a Multi-Level Cell (MLC).

The control unit 130 may receive a write request from an external host 140, and may control the page buffer 120 to receive write data from the host 140. The page buffer 120 may receive the write data from the host 140 and store the received write data.

The page buffer 120 may receive the write data by a byte unit or a word unit from the host 140.

Since a process of programming data in the plurality of memory cells takes a longer amount of time than a process of reading the data from the plurality of memory cells, the flash memory device 100 may program data by a page unit. A page may be a set of a plurality of memory cells that are to be simultaneously programmed. Data to be programmed to a single page is referred to as a data page. The data page may be, for an example, 145 bytes or 4 kilobytes. The page buffer 120 may store at least one data page. The page buffer 120 may store the write data received from the host 140 in a location corresponding to an address in a page of the write data.

The page buffer 120 may enable random access between the host 140 and the flash memory device 100. The page buffer 120 may store data transmitted from the host 140 and may simultaneously program the data to the memory cell array 110 in response to a program command.

The flash memory device 100 may determine whether a threshold voltage of a memory cell or memory cells which is a target for programming reaches a target range, thereby determining whether the programming is successful. As an example, a target range for a threshold voltage of a cell corresponding to data "1" may be IV through 2 V, and a target range for a threshold voltage of a cell corresponding to data "0" may be 3V through 4 V. The flash memory device 100 may determine whether the programming is successful based on data corresponding to the programming and a threshold voltage of a memory cell.

When the programming with respect to the memory cell array 110 from the page buffer 120 fails, the memory cell or the memory cells which is a target for the programming is no longer free or valid.

The flash memory device 100 may select a new memory cell or new memory cells, and may program data corresponding to the failed programming to the selected new memory cell or new memory cells.

In this instance, data of re-tried programming is the same as the data of the failed programming. The flash memory device 100 may provide a write command that only resets an address without retransmitting of data. The host 140 may not retransmit data to the flash memory device 100 and may only transmit a newly set address together with the write command to the flash memory device 100.

In this instance, since unnecessary data transmission between the flash memory device 100 and the host 140 is eliminated, the host 140 may effectively use a data path with the flash memory device 100.

According to another example embodiment, the flash memory device 100 may internally generate a new address. In this instance, the host 140 may not transmit data and a new address, and may transmit a re-write command to the flash memory device 100. The re- write command may be referred to as a re-try command.

When the flash memory device 100 internally generates the new address, the newly generated address may be a physical address, and an address, corresponding to a failed programming, transmitted from the host 140 to the flash memory device 100 may be a logical address. The control unit 130 may store mapping information between the logical address and the physical address.

According to another example embodiment, the flash memory device 100 may provide a program operation that programs the same data to a plurality of addresses. The program operation may be a test operation or a program operation corresponding to a variety of types of a Redundant Arrays of Independent Disks (RAID).

As an example, an RAID 1 type may repeatedly store the same data to a plurality of blocks. The RAID 1 type may improve a read rate of stored data, and may maintain stability even when one device is out of order. The described method is referred to as mirroring.

The test operation may be performed for testing whether a memory cell of the memory cell array 110 is valid or for testing stability of write/read operation. In this instance, a method of repeatedly programming the same data to different addresses may reduce a time expended for an entire test operation. In this instance, only one data transmission between the host 140 and the flash memory device 100 is sufficient, and thus, the time expended for the entire test operation is reduced.

According to another example embodiment, the page buffer 120 may store one or more data page, the control unit 130 may determine whether a program command received from the host 140 corresponds to any one of the one or more data pages stored in the page buffer 120. When the received program command corresponds to any one of the one or more data pages stored in the page buffer 120, the control unit 130 may control the page buffer 120 to program the data page corresponding to the program command to a new address of the memory cell array 110. In this instance, the page buffer 120 may not additionally receive data corresponding to the program command from the host 140. The control unit 130 may internally generate the new address, or may simultaneously receive the new address together with the program command or may receive the new address after receiving the program command from the host 140.

In this instance, the page buffer 120 may not delete data stored on a page even after completing the programming and may maintain the data page.

FIG. 1 illustrates an example embodiment that the control unit 130 located inside the flash memory device 100 controls the page buffer 120. The flash memory device 100 may be embodied by one or more chips. The control unit 130 may be included inside a chip where the flash memory device 100 is embodied or may be located outside the chip. The control unit 130 may be embodied in a software manner or may be embodied using a peripheral circuit inside the chip.

FIG. 2 illustrates a controller module 210 and NAND Flash Chip 220 according to an example embodiment of the present invention.

Referring to FIG. 2, the controller module 210 may receive an abstracted command from an external host, and may convert the abstracted command into a control signal. The controller module 210 may transmit the converted control signal to the NAND flash chip 220 to control an operation of the NAND flash chip 220.

In the example embodiment of FIG. 2, the NAND flash chip 220 may include a memory cell array and a page buffer, and the controller module 210 may control an operation of the page buffer.

FIG. 3 illustrates a flowchart of a method of using flash memory according to an example embodiment of the present invention.

Referring to FIG. 3, a flash memory device 100 receives an address of a write command from a host 140 in operation S310.

The flash memory device 100 loads data of the write command to a page buffer from the host 140 in operation S320. The flash memory device 100 programs the loaded data to the received address in a memory cell array 110, from the page buffer 120 in operation S330.

The flash memory device 100 determines whether the write command is successful in operation S340.

The flash memory device 100 receives a new address, when the write command fails in operation S350. In this instance, depending on an example embodiment, the flash memory device 100 may internally generate a new address.

The flash memory device 100 may program data loaded using the new address to the memory cell array 110 from the page buffer 120 in operation S330.

When the write command is successful, the flash memory device 100 finishes the corresponding process.

FIG. 4 illustrates a flash memory device 400 according to an example embodiment of the present invention.

Referring to FIG. 4, the flash memory device 400 includes a page buffer 420 and a memory cell array 410. The memory cell array 410 may include a first page 411, a second page 412, and a third page 413 according to an address.

Memory cells in the memory cell array 410 may be accessed by a page unit. A set of memory cells which are erased simultaneously is referred to as a block or a erase block, and a set of memory cells which are targets for a simultaneous programming operation is referred to as a page.

The block may include a plurality of pages. An address that indicates the pages in the memory cell array 410 may include a block address field and a page offset field. As an example, when a first page 411 is included in a block 0, a block address field of the first page 411 may be "0". A location of the first page 411 in the block 0 is indicated by a page offset field.

FIG. 4 illustrates an example embodiment of programming data stored in the page buffer 420 to three different pages 411, 412, and 413. The operation may be a test operation or an operation relating to data mirroring.

Although FIG. 4 illustrates an example embodiment of programming the same data to the three pages 411, 412, and 413, the idea of the present invention may not be limited to the present example embodiment and may not be limited to a number of pages to which the same data is programmed.

The method of using the flash memory according to the exemplary embodiments of the present invention includes computer-readable media including program instructions to implement various operations embodied by a computer. The media may also include, alone or in combination with the program instructions, data files, data structures, tables, and the like. The media and program instructions may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD ROM disks; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory devices (ROM) and random access memory (RAM). Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules in order to perform the operations of the above-described embodiments of the present invention, or vice versa. The hardware device may be embodied by a peripheral circuit contained in a flash memory device or may be embodied by an external controller of the flash memory device.

Although a few embodiments of the present invention have been shown and described, the present invention is not limited to the described embodiments. Instead, it would be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A flash memory device, comprising: a memory cell array including a plurality of memory cells; a page buffer to store data received from an external host as a data page; and a controller unit to control the page buffer to program the stored data page to a first address in the memory cell array, wherein the controller unit controls the page buffer to program the stored data page to a second address in the memory cell array based on a predetermined condition.

2. The flash memory device of claim 1, wherein the predetermined condition is a condition that the programming corresponding to the first address fails.

3. The flash memory device of claim 1, wherein the buffer page does not delete the stored data page even after completing the programming corresponding to either the first address or the second address.

4. The flash memory device of claim 1, wherein the predetermined condition is a condition that a programming operation programs the same data page to a plurality of addresses.

5. The flash memory device of claim 4, wherein the predetermined condition is a condition that the programming operation is a test operation which programs the same data page to the plurality of addresses.

6. The flash memory device of claim 4, wherein the predetermined condition is a condition that the programming operation is a Redundant Arrays of Independent Disks (RAID) operation which performs mirroring of the same data page to the plurality of addresses.

7. The flash memory device of claim 1, wherein the page buffer stores at least one data page; and when receiving, from the external host, a programming command corresponding to any one of the at least one data page stored in the page buffer, the controller unit does not receive additional data from the external host, and controls the page buffer to program a data page corresponding to the program command to a second address of the memory cell array.

8. The flash memory device of claim 1, wherein the controller unit receives the second address from the external host or internally generates the second address.

9. A method of using flash memory, the method comprising: receiving data from an external host and storing the data in a page buffer; programming the data stored in the page buffer to a first address in a memory cell array in response to a program command received from the external host; determining whether the programming corresponding to the first address is successful; and programming the data stored in the page buffer to a second address in the memory cell array when the programming corresponding to the first address fails.

10. The method of claim 9, wherein the programming in the second address does not receive additional data from the external host.

11. The method of claim 9, wherein the programming in the second address internally generates the second address or receives the second address from the external host.

12. A method of using a flash memory, the method comprising: receiving data from an external host and storing the data in a page buffer; programming the data stored in the page buffer to a first address in a memory cell array in response to a first program command received from the external host, the first address corresponding to the first program command; and programming the data stored in the page buffer to a second address in the memory cell array in response to a second program command received from the external host, the second address corresponding to the second program command.

13. The method of claim 12, wherein the first program command and the second program command are commands to program the same data.

14. The method of claim 13, wherein the first program command and the second program command are commands to perform mirroring of the same data respectively to the first address and the second address.

15. The method of claim 13, wherein the first program command and the second program command are test commands to program the same data.

16. A method of using a flash memory, the method comprising: storing data to a page buffer; programming the data stored in the page buffer to a first address in a memory cell array in response to a first program command, the first address corresponding to the first program command; determining whether a second program command is a command that uses the data stored in the page buffer; and programming the data stored in the page buffer to a second address in the memory cell array in response to the second program command, when the second program command uses the data stored in the page buffer, the second address corresponding to the second program command.

17. The method of claim 16, wherein the programming to the second address does not receive additional data corresponding to the second program command.

18. The method of claim 16, wherein the programming to the first address or programming to the second address does not delete the data stored in the page buffer even after completing the programming.

19. A computer readable recording medium storing a program implementing the method according to any one of claims 9 to 18.