WO2010012167A1

WO2010012167A1 - Method and apparatus of instruction execution

Info

Publication number: WO2010012167A1
Application number: PCT/CN2009/071558
Authority: WO
Inventors: 高秋明
Original assignee: 华为技术有限公司
Priority date: 2008-07-31
Filing date: 2009-04-29
Publication date: 2010-02-04
Also published as: CN101324838A

Abstract

A method and apparatus of instruction execution. The method comprises: reading a summand variable according to the address of the summand variable; carrying out the comparing operation on the summand variable and the preset value; when the comparing result is feasible, performing the addition operation on the summand variable, and assigning the result of the addition operation to the summand variable; returning a value which is the value of the summand variable before the comparing operation.

Description

Instruction execution method and device

The present application claims priority to Chinese Patent Application No. 200810144462. 5, the entire disclosure of which is incorporated herein by reference. In the present application.

The present invention relates to the field of computer technologies, and in particular, to an instruction execution method and apparatus. Background technique

At present, multi-core processors are booming and more widely used, but the concurrent design of software is relatively lagging behind the development of hardware, which restricts the advantages of multi-core processors. One of the main reasons behind software lag is that multi-core processors have not been able to provide software with a complete set of standard and efficient concurrent instruction sets to support software concurrent processing and design.

Currently implemented atomic/concurrent instructions are: atomic plus instructions, atomic swap instructions, and atomic analog swap instructions. Although the above instructions are all atomic single instructions, they can not fully meet the needs of concurrent software design. Summary of the invention

Embodiments of the present invention provide an instruction execution method and apparatus, which combines a comparison operation and an addition operation into a new atomic comparison plus operation instruction, which enhances the parallel function and improves the execution efficiency.

To achieve the above objective, an embodiment of the present invention provides an instruction execution method, including: reading the addend variable according to an address of an addend variable;

Comparing the added variable with a preset value;

When the result of the comparison operation is established, performing an add operation on the addend variable, and assigning a result of the add operation to the addend variable; Returns the value of the addend variable before the comparison operation.

On the other hand, an embodiment of the present invention further provides an instruction execution apparatus, including:

a reading module, configured to read the addend variable according to an address of the addend variable; a comparison module, configured to compare the addend variable read by the read module with a preset value;

An execution module, configured to perform an add operation on the addend variable when the result of the comparison operation of the comparison module is established, and assign a result of the add operation to the addend variable; The addend variable before returning the comparison operation.

The technical solution of the embodiment of the present invention has the following advantages, because the embodiment of the present invention combines the comparison operation and the addition operation into a new atomic comparison plus operation instruction, thereby enhancing the parallel function and improving the execution efficiency.

The technical solution of the present invention will be further described in detail below through the accompanying drawings and embodiments. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present invention, Those skilled in the art can also obtain other drawings based on these drawings without paying any creative work.

1 is a flowchart of an instruction execution method according to an embodiment of the present invention;

1 is a typical description of an instruction that is greater than plus, and the addition operation is 32B i t signed plus in the embodiment of the present invention;

3 is a mnemonic abbreviation of six comparisons in an embodiment of the present invention;

4 is a flowchart of a specific implementation manner of an instruction execution method according to an embodiment of the present invention; FIG. 5 is a flowchart of another specific implementation manner of an instruction execution method according to an embodiment of the present invention; Execute the device structure diagram. detailed description

Embodiments of the present invention combine a comparison operation with an addition operation to form a new single instruction for atomic operations: an atomic comparison plus instruction, and a method and apparatus for performing the instruction.

The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings and embodiments.

As shown in FIG. 1, it is a flowchart of an instruction execution method in the embodiment of the present invention, that is, an execution flowchart of an atomic comparison plus instruction, which includes the following steps:

S 1 0 Reads the value of the addend variable from the memory based on the address of the addend variable.

51 02. Compare the value of the addend variable with the preset value.

If the result of the comparison operation is established, that is, the relationship between the value of the addend variable and the preset value does exist in the relationship corresponding to the comparison operation, then S 1 03 is executed;

If the result of the comparison operation is not established, that is, the relationship between the value of the addend variable and the preset value does not exist in the relationship corresponding to the comparison operation, execute S 1 05;

For example: the comparison operation is specifically to compare whether the added variable is greater than the preset value, when the value of the added variable is greater than the preset value, the result of the comparison operation is established, when the value of the added variable is not greater than the preset value The result of the comparison operation is not established.

The comparison operation is divided into six types, that is, greater than, less than, greater than or equal to, less than or equal to, equal to, and not equal to.

Corresponding to the six comparison operations, the execution instructions proposed by the embodiments of the present invention are also divided into six comparison and addition operations, that is, greater than plus, less than plus, greater than or equal to plus, less than or equal to plus, equal to plus, not equal to plus.

Based on the foregoing operation classification, in the process of applying the execution instruction proposed by the embodiment of the present invention, as long as the specific content of the comparison process is replaced, the operation corresponding to the execution instruction may also generate a corresponding change. Therefore, the execution of the embodiment of the present invention is performed. An instruction is actually a set of instructions, and the instruction is atomic, single instruction.

51 03 , Perform the addition operation on the value of the added variable. SI 04, assigns the result of the addition operation to the added variable.

If the result of the comparison operation is established, an addition operation is performed on the value of the addend variable.

There are also many types of addition operations, such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system. After the addition operation is performed on the value of the addend variable, the result of the addition operation is assigned to the addend variable.

In this step, the value of the addend variable in memory is updated.

S105, returning the value of the addend variable before the comparison operation.

If the result of the comparison operation of S102 is satisfied, after the execution of S104 is completed, the step is directly executed, and the value of the addend variable before the comparison operation is returned; if the result of the comparison operation of S102 is not satisfied, the execution is performed directly after the execution of S102 is completed. Step, return the value of the addend variable before the comparison operation.

It should be further pointed out that after the execution of the instruction, that is, after the execution of the atomic comparison plus instruction described in the above S101 to S104 is completed, the value of the addend variable before the comparison operation returned by S105 can be further used for the subsequent instruction. It is judged whether the instruction actually performs the addition operation on the addend variable, that is, the execution result of the instruction is verified.

The subsequent instruction may be the repeated execution of the atomic comparison plus instruction, so that the value of the addend variable before the comparison operation returned by S105 is needed to determine whether the previous execution of the atomic comparison plus instruction is completed; or other operation instruction , the referenced variable needs to be referenced. Therefore, it is judged whether or not the above-described atomic comparison plus instruction execution is completed by the value of the addend variable before the comparison operation returned by S105.

Further, the subsequent instruction determines whether the instruction actually performs an operation on the addend variable, specifically:

The value of the added variable before the comparison operation is compared with the preset value for the comparison of the contents of S102.

If the result of the comparison operation is established, it is judged that the atomic comparison plus instruction performs an addition operation on the added variable. If the result of the comparison operation is not true, then it is judged that the atomic comparison plus instruction does not perform an addition operation on the added variable.

It should be further noted that there is no necessary sequence relationship between S105 and S104 in this embodiment, and S105 can be executed at any time after the execution of S101 is completed until the end of the instruction, thereby returning the value of the addend variable before the comparison. That is, the value of the addend variable read in S101 is returned. Therefore, the schematic flow diagram shown in FIG. 1 corresponds to only a preferred embodiment of the present invention, and the change in the position of S 105 does not affect the scope of protection of the present invention.

S106, ending the instruction operation.

The atomic comparison plus instruction in the embodiment of the present invention is a set of instructions, which is a combination of addition and comparison on the mnemonic. As shown in Figure 2, the most typical is greater than plus, and the addition operation is a 32Bit signed plus instruction description. "gt" is an abbreviation for greater than.

The comparison operation is divided into six types, that is, greater than, less than, greater than or equal to, less than or equal to, equal to, and not equal to. As shown in FIG. 3, it is a mnemonic abbreviation for six comparisons in the embodiment of the present invention.

There are also many types of addition operations, such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system.

There are many combinations of addition and comparison operations. We choose a typical form for specific interpretation.

The format of the atomic 32BU signed number greater than the added instruction operation is as follows:

Addgt Ra, Rb, Rc

Among them, the above Ra, Rb and Rc are three general-purpose 32-bit registers.

As shown in FIG. 4, it is a flow chart of a specific implementation manner of the instruction execution method in the embodiment of the present invention, and the instruction operation corresponding to the above format is described by using the most common greater than plus, including the following steps:

S401, the value of Ra is the address of the addend variable, and the instruction executing device extracts the value v of the addend variable from the register Ra according to the address.

V is a signed 32-bit data that acts as an addend. 5402. The instruction execution device compares the preset values stored in the values V and Rb of the addend variable, that is, whether the comparison V is greater than the data in the Rb.

Pre-set signed 32-bit data is stored in Rb, which is used to compare with the added number read in S401.

The specific comparison operation may be one of the foregoing six comparison operations. The comparison operation applied in this embodiment is greater than the comparison, that is, whether the value V of the comparison addend variable is greater than the preset value in Rb.

If the result of the comparison operation is established, that is, the value V of the addend variable is greater than the preset value in Rb, then S403 is performed;

If the result of the comparison operation is not established, that is, the value V of the addend variable is not greater than the preset value in Rb, S405 is executed.

5403. The instruction execution device performs an operation on the added value V.

If the result of the comparison operation is established, ie, ¥>111), then result=v+Rc is executed, that is, the value V of the addend variable is added to the data value stored in Rc, and Rc represents the read from the register Rc. The signed 32-bit data subjected to the addition operation by the value V of the addend variable, and the result represents the result data generated after the addition operation is performed on the data values stored in the values V and Rc of the addend variable.

5404. The instruction execution device assigns the result of the addition operation to the addend variable.

After executing result=v+Rc, the instruction execution device writes the value of result back to the memory according to the address of the addend variable in the Ra register, that is, the value v of the addend variable in the memory is updated.

It should be noted that the memory refers specifically to an external storage device, and the instruction execution device can be accessed through an external address or interface, and the register refers to a temporary data storage unit inside the instruction execution device for storing the generated during the operation of the instruction execution device. Temporary data can be automatically or manually emptied after the run ends.

S405. The instruction execution device stores the value V of the addend variable before the comparison operation into Ra.

S406, ending the instruction operation. When the above-described atomic comparison plus instruction is executed, the instruction execution device needs to access the external memory according to the value of the register Ra (that is, the address of the variable V), and performs a read operation and a write operation, which may cause an address class access abnormality. However, exceptions do not produce a modified effect on the memory, so read and write access exceptions do not affect the consistency and integrity of the data.

Further, after the completion of the atomic comparison operation, that is, after S206 is completed, the subsequent instructions may take further steps, and the other device further determines whether the value V of the addend variable in the memory performs the actual addition operation. That is, whether the new value writing operation of the memory is actually performed, as shown in FIG. 5, as follows:

5501, Read the value in Ra (When the atomic comparison plus instruction is executed, Ra stores the value of the added V before the comparison operation).

5502: Perform the same comparison operation as the foregoing S 402 with the value in Ra and the preset value stored in Rb.

That is, whether the comparison Ra is greater than the preset value stored in the Rb. Further, the comparison operation in this step may be an instruction execution device or other device that needs to know whether the operation is performed, and the change of the main body of the comparison operation does not affect the present. The scope of protection of the invention.

If the result of the comparison operation is established, then S 503 is performed;

If the result of the comparison operation is not established, S 504 is executed.

55 03 , Judging the atomic comparison plus instruction to perform the addition operation.

55 04 , Judging that the atomic comparison plus instruction does not perform the addition operation.

The embodiment of the present invention combines the comparison operation and the addition operation into a new atomic comparison plus operation instruction, thereby enhancing the parallel function and improving the execution efficiency.

The following is the function pseudo code when the instruction execution device executes the above atomic comparison plus instruction: addg t ( &Ra, &Rb, &Rc)

{

/ * With Ra as the address, read the addend and save the copy.

Read operation, may cause read exception * / rodTemp = * (volatile signed int *) Ra

/* 32Bit Signed comparison */

If ( WrodTemp > Rb)

{

The result of I* will be added to the memory with Ra as the address.

Write operation, may cause write exception * /

* ( (volatile signed int * ) Ra ) = WrodTemp + Rc ; } Returns the original addend to Ra, which can be used to determine whether an add operation has been performed */ Ra = WrodTemp;

Return ;

}

As shown in FIG. 6, it is a structural diagram of an instruction execution apparatus according to an embodiment of the present invention, including: a reading module 610, configured to read a value of an addend variable according to an address of an addend variable. The comparison module 620 is configured to compare the value of the addend variable read by the reading module 610 with a preset value.

The execution module 630 is configured to perform an add operation on the value of the addend variable when the comparison module 620 determines that the result of the comparison operation is established, and assign the result of the add operation to the addend variable.

There are also many types of addition operations, such as signed addition, unsigned addition, 32-bit addition, and 64-bit addition, which are the same as the actual addition instructions in the system. After performing the addition operation on the value of the addend variable, the result of the addition operation is assigned to the addend variable, and the value of the addend variable is stored to the original address.

The execution module 6 30 specifically includes:

The execution sub-module 631 is configured to perform an addition operation on the value of the addend variable.

The assignment submodule 632 is configured to assign the result of the addition operation performed by the execution submodule 631 to the addend variable.

The storage module 640 is configured to store temporary data during execution of the instruction, including one or more of the following values:

The value of the addend variable read by the module 61 0 is read, the execution result of the module 630 is executed, and the data value read from each register, such as the preset value read from Rb, Rc in the foregoing embodiment. .

The return module 650 is configured to return the value of the addend variable read by the reading module 61 0 for subsequent instructions to determine whether the instruction performs the adding operation.

Subsequent devices (subsequent instructions) following this instruction may return the value of the addend variable before the comparison operation (such as the value of the addend variable V described above) and the preset value according to the return module 650 (as in the foregoing Rb Set value) The same comparison operation as that performed in the comparison module 620 is performed.

If the result of the comparison operation is established, it is judged that the atomic comparison plus instruction performs the addition operation; if the result of the comparison operation is not established, it is judged that the atomic comparison plus instruction does not perform the addition operation.

The above modules may be distributed in one device or distributed in multiple devices. The above modules can be combined into one module or further split into multiple sub-modules.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary general hardware platform, and of course, can also be hard. Pieces, but in many cases the former is a better implementation. Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium, including a plurality of instructions for making a The terminal device (which may be a cell phone, a personal computer, a server, or a network device, etc.) performs the methods described in various embodiments of the present invention. It should be noted that the above embodiments are only for explaining the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: The technical solutions described in the foregoing embodiments are modified, or some of the technical features are equivalently replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

Claim

1. An instruction execution method, comprising:

Reading the addend variable according to the address of the addend variable;

Comparing the added variable with a preset value;

And when the result of the comparing operation is established, performing an adding operation on the addend variable, and assigning a result of the adding operation to the addend variable;

Returns the value of the addend variable before the comparison operation.

2. The instruction execution method according to claim 1, further comprising: the subsequent instruction determining whether the instruction has performed an addition operation by the addend variable before the returning comparison operation after the instruction is executed.

The instruction execution method according to claim 1, wherein the comparing operation specifically includes one of the following relationships between the addend variable and the preset value:

Greater than, less than, greater than or equal to, less than or equal to, equal to or not equal to.

4. An instruction execution apparatus, comprising:

The instruction execution device according to claim 4, wherein the execution module specifically includes:

An execution submodule, configured to perform an adding operation on the added variable;

And an assignment submodule, configured to assign a result of the adding operation performed by the execution submodule to the addend variable.

The instruction execution device according to claim 4, further comprising: And a storage module, configured to store an execution result of the execution module.

The instruction execution device according to claim 6, wherein the storage module is further configured to store the addend variable read by the reading module.