WO2010000806A1 - Rfid device - Google Patents

Rfid device Download PDF

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Publication number
WO2010000806A1
WO2010000806A1 PCT/EP2009/058336 EP2009058336W WO2010000806A1 WO 2010000806 A1 WO2010000806 A1 WO 2010000806A1 EP 2009058336 W EP2009058336 W EP 2009058336W WO 2010000806 A1 WO2010000806 A1 WO 2010000806A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
coil
substrate
windings
contact pad
Prior art date
Application number
PCT/EP2009/058336
Other languages
French (fr)
Inventor
Sören STEUDEL
Original Assignee
Imec
Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Nederlandse Organisatie Voor Toegepast-Natuurwetenschappelijk Onderzoek Tno filed Critical Imec
Publication of WO2010000806A1 publication Critical patent/WO2010000806A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips

Definitions

  • the present invention relates to an RFID device comprising an integrated circuit connected with a first side on a first substrate for producing an RFID code and an antenna connected to the integrated circuit for transmitting the RFID code, the antenna comprising an inductive coil on a top surface of a second substrate, the inductive coil comprising a plurality of windings, a first coil terminal located at an inner side of the plurality of windings and a second coil terminal located at an outer side of the plurality of windings, the integrated circuit comprising an electrically insulating outer surface which exposes a first contact pad and a second contact pad via which the integrated circuit is electrically connected to the first and second coil terminals.
  • a typical RFID tag comprises an antenna and an integrated circuit electrically connected to the antenna.
  • the RFID antenna may be an inductive antenna, which can comprise a capacitor and a coil.
  • the capacitor of the antenna can be part of the integrated circuit.
  • the coil of the antenna typically comprises a plurality of windings and two coil terminals or contact pads located on a distance from each other. In fact, a first coil terminal or contact pad is located at an inner side of the plurality of windings and a second coil terminal or contact pad is located at an outer side of the plurality of windings. Both coil terminals need to be electrically connected to the integrated circuit.
  • the integrated circuit is usually located at the inner side of the coil windings. Therefore, there is a need for providing an electrical connection between the second coil terminal located at the outer side of the windings and a third terminal or pad located at the inner side of the windings, across the plurality of coil windings.
  • This electrical connection bridges the windings of the coil, i.e. it forms a bridge between the inner side of the plurality of windings and the outer side of the plurality of windings, and it is electrically isolated from the windings.
  • the electrical pads on the integrated circuit can be electrically connected to the coil terminals of the antenna of the RFID tag.
  • the integrated circuit can for example comprise a capacitor, a rectifier, a digital block and/or a modulator. In case of an active tag a battery is present to provide power to the integrated circuit.
  • the capacitor on the integrated circuit forms, together with the coil, an antenna as a resonant LC tank at an RF carrier frequency.
  • the digital block can for example comprise a clock generator and a memory that can for example be a read-only memory (e.g.
  • the digital block can further comprise a circuit to read out the memory.
  • Data can be modulated by the modulator and a modulated signal can be sent back to a reader via the antenna.
  • One solution comprises providing the windings of the coil on one side of a substrate, forming vias with electrical connections through the substrate and providing metal contacts at the second side of the substrate.
  • the integrated circuit is then connected to the metal contacts at the second side of the substrate.
  • This method requires forming metal patterns at both sides of the substrate. Therefore alignment between the two sides is crucial.
  • Another method e.g. as described in US 6,693,541 comprises providing a separate electrical conductor to form a bridge over de plurality of windings (at the same side of the substrate as the windings), with a dielectric material between the separate electrical conductor and the coil windings.
  • RFID integrated circuits are generally based on silicon integrated circuits. These silicon integrated circuits are relatively small and have tiny bonding pads.
  • a technique known in the prior art for positioning a small integrated circuit accurately on a relatively large (e.g. credit card size) substrate is known as "pick and place". This technique is relatively slow when the positioning precision needs to be high (e.g. because of the tiny bonding pads) while the substrate on which the chip is to be positioned is relatively large.
  • the tiny chip bonding pads may have a low reliability, e.g. due to stress, in particular on flexible substrates.
  • Thin film transistor technologies such as e.g. technologies using amorphous silicon, carbon nanotubes, metal oxides, chalcogenides, Si precursors or organic semiconductors, provide options to realize flexible low- cost circuits such as e.g. RFID tags, fabricated with relatively cheap production methods on flexible substrates.
  • the production methods can for example comprise methods for patterning features on a circuit that provide a relatively cheap alternative to optical lithography.
  • Printing techniques such as imprint, nano-imprint, flexography, gravure, contact printing or inkjet printing may in the future allow patterning features at high throughput and good accuracy.
  • Thin-film circuits offer particular advantages when they are integrated into devices. Whereas silicon integrated circuits have tiny bonding pads, with sizes of 10 ⁇ m to 300 ⁇ m in lateral dimension, the bonding pads of thin film devices can be much larger, e.g. 0.1 to 10 mm in size, because the substrate area consumed by large pads represents only a minor cost. For silicon integrated circuits the bonding of circuits to a substrate and the creation of electrical connections between pads on a circuit and pads on a substrate is typically done by means of solder bumps or wire bonding.
  • bonding of circuits to a substrate and the creation of electrical connections can be obtained by lamination of a carrier comprising the active thin-film circuit to a substrate, wherein an electrically conductive adhesive can be used for forming electrical connections between pads of the thin-film circuit and pads on the substrate.
  • It is a first aim of the present invention to provide an RFID device comprising an integrated circuit connected with a first side on a first substrate for producing an RFID code and an antenna connected to the integrated circuit for transmitting the RFID code, the antenna comprising an inductive coil on a top surface of a second substrate, the inductive coil comprising a plurality of windings, a first coil terminal located at an inner side of the plurality of windings and a second coil terminal located at an outer side of the plurality of windings, the integrated circuit comprising an electrically insulating outer surface which exposes a first contact pad and a second contact pad via which the integrated circuit is electrically connected to the first and second coil in a less complex way compared to prior art RFID devices.
  • the first aim is achieved according to the present invention with an RFID device showing the technical features of the characterizing part of the first claim.
  • the integrated circuit is attached directly on top of the first and second coil terminals and an electrically insulating layer present at an outer surface of the integrated circuit is used for providing an electrical insulation between the integrated circuit and the plurality of coil windings.
  • the integrated circuit is attached directly on top of the terminals' as used herein is meant that the integrated circuit, i.e. the integrated circuit with the electrically insulating outer surface, is in direct contact with the terminals or only separated with an adhesion layer from the terminals.
  • the first substrate or an encapsulation layer encapsulating the integrated circuit can be used as an insulating layer providing electrical insulation between the integrated circuit and the plurality of coil windings.
  • the distance between the first coil terminal and the second coil terminal and the distance between the first contact pad and the second contact pad is chosen such that the first and the second contact pads respectively at least partially overlap with the first and the second coil terminals to provide the electrical connection.
  • the integrated circuit of the RFID device according to the present invention can be used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the integrated circuit.
  • the integrated circuit By using the integrated circuit to bridge the coil windings, the need for additional processes for bridging the windings can be avoided.
  • the second aim is achieved according to the present invention with a method showing the technical features of the characterizing part of the eighth claim.
  • the method comprises the steps of: (a) providing the integrated circuit; (b) encapsulating the integrated circuit to obtain an electrically insulating outer surface which exposes the first contact pad and the second contact pad
  • the method according to the present invention further has the advantage that the integrated circuit itself, i.e. an insulating layer present at an outer surface of the integrated circuit, can be used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the integrated circuit. As a result the need for additional processes for bridging the windings can be avoided.
  • the integrated circuit itself i.e. an insulating layer present at an outer surface of the integrated circuit
  • the process for manufacturing the integrated circuit typically requires patterning steps allowing smaller dimensions as compared to the patterning steps needed for manufacturing the coil.
  • the integrated circuit is formed on a first substrate, which may be used as a bridging part for bridging the coil windings.
  • a plurality of integrated circuits is formed on a single first substrate.
  • the integrated circuit are preferably thin film circuits, formed by thin film deposition techniques.
  • the first substrate comprising the thin film circuits is cut into dies, each die comprising at least one integrated circuit. Such a die is subsequently laminated to the coil substrate, thereby aligning contact pads of the thin film circuit on the die with contact pads or terminals of the coil, wherein the contact pads of the coil are located at opposite sides of the coil windings.
  • the die comprising the thin film circuit is used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the thin film circuit. It is an advantage of the present invention that the die comprising the thin film circuit is used to bridge the coil windings, such that the need for additional processes for bridging the windings can be avoided.
  • electrically conductive paths are created between predetermined pads on the thin film circuit and the terminals or contact pads of the coil.
  • the materials used to ensure the electrical connection between pads of the thin film circuit and pads of the coil can be applied by dispensing techniques rather than by solder techniques or wire bonding. In preferred embodiments a single lamination step may be used for attaching the die comprising the thin film circuit to the coil substrate and forming electrical connections.
  • Electrically connecting the first contact pad to the first terminal and the second contact pad to the second terminal preferably comprises the steps of (i) aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal; (ii) laminating the first substrate and the second substrate; (iii) and forming an electrical connection between the first contact pad and the first terminal and between the second contact pad and the second terminal.
  • the step of laminating the first substrate and the second substrate and the step of forming an electrical connection between the first contact pad and the first terminal and between the second contact pad and the second terminal can be a single step or it can be separate steps.
  • aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal may comprise orienting the first substrate and the second substrate such that a surface of the first substrate on which the integrated circuit is provided faces a surface of the second substrate on which the coil is provided.
  • Laminating the first substrate and the second substrate can comprise providing an electrically conductive material in between the integrated circuit on the first substrate and the inductive coil on the second substrate.
  • the electrically conductive material can be an anisotropically conductive material that is electrically conductive in a direction substantially perpendicular to a surface of the first substrate.
  • Laminating the first substrate and the second substrate may further comprise providing an electrically insulating material in between the integrated circuit on the first substrate and the inductive coil on the second substrate at locations separated from the first contact pad, the second contact pad, the first terminal and the second terminal.
  • aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal may comprise orienting the first substrate and the second substrate such that a surface of the first substrate opposite to the surface on which the integrated circuit is provided faces a surface of the second substrate on which the coil is provided.
  • the layer of insulating material forms part of a dielectric layer encapsulating the integrated circuit, as a result of which the manufacturing process can be simplified.
  • the first substrate may provide an electrical insulation between the integrated circuit and the plurality of windings of the coil.
  • the contact pads of the integrated circuit and the contact terminals of the coil are relatively large, e.g. they have a lateral size in the range between 0.1 mm and 10 mm. It is an advantage of such relatively large contact pads and terminals that the process of placing the die over the coil windings and the process of aligning contact pads of the integrated circuit with contact terminals of the coil can be a faster process as compared to prior art processes, because the alignment precision that is required is less stringent (typically 0.1 to 10 mm). It is a further advantage of such relatively large contact pads and contact terminals that a good reliability of the electrical connections can be obtained, in particular in combination with flexible substrates.
  • the first substrate for the thin film circuit and the second substrate for the coil as used in the device and/or method according to the present invention can be any kind of substrate considered suitable by the person skilled in the art. At least one of the first and second substrate may for instance be flexible substrates, such as for example a flexible foil or paper.
  • the process flows for manufacturing the coil and the integrated circuit are preferably based on thin film deposition techniques, allowing relatively cheap manufacturing steps.
  • Such a thin film integrated circuit may for instance be an organic circuit.
  • Figure 1 gives a schematic overview of a prior art inductive organic RFID device.
  • Figure 2 illustrates different organic thin film transistor configurations that may be used in the context of the present invention: (a) bottom-gate bottom-source-drain structure; (b) top-gate bottom-source-drain structure; (c) bottom-gate top-source-drain structure; (d) top-gate top-source-drain structure.
  • Figure 3 shows an organic circuit foil with two large contact pads.
  • Figure 4 shows an inductive coil on a foil.
  • Figure 5 illustrates a process flow for fabricating an organic circuit foil.
  • Figure 6 illustrates a method for laminating an organic circuit foil or die to a foil comprising a coil, according to the present invention.
  • Figure 7 illustrates a method for laminating a plurality of organic circuit foils or dies to a foil comprising a plurality of coils, according to the present invention.
  • Figure 8 illustrates a method for laminating an organic circuit foil or die to a foil comprising a coil, according to the present invention.
  • Figure 9 illustrates a method for laminating a plurality of organic circuit foils or dies to a foil comprising a plurality of coils, according to the present invention.
  • foil is used to refer to a substrate on which thin film technologies are applied.
  • a foil can for example comprise glass, plastic, paper, metal, oxides, or laminates. It can comprise a stack of layers of different types, including for example barrier layers against permeation of moist or oxygen, adhesive layers or planarization layers.
  • the term “foil” can refer to a rigid substrate or to a flexible substrate.
  • the term “thin film circuit foil” is used to indicate a foil comprising a thin film circuit.
  • coating foil is used to indicate a foil comprising an inductive coil.
  • the present invention provides a method for electrically connecting contact pads of an integrated circuit with terminals of an inductive coil comprising a plurality of windings, wherein the integrated circuit is used as a bridge over the windings without causing short-circuits between the windings or between the integrated circuit and the windings.
  • the method of the present invention is less complex than prior art methods, can be performed at a lower cost than prior art methods and allows obtaining a good performance and a good reliability of the resulting device, especially on flexible substrates.
  • the present invention provides a method for electrically connecting contact pads of a circuit comprising thin film transistors (a thin film circuit) with at least two terminals of a coil comprising a plurality of windings on a substrate, at least two terminals of the coil being located at opposite sides of the plurality of windings.
  • a separate bridge e.g. comprising an electrical conductor and a dielectric material to bridge the windings of the antenna.
  • a layer of the integrated circuit e.g. thin film circuit
  • the integrated circuit e.g. thin film circuit
  • electrical insulation between the thin film circuit and the plurality of coil windings is formed by the first substrate of the integrated circuit.
  • the electrical insulation is formed by a dielectric layer covering the integrated circuit, e.g. an encapsulation layer.
  • the second embodiment has the advantage that the electrical contact pads are formed during lamination and no further steps are needed afterwards.
  • the method of the present invention allows manufacturing thin film transistor circuits, such as e.g. RFID tag circuits, on flexible substrates that are more reliable than prior circuits, e.g. RFID tag circuits, because of the larger contact pads that can be used.
  • the present invention is further described for organic thin film transistor circuits.
  • the methods according to the present invention can also be used for other types of thin film transistor circuits, such as for example circuits based on amorphous silicon, carbon nanotubes, metal oxides, chalcogenides, Si precursors, etc.
  • Fig. 1 shows the schematic outline of a prior art inductive organic RFID tag that may for example be fabricated on a flexible substrate, such as a flexible foil (e.g. PEN, PET, polyimide, metal foil, paper).
  • the RFID tag comprises a coil with inductance L on a foil, and one or more other foils comprising a resonant capacitance C and a transponder circuit.
  • the resonant capacitance and the coil form together a resonant HF antenna.
  • the transponder circuit is manufactured with thin-film transistor technologies and may comprise a rectifier. It may also comprise a memory, such as for example a read-only memory or a write-once-read-many (WORM) memory or a reprogrammable memory, e.g. an electrically reprogrammable memory.
  • Fig. 1 also shows a reader for reading data code that is stored in a memory of the transponder circuit.
  • the prior art inductive organic RFID tag comprises four integrated foils, as indicated with dotted lines in Fig.
  • a foil comprising the coil of the antenna a foil comprising a resonant capacitance, a foil comprising a rectifier fabricated using thin-film technologies and a foil comprising a transponder circuit fabricated using thin-film technologies.
  • the RFID system may for example be suitable for operating at a base carrier frequency of 13.56 MHz.
  • the resonant capacitor is designed for matching the resonance frequency of the LC antenna at 13.56 MHz.
  • This LC-antenna detects the signal transmitted by the reader and energizes the organic rectifier with an AC-voltage at 13.56 MHz. From this voltage the rectifier generates a DC supply voltage for the organic transponder circuit, which drives the modulation transistor between the on and off state with a code sequence.
  • a thin film circuit comprising a resonant capacitance module, a rectifier module and a thin-film transponder module may be realized on one foil, i.e. a first substrate, and a coil of the LC antenna comprising a plurality of windings and two terminals may be formed on a separate foil, i.e. on a second substrate. Both foils may then be laminated to each other, whereby electrical connections are made between contact pads on the organic thin film circuit and the coil terminals.
  • a typical size of a foil comprising a thin film circuit is e.g. about 1 cm to 4 cm by 0.2 cm to 2 cm.
  • the foil may have a thickness in the range between 25 ⁇ m and 500 ⁇ m and may comprise for example a plastic foil (e.g. PEN, PET, Polyimide), a metal foil (e.g. Al, Cu), paper, laminates or stacks.
  • the thin film capacitors formed on the thin film circuit foil comprise two conductive layers separated by a dielectric layer.
  • the conductive layers of the thin film capacitors may for example comprise Cu, Al, Au, Ag, ITO, ZnO, Ag-ink, or a carbon-nanotube ink, with a thickness in the range between 10 nm and 10 ⁇ m.
  • the dielectric layer in between both conductive layers of the thin film capacitors may comprise for example an organic dielectric material such as e.g. polystyrene, poly-4-venylphenol (PVP), benzcocyclobutene
  • the dielectric layer in between the conductive layers of the thin film capacitors may comprise an inorganic dielectric material such as e.g. SiO 2 , Ta 2 O 5 , BZT (barium zirconate titanate), AI 2 O 3 , YO x or SiN 4 .
  • the thickness of the dielectric layer may be in the range between 10 nm and 10 ⁇ m.
  • Thin film diodes may be provided on the thin film circuit foil, e.g. diodes that are part of a rectifier.
  • the diodes may comprise a thin film semiconductor layer such as e.g. pentacene, polythiophene, Cu-pthalocyanine, C60, thin film semiconductor oxides such as ZnO, thin film semiconductor sulfides or selenides, amorphous Si, or carbon nanotubes, sandwiched in between a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer having a different workfunction.
  • a first conductive layer may comprise electrodes with high (5eV to 6eV and more) to medium (4eV to 5eV) workfunction such as e.g.
  • a second conductive layer my comprise electrodes with a medium (4 eV to 5 eV) to low (less than 3 eV to 4 eV) workfunction such as Al, Ti, conductive oxides such as e.g. TiO x , ZnO, Aluminum-doped ZnO (AZO), Ag, Cu.
  • a medium (4 eV to 5 eV) to low (less than 3 eV to 4 eV) workfunction such as Al, Ti, conductive oxides such as e.g. TiO x , ZnO, Aluminum-doped ZnO (AZO), Ag, Cu.
  • Thin film transistors on the thin film circuit foil 10 may be realized in different configurations, as illustrated in Figure 2.
  • the source contacts 12, the drain contacts 13 as well as the gate contacts 1 1 and the electrically conductive filling 16 (e.g. metal filling) of the via holes through the dielectric layer 14 may comprise either the same or different conductive layers (such as e.g. Cu, Al, Au, Ag, ITO, ZnO, Ag-ink, carbon-nanotube ink) with a thickness in the range between 10 nm to 10 ⁇ m and with lateral dimensions of the source and drain contacts in the range between 100 nm and 100 ⁇ m, preferably between 500 nm and 10 ⁇ m.
  • Vias are provided for electrically connecting different layers of thin film transistors of the thin film circuit.
  • the gate dielectric layer 14 may comprise either an organic dielectric material (for example a polymer such as e.g. polystyrene, poly-4-venylphenol (PVP), benzcocyclobutene (BCB), polyimide, parylene, PVDF polymers and copolymers, or for example small molecules) or an inorganic dielectric material (such as e.g. SiO 2 , Ta 2 O 5 , BZT (barium zirconate titanate), AI 2 O 3 , YO x or SiN 4 ) with a thickness in the range between 10 nm and 10 ⁇ m.
  • organic dielectric material for example a polymer such as e.g. polystyrene, poly-4-venylphenol (PVP), benzcocyclobutene (BCB), polyimide, parylene, PVDF polymers and copolymers, or for example small molecules
  • an inorganic dielectric material such as e.g. SiO 2 , Ta 2 O 5
  • the thin film semiconductor layer 15 in contact with the source 12 and drain 13 may for example comprise pentacene, polythiophene, Cu-pthalocyanine, C60, ZnO, amorphous Si, or carbon nanotubes and may have a thickness in the range between 5 nm and 5 ⁇ m.
  • Figure 3 shows a first substrate 10, e.g. a thin film circuit foil, comprising an integrated circuit 18, e.g. a thin film circuit, with a first 171 and a second 172 contact pad provided on a first predetermined distance from each other, to be used in an RFID device according to the present invention or in a method according to the invention for electrically connecting to the coil terminals of an inductive coil.
  • a first substrate 10 e.g. a thin film circuit foil
  • an integrated circuit 18 e.g. a thin film circuit
  • a first 171 and a second 172 contact pad provided on a first predetermined distance from each other
  • the contact pads 171 , 172 are preferably relatively large having a size in the range between 100 ⁇ m x 100 ⁇ m to 10 mm x 10 mm, more preferably in the range between 200 ⁇ m x 200 ⁇ m and 3 mm x 3 mm, as e.g. illustrated in Figure 3, such that alignment of the contact pads with the coil terminals is simplified.
  • Figure 4 shows an inductive coil 28 to be used in an RFID device according to the present invention or in a method according to the invention for electrically connecting to the contact pads of an integrated circuit.
  • the inductive coil 28 comprises a plurality of windings, a first coil terminal 271 provided at an inner side of the coil and a second coil terminal 272 provided at an outer side of the coil.
  • the first and the second coil terminal 271 , 272 are provided at a second predetermined distance from each other.
  • the contact pads 171 , 172 shown in figure 3 are provided for being electrically connected to the two coil terminals 271 , 272 of the coil 28 that is provided on a second surface of a second substrate 20, e.g. a separate foil as is illustrated in Figure 4.
  • the contact pads 171 , 172 of the integrated circuit can comprise the same conductive material as the electrically conductive filling 16 of the via holes 16 of Figure 2 through the gate dielectric 14 of the thin film circuit 18, such as for example Al, Cu or Au, or they can comprise a different conductive material.
  • the size of the contact pads 271 , 272 of the coil 28 and the contact pads 171 , 172 of the thin film circuit 18 may be the same or be different.
  • the first contact pad 171 and the second contact pad 172 of the thin film circuit 18 are respectively electrically connected to a first and a second terminal of a capacitor on the thin film circuit 18.
  • the coil foil 20, i.e. the second substrate, for an RFID device working at 13.56 MHz has commonly a smart card format (4.8 cm x 7.6 cm) with two to ten windings 26 of a metal such as for example copper or silver and with two coil terminals or contact pads 271 , 272, a first one (271 ) being located at the inner side of the coil windings 26 and the second one (272) being located at the outer side of the coil windings 26 as for example illustrated in Figure 4.
  • the coil terminals 271 , 272 preferably comprise the same material as the coil windings 26, such as for example Cu or Ag, but may also be chosen differently.
  • the coil foil 20, i.e. the second substrate is commonly a PET foil, but other materials, preferably flexible materials, such as e.g. PEN, PET, polyimide or paper may be used.
  • the production process of the coil 28 on the foil 20 may for example comprise a roll-to-roll process, e.g. based on etching of Cu that has been sputtered on the foil or e.g. based on screen printing of an electrically conductive ink, such as for example a silver ink.
  • a roll-to-roll process e.g. based on etching of Cu that has been sputtered on the foil or e.g. based on screen printing of an electrically conductive ink, such as for example a silver ink.
  • Other production processes known by a person skilled in the art may be used.
  • Methods that may be used for depositing the thin films in the context of the present invention comprise process steps performed in vacuum (e.g. evaporation, sputtering, laser ablation, Chemical Vapour Deposition, ion-beam sputtering, organic vapour phase deposition) and process steps performed at near-ambient pressure (e.g. spin-coating, spray-coating, printing, lamination).
  • vacuum e.g. evaporation, sputtering, laser ablation, Chemical Vapour Deposition, ion-beam sputtering, organic vapour phase deposition
  • near-ambient pressure e.g. spin-coating, spray-coating, printing, lamination
  • Processing at near-ambient pressure may include steps that are performed in a controlled environment, e.g. in an environment with controlled oxygen, water vapour or ozone concentration.
  • the patterning steps may be based on additive processes (such as e.g. direct printing, deposition through a shadow mask) as well as subtractive processes whereby a pattern is obtained by removing parts of a layer that is deposited e.g. over a complete substrate.
  • Subtractive processes may for example be based on etching, laser ablation or lift-off techniques.
  • Figure 5 shows a possible process flow for fabricating a thin film circuit 18, i.e. an integrated circuit, on a thin film circuit foil 10, i.e. on a first substrate, wherein the thin-film semiconductor is an organic semiconductor 15 such as e.g. pentacene.
  • the foil 10, e.g. PEN foil, on which the thin film circuit 18 is to be formed may first be laminated to a rigid carrier 30 such as for example glass or a silicon wafer (Fig. 5(a)).
  • a planarization layer 31 may be provided, e.g. by spin coating a resist layer (e.g. SU8), e.g. with a thickness in the order of 2 ⁇ m, to smoothen out roughness spikes (Fig.
  • a first thin metal layer 32 may be provided, e.g. by sputtering a 30 nm thin Al layer.
  • the first thin metal layer 32 may be patterned, for example by means of photolithography and etching (Fig. 5(c)).
  • Other materials and methods known by a person skilled in the art may be used for forming and patterning the first thin metal layer 32.
  • This layer 32 can form the gate metal layer 1 1. It can also be part of an electrode layer for a diode on the thin film circuit 18. It can also be an electrode layer for a capacitor on the thin film circuit 18.
  • a dielectric layer 33 such as e.g. a 200 nm thick layer comprising paryelene N, may be provided.
  • This dielectric layer 33 can be the gate dielectric 14. It can also be the dielectric layer of a capacitor of the thin-film circuit 18, more in particular the capacitor for the LC resonant antenna.
  • Via holes may then be formed through the dielectric layer 33, for example based on photolithography and dry etching. The holes may be filled with a conductive material, e.g. metal 34, such as for example 200 nm of Al (as illustrated in Fig. 5(e)).
  • a second thin metal layer 35 may be provided, e.g. by sputtering a 30 nm thin Au layer.
  • This second thin metal layer 35 may be patterned, for example based on photolithography and etching (Fig. 5(f)). Other materials and methods known by a person skilled in the art may be used for forming and patterning the second thin metal layer 35.
  • the second thin metal layer 35 may for example be used for forming the source 12 and drain 13 of a transistor.
  • the patterned layer 35 can also form an electrical connection between transistors, or it can be used as an electrode for a diode.
  • the second thin metal layer 35 can make contact with metal 34 in via holes at predetermined locations on the thin film circuit 18. This is illustrated in Fig.
  • Figure 5(g) illustrates a next step, wherein a thick patterned dielectric layer 36 is provided.
  • This thick dielectric layer 36 may for example comprise a 4 ⁇ m thick SU8 resist layer. Other suitable materials known by a person skilled in the art may be used.
  • the thick patterned dielectric layer 36 can for example have the function of an integrated shadow mask to achieve patterning of a thin film semiconductor layer (to be provided in a subsequent step), in order to reduce leakage current paths between adjacent transistors.
  • the thick patterned dielectric layer 36 can also create a 'box' in which a semiconductor layer can be printed in a subsequent step.
  • a first organic semiconductor layer 37 can for example be provided at a predetermined location by e.g.
  • a 200 nm thick pentacene layer e.g. for forming diodes.
  • Other materials and methods known by a person skilled in the art may be used for providing the first organic semiconductor layer 37.
  • This step may be followed by the deposition of a third metal layer 38, e.g. comprising 100 nm of Al, for forming an electrode of a diode.
  • a second organic semiconductor layer 39 may be provided, e.g. comprising 50 nm of pentacene, for forming transistors (Fig. 5(i)).
  • Other materials and methods known by a person skilled in the art may be used for providing the second organic semiconductor layer 39.
  • This second organic semiconductor layer 39 can be provided on the transistor structures through openings in the integrated shadow mask formed by the thick patterned dielectric layer 36.
  • an organic semiconductor layer 39 may for example be provided by inkjet printing in openings of the integrated shadow mask formed by the thick patterned dielectric layer 36.
  • the circuit may be encapsulated (Fig. 5(j)), e.g. by deposition of a 2 ⁇ m to 20 ⁇ m thick layer 40 of parylene.
  • a silicon nitride layer 41 e.g. with a thickness of 100 nm to 2 ⁇ m, may be sputtered.
  • This silicon nitride layer 41 may act as a barrier layer, e.g. an oxygen barrier or a moist barrier.
  • stacks comprising a plurality of layers of organic and inorganic materials can be used for forming an encapsulation layer.
  • At least two contact pads 171 , 172 may be formed, e.g. at an edge of the thin film circuit 18, the contact pads 171 , 172 being electrically connected to a first terminal and a second terminal of a capacitor on the integrated circuit 18, e.g. to realize an LC antenna.
  • the formation of the contact pads 171 , 172 may for example be based on photolithography and dry etching through the encapsulation layer. Other methods known by a person skilled in the art may be used.
  • the foil 10 may then be removed (delaminated) from the carrier 30, for example by peal-off.
  • the foil 10 is then cut into dies that are subsequently laminated to a foil 20, i.e. a second substrate, comprising an antenna coil 28 (see e.g.
  • Fig. 6, 7, 8, 9 Several methods may be used to connect the foil 10 comprising the thin film circuit 18 to the foil 20 comprising the coil 28 with multiple windings 26, thereby providing an electrical contact between a first contact pad 171 on the thin film circuit foil and a first contact terminal 271 on the coil foil and between a second contact pad 172 on the thin film circuit foil and a second contact terminal 272 on the coil foil.
  • a die i.e. a first substrate, comprising a thin film circuit 18, i.e. an integrated circuit
  • a thin film circuit 18 i.e. an integrated circuit
  • the thin film circuit die is oriented with respect to the coil foil such that the first surface of the thin film circuit die on which the thin film circuit 18 is provided faces the second surface of the coil foil on which the coil 28 is provided. This is illustrated in Fig. 6(a).
  • the contact pads 171 , 172 that are provided for making an electrical contact with the coil 28 are aligned with the coil terminals 271 , 272.
  • the die comprising the thin film circuit 18 may then be laminated to the foil 20 comprising the coil 28.
  • a pressure sensitive electrically conductive glue 50 i.e. a glue that is permanently and anisotropically electrically conductive in the direction of an applied pressure, is provided on the thin film circuit die at the side of the thin film circuit 18, or on the foil 20 comprising the coil 28 at a location where the thin film circuit die is to be attached, or on both the thin film circuit die and the foil comprising the coil (Fig. 6(a)).
  • an anistropically electrically conductive electrically conducts in the direction in which pressure is exerted; in the other direction(s) it behaves as an electrical insulator.
  • the applied electrically conductive glue 50 electrically conducts in the upright direction, i.e. the direction in which contact is to be made between the coil terminals and the contact pads, and electrically insulates in the plane of the coil, i.e. provides an electrical insulating layer between the windings of the coil.
  • Materials known in the art with the appropriate properties are for example CN8205-EJD (Al
  • the thin film circuit die and the coil foil are then brought into contact (Fig. 6(b)) and a pressure cycle may be applied for attaching the thin film circuit die to the coil foil while electrical contacts are provided between the pads 171 and 271 and between the pads 172 and 272.
  • a heat cycle may be applied.
  • the windings 26 of the coil 28 remain electrically insulated from the remainder of the thin-film circuit 18 because the encapsulation layer 40, only opened at the location of the contact pads 171 ,
  • the integrated circuit 18 and the windings 26 of the coil 28 are electrically insulated by a bridging part 40a of the encapsulation layer 40 separating the first and the second contact pads and provided on a second side of the integrated circuit.
  • the windings 26 of the coil 28 and the terminals 271 , 272 are electrically insulated from each other because the glue 50 is not electrically conductive in a lateral direction, i.e. in a direction parallel to the substrate 20.
  • an electrically conductive paste or glue 51 such as for example a conductive paste, e.g. silver paste, silver conductive epoxy, metal nanoparticle ink, may be provided on the contact pads 171 , 172 while an electrically insulating glue 52 is applied over at least part of the remainder of the thin-film circuit 18.
  • Methods that may be used for applying the glues may comprise dispensing, printing, screen printing, inkjet printing and other methods known by a person skilled in the art. Lamination of both foils, i.e. the integrated circuit foil or die and the coil foil, is then performed by pressing them together, e.g with a laminator.
  • the process may include an anneal step, for example during 1 s to 100 s, in air or nitrogen, e.g. at a temperature in the range between 5O 0 C and 15O 0 C.
  • the thin film circuit die is physically attached to the coil foil while electrical contacts are provided between the pads 171 and 271 and between the pads 172 and 272.
  • the windings 26 of the 28 coil remain electrically insulated from the remainder of the thin-film circuit 18 on the circuit foil because the encapsulation layer 40, only opened at the location of the contact pads 171 , 172 provides an electrical insulation and because a conductive glue is applied only to the contact pads.
  • FIG. 6 (b) shows the result of a process, e.g. a lamination process, wherein the organic circuit contact pads 171 , 172 are electrically connected to the coil terminals 271 , 272, and wherein the organic circuit 18 bridges the coil windings 26.
  • the encapsulation layer 40, and more in particularly the bridging part 40a of the encapsulation layer 40, of the organic circuit 18 provides an electrical insulation between the coil windings 26 and the integrated circuit 18.
  • an array (one-dimensional or two-dimensional) of thin film circuits 18 on pieces of foil 10 or dies are arranged on an intermediate carrier 60.
  • the distances in both X and Y directions between the circuits 18 on the intermediate carrier 60 are selected to match the distances in both X and Y directions between coils 28 on a second foil 20.
  • a process of applying one or several types of glue and providing electrical connections between contact pads on the thin film circuit die and contact pads of the coil can then be performed as described above for the embodiments of the first method.
  • the lamination process can be applied to the array of circuit foils or dies and to the array of coils 28 simultaneously.
  • the intermediate carrier 60 may either remain attached to the thin film circuit foil 10, or it may be removed, and it may be re-used. In the latter case, the intermediate carrier 60 is a temporary carrier.
  • a die of a thin film circuit foil is placed with its first substrate 10 facing the coil terminals 271 , 272.
  • the thin film circuit die is oriented with respect to the coil foil such that the surface of the thin film circuit die opposite to the surface on which the thin film circuit 18 is provided faces the surface of the coil foil on which the coil 28 is provided.
  • Glue can be applied to the substrate 10 of the circuit foil, or to the coil foil at a location corresponding to the place where the circuit foil will be attached, or to both.
  • Lamination or gluing of the thin film circuit foil is performed over the windings 26 of the coil 28, such that the substrate side of the thin film circuit foil (i.e.
  • the side of the thin film circuit foil opposite to the side where the thin film circuit 18 is provided is attached to the coil foil, thereby bridging the windings 26 of the coil.
  • the distance between the outer edges of the coil terminals 271 , 272 is preferably chosen such that it is larger than the lateral size of the die that is attached to the coil foil.
  • the electrical connection can be made with a film of conductive material 53 that is sufficiently thick so as to run over the side of the thin film circuit foil (as illustrated in Fig. 8), the foil having a typical thickness of 25 micron to 200 micron.
  • conductive paste Materials known in the state of the art to be applicable as conductive paste are for example silver paste and conductive inks including particles.
  • a layer of insulating material 52 provides an electrical insulation between the coil windings 26 and the first substrate 10. This third method may also be applied to an array of dies, as shown in
  • FIG. 9 An array (one-dimensional or two-dimensional) of thin film circuit dies are arranged on an intermediate carrier 60, which can be a temporary carrier. The distances in both X and Y directions between the thin film circuits 18 on the temporary carrier 60 are selected to match the distances in both X and Y directions between coils 28 on a second foil 20. A process is then performed of applying a glue or a paste on the substrate side of the thin film circuit dies or on the coil foil at locations where the thin film circuit dies are to be attached or on both, as described above. The lamination or gluing process can be applied to an array of thin film circuit dies and to an array of coil foils simultaneously.
  • the intermediate carrier 60 is removed, and possibly re-used. Patterns of conductive paste or glue 53 are applied to provide electrical contacts between parts of the coil terminals 271 , 272 that remained uncovered after gluing of the dies on the coil foil, and corresponding contact pads 171 , 172 on the thin film circuit dies.

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Abstract

An RFID device comprises an integrated circuit comprising a first and second contact pad and an inductive coil comprising a plurality of windings. The integrated circuit is attached directly on top of the first and second coil terminals. An outer surface of the integrated circuit comprises an electrically insulating layer providing electrical insulation between the integrated circuit and the plurality of windings.

Description

RFID device
The present invention relates to an RFID device comprising an integrated circuit connected with a first side on a first substrate for producing an RFID code and an antenna connected to the integrated circuit for transmitting the RFID code, the antenna comprising an inductive coil on a top surface of a second substrate, the inductive coil comprising a plurality of windings, a first coil terminal located at an inner side of the plurality of windings and a second coil terminal located at an outer side of the plurality of windings, the integrated circuit comprising an electrically insulating outer surface which exposes a first contact pad and a second contact pad via which the integrated circuit is electrically connected to the first and second coil terminals.
A typical RFID tag comprises an antenna and an integrated circuit electrically connected to the antenna. The RFID antenna may be an inductive antenna, which can comprise a capacitor and a coil. The capacitor of the antenna can be part of the integrated circuit. The coil of the antenna typically comprises a plurality of windings and two coil terminals or contact pads located on a distance from each other. In fact, a first coil terminal or contact pad is located at an inner side of the plurality of windings and a second coil terminal or contact pad is located at an outer side of the plurality of windings. Both coil terminals need to be electrically connected to the integrated circuit.
The integrated circuit is usually located at the inner side of the coil windings. Therefore, there is a need for providing an electrical connection between the second coil terminal located at the outer side of the windings and a third terminal or pad located at the inner side of the windings, across the plurality of coil windings. This electrical connection bridges the windings of the coil, i.e. it forms a bridge between the inner side of the plurality of windings and the outer side of the plurality of windings, and it is electrically isolated from the windings. By placing the integrated circuit at the inner side of the coil windings and by providing an electrical connection between electrical pads of the integrated circuit and the first and third contact pad respectively, the electrical pads on the integrated circuit can be electrically connected to the coil terminals of the antenna of the RFID tag. The integrated circuit can for example comprise a capacitor, a rectifier, a digital block and/or a modulator. In case of an active tag a battery is present to provide power to the integrated circuit. The capacitor on the integrated circuit forms, together with the coil, an antenna as a resonant LC tank at an RF carrier frequency. The digital block can for example comprise a clock generator and a memory that can for example be a read-only memory (e.g. hard-wired, write-once-read-many) or an electrically programmable memory. The digital block can further comprise a circuit to read out the memory. Data can be modulated by the modulator and a modulated signal can be sent back to a reader via the antenna.
Different methods are known for bridging the coil windings. One solution comprises providing the windings of the coil on one side of a substrate, forming vias with electrical connections through the substrate and providing metal contacts at the second side of the substrate. The integrated circuit is then connected to the metal contacts at the second side of the substrate. This method requires forming metal patterns at both sides of the substrate. Therefore alignment between the two sides is crucial.
Another method, e.g. as described in US 6,693,541 comprises providing a separate electrical conductor to form a bridge over de plurality of windings (at the same side of the substrate as the windings), with a dielectric material between the separate electrical conductor and the coil windings.
Another possible solution is described in US 6,549,176, wherein a terminal of the coil bridges the windings of the coil and is separated from the windings by a non-conductive insulator. In US 7,224,280 a method is described wherein an interposer is provided in between the coil and the integrated circuit, the interposer comprising interposer leads electrically connected to the integrated circuit and to the coil, and an interposer substrate preventing electrical contact between the interposer leads and the coil. However, the required manufacturing steps for these prior art solutions are relatively complex and costly.
Currently, RFID integrated circuits are generally based on silicon integrated circuits. These silicon integrated circuits are relatively small and have tiny bonding pads. A technique known in the prior art for positioning a small integrated circuit accurately on a relatively large (e.g. credit card size) substrate (such as e.g. a substrate comprising RFID antenna coils) is known as "pick and place". This technique is relatively slow when the positioning precision needs to be high (e.g. because of the tiny bonding pads) while the substrate on which the chip is to be positioned is relatively large. Moreover, the tiny chip bonding pads may have a low reliability, e.g. due to stress, in particular on flexible substrates.
Thin film transistor technologies, such as e.g. technologies using amorphous silicon, carbon nanotubes, metal oxides, chalcogenides, Si precursors or organic semiconductors, provide options to realize flexible low- cost circuits such as e.g. RFID tags, fabricated with relatively cheap production methods on flexible substrates. The production methods can for example comprise methods for patterning features on a circuit that provide a relatively cheap alternative to optical lithography. Printing techniques such as imprint, nano-imprint, flexography, gravure, contact printing or inkjet printing may in the future allow patterning features at high throughput and good accuracy.
Thin-film circuits offer particular advantages when they are integrated into devices. Whereas silicon integrated circuits have tiny bonding pads, with sizes of 10 μm to 300 μm in lateral dimension, the bonding pads of thin film devices can be much larger, e.g. 0.1 to 10 mm in size, because the substrate area consumed by large pads represents only a minor cost. For silicon integrated circuits the bonding of circuits to a substrate and the creation of electrical connections between pads on a circuit and pads on a substrate is typically done by means of solder bumps or wire bonding. For thin-film circuits, bonding of circuits to a substrate and the creation of electrical connections can be obtained by lamination of a carrier comprising the active thin-film circuit to a substrate, wherein an electrically conductive adhesive can be used for forming electrical connections between pads of the thin-film circuit and pads on the substrate.
Research directed towards high frequency (13.56 MHz carrier wave frequency) organic or plastic RFID tags is one of the drivers for the field of organic electronics, because low-cost high-volume plastic RFID tags could replace barcodes in the future. In "An inductively-coupled 64b organic RFID tag operating at 13,56 Mhz with a data rate of 787 b/s", ISSCC 2008, K. Myny et al. reported an organic RFID tag, producing a hard-coded 64 bit data sequence, using an inductive antenna, at reading distances beyond 10 cm. Separate foils were provided for the antenna coil, a resonant capacitance, a rectifier and a transponder. Integration of these four foils was done on a PCB, using sockets for every foil.
In the field of organic electronics manufacturing, a lot of effort goes to the development of cheap printing processes. Using such printing processes for the realization of RFID tags or labels, the coil, the capacitors as well as the active elements of organic transistor based RFID tags may for example be realized in a fully additive roll-to-roll printing process. However, nowadays additive printing processes still have shortcomings in resolution and therefore in performance. It is a first aim of the present invention to provide an RFID device comprising an integrated circuit connected with a first side on a first substrate for producing an RFID code and an antenna connected to the integrated circuit for transmitting the RFID code, the antenna comprising an inductive coil on a top surface of a second substrate, the inductive coil comprising a plurality of windings, a first coil terminal located at an inner side of the plurality of windings and a second coil terminal located at an outer side of the plurality of windings, the integrated circuit comprising an electrically insulating outer surface which exposes a first contact pad and a second contact pad via which the integrated circuit is electrically connected to the first and second coil in a less complex way compared to prior art RFID devices.
The first aim is achieved according to the present invention with an RFID device showing the technical features of the characterizing part of the first claim. Thereto, the integrated circuit is attached directly on top of the first and second coil terminals and an electrically insulating layer present at an outer surface of the integrated circuit is used for providing an electrical insulation between the integrated circuit and the plurality of coil windings. With the term 'the integrated circuit is attached directly on top of the terminals' as used herein is meant that the integrated circuit, i.e. the integrated circuit with the electrically insulating outer surface, is in direct contact with the terminals or only separated with an adhesion layer from the terminals. In embodiments of the present invention the first substrate or an encapsulation layer encapsulating the integrated circuit can be used as an insulating layer providing electrical insulation between the integrated circuit and the plurality of coil windings. When using the encapsulation layer as an insulating layer, the distance between the first coil terminal and the second coil terminal and the distance between the first contact pad and the second contact pad is chosen such that the first and the second contact pads respectively at least partially overlap with the first and the second coil terminals to provide the electrical connection.
As a result, the integrated circuit of the RFID device according to the present invention can be used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the integrated circuit. By using the integrated circuit to bridge the coil windings, the need for additional processes for bridging the windings can be avoided.
It is a second aim of the invention to provide a method for electrically connecting contact pads of an integrated circuit with terminals of an inductive coil comprising a plurality of windings, wherein the method is less complex than prior art methods, wherein the method can be performed at a lower cost than prior art methods and wherein a good performance and a good reliability can be obtained.
The second aim is achieved according to the present invention with a method showing the technical features of the characterizing part of the eighth claim.
Thereto, the method comprises the steps of: (a) providing the integrated circuit; (b) encapsulating the integrated circuit to obtain an electrically insulating outer surface which exposes the first contact pad and the second contact pad
(c) providing a second substrate comprising the inductive coil; (d) laminating the integrated circuit and the second substrate such that an electrically insulating layer of the outer surface of the integrated circuit provides electrical insulation between the integrated circuit and the plurality of windings;
(e) electrically connecting the first contact pad to the first coil terminal and the second contact pad to the second coil terminal.
The method according to the present invention further has the advantage that the integrated circuit itself, i.e. an insulating layer present at an outer surface of the integrated circuit, can be used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the integrated circuit. As a result the need for additional processes for bridging the windings can be avoided.
The process for manufacturing the integrated circuit typically requires patterning steps allowing smaller dimensions as compared to the patterning steps needed for manufacturing the coil. By processing the integrated circuit and the coil on separate substrates with different processes and by selecting optimum processes, a good performance of the integrated circuit can be obtained.
Preferably, the integrated circuit is formed on a first substrate, which may be used as a bridging part for bridging the coil windings. Typically, a plurality of integrated circuits is formed on a single first substrate. The integrated circuit are preferably thin film circuits, formed by thin film deposition techniques. After forming the plurality of thin film circuits, the first substrate comprising the thin film circuits is cut into dies, each die comprising at least one integrated circuit. Such a die is subsequently laminated to the coil substrate, thereby aligning contact pads of the thin film circuit on the die with contact pads or terminals of the coil, wherein the contact pads of the coil are located at opposite sides of the coil windings. Thereby the die comprising the thin film circuit is used as a bridge over the coil windings, without causing short-circuits between the windings or between the windings and the thin film circuit. It is an advantage of the present invention that the die comprising the thin film circuit is used to bridge the coil windings, such that the need for additional processes for bridging the windings can be avoided. During or after the lamination step, electrically conductive paths are created between predetermined pads on the thin film circuit and the terminals or contact pads of the coil. It is an advantage of the present invention that the materials used to ensure the electrical connection between pads of the thin film circuit and pads of the coil can be applied by dispensing techniques rather than by solder techniques or wire bonding. In preferred embodiments a single lamination step may be used for attaching the die comprising the thin film circuit to the coil substrate and forming electrical connections.
Electrically connecting the first contact pad to the first terminal and the second contact pad to the second terminal preferably comprises the steps of (i) aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal; (ii) laminating the first substrate and the second substrate; (iii) and forming an electrical connection between the first contact pad and the first terminal and between the second contact pad and the second terminal. The step of laminating the first substrate and the second substrate and the step of forming an electrical connection between the first contact pad and the first terminal and between the second contact pad and the second terminal can be a single step or it can be separate steps.
In embodiments of the present invention, aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal may comprise orienting the first substrate and the second substrate such that a surface of the first substrate on which the integrated circuit is provided faces a surface of the second substrate on which the coil is provided. Laminating the first substrate and the second substrate can comprise providing an electrically conductive material in between the integrated circuit on the first substrate and the inductive coil on the second substrate. The electrically conductive material can be an anisotropically conductive material that is electrically conductive in a direction substantially perpendicular to a surface of the first substrate. Laminating the first substrate and the second substrate may further comprise providing an electrically insulating material in between the integrated circuit on the first substrate and the inductive coil on the second substrate at locations separated from the first contact pad, the second contact pad, the first terminal and the second terminal.
In embodiments of the present invention, aligning the first contact pad to the first terminal and aligning the second contact pad to the second terminal may comprise orienting the first substrate and the second substrate such that a surface of the first substrate opposite to the surface on which the integrated circuit is provided faces a surface of the second substrate on which the coil is provided.
In a preferred embodiment of the device and/or method according to the invention the layer of insulating material forms part of a dielectric layer encapsulating the integrated circuit, as a result of which the manufacturing process can be simplified. In another preferred embodiment of the device and/or method according to the invention the first substrate may provide an electrical insulation between the integrated circuit and the plurality of windings of the coil.
In a preferred embodiment of the device and/or method according to the invention, the contact pads of the integrated circuit and the contact terminals of the coil are relatively large, e.g. they have a lateral size in the range between 0.1 mm and 10 mm. It is an advantage of such relatively large contact pads and terminals that the process of placing the die over the coil windings and the process of aligning contact pads of the integrated circuit with contact terminals of the coil can be a faster process as compared to prior art processes, because the alignment precision that is required is less stringent (typically 0.1 to 10 mm). It is a further advantage of such relatively large contact pads and contact terminals that a good reliability of the electrical connections can be obtained, in particular in combination with flexible substrates.
The first substrate for the thin film circuit and the second substrate for the coil as used in the device and/or method according to the present invention can be any kind of substrate considered suitable by the person skilled in the art. At least one of the first and second substrate may for instance be flexible substrates, such as for example a flexible foil or paper. The process flows for manufacturing the coil and the integrated circuit are preferably based on thin film deposition techniques, allowing relatively cheap manufacturing steps. Such a thin film integrated circuit may for instance be an organic circuit.
The invention is further elucidated in figures 1-9.
Figure 1 gives a schematic overview of a prior art inductive organic RFID device. Figure 2 illustrates different organic thin film transistor configurations that may be used in the context of the present invention: (a) bottom-gate bottom-source-drain structure; (b) top-gate bottom-source-drain structure; (c) bottom-gate top-source-drain structure; (d) top-gate top-source-drain structure. Figure 3 shows an organic circuit foil with two large contact pads.
Figure 4 shows an inductive coil on a foil.
Figure 5 illustrates a process flow for fabricating an organic circuit foil.
Figure 6 illustrates a method for laminating an organic circuit foil or die to a foil comprising a coil, according to the present invention. Figure 7 illustrates a method for laminating a plurality of organic circuit foils or dies to a foil comprising a plurality of coils, according to the present invention.
Figure 8 illustrates a method for laminating an organic circuit foil or die to a foil comprising a coil, according to the present invention. Figure 9 illustrates a method for laminating a plurality of organic circuit foils or dies to a foil comprising a plurality of coils, according to the present invention.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention and how it may be practiced in particular embodiments. However it will be understood that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present invention. While the present invention will be described with respect to particular embodiments and with reference to certain drawings, the reference is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the invention. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes.
Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
In the context of the present invention, the term "foil" is used to refer to a substrate on which thin film technologies are applied. A foil can for example comprise glass, plastic, paper, metal, oxides, or laminates. It can comprise a stack of layers of different types, including for example barrier layers against permeation of moist or oxygen, adhesive layers or planarization layers. The term "foil" can refer to a rigid substrate or to a flexible substrate. The term "thin film circuit foil" is used to indicate a foil comprising a thin film circuit. The term "coil foil" is used to indicate a foil comprising an inductive coil.
The present invention provides a method for electrically connecting contact pads of an integrated circuit with terminals of an inductive coil comprising a plurality of windings, wherein the integrated circuit is used as a bridge over the windings without causing short-circuits between the windings or between the integrated circuit and the windings. The method of the present invention is less complex than prior art methods, can be performed at a lower cost than prior art methods and allows obtaining a good performance and a good reliability of the resulting device, especially on flexible substrates. More in particular, the present invention provides a method for electrically connecting contact pads of a circuit comprising thin film transistors (a thin film circuit) with at least two terminals of a coil comprising a plurality of windings on a substrate, at least two terminals of the coil being located at opposite sides of the plurality of windings. As opposed to prior art solutions, there is no need for providing a separate bridge e.g. comprising an electrical conductor and a dielectric material to bridge the windings of the antenna. Instead, a layer of the integrated circuit, e.g. thin film circuit, is used as insulating layer and the integrated circuit, e.g. thin film circuit, is used as a bridge over the windings of the coil.
In a first preferred embodiment of the invention, electrical insulation between the thin film circuit and the plurality of coil windings is formed by the first substrate of the integrated circuit. In a second preferred embodiment, the electrical insulation is formed by a dielectric layer covering the integrated circuit, e.g. an encapsulation layer. The second embodiment has the advantage that the electrical contact pads are formed during lamination and no further steps are needed afterwards.
Preferably, large contact pads are used on the integrated circuit, such that the need for accurate alignment can be avoided. This may lead to a cheaper process, a shorter process time and a better reliability, especially on flexible substrates. As a result, the method of the present invention allows manufacturing thin film transistor circuits, such as e.g. RFID tag circuits, on flexible substrates that are more reliable than prior circuits, e.g. RFID tag circuits, because of the larger contact pads that can be used. The present invention is further described for organic thin film transistor circuits. However, the methods according to the present invention can also be used for other types of thin film transistor circuits, such as for example circuits based on amorphous silicon, carbon nanotubes, metal oxides, chalcogenides, Si precursors, etc. The present invention is further described with an RFID tag circuit as a thin film transistor circuit. However, the present invention can also be used for other types of circuits, such as for example thin-film circuits that comprise a function of communication at a HF frequency with a base station and that can furthermore comprise functions such as a memory, display, sensor or actuator. Fig. 1 shows the schematic outline of a prior art inductive organic RFID tag that may for example be fabricated on a flexible substrate, such as a flexible foil (e.g. PEN, PET, polyimide, metal foil, paper). The RFID tag comprises a coil with inductance L on a foil, and one or more other foils comprising a resonant capacitance C and a transponder circuit. The resonant capacitance and the coil form together a resonant HF antenna. The transponder circuit is manufactured with thin-film transistor technologies and may comprise a rectifier. It may also comprise a memory, such as for example a read-only memory or a write-once-read-many (WORM) memory or a reprogrammable memory, e.g. an electrically reprogrammable memory. Fig. 1 also shows a reader for reading data code that is stored in a memory of the transponder circuit. The prior art inductive organic RFID tag comprises four integrated foils, as indicated with dotted lines in Fig. 1 : a foil comprising the coil of the antenna, a foil comprising a resonant capacitance, a foil comprising a rectifier fabricated using thin-film technologies and a foil comprising a transponder circuit fabricated using thin-film technologies. The RFID system may for example be suitable for operating at a base carrier frequency of 13.56 MHz. The resonant capacitor is designed for matching the resonance frequency of the LC antenna at 13.56 MHz. This LC-antenna detects the signal transmitted by the reader and energizes the organic rectifier with an AC-voltage at 13.56 MHz. From this voltage the rectifier generates a DC supply voltage for the organic transponder circuit, which drives the modulation transistor between the on and off state with a code sequence. Fig. 1 depicts a general overview of the subsequent foils of an inductively-coupled RFID tag, wherein load modulation is done at the output of the rectifier (DC load modulation), which is preferable in organic RFID tags because it does not require that the load transistor operates at the HF frequency. However, modulation directly on the antenna (AC load modulation) is also possible. In embodiments of the present invention, a thin film circuit comprising a resonant capacitance module, a rectifier module and a thin-film transponder module may be realized on one foil, i.e. a first substrate, and a coil of the LC antenna comprising a plurality of windings and two terminals may be formed on a separate foil, i.e. on a second substrate. Both foils may then be laminated to each other, whereby electrical connections are made between contact pads on the organic thin film circuit and the coil terminals.
In embodiments of the present invention, a typical size of a foil comprising a thin film circuit is e.g. about 1 cm to 4 cm by 0.2 cm to 2 cm. The foil may have a thickness in the range between 25 μm and 500 μm and may comprise for example a plastic foil (e.g. PEN, PET, Polyimide), a metal foil (e.g. Al, Cu), paper, laminates or stacks.
The thin film capacitors formed on the thin film circuit foil comprise two conductive layers separated by a dielectric layer. The conductive layers of the thin film capacitors may for example comprise Cu, Al, Au, Ag, ITO, ZnO, Ag-ink, or a carbon-nanotube ink, with a thickness in the range between 10 nm and 10 μm. The dielectric layer in between both conductive layers of the thin film capacitors may comprise for example an organic dielectric material such as e.g. polystyrene, poly-4-venylphenol (PVP), benzcocyclobutene
(BCB), polyimide or parylene. The dielectric layer in between the conductive layers of the thin film capacitors may comprise an inorganic dielectric material such as e.g. SiO2, Ta2O5, BZT (barium zirconate titanate), AI2O3, YOx or SiN4. The thickness of the dielectric layer may be in the range between 10 nm and 10 μm.
Thin film diodes may be provided on the thin film circuit foil, e.g. diodes that are part of a rectifier. The diodes may comprise a thin film semiconductor layer such as e.g. pentacene, polythiophene, Cu-pthalocyanine, C60, thin film semiconductor oxides such as ZnO, thin film semiconductor sulfides or selenides, amorphous Si, or carbon nanotubes, sandwiched in between a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer having a different workfunction. For example, a first conductive layer may comprise electrodes with high (5eV to 6eV and more) to medium (4eV to 5eV) workfunction such as e.g. Au, conductive oxides such as Indium Tin Oxide (ITO), Pt, Pd, Ag, Ag-ink, Cu. A second conductive layer my comprise electrodes with a medium (4 eV to 5 eV) to low (less than 3 eV to 4 eV) workfunction such as Al, Ti, conductive oxides such as e.g. TiOx, ZnO, Aluminum-doped ZnO (AZO), Ag, Cu.
Thin film transistors on the thin film circuit foil 10 may be realized in different configurations, as illustrated in Figure 2. The source contacts 12, the drain contacts 13 as well as the gate contacts 1 1 and the electrically conductive filling 16 (e.g. metal filling) of the via holes through the dielectric layer 14 may comprise either the same or different conductive layers (such as e.g. Cu, Al, Au, Ag, ITO, ZnO, Ag-ink, carbon-nanotube ink) with a thickness in the range between 10 nm to 10 μm and with lateral dimensions of the source and drain contacts in the range between 100 nm and 100 μm, preferably between 500 nm and 10 μm. Vias are provided for electrically connecting different layers of thin film transistors of the thin film circuit. The gate dielectric layer 14 may comprise either an organic dielectric material (for example a polymer such as e.g. polystyrene, poly-4-venylphenol (PVP), benzcocyclobutene (BCB), polyimide, parylene, PVDF polymers and copolymers, or for example small molecules) or an inorganic dielectric material (such as e.g. SiO2, Ta2O5, BZT (barium zirconate titanate), AI2O3, YOx or SiN4) with a thickness in the range between 10 nm and 10 μm. The thin film semiconductor layer 15 in contact with the source 12 and drain 13 may for example comprise pentacene, polythiophene, Cu-pthalocyanine, C60, ZnO, amorphous Si, or carbon nanotubes and may have a thickness in the range between 5 nm and 5 μm.
Figure 3 shows a first substrate 10, e.g. a thin film circuit foil, comprising an integrated circuit 18, e.g. a thin film circuit, with a first 171 and a second 172 contact pad provided on a first predetermined distance from each other, to be used in an RFID device according to the present invention or in a method according to the invention for electrically connecting to the coil terminals of an inductive coil.
The contact pads 171 , 172 are preferably relatively large having a size in the range between 100 μm x 100 μm to 10 mm x 10 mm, more preferably in the range between 200 μm x 200 μm and 3 mm x 3 mm, as e.g. illustrated in Figure 3, such that alignment of the contact pads with the coil terminals is simplified.
Figure 4 shows an inductive coil 28 to be used in an RFID device according to the present invention or in a method according to the invention for electrically connecting to the contact pads of an integrated circuit. The inductive coil 28 comprises a plurality of windings, a first coil terminal 271 provided at an inner side of the coil and a second coil terminal 272 provided at an outer side of the coil. The first and the second coil terminal 271 , 272 are provided at a second predetermined distance from each other. The contact pads 171 , 172 shown in figure 3 are provided for being electrically connected to the two coil terminals 271 , 272 of the coil 28 that is provided on a second surface of a second substrate 20, e.g. a separate foil as is illustrated in Figure 4. The contact pads 171 , 172 of the integrated circuit can comprise the same conductive material as the electrically conductive filling 16 of the via holes 16 of Figure 2 through the gate dielectric 14 of the thin film circuit 18, such as for example Al, Cu or Au, or they can comprise a different conductive material. The size of the contact pads 271 , 272 of the coil 28 and the contact pads 171 , 172 of the thin film circuit 18 may be the same or be different.
In a preferred embodiment of the invention, the first contact pad 171 and the second contact pad 172 of the thin film circuit 18 are respectively electrically connected to a first and a second terminal of a capacitor on the thin film circuit 18. By electrically connecting the first contact pad 171
(connected to the first capacitor terminal) with the first coil terminal 271 and electrically connecting the second contact pad 172 (connected to the second capacitor terminal) with the second coil terminal 272, an LC circuit, e.g. an LC resonant antenna, can be obtained. The coil foil 20, i.e. the second substrate, for an RFID device working at 13.56 MHz has commonly a smart card format (4.8 cm x 7.6 cm) with two to ten windings 26 of a metal such as for example copper or silver and with two coil terminals or contact pads 271 , 272, a first one (271 ) being located at the inner side of the coil windings 26 and the second one (272) being located at the outer side of the coil windings 26 as for example illustrated in Figure 4.
However, any size of the substrate and/or any number of windings of the coil can be chosen as considered suitable by the person skilled in the art. The coil terminals 271 , 272 preferably comprise the same material as the coil windings 26, such as for example Cu or Ag, but may also be chosen differently. The thickness of the metal layer forming the coil windings 26 and the coil terminals
271 , 272 is typically in the range between 10 μm and 100 μm to allow achieving a low resistance (e.g. in the range between 0.5 Ohm and 5 Ohm) and therefore a high quality factor. The coil foil 20, i.e. the second substrate, is commonly a PET foil, but other materials, preferably flexible materials, such as e.g. PEN, PET, polyimide or paper may be used.
The production process of the coil 28 on the foil 20 may for example comprise a roll-to-roll process, e.g. based on etching of Cu that has been sputtered on the foil or e.g. based on screen printing of an electrically conductive ink, such as for example a silver ink. Other production processes known by a person skilled in the art may be used.
Methods that may be used for depositing the thin films in the context of the present invention comprise process steps performed in vacuum (e.g. evaporation, sputtering, laser ablation, Chemical Vapour Deposition, ion-beam sputtering, organic vapour phase deposition) and process steps performed at near-ambient pressure (e.g. spin-coating, spray-coating, printing, lamination).
Processing at near-ambient pressure may include steps that are performed in a controlled environment, e.g. in an environment with controlled oxygen, water vapour or ozone concentration. The patterning steps may be based on additive processes (such as e.g. direct printing, deposition through a shadow mask) as well as subtractive processes whereby a pattern is obtained by removing parts of a layer that is deposited e.g. over a complete substrate. Subtractive processes may for example be based on etching, laser ablation or lift-off techniques.
Figure 5 shows a possible process flow for fabricating a thin film circuit 18, i.e. an integrated circuit, on a thin film circuit foil 10, i.e. on a first substrate, wherein the thin-film semiconductor is an organic semiconductor 15 such as e.g. pentacene. The foil 10, e.g. PEN foil, on which the thin film circuit 18 is to be formed may first be laminated to a rigid carrier 30 such as for example glass or a silicon wafer (Fig. 5(a)). On the surface of the foil 10 a planarization layer 31 may be provided, e.g. by spin coating a resist layer (e.g. SU8), e.g. with a thickness in the order of 2 μm, to smoothen out roughness spikes (Fig. 5(b)). Other materials and methods known by a person skilled in the art may be used for providing the planarization layer 31. On top of the planarization layer 31 a first thin metal layer 32 may be provided, e.g. by sputtering a 30 nm thin Al layer. The first thin metal layer 32 may be patterned, for example by means of photolithography and etching (Fig. 5(c)). Other materials and methods known by a person skilled in the art may be used for forming and patterning the first thin metal layer 32. This layer 32 can form the gate metal layer 1 1. It can also be part of an electrode layer for a diode on the thin film circuit 18. It can also be an electrode layer for a capacitor on the thin film circuit 18. In a next step (illustrated in Fig. 5(d)) a dielectric layer 33, such as e.g. a 200 nm thick layer comprising paryelene N, may be provided. This dielectric layer 33 can be the gate dielectric 14. It can also be the dielectric layer of a capacitor of the thin-film circuit 18, more in particular the capacitor for the LC resonant antenna. Via holes may then be formed through the dielectric layer 33, for example based on photolithography and dry etching. The holes may be filled with a conductive material, e.g. metal 34, such as for example 200 nm of Al (as illustrated in Fig. 5(e)). These via holes filled with metal 34 are provided to enable electrical connections, for example between the gate 1 1 of a transistor on the thin film circuit 18 and the source 12 or drain 13 of another transistor on the thin film circuit 18. After forming and filling the vias a second thin metal layer 35 may be provided, e.g. by sputtering a 30 nm thin Au layer. This second thin metal layer 35 may be patterned, for example based on photolithography and etching (Fig. 5(f)). Other materials and methods known by a person skilled in the art may be used for forming and patterning the second thin metal layer 35. The second thin metal layer 35 may for example be used for forming the source 12 and drain 13 of a transistor. The patterned layer 35 can also form an electrical connection between transistors, or it can be used as an electrode for a diode.
The second thin metal layer 35 can make contact with metal 34 in via holes at predetermined locations on the thin film circuit 18. This is illustrated in Fig.
5(f). Figure 5(g) illustrates a next step, wherein a thick patterned dielectric layer 36 is provided. This thick dielectric layer 36 may for example comprise a 4 μm thick SU8 resist layer. Other suitable materials known by a person skilled in the art may be used. The thick patterned dielectric layer 36 can for example have the function of an integrated shadow mask to achieve patterning of a thin film semiconductor layer (to be provided in a subsequent step), in order to reduce leakage current paths between adjacent transistors. The thick patterned dielectric layer 36 can also create a 'box' in which a semiconductor layer can be printed in a subsequent step. As shown in Fig. 5(h), a first organic semiconductor layer 37 can for example be provided at a predetermined location by e.g. evaporating a 200 nm thick pentacene layer, e.g. for forming diodes. Other materials and methods known by a person skilled in the art may be used for providing the first organic semiconductor layer 37. This step may be followed by the deposition of a third metal layer 38, e.g. comprising 100 nm of Al, for forming an electrode of a diode. Next a second organic semiconductor layer 39 may be provided, e.g. comprising 50 nm of pentacene, for forming transistors (Fig. 5(i)). Other materials and methods known by a person skilled in the art may be used for providing the second organic semiconductor layer 39. This second organic semiconductor layer 39 can be provided on the transistor structures through openings in the integrated shadow mask formed by the thick patterned dielectric layer 36. In an alternative embodiment an organic semiconductor layer 39 may for example be provided by inkjet printing in openings of the integrated shadow mask formed by the thick patterned dielectric layer 36. Next the circuit may be encapsulated (Fig. 5(j)), e.g. by deposition of a 2 μm to 20 μm thick layer 40 of parylene. On the parylene layer 40 a silicon nitride layer 41 , e.g. with a thickness of 100 nm to 2μm, may be sputtered. This silicon nitride layer 41 may act as a barrier layer, e.g. an oxygen barrier or a moist barrier. Also stacks comprising a plurality of layers of organic and inorganic materials can be used for forming an encapsulation layer.
Next at least two contact pads 171 , 172 may be formed, e.g. at an edge of the thin film circuit 18, the contact pads 171 , 172 being electrically connected to a first terminal and a second terminal of a capacitor on the integrated circuit 18, e.g. to realize an LC antenna. The formation of the contact pads 171 , 172 may for example be based on photolithography and dry etching through the encapsulation layer. Other methods known by a person skilled in the art may be used. The foil 10 may then be removed (delaminated) from the carrier 30, for example by peal-off. The foil 10 is then cut into dies that are subsequently laminated to a foil 20, i.e. a second substrate, comprising an antenna coil 28 (see e.g. Fig. 6, 7, 8, 9). Several methods may be used to connect the foil 10 comprising the thin film circuit 18 to the foil 20 comprising the coil 28 with multiple windings 26, thereby providing an electrical contact between a first contact pad 171 on the thin film circuit foil and a first contact terminal 271 on the coil foil and between a second contact pad 172 on the thin film circuit foil and a second contact terminal 272 on the coil foil.
In a first method, illustrated in Fig. 6, a die, i.e. a first substrate, comprising a thin film circuit 18, i.e. an integrated circuit, is cut from the wafer or roll on which it has been fabricated, and it is placed with its contact pads 171 , 172 face-to-face with the terminal pads 271 , 272 of the coil 28. In other words, the thin film circuit die is oriented with respect to the coil foil such that the first surface of the thin film circuit die on which the thin film circuit 18 is provided faces the second surface of the coil foil on which the coil 28 is provided. This is illustrated in Fig. 6(a). The contact pads 171 , 172 that are provided for making an electrical contact with the coil 28 are aligned with the coil terminals 271 , 272. The die comprising the thin film circuit 18 may then be laminated to the foil 20 comprising the coil 28. For example, a pressure sensitive electrically conductive glue 50, i.e. a glue that is permanently and anisotropically electrically conductive in the direction of an applied pressure, is provided on the thin film circuit die at the side of the thin film circuit 18, or on the foil 20 comprising the coil 28 at a location where the thin film circuit die is to be attached, or on both the thin film circuit die and the foil comprising the coil (Fig. 6(a)). An anistropically electrically conductive electrically conducts in the direction in which pressure is exerted; in the other direction(s) it behaves as an electrical insulator. In figures 6(a) and 6(b) the applied electrically conductive glue 50 electrically conducts in the upright direction, i.e. the direction in which contact is to be made between the coil terminals and the contact pads, and electrically insulates in the plane of the coil, i.e. provides an electrical insulating layer between the windings of the coil. Materials known in the art with the appropriate properties are for example CN8205-EJD (Al
Technology Inc.) or materials as described in US 5,433,892. The thin film circuit die and the coil foil are then brought into contact (Fig. 6(b)) and a pressure cycle may be applied for attaching the thin film circuit die to the coil foil while electrical contacts are provided between the pads 171 and 271 and between the pads 172 and 272. In addition to the pressure cycle, also a heat cycle may be applied. The windings 26 of the coil 28 remain electrically insulated from the remainder of the thin-film circuit 18 because the encapsulation layer 40, only opened at the location of the contact pads 171 ,
172, provides an electrical insulation of the thin film circuit. In fact, the integrated circuit 18 and the windings 26 of the coil 28 are electrically insulated by a bridging part 40a of the encapsulation layer 40 separating the first and the second contact pads and provided on a second side of the integrated circuit. The windings 26 of the coil 28 and the terminals 271 , 272 are electrically insulated from each other because the glue 50 is not electrically conductive in a lateral direction, i.e. in a direction parallel to the substrate 20.
In an alternative embodiment, an electrically conductive paste or glue 51 , such as for example a conductive paste, e.g. silver paste, silver conductive epoxy, metal nanoparticle ink, may be provided on the contact pads 171 , 172 while an electrically insulating glue 52 is applied over at least part of the remainder of the thin-film circuit 18. Methods that may be used for applying the glues may comprise dispensing, printing, screen printing, inkjet printing and other methods known by a person skilled in the art. Lamination of both foils, i.e. the integrated circuit foil or die and the coil foil, is then performed by pressing them together, e.g with a laminator. The process may include an anneal step, for example during 1 s to 100 s, in air or nitrogen, e.g. at a temperature in the range between 5O0C and 15O0C. After lamination, the thin film circuit die is physically attached to the coil foil while electrical contacts are provided between the pads 171 and 271 and between the pads 172 and 272. Using this alternative embodiment, the windings 26 of the 28 coil remain electrically insulated from the remainder of the thin-film circuit 18 on the circuit foil because the encapsulation layer 40, only opened at the location of the contact pads 171 , 172 provides an electrical insulation and because a conductive glue is applied only to the contact pads. The windings 26 of the coil 28 and the terminals 271 , 272 are electrically insulated from each other because a conductive glue is applied only to the contact pads. Figure 6 (b) shows the result of a process, e.g. a lamination process, wherein the organic circuit contact pads 171 , 172 are electrically connected to the coil terminals 271 , 272, and wherein the organic circuit 18 bridges the coil windings 26. The encapsulation layer 40, and more in particularly the bridging part 40a of the encapsulation layer 40, of the organic circuit 18 provides an electrical insulation between the coil windings 26 and the integrated circuit 18.
Therefore, there is no need for providing a separate bridge comprising a dielectric material to cross the windings.
In a second method, illustrated in Fig. 7, an array (one-dimensional or two-dimensional) of thin film circuits 18 on pieces of foil 10 or dies are arranged on an intermediate carrier 60. The distances in both X and Y directions between the circuits 18 on the intermediate carrier 60 are selected to match the distances in both X and Y directions between coils 28 on a second foil 20. A process of applying one or several types of glue and providing electrical connections between contact pads on the thin film circuit die and contact pads of the coil can then be performed as described above for the embodiments of the first method. In this second method, illustrated in Fig. 7, the lamination process can be applied to the array of circuit foils or dies and to the array of coils 28 simultaneously. After lamination, the intermediate carrier 60 may either remain attached to the thin film circuit foil 10, or it may be removed, and it may be re-used. In the latter case, the intermediate carrier 60 is a temporary carrier.
In a third method, illustrated in Fig. 8, a die of a thin film circuit foil is placed with its first substrate 10 facing the coil terminals 271 , 272. In other words, the thin film circuit die is oriented with respect to the coil foil such that the surface of the thin film circuit die opposite to the surface on which the thin film circuit 18 is provided faces the surface of the coil foil on which the coil 28 is provided. Glue can be applied to the substrate 10 of the circuit foil, or to the coil foil at a location corresponding to the place where the circuit foil will be attached, or to both. Lamination or gluing of the thin film circuit foil is performed over the windings 26 of the coil 28, such that the substrate side of the thin film circuit foil (i.e. the side of the thin film circuit foil opposite to the side where the thin film circuit 18 is provided) is attached to the coil foil, thereby bridging the windings 26 of the coil. The distance between the outer edges of the coil terminals 271 , 272 is preferably chosen such that it is larger than the lateral size of the die that is attached to the coil foil. After laminating the thin film circuit die to the coil foil, an electrically conductive material, e.g. paste or glue 53, is applied for providing an electrical connection between the first pad 171 of the thin film circuit and the first coil terminal 271 and between the second pad 172 of the thin film circuit and the second coil terminal 272. The electrical connection can be made with a film of conductive material 53 that is sufficiently thick so as to run over the side of the thin film circuit foil (as illustrated in Fig. 8), the foil having a typical thickness of 25 micron to 200 micron. Materials known in the state of the art to be applicable as conductive paste are for example silver paste and conductive inks including particles. A layer of insulating material 52 provides an electrical insulation between the coil windings 26 and the first substrate 10. This third method may also be applied to an array of dies, as shown in
Fig. 9. An array (one-dimensional or two-dimensional) of thin film circuit dies are arranged on an intermediate carrier 60, which can be a temporary carrier. The distances in both X and Y directions between the thin film circuits 18 on the temporary carrier 60 are selected to match the distances in both X and Y directions between coils 28 on a second foil 20. A process is then performed of applying a glue or a paste on the substrate side of the thin film circuit dies or on the coil foil at locations where the thin film circuit dies are to be attached or on both, as described above. The lamination or gluing process can be applied to an array of thin film circuit dies and to an array of coil foils simultaneously. After lamination or gluing of the arrays, the intermediate carrier 60 is removed, and possibly re-used. Patterns of conductive paste or glue 53 are applied to provide electrical contacts between parts of the coil terminals 271 , 272 that remained uncovered after gluing of the dies on the coil foil, and corresponding contact pads 171 , 172 on the thin film circuit dies.

Claims

Claims
1. An RFID device comprising an integrated circuit (18) connected with a first side on a first substrate (10) for producing an RFID code and an antenna connected to the integrated circuit for transmitting the RFID code, the antenna comprising an inductive coil (28) on a top surface of a second substrate (20), the inductive coil (28) comprising a plurality of windings (26), a first coil terminal (271 ) located at an inner side of the plurality of windings and a second coil terminal (272) located at an outer side of the plurality of windings, the integrated circuit (18) comprising an electrically insulating outer surface (10, 40) which exposes a first contact pad (171 ) and a second contact pad (172) via which the integrated circuit (18) is electrically connected to the first and second coil terminals, characterised in that the integrated circuit (18) is attached directly on top of the second substrate (20) and in that an electrically insulating layer of the outer surface of the integrated circuit (18) provides electrical insulation between the integrated circuit (18) and the plurality of windings (26).
2. An RFID device according to claim 1 , characterised in that the electrically insulating layer (10, 40) comprises a bridging part (40a) formed by at least part of a dielectric layer (40) encapsulating the integrated circuit provided for separating the first (171 ) and second (172) contact pads and provided on a second side of the integrated circuit.
3. An RFID device according to claim 2, characterised in that the integrated circuit (18) is attached to the coil terminals (271 , 272) with the second side facing the top surface of the second substrate (20), the first (271 ) and the second (272) coil terminals being provided at a first distance from each other and the first (171 ) and the second (172) contact pads being provided at a second distance from each other, the first distance chosen to correspond to the second distance such that the first (171 ) and the second (172) contact pads respectively at least partially overlap with the first (271 ) and the second (272) coil terminals to provide the electrical connection.
4. An RFID device according to any one of claims 1-2, characterised in that the integrated circuit (18) is attached to the coil terminals (271 , 272) with the first side facing the top surface of the second substrate (20) and the contact pads (171 , 172) being electrically connected to the coil terminals (271 , 272) by means of a conductive material (53) provided along side parts of the electrically insulating outer surface.
5. An RFID device according to any one of claims 1-4, characterized in that the integrated circuit (18) is a thin film integrated circuit.
6. An RFID device according to any one of claims 1-5, characterized in that the first (171 ) and second (172) contact pads and the first (271 ) and second (272) coil terminals have lateral dimensions in the range between 0.1 mm and 10 mm.
7. An RFID device according to any one of claims 1-6, characterized in that at least one of the first substrate (10) and the second substrate (20) is a foil.
8. An RFID device according to any one of claims 1-7, characterized in that at least one of the first substrate (10) and the second substrate (20) is a flexible substrate.
9. An RFID device according to any one of claims 1-8, characterized in that the integrated circuit is an organic circuit.
10. A method for electrically connecting a first contact pad (171 ) of an integrated circuit (18) with a first coil terminal (271 ) of an inductive coil (28) and for electrically connecting a second contact pad (172) of the integrated circuit (18) with a second coil terminal (272) of the inductive coil (28), the inductive coil (28) comprising a plurality of windings (26), the first coil terminal (271 ) being located at an inner side of the plurality of windings and the second coil terminal (272) being located at an outer side of the plurality of windings, the method comprising the steps of:
(a) providing the integrated circuit (18);
(b) encapsulating the integrated circuit to obtain an electrically insulating outer surface which exposes the first contact pad (171 ) and the second contact pad (172);
(c) providing a second substrate (20) comprising the inductive coil (28);
(d) laminating the integrated circuit (18) and the second substrate (20) such that an electrically insulating layer (10, 40) of the outer surface of the integrated circuit provides electrical insulation between the integrated circuit and the plurality of windings;
(e) electrically connecting the first contact pad (171 ) to the first coil terminal (271 ) and the second contact pad (172) to the second coil terminal (272).
1 1. A method according to claim 10, characterized in that step (b) comprises the step of providing the integrated circuit on a first substrate (10) forming a first side of the outer surface.
12. A method according to any one of claims 10-1 1 , characterized in that step (b) comprises the step of providing a layer of electrically insulating material (40a) on a second side of the integrated circuit thereby electrically insulating the first and second contact pads from each other.
13. A method according to claim 12, characterized in that step (d) comprises the steps of: (i) aligning the first contact pad (171 ) to the first coil terminal (271 ) and aligning the second contact pad (172) to the second coil terminal (272) (ii) laminating the first (10) and the second (20) substrate; (iii) forming an electrical connection between the first contact pad (171 ) and the first terminal (271 ) and between the second contact pad (172) and the second coil terminal (272).
14. A method according to claim 13, characterized in that steps (ii) and (iii) are performed in one single step.
15. A method according to any one of claims 13-14, characterized in that step (i) comprises the step of orienting the first substrate (10) and the second substrate (20) such that a surface of the first substrate on which the integrated circuit is provided faces a surface of the second substrate (20) on which the coil is provided.
16. A method according to any one of claims 13-15, characterized in that step (ii) comprises the step of providing an electrically conductive material (50) in between the integrated circuit on the first substrate and the inductive coil on the second substrate.
17. A method according to claim 16, characterized in that the electrically conductive material (50) is anisotropically conductive in a direction substantially perpendicular to a surface of the first substrate.
18. A method according to any one of claims 13-17, characterized in that step (ii) further comprises the step of providing an electrically insulating material (40, 52) in between the integrated circuit and the inductive coil at i locations separated from the first contact pad, the second contact pad, the first coil terminal and the second coil terminal.
PCT/EP2009/058336 2008-07-02 2009-07-02 Rfid device WO2010000806A1 (en)

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US61/077,840 2008-07-02

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TWI549195B (en) * 2011-07-21 2016-09-11 劍橋顯示科技有限公司 Method of forming a top gate transistor
WO2017176257A1 (en) * 2016-04-05 2017-10-12 Hewlett-Packard Development Company, L.P. Modular radio frequency identification (rfid) devices
WO2022097926A1 (en) * 2020-11-06 2022-05-12 삼성전자주식회사 Electronic device comprising solder wall

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EP0908843A1 (en) * 1997-10-07 1999-04-14 Koninklijke Philips Electronics N.V. Contactless electronic card and its manufacturing method

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI549195B (en) * 2011-07-21 2016-09-11 劍橋顯示科技有限公司 Method of forming a top gate transistor
WO2017176257A1 (en) * 2016-04-05 2017-10-12 Hewlett-Packard Development Company, L.P. Modular radio frequency identification (rfid) devices
CN109313714A (en) * 2016-04-05 2019-02-05 惠普发展公司,有限责任合伙企业 Modular radio frequency identifies (RFID) equipment
US10860909B2 (en) 2016-04-05 2020-12-08 Hewlett-Packard Development Company, L.P. Modular radio frequency identification (RFID) devices
CN109313714B (en) * 2016-04-05 2022-03-01 惠普发展公司,有限责任合伙企业 Modular Radio Frequency Identification (RFID) device
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WO2022097926A1 (en) * 2020-11-06 2022-05-12 삼성전자주식회사 Electronic device comprising solder wall

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