WO2009142265A1 - Iii nitride semiconductor light emitting element and method for manufacturing the same, and lamp - Google Patents

Iii nitride semiconductor light emitting element and method for manufacturing the same, and lamp Download PDF

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Publication number
WO2009142265A1
WO2009142265A1 PCT/JP2009/059357 JP2009059357W WO2009142265A1 WO 2009142265 A1 WO2009142265 A1 WO 2009142265A1 JP 2009059357 W JP2009059357 W JP 2009059357W WO 2009142265 A1 WO2009142265 A1 WO 2009142265A1
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layer
iii nitride
group iii
nitride semiconductor
substrate
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Japanese (ja)
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裕直 篠原
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昭和電工株式会社
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present invention relates to a group III nitride semiconductor light-emitting device having a light-emitting diode (LED) structure and an emission wavelength of 490 to 570 nm, a method for manufacturing the same, and a lamp.
  • LED light-emitting diode
  • Group III nitride semiconductors have attracted attention as semiconductor materials for light-emitting elements that emit light of short wavelengths.
  • MOCVD method metal organic chemical vapor deposition method
  • MBE method molecular beam epitaxy method
  • an n-type semiconductor layer, a light emitting layer, and a p type semiconductor layer made of a group III nitride semiconductor are arranged in this order on a sapphire single crystal substrate.
  • stacked is mentioned.
  • the sapphire substrate is an insulator. Therefore, the element structure using the sapphire substrate generally has a structure in which the positive electrode formed on the p-type semiconductor layer and the negative electrode formed on the n-type semiconductor layer are present on the same plane in the lateral direction. .
  • a face-up method in which a transparent electrode is used as a positive electrode and light is extracted from the p-type semiconductor side, and a highly reflective film such as Ag is used as a positive electrode from the sapphire substrate side.
  • a flip chip type that extracts light.
  • External quantum efficiency is used as an index of the output of such a light emitting element. If the external quantum efficiency is high, it can be said that the light-emitting element has a high output.
  • the external quantum efficiency is a value obtained by multiplying the internal quantum efficiency and the light extraction efficiency.
  • the internal quantum efficiency is a rate at which the energy of current injected into the device is converted into light in the light emitting layer.
  • the light extraction efficiency is a ratio of light that can be extracted outside the light emitting element among light generated in the light emitting layer. Therefore, in order to improve the external quantum efficiency, it is necessary to improve the light extraction efficiency.
  • an element that emits green light having an emission wavelength of 490 to 570 nm is used in various fields that require such an emission color.
  • the emission wavelength is a long wavelength of 490 nm or longer, the emission color is green.
  • the emission wavelength is around 505 nm, a blue-green color used for a traffic light or the like is exhibited.
  • the emission wavelength is in the vicinity of 525 nm, a pure green color that is used as a light source for three primary colors such as a display can be obtained.
  • the emission wavelength when the emission wavelength is near 560 nm, a yellowish green color used for, for example, a pilot lamp is obtained, and when the emission wavelength is 570 nm, the emission color becomes a color tone close to yellow.
  • the emission wavelength needs to be 490 nm or more.
  • indium (In) contained in a well layer (active layer) included in the light emitting layer is used. It is necessary to increase the concentration. However, when the indium concentration is increased, the lattice constant increases, and the difference in lattice constant between the lower layer (substrate side) layer and the barrier layer located below the light emitting layer increases. For this reason, there is a problem that distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. Moreover, indium is easy to evaporate. For this reason, in the temperature rising process for forming the barrier layer, indium evaporates from the well layer, and as a result, the crystallinity is lowered and distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. appear.
  • the present invention has been made in view of the above problems, and provides a group III nitride semiconductor light-emitting device excellent in light extraction efficiency and a manufacturing method thereof without reducing the internal quantum efficiency of an LED structure that emits green light.
  • an object of the present invention is to provide a lamp that uses the above-mentioned group III nitride semiconductor light emitting device and has excellent light emission characteristics.
  • a group III nitride semiconductor light emitting device in which an LED structure is formed on a single crystal group III nitride semiconductor layer formed on a substrate,
  • the substrate has a main surface composed of a flat portion made of a (0001) C plane and a plurality of convex portions, and a back surface, and the base width of the convex portion is 0.05 to 1.5 ⁇ m
  • the group III nitride semiconductor layer is formed so as to cover the planar portion and the convex portion on the main surface of the substrate by epitaxial growth of the group III nitride semiconductor.
  • the group III nitride semiconductor light-emitting device characterized in that the light emission wavelength of the LED structure is in the range of 490 to 570 nm.
  • the group III nitride semiconductor light-emitting device according to the above [1], wherein the convex portion is configured by a surface non-parallel to the C-plane.
  • the convex portion has a base width of 0.05 to 1 ⁇ m, a height in the range of 0.05 to 1 ⁇ m, and 1 ⁇ 4 or more of the base width, and between adjacent convex portions.
  • the LED structure includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, each of which is made of a group III nitride semiconductor, in this order on the main surface of the substrate.
  • the group III nitride semiconductor light-emitting device according to any one of [8].
  • a buffer layer made of polycrystalline Al x Ga 1-x N (0 ⁇ x ⁇ 1) and having a thickness of 0.01 to 0.5 ⁇ m is stacked on the main surface of the substrate by sputtering.
  • a buffer layer made of single-crystal Al x Ga 1-x N (0 ⁇ x ⁇ 1) and having a thickness of 0.01 to 0.5 ⁇ m is stacked on the main surface of the substrate by sputtering.
  • the group III nitride semiconductor light-emitting device according to any one of the above [1] to [10], wherein the group III nitride semiconductor layer is stacked on the buffer layer.
  • the n-type semiconductor layer includes an n-type cladding layer
  • the p-type semiconductor layer includes a p-type cladding layer
  • at least one of the n-type cladding layer and the p-type cladding layer has a superlattice structure.
  • the group III nitride semiconductor light-emitting device according to any one of the above [8] to [12], comprising: [14] Any one of [1] to [13] above, wherein a half width of an X-ray rocking curve (XRC) in the (10-10) plane of the group III nitride semiconductor layer is 150 arcsec or more.
  • XRC X-ray rocking curve
  • a substrate processing step for forming a main surface comprising: An epitaxial step of forming a single crystal group III nitride semiconductor layer covering the planar portion and the convex portion by epitaxially growing a group III nitride semiconductor on the main surface of the substrate;
  • a method of manufacturing a group III nitride semiconductor light emitting device comprising: an LED stacking step of forming an LED structure having an emission wavelength in the range of 490 to 570 nm on the group III nitride semiconductor layer.
  • the group III nitride semiconductor light-emitting device according to [15], wherein in the substrate processing step, the surface of the convex portion is formed by a surface non-parallel to the C-plane Manufacturing method.
  • the base width is in the range of 0.05 to 1 ⁇ m
  • the height is in the range of 0.05 to 1 ⁇ m
  • a mask pattern is formed on the (0001) C surface of the substrate using one of a stepper exposure method, a nanoimprint method, an electron beam (EB) exposure method, and a laser exposure method.
  • the LED structure is formed by stacking an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor in this order on the main surface of the substrate.
  • the method for producing a group III nitride semiconductor light-emitting device according to any one of the above [15] to [23], wherein [25] The method for producing a group III nitride semiconductor light-emitting element according to the above [24], wherein, in the LED stacking step, an In concentration of a light-emitting layer provided in the LED structure is 7% by mass or more.
  • a thickness of 0.1% of the polycrystalline Al x Ga 1-x N (0 ⁇ x ⁇ 1) is formed on the main surface of the substrate.
  • the group III nitride semiconductor light-emitting device according to any one of [15] to [25], wherein a buffer layer forming step of laminating a buffer layer of 01 to 0.5 ⁇ m by a sputtering method is included. Production method.
  • the n-type semiconductor layer includes an n-type cladding layer
  • the p-type semiconductor layer includes a p-type cladding layer
  • the n-type cladding layer and the p-type cladding layer are the n-type cladding layer and the p-type cladding layer.
  • XRC line rocking curve
  • the substrate has a flat surface composed of a (0001) C plane, a main surface composed of a plurality of convex portions, and a back surface.
  • the base width is 0.05 to 1.5 ⁇ m.
  • the group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor on the main surface of the substrate so as to cover the planar portion and the convex portion.
  • the emission wavelength in the LED structure is in the range of 490 to 570 nm.
  • the present invention can appropriately control the crystallinity of the group III nitride semiconductor layer and suppress the occurrence of lattice mismatch with the LED structure further stacked on this layer. can do. Moreover, the said effect becomes more remarkable and the exceptional effect is acquired because the convex part of a board
  • substrate is comprised by the surface non-parallel to C surface. With these characteristics, there is no distortion in the LED structure that emits green light, and it is possible to suppress the decrease in internal quantum efficiency and the occurrence of leakage current, so that the electrical characteristics are excellent and the light emission output is high. A group nitride semiconductor light emitting device is obtained.
  • the light emitting device of the present invention includes an n-type cladding layer and / or a p-type cladding layer, and when the n-type cladding layer and / or the p-type cladding layer has a superlattice structure, the output is remarkably high. Thus, a light-emitting element having excellent electrical characteristics can be obtained.
  • a plurality of convex portions having a base width of 0.05 to 1.5 ⁇ m are formed on the plane composed of the (0001) C plane of the substrate. Is done.
  • a substrate processing step for forming a main surface composed of a flat portion and a convex portion on a substrate, and a group III nitride semiconductor is epitaxially grown on the main surface of the substrate to cover the flat surface and the convex portion.
  • an epitaxial process for forming the group III nitride semiconductor layer and an LED stacking process for forming the LED structure with an emission wavelength in the LED structure in the range of 490 to 570 nm are included.
  • a group III nitride semiconductor layer with properly controlled crystallinity can be formed, and it is possible to suppress the occurrence of lattice mismatch with the LED structure formed on this layer, distortion, etc. It is possible to form an LED structure without causing the above.
  • the said effect becomes more remarkable by using the method of forming the convex part comprised by the surface which is non-parallel with respect to C surface in a board
  • the lamp according to the present invention has excellent light emission characteristics.
  • FIG. 1 It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is sectional drawing which shows the light-emitting device in which the LED structure was formed on the laminated structure shown in FIG. It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is an expanded sectional view which shows the principal part of FIG. It is the schematic explaining typically an example of the lamp
  • FIG. 1 is a diagram for explaining a part of a light emitting device 1 according to the present invention.
  • FIG. 1 is a cross-sectional view showing a laminated structure in which a buffer layer and a single crystal underlayer (group III nitride semiconductor layer) 103 are formed on a main surface 10 of a substrate 101.
  • FIG. FIG. 2 is a perspective view for explaining the substrate 101 shown in FIG.
  • FIG. 3 is a cross-sectional view showing the light-emitting element 1 in which the LED structure 20 is formed on the base layer (group III nitride semiconductor layer) 103 having the stacked structure shown in FIG.
  • reference numeral 107 denotes a positive electrode bonding pad
  • reference numeral 108 denotes a negative electrode bonding pad.
  • 4 is a partial cross-sectional view showing cross sections of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 in the light-emitting element 1 shown in FIG.
  • a light-emitting element 1 according to the present invention is schematically configured as in the example shown in FIGS. 1 to 4, and is formed on a single crystal underlayer (group III nitride semiconductor layer) 103 formed on a substrate 101.
  • An LED structure 20 is formed.
  • the substrate 101 has a main surface 10 composed of a back surface, a flat portion 11 made of a (0001) C plane, and a plurality of convex portions 12 made of a surface 12c non-parallel to the C surface.
  • the base width of the convex portion 12 is 0.05 to 3 ⁇ m.
  • the underlayer 103 is formed by epitaxially growing a group III nitride semiconductor on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12.
  • the emission wavelength in the LED structure 20 is in the range of 490 to 570 nm.
  • a buffer layer 102 is provided on the substrate 101, and a base layer 103 is further formed on the buffer layer 102.
  • the light-emitting element 1 which is an example of the present invention described in the present embodiment is a single electrode type as shown in FIG.
  • a buffer layer 102 and an LED structure (Group III nitride semiconductor layer) 20 made of a Group III nitride semiconductor containing Ga as a Group III element are formed on the substrate 101 as described above.
  • the LED structure 20 provided in the light-emitting element 1 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 stacked in this order.
  • the group III nitride semiconductor light-emitting device of the present invention has a light emission wavelength of 490 nm by controlling the indium (In) content of the well layer constituting the light-emitting layer to be high concentration in the LED structure described in detail later. It exhibits green light emission as described above, and more preferably exhibits an emission wavelength in the range of 490 to 570 nm.
  • the element of the present invention can emit good green light.
  • the laminated structure of the light emitting element 1 will be described in detail.
  • the material that can be used for the substrate 101 is not particularly limited as long as it is a substrate material on which a group III nitride semiconductor crystal is epitaxially grown, and various materials can be selected and used. it can.
  • sapphire SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide Lanthanum strontium oxide aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum and the like.
  • sapphire is particularly preferable. It is desirable that an intermediate layer (buffer layer) 102 be formed on the c-plane of the sapphire substrate.
  • the buffer layer 102 is preferably used.
  • the buffer layer 102 in the case where an underlayer 103 described later is formed by a method using ammonia after forming the buffer layer 102 without using ammonia, the buffer layer 102 also functions as a coat layer. It is effective in preventing chemical alteration. It is also preferable to form the buffer layer 102 by sputtering. In the case where the buffer layer 102 is formed by a sputtering method, the temperature of the substrate 101 can be kept low. Therefore, even when the substrate 101 made of a material that decomposes at a high temperature is used, the formation of each layer on the substrate without damaging the substrate 101 by forming the buffer layer 102 by sputtering. A membrane is possible.
  • a plurality of convex portions 12 are formed on the main surface 10 of the substrate 101 used in this embodiment, as in the example shown in FIG.
  • a portion of the main surface 10 of the substrate 101 where the convex portion 12 is not formed is constituted by a flat portion 11 made of a (0001) C plane. Therefore, as in the example shown in FIGS. 2 and 3, the main surface 10 of the substrate 101 is composed of a flat surface portion 11 made of a C surface and a plurality of convex portions 12.
  • the surface of the convex portion 12 is a surface 12 c that is non-parallel to the C plane.
  • the C surface does not appear on the surface 12c.
  • the convex portions 12 shown in FIGS. 1 and 2 have an obstructed bowl-like (hemispherical) shape. That is, the planar shape of the base 12a (the shape of the bottom surface of the convex portion 12) is substantially circular, and the convex portion 12 has a shape in which the outer shape (cross-sectional area) gradually decreases toward the top.
  • the side surface 12b of the convex portion 12 is curved outward.
  • the planar arrangement of the protrusions 12 is arranged in a grid pattern at regular intervals.
  • the base width d 1 is 0.05 to 1.5 ⁇ m
  • the height h is 0.05 to 1 ⁇ m
  • the distance d 2 between the adjacent convex portions 12 is 0.5 to 5 times the base width d 1 .
  • the base width d 1 of the convex portion 12 refers to the maximum width at the bottom surface (base portion 12 a) of the convex portion 12.
  • the distance d 2 between the adjacent convex portions 12 refers to the shortest distance between the edge of the base portion 12 a of the convex portion 12 and the edge of the base portion 12 a of the convex portion 12 closest to the convex portion 12.
  • the distance d 2 between the convex portions 12 adjacent to each other is preferably 0.5 to 5 times the base width d 1 . If the interval d 2 between the convex portions 12 adjacent is less than 0.5 times the base width d 1 from each other, when epitaxially growing a base layer 103 of n-type semiconductor layer 104 (semiconductor layer 30) is formed thereon. In addition, it is difficult to promote crystal growth from the C-plane flat portion 11, and it becomes difficult to completely fill the convex portion 12 with the underlayer 103, and the flatness of the surface 103 a of the underlayer 103 is sufficiently high. It may not be obtained.
  • the base width d 1 is preferably 0.05 to 1.5 ⁇ m.
  • the base width d 1 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be obtained sufficiently.
  • the base width d 1 exceeds 1.5 ⁇ m, it may be difficult to completely fill the convex portion 12 and epitaxially grow the base layer 103. Further, even if an underlayer with good flatness and crystallinity can be formed, the distortion between the underlayer and the light-emitting layer may increase, leading to a decrease in internal quantum efficiency.
  • the base width d 1 is within the above range, the light emission output of the light emitting element can be further improved as the configuration is made smaller.
  • the base width d 1 is more preferably 0.05 to 1 ⁇ m.
  • the height h of the convex portion 12 is preferably 0.05 to 1 ⁇ m.
  • the height h of the convex portion 12 is less than 0.05 ⁇ m, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be sufficiently obtained.
  • the height h of the convex portion 12 exceeds 1 ⁇ m, it may be difficult to epitaxially grow the base layer 103 by filling the convex portion 12, and the flatness of the surface 14a of the base layer 103 may not be sufficiently obtained. is there.
  • the height h of the convex portion 12 is preferably 1/4 or more base portion width d 1. More preferably, it is 1 ⁇ 2 or more and 1/1 or less. When the height h of the convex portion 12 is less than 1 ⁇ 4 of the base width d 1 , the effect of irregularly reflecting light when the substrate 101 is used to form a group III nitride semiconductor light-emitting device and the light extraction efficiency are improved. The effect of improving may not be obtained sufficiently.
  • the shape of the convex part 12 is not limited to the example shown in FIG.1 and FIG.2, and what kind of shape may be sufficient if it is comprised from the surface non-parallel to C surface.
  • the planar shape of the base may be substantially polygonal, and the outer shape may gradually decrease toward the top, or the side surface 12 may be curved outward.
  • the shape of the convex part 12 may be a substantially conical shape or a substantially polygonal pyramid whose side width gradually decreases toward the top.
  • the side surface may protrude outward.
  • the side surface inclination angle may be a shape that changes in multiple stages, for example, in two stages.
  • planar arrangement of the protrusions 12 is not limited to the example shown in FIGS. 1 and 2 (a grid pattern), and may be arranged at equal intervals or may be arranged at non-equal intervals. . Further, the planar arrangement of the convex portions 12 may be a quadrangular shape, a triangular shape, or a random shape.
  • the convex portion 12 provided on the substrate 101 can be formed by etching the substrate 101 by a manufacturing method described in detail later.
  • the manufacturing method is not limited to this.
  • the convex portion may be formed by depositing another material forming the convex portion on the C surface of the substrate 101 on the substrate.
  • a method for depositing another material for forming a convex portion on the substrate for example, a sputtering method, a vapor deposition method, a CVD method, or the like can be used.
  • the material forming the convex portion it is preferable to use a material having a refractive index substantially equal to the material of the substrate, such as an oxide or a nitride.
  • the substrate is a sapphire substrate, for example, SiO 2 , Al 2 O 3 , SiN, ZnO, or the like can be used.
  • the substrate 101 since the substrate 101 has the above-described configuration including the main surface 10 including the flat portion 11 and the convex portion 12, the interface between the substrate 101 and the underlayer 103, which will be described in detail later, is a buffer layer. Concavities and convexities are formed through 102. For this reason, confinement of light inside the light emitting element due to irregular reflection of light due to the unevenness is reduced, and the light emitting element 1 having excellent light extraction efficiency can be realized. Further, since the substrate 101 has the above-described structure, the crystallinity of the base layer 103 can be appropriately controlled, so that a lattice is formed between the light emitting layer 105 (well layer 105b) provided in the LED structure 20 described later and the base layer 103.
  • Inconsistencies are prevented from occurring. Thereby, even when the In concentration of the well layer 105b provided in the light emitting layer 105 is set to a high concentration to constitute the light emitting element 1 that emits green light, the occurrence of distortion or the like in the well layer 105b is suppressed. Accordingly, it is possible to realize the light emitting device 1 that has excellent internal quantum efficiency, has a high light emission output, and is excellent in electrical characteristics by suppressing generation of leakage current.
  • buffer layer In the present invention, it is preferable to form the buffer layer 102 on the main surface 10 of the substrate 101 and form an underlayer 103 described later on the buffer layer 102.
  • the buffer layer 102 is stacked on the substrate 101 with a composition of Al X Ga 1-X N (0 ⁇ x ⁇ 1).
  • the buffer layer can be formed by a reactive sputtering method in which a gas containing a group V element and a metal material are activated and reacted with plasma.
  • a film formed by a method using a plasma metal raw material as in this embodiment has an effect that alignment is easily obtained.
  • the buffer layer 102 has a function of alleviating the difference in lattice constant between the substrate 101 and the base layer 103 and, as a result, easily forming a C-axis oriented single crystal layer on the C plane of the substrate 101. Therefore, when a single-crystal group III nitride semiconductor layer (underlayer 103) is stacked on the buffer layer 102 formed on the substrate, the underlayer has better crystallinity than the case without the buffer layer. 103 can be formed. In the present embodiment, it is most preferable to form the buffer layer 102 between the substrate 101 and the base layer 103, but a configuration in which the buffer layer is omitted may be employed.
  • the buffer layer 102 preferably has a composition of Al X Ga 1-X N (0 ⁇ x ⁇ 1), and more preferably AlN.
  • the buffer layer laminated on the substrate preferably has a composition containing Al, and may be a group III nitride compound represented by the general formula Al X Ga 1-X N (0 ⁇ x ⁇ 1). Any material can be used. Furthermore, it can also be set as the composition containing As and P as V group.
  • the Al composition is more preferably 50% or more.
  • a material constituting the buffer layer 102 a material having the same crystal structure as that of the group III nitride semiconductor can be used, but the length of the lattice is close to that of the group III nitride semiconductor constituting the underlayer described later. And nitrides of group IIIa elements of the periodic table are particularly preferred.
  • the group III nitride crystal forming the buffer layer has a hexagonal crystal structure, and can be formed into a single crystal film by controlling the film formation conditions. Further, the group III nitride crystal can be formed into a columnar crystal (polycrystal) having a texture based on a hexagonal column by controlling the film forming conditions. Note that the columnar crystal described here is a crystal which is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape.
  • the buffer layer 102 preferably has a single crystal structure from the viewpoint of the buffer function.
  • the group III nitride crystal has a hexagonal crystal and forms a structure based on a hexagonal column.
  • the buffer layer 102 having the single crystal structure as described above is formed over the substrate 101, the buffer function of the buffer layer 102 effectively operates. Therefore, the group III nitride semiconductor layer formed thereon is a crystal film having good orientation and crystallinity.
  • the thickness of the buffer layer 102 is preferably in the range of 0.01 to 0.5 ⁇ m. By setting the thickness of the buffer layer 102 in the above range, it has good orientation and functions effectively as a coating layer when each layer made of a group III nitride semiconductor is formed on the buffer layer 102. The buffer layer 102 is obtained. When the film thickness of the buffer layer 102 is less than 0.01 ⁇ m, a sufficient function as the above-described coat layer cannot be obtained, and the buffer function that alleviates the difference in lattice constant between the substrate 101 and the base layer 103. May not be sufficiently obtained.
  • the buffer layer 102 when the buffer layer 102 is formed with a film thickness exceeding 0.5 ⁇ m, the film formation processing time is prolonged and the productivity is lowered although there is no change in the buffer function and the function as the coat layer. There is.
  • the thickness of the buffer layer 102 is more preferably in the range of 0.02 to 0.1 ⁇ m.
  • the underlayer (group III nitride semiconductor layer) 103 provided in the light emitting device 1 of the present invention is made of a group III nitride semiconductor as described above, and is laminated on the buffer layer 102 by a conventionally known MOCVD method. can do.
  • the base layer 103 described in this example is formed of a group III nitride semiconductor on the main surface 10 of the substrate 101 via the buffer layer 102 so as to cover the planar portion 11 and the convex portion 12. It is formed by epitaxial growth.
  • the use of an Al y Ga 1-y N layer (0 ⁇ y ⁇ 1, preferably 0 ⁇ y ⁇ 0.5, more preferably 0 ⁇ y ⁇ 0.1) as the base layer 103 provides good crystallinity. It is more preferable in that the underlayer 103 can be formed.
  • a material different from that of the buffer layer 102 may be used as the material of the base layer 103, but the same material as that of the buffer layer 102 may be used.
  • the underlayer 103 may have a configuration in which n-type impurities are doped in the range of 1 ⁇ 10 17 to 1 ⁇ 10 19 atoms / cm 3 as necessary, but may be undoped ( ⁇ 1 ⁇ 10 17 atoms / cm 3). 3 ). Undoped is preferable in that good crystallinity can be maintained.
  • the base layer 103 is doped with a dopant so that the substrate 101 is conductive, whereby electrodes can be provided above and below the light emitting element.
  • a chip structure in which the positive electrode and the negative electrode are provided on the same surface of the light-emitting element is employed.
  • the base layer 103 be an undoped crystal because crystallinity is improved.
  • the n-type impurity doped in the base layer 103 is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge.
  • the thickness of the underlayer 103 is preferably in the range of 1 to 8 ⁇ m, from the viewpoint of obtaining an underlayer with good crystallinity, and in the range of 2 to 5 ⁇ m shortens the process time required for film formation. This is more preferable in terms of productivity.
  • the maximum thickness H of the base layer 103 illustrated in FIG. 1 is not less than twice the height h of the convex portion 12 of the substrate 101 because a flat base layer 103 having a surface 103a can be obtained.
  • the maximum thickness H of the base layer 103 is smaller than twice the height h of the convex portion 12, the flatness of the surface 103a of the base layer 103 grown so as to cover the convex portion 12 becomes insufficient. There is a possibility that the crystallinity of each layer which is laminated on the underlayer 103 and constitutes the LED structure 20 is lowered.
  • the X-ray rocking curve (XRC) half width of the (10-10) plane of the underlayer 103 is 150 arcsec or more. If the XRC half width of the underlayer 103 is 150 arcsec or more, the crystallinity of the underlayer 103 does not become too high and is controlled within an appropriate range. Therefore, the LED structure 20, particularly the light emitting layer 105, laminated on the surface 103 a is prepared. The well layer 105b is free from distortion and becomes a good crystal layer.
  • the XRC half-width of the (10-10) plane of the underlayer is an index of crystallinity, and the smaller this value, the higher the crystallinity of the underlayer.
  • the half-value width affects the crystallinity of the LED structure formed thereon, a method of increasing the crystallinity of the entire light-emitting element by setting the value as small as possible has been employed.
  • a light emitting element that emits green light with an emission wavelength of 490 to 570 nm as in the present invention, it is necessary to increase the In concentration of the well layer provided in the light emitting element. Lattice constant increases.
  • the crystallinity of the underlayer 103 is set within an appropriate range.
  • Well controlled In order to obtain green light emission, even when the In concentration of the well layer 105b of the light emitting layer 105 provided in the LED structure 20 is increased, there is a large lattice mismatch between the base layer 103 and the well layer 105b. It is suppressed from occurring. Accordingly, the occurrence of defects such as strain in the well layer 105b is suppressed, and the internal quantum efficiency is not lowered, so that the light emitting element 1 having a high light emission output can be realized.
  • XRC X-ray rocking curve
  • the XRC half width of the underlayer 103 can be appropriately controlled by the base width d 1 of the convex portion 12 formed on the substrate 101 described above.
  • the base width d 1 of the convex portion 12 of the substrate 101 is 1 ⁇ m
  • the XRC half width of the base layer 103 is about 150 to 200 arcsec. If the base width d 1 is kept within the preferred range of the present invention, the half width tends to be 150 arcsec or more.
  • the XRC half-value width of the underlayer is about 100 arcsec or more and less than 150 arcsec, and the crystallinity of the underlayer is greatly enhanced.
  • the XRC half-value width of the (10-10) plane of the underlayer 103 is 150 arcsec or more from the viewpoint of controlling the crystallinity of the underlayer 103 appropriately.
  • crystallinity will fall too much when the XRC half value width of a base layer exceeds 250 arcsec, it is preferable to control so that it may become 250 arcsec or less.
  • the XRC half-value width of the (10-10) plane on the side of the mold semiconductor layer 106 has the same tendency as that of the base layer 103. Therefore, in the present invention, the XRC half width of the (10-10) plane of the underlayer is used as an index representing crystallinity.
  • the LED structure 20 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 each made of a group III nitride semiconductor. By forming each layer of such an LED structure 20 by MOCVD, a layer with higher crystallinity can be obtained.
  • the n-type semiconductor layer 104 is generally composed of an n-type contact layer 104a and an n-type cladding layer 104b.
  • the n-type contact layer 104a can also serve as the n-type cladding layer 104b.
  • the n-type contact layer 104a is a layer for providing a negative electrode.
  • the n-type contact layer 104a is preferably composed of an Al x Ga 1-x N layer (0 ⁇ x ⁇ 1, preferably 0 ⁇ x ⁇ 0.5, more preferably 0 ⁇ x ⁇ 0.1).
  • the n-type contact layer 104a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 ⁇ 10 17 to 1 ⁇ 10 20 / cm 3 , preferably 1 ⁇ 10 18 to 1 ⁇ 10 19 /. Containing at a concentration of cm 3 is preferable in terms of maintaining good ohmic contact with the negative electrode.
  • an n-type impurity For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.
  • the film thickness of the n-type contact layer 104a is preferably 0.5 to 5 ⁇ m, and more preferably set to a range of 1 to 3 ⁇ m. When the film thickness of the n-type contact layer 104a is in the above range, the crystallinity of the semiconductor is maintained well.
  • the n-type cladding layer 104b is a layer that injects carriers into the light emitting layer 105 and confines carriers.
  • the n-type cladding layer 104b can be formed of AlGaN, GaN, GaInN, or the like. Further, a structure in which these are heterojunctioned or a superlattice structure in which a plurality of layers are laminated may be used.
  • the n-type cladding layer 104b is formed of GaInN, it is desirable to make the band gap of the n-type cladding layer 104b larger than the band gap of GaInN of the light emitting layer 105.
  • the film thickness of the n-type cladding layer 104b is not particularly limited, but is preferably 0.005 to 0.5 ⁇ m, and more preferably 0.005 to 0.1 ⁇ m.
  • the n-type doping concentration of the n-type cladding layer 104b is preferably 1 ⁇ 10 17 to 1 ⁇ 10 20 / cm 3 , more preferably 1 ⁇ 10 18 to 1 ⁇ 10 19 / cm 3 . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.
  • n-type cladding layer 104b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less.
  • the n-type cladding layer 104b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. Preferably, either the n-side first layer or the n-side second layer is in contact with the active layer (light-emitting layer 105).
  • compositions of the n-side first layer and the n-side second layer as described above include, for example, AlGaN-based Al (sometimes simply referred to as AlGaN) and GaInN-based (including simply InGa). Or a composition of GaN.
  • the n-side first layer and the n-side second layer have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, a GaInN / AlGaN alternating structure, and a GaInN / GaInN alternating structure having a different composition (the present invention).
  • the n-side first layer and the n-side second layer are preferably GaInN / GaInN having different GaInN / GaN structures or different compositions.
  • the n-side first layer and the n-side second layer which are superlattice layers, are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Most preferably it is. If the thickness of each of the n-side first layer and the n-side second layer forming the superlattice layer exceeds 100 angstroms, crystal defects are likely to occur, which is not preferable.
  • the n-side first layer and the n-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
  • the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
  • an n-type cladding layer is formed of an alternate structure of GaInN / GaN or a combination of an n-side first layer and an n-side second layer having an alternate structure of GaInN / GaInN having different compositions, Si as an impurity. Is preferred.
  • the n-side superlattice multilayer film as described above may be formed in a multilayer structure using the same composition typified by GaInN, AlGaN, and GaN while appropriately turning ON / OFF doping.
  • the n-type cladding layer 104b has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting element 1 having excellent electric characteristics can be obtained.
  • Examples of the light emitting layer 105 stacked on the n-type semiconductor layer 104 include a light emitting layer 105 having a single quantum well structure or a multiple quantum well structure.
  • a well layer having a quantum well structure as shown in FIG. 4 for example, in the case of a structure exhibiting blue light emission, a composition having a composition of Ga 1-y In y N (0 ⁇ y ⁇ 0.04) is usually used.
  • a group III nitride semiconductor is used, in the case of the well layer 105b exhibiting green light emission as in the present invention, the composition of indium such as Ga 1-y In y N (0.07 ⁇ y ⁇ 0.20) is used. The one with increased is used.
  • the Ga 1-y In y N is used as the well layer 105b, and Al x Ga 1-x N (0 ⁇ z ⁇ 0.3) is preferably the barrier layer 105a.
  • the well layer 105b and the barrier layer 105a may or may not be doped with impurities depending on the design.
  • the film thickness of the well layer 105b can be, for example, a film thickness at which a quantum effect can be obtained, that is, 1 to 10 nm, and more preferably 2 to 6 nm from the viewpoint of light emission output.
  • the emission wavelength In order for the group III nitride semiconductor light emitting device to emit green light, the emission wavelength needs to be 490 nm or more. In order to obtain good green light emission, the emission wavelength is more preferably in the range of 490 to 570 nm. For this reason, in the light emitting element 1 of the present invention, the In composition ratio of the well layer 105b forming the light emitting layer 105 is preferably 7% or more. If the In concentration of the well layer 105b is within this range, good green light emission with an emission wavelength of 490 to 570 nm can be obtained.
  • the light emitting element 1 emits green light when the In concentration of the well layer 105b is as high as described above and the emission wavelength is in the above range.
  • the well layer 105b included in the light emitting layer 105 is configured with a high In concentration
  • the crystallinity of the underlying layer 103 which is the lower layer
  • the internal quantum efficiency is reduced due to crystal defects in the well layer, and thus the emission intensity is low. End up.
  • the substrate 101 has the main surface 10 composed of the flat portion 11 and the convex portion 12 and the back surface thereof, and the base width of the convex portion 12 is 0.05 to 1.5 ⁇ m.
  • a base layer 103 formed by epitaxially growing a single crystal group III nitride semiconductor is provided on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12.
  • a crystal does not grow from the parallel surface 12c, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane. Therefore, the underlying layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10 and does not cause crystal defects such as dislocations in the crystal. It becomes a controlled layer.
  • each layer constituting the LED structure 20 on the base layer 103 whose crystallinity is well controlled in an appropriate range as described above, the well layer 105b exhibiting green light emission with a high In concentration. Even when the layer is formed, the occurrence of lattice mismatch between the base layer 103 and the well layer 105b is suppressed. Thereby, crystal defects such as strain do not occur in the well layer 105b, it is possible to suppress a decrease in internal quantum efficiency and a leak current, and the light emitting device 1 having excellent electrical characteristics and high light emission output. It becomes possible to do.
  • the p-type semiconductor layer 106 is generally composed of a p-type cladding layer 106a and a p-type contact layer 106b.
  • the p-type contact layer 106b can also serve as the p-type cladding layer 106a.
  • the p-type cladding layer 106 a is a layer that performs confinement of carriers and injection of carriers in the light emitting layer 105.
  • the composition of the p-type cladding layer 106 a is not particularly limited as long as the composition is larger than the band gap energy of the light emitting layer 105 and can confine carriers in the light emitting layer 105.
  • a preferable composition is Al x Ga 1-x N (0 ⁇ x ⁇ 0.4).
  • the p-type cladding layer 106a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer.
  • the film thickness of the p-type cladding layer 106a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm.
  • the p-type doping concentration of the p-type cladding layer 106a is preferably 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , more preferably 1 ⁇ 10 19 to 1 ⁇ 10 20 / cm 3 .
  • the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
  • the p-type cladding layer 106a may have a superlattice structure in which a plurality of layers are stacked.
  • the p-type cladding layer 106a is a layer including a superlattice structure, a detailed illustration is omitted, but a p-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less.
  • the p-type cladding layer 106a may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.
  • composition of the p-side first layer and the p-side second layer as described above may be different compositions, for example, any composition of AlGaN, GaInN, or GaN.
  • the p-side first layer and the p-side second layer may have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, or a GaInN / AlGaN alternating structure.
  • the p-side first layer and the p-side second layer preferably have an AlGaN / AlGaN or AlGaN / GaN alternating structure.
  • the superlattice layers of the p-side first layer and the p-side second layer are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Is most preferred. If the thickness of each of the p-side first layer and the p-side second layer forming the superlattice layer exceeds 100 angstroms, it becomes a layer containing many crystal defects and the like, which is not preferable.
  • the p-side first layer and the p-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure.
  • the impurity to be doped conventionally known impurities can be applied to the material composition without any limitation.
  • Mg is suitable as the impurity.
  • the p-side superlattice multilayer film as described above has the same composition as GaInN, AlGaN, or GaN, a multilayer structure can be produced by appropriately turning ON / OFF doping.
  • the p-type cladding layer 105a has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting device 1 having excellent electric characteristics can be obtained.
  • the p-type contact layer 106b is a layer for providing a positive electrode.
  • the p-type contact layer 106b preferably has a composition of Al x Ga 1-x N (0 ⁇ x ⁇ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity is maintained and good ohmic contact with the p ohmic electrode is possible.
  • the p-type contact layer 106b contains a p-type impurity (dopant) at a concentration of 1 ⁇ 10 18 to 1 ⁇ 10 21 / cm 3 , preferably 5 ⁇ 10 19 to 5 ⁇ 10 20 / cm 3 .
  • the thickness of the p-type contact layer 106b is not particularly limited, but is preferably 0.01 to 0.5 ⁇ m, and more preferably 0.05 to 0.2 ⁇ m. When the film thickness of the p-type contact layer 106b is within this range, it is preferable in terms of light emission output.
  • a translucent positive electrode 109 made of a translucent conductive oxide film layer is provided in contact with the p-type semiconductor layer 106.
  • the positive electrode bonding pad 107 is provided on a part of the translucent positive electrode 109.
  • the translucent positive electrode 109 is selected from ITO (In 2 O 3 —SnO 2 ), AZnO (ZnO—Al 2 O 3 ), ISnO (In 2 O 3 —ZnO), and GZO (ZnO—Ga 2 O 3 ).
  • ITO In 2 O 3 —SnO 2
  • AZnO ZnO—Al 2 O 3
  • ISnO In 2 O 3 —ZnO
  • GZO ZnO—Ga 2 O 3
  • the structure of the translucent positive electrode 109 can be used without any limitation, including a conventionally known structure.
  • the translucent positive electrode 109 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 106, or may be formed in a lattice shape or a tree shape with a gap. After forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
  • the positive electrode bonding pad 107 is provided for electrical connection with a circuit board, a lead frame or the like.
  • various structures using Au, Al, Ni, Cu and the like are well known, and these known materials and structures can be used without any limitation.
  • the thickness of the positive electrode bonding pad 107 is preferably in the range of 100 to 1500 nm. Further, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 107 is more preferably 300 nm or more.
  • the negative electrode bonding pad 108 is formed in contact with the n-type semiconductor layer 104 of the LED structure 20. For this reason, when forming the negative electrode bonding pad 108, the light emitting layer 105 and the p-type semiconductor layer 106 are partially removed to expose the n-type contact layer of the n-type semiconductor layer 104, and the negative electrode bonding pad is formed thereon. 108 is installed.
  • compositions and structures are well known, and these well known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.
  • the substrate 101 has the principal surface 10 composed of the planar portion 11 composed of the (0001) C plane and the plurality of convex portions 12.
  • the base width d 1 of the convex portion 12 is 0.05 to 1.5 ⁇ m
  • the base layer (group III nitride semiconductor layer) 103 covers the planar portion 11 and the convex portion 12 on the main surface 10 of the substrate 101.
  • the group III nitride semiconductor is formed by epitaxial growth.
  • the LED structure 20 has a configuration in which the emission wavelength is in the range of 490 to 570 nm.
  • the crystallinity of the underlayer 103 is appropriately controlled, so that it is possible to suppress the occurrence of lattice mismatch with the LED structure 20 stacked thereon.
  • the LED structure 20 that emits green light in particular, the well layer 105b included in the light emitting layer 105 is not distorted, and it is possible to suppress a decrease in internal quantum efficiency and a leakage current.
  • the light emitting device 1 having excellent optical characteristics and high light emission output can be obtained.
  • the interface between the substrate 101 and the base layer 103 is uneven through the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light, so that light extraction efficiency is excellent.
  • the light emitting device 1 can be realized.
  • the n-type cladding layer 104b and / or the p-type cladding layer 105a has a layer structure including a superlattice structure, whereby the output is remarkably improved and the light emitting device 1 having excellent electrical characteristics is provided. can do.
  • a single crystal underlayer (group III nitride semiconductor layer) 103 is formed on a substrate 101, and an LED structure 20 is formed on the underlayer 103.
  • a plurality of convex portions 12 having a base width of 0.05 to 3 ⁇ m are formed on the flat portion 11 made of the (0001) C surface of the substrate 101, thereby forming the flat portion 11 on the substrate 101.
  • each process with which the manufacturing method of this invention is equipped is demonstrated in detail.
  • FIG. 2 is a diagram for explaining an example of a process for manufacturing the laminated structure shown in the schematic diagram of FIG. 1. Specifically, it is a perspective view showing a substrate 101 prepared in the manufacturing method of the present embodiment.
  • the substrate 101 has a main surface 10 composed of a flat surface portion 11 composed of a C surface and a plurality of convex portions 12 formed on the C surface.
  • a method for processing the substrate 101 as shown in FIG. 2 will be described.
  • the substrate processing step for example, by forming a plurality of convex portions 12 having a surface non-parallel to the C plane on the (0001) C plane of the sapphire substrate, the plane portion 11 and the convex portion 12 having the C plane are formed.
  • a substrate 101 having a main surface 10 made of is manufactured.
  • Such a substrate processing step includes, for example, a patterning step for forming a mask on the substrate 101 so as to have a planar arrangement of the convex portions 12 on the substrate 101, and a substrate 101 using the mask formed by the patterning step. And a method including an etching step of forming the convex portion 12 by etching.
  • a sapphire single crystal wafer having a (0001) C plane as a surface is used as a substrate material for forming the plurality of convex portions 12.
  • the substrate having the (0001) C plane as the surface includes a substrate in which an off angle is given in the range of ⁇ 3 ° from the (0001) direction in the plane direction of the substrate.
  • the surface that is not parallel to the C plane means a surface that is not within a range of ⁇ 3 ° from the (0001) C plane.
  • the patterning process can be performed by a general photolithography method.
  • the base width d 1 of the base portion 12a is preferably at 1.5 ⁇ m or less. Therefore, in order to uniformly pattern the entire surface of the substrate 101, it is preferable to use a stepper exposure method among photolithography methods.
  • an expensive stepper device is required, resulting in high cost.
  • a laser exposure method, a nanoimprint method, an electron beam (EB) exposure method, or the like used in the field of optical discs is used. Is preferred.
  • Examples of the method for etching the substrate in the etching process include a dry etching method and a wet etching method.
  • a dry etching method since the crystal plane of the substrate 101 is exposed, it is difficult to form the convex portion 12 formed of the surface 12c that is non-parallel to the C plane. For this reason, it is preferable to use a dry etching method in an etching process.
  • the convex part 12 constituted by the surface 12c non-parallel to the C plane can be formed, for example, by dry etching the substrate 101 until the mask formed in the patterning process described above disappears. More specifically, for example, a resist is formed on the substrate 101 and then patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, the convex portion 12 can be formed by performing dry etching under predetermined conditions that promote lateral etching until the resist disappears.
  • the convex portion 12 constituted by the surface 12c non-parallel to the C-plane may be formed by using a method in which the substrate is dry-etched using a mask and then the mask is removed again and the substrate 101 is dry-etched. I can do it. More specifically, for example, a resist is formed on the substrate 101 and patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, dry etching is performed under a predetermined condition that promotes lateral etching, and the dry etching is interrupted before the resist disappears.
  • the convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension.
  • the convex portion 12 constituted by the surface 12c non-parallel to the C plane can be formed by combining with the dry etching method.
  • the wet etching can be performed by using a mixed acid of phosphoric acid and sulfuric acid at a high temperature of 250 ° C. or higher.
  • the convex portion 12 is formed by performing a predetermined amount of wet etching using a high-temperature acid. can do.
  • the convex portion 12 By forming the convex portion 12 using such a method, the crystal plane is exposed on the slope constituting the side surface of the convex portion 12, and the angle of the slope constituting the side surface of the convex portion 12 is formed with good reproducibility. Can do. Further, a good crystal plane can be exposed to the main surface 10 with good reproducibility.
  • a mask made of a material resistant to an acid such as SiO 2 is formed and wet etching is performed, and then the mask is peeled off.
  • the convex portion 12 can also be formed by a method of performing dry etching under a predetermined condition for promoting lateral etching.
  • the convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension. Moreover, even when the convex part 12 is formed using such a method, the angle of the slope which comprises the side surface of the convex part 12 can be formed with sufficient reproducibility.
  • the convex part is formed of oxide or nitride, after depositing a material on the substrate, a mask patterned by a method such as nanoimprinting is formed, and the convex part is formed by dry etching or wet etching. It can be a method to do.
  • this invention is not limited to the said method.
  • a buffer layer 102 as shown in FIGS. 1 and 3 is laminated on the main surface 10 of the substrate 101 prepared by the above method.
  • the buffer layer 102 as shown in FIG. 1 is stacked on the main surface 10 of the substrate 101 by performing a buffer layer forming step after the substrate processing step and before the epitaxial step.
  • the buffer layer may be omitted. In this case, the buffer layer forming step may not be performed.
  • Pretreatment of substrate In this embodiment, after introducing the substrate 101 into the chamber of the sputtering apparatus and before forming the buffer layer 102, it is desirable to perform pretreatment using a method such as reverse sputtering by plasma treatment.
  • the surface can be prepared by exposing the substrate 101 to Ar or N 2 plasma.
  • organic matter and oxide attached to the surface of the substrate 101 can be removed by reverse sputtering in which plasma such as Ar gas or N 2 gas is applied to the surface of the substrate 101.
  • plasma such as Ar gas or N 2 gas
  • the buffer layer 102 can be formed over the entire surface of the substrate 101 in the subsequent steps, and a film made of a group III nitride semiconductor formed thereon It becomes possible to increase the crystallinity. Further, it is more preferable that the substrate 101 is subjected to a wet pretreatment before the pretreatment by reverse sputtering as described above.
  • the pretreatment for the substrate 101 plasma is performed in an atmosphere in which ion components such as N + and (N 2 ) + and radical components having no charge such as N radicals and N 2 radicals are mixed. It is preferable to carry out by processing.
  • the pretreatment on the substrate 101 is a method using plasma treatment performed in an atmosphere in which an ionic component and a radical component are mixed as described above.
  • Deposition of buffer layer After performing the pretreatment to the substrate 101 on the substrate 101 by a reactive sputtering method, forming an Al X Ga 1-X N ( 0 ⁇ X ⁇ 1) buffer layer 102 of the composition it is.
  • the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is in the range of 50 to 100%. It is preferable to control so that it is about 75%.
  • the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is 1 to 50%. It is preferable to control to be within the range, and more preferably about 25%.
  • the buffer layer 102 is not limited to the reactive sputtering method described above, and can be formed using, for example, the MOCVD method. However, since the convex portion 12 is formed on the main surface 10 of the substrate 101, the flow of the source gas may be disturbed on the main surface 10 when the buffer layer is formed by the MOCVD method. In contrast to the MOCVD method, the reactive sputtering method has a high degree of straightness of the raw material particles, so that the uniform buffer layer 102 can be stacked without being affected by the shape of the main surface 10. Therefore, the buffer layer 102 is preferably formed using a reactive sputtering method.
  • the buffer layer forming step As shown in FIGS. 1 and 3, a single crystal group III nitride semiconductor is epitaxially grown on the buffer layer 102 formed on the main surface 10 of the substrate 101. An epitaxial process is performed to form a base layer (group III nitride semiconductor layer) 103 so as to cover 10.
  • the LED stacking process includes the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103.
  • An LED structure 20 is formed.
  • the description of the configuration common to both processes may be partially omitted for the epitaxial process and the LED stacking process in which each layer is formed using a group III nitride semiconductor.
  • the growth method of the gallium nitride compound semiconductor (group III nitride semiconductor) when forming the base layer 103, the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 is not particularly limited. All methods known to grow nitride semiconductors such as reactive sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), etc. Applicable.
  • the MOCVD method for example, hydrogen (H 2 ) or nitrogen (N 2 ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source as a group III source, and as an Al source Trimethylaluminum (TMA) or triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, ammonia (NH 3 ), hydrazine (N 2 H 4 ), etc. as the N source that is a group V source Can be used.
  • monosilane (SiH 4 ) or disilane (Si 2 H 6 ) can be used as a Si raw material for the n-type, and germane gas (GeH 4 ) or tetramethyl germanium ((CH 3 ) as a Ge raw material.
  • germane gas GeH 4
  • tetramethyl germanium (CH 3 )
  • Organic germanium compounds such as 4 Ge) and tetraethyl germanium ((C 2 H 5 ) 4 Ge) can be used.
  • elemental germanium can also be used as a doping source.
  • the p-type for example, biscyclopentadienyl magnesium (Cp 2 Mg) or bisethylcyclopentadienyl magnesium (EtCp 2 Mg) can be used as the Mg raw material.
  • the gallium nitride compound semiconductor as described above can contain other group III elements in addition to Al, Ga, and In, and can contain Ge, Si, Mg, Ca, Zn, and Be as necessary.
  • a dopant element can be contained.
  • it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.
  • the MOCVD method is preferably used from the viewpoint of obtaining a film having good crystallinity.
  • an example using the MOCVD method in the epitaxial process and the LED stacking process will be described. To do.
  • a base layer 103 is formed on a buffer layer 102 formed on a substrate 101 by using a conventionally known MOCVD method, and a planar portion 11 that forms the main surface 10 of the substrate 101. And it forms so that the convex part 12 may be covered.
  • the underlayer 103 is formed using the MOCVD method.
  • the method for stacking the base layer 103 is not particularly limited, and any crystal growth method that can cause dislocation looping can be used without any limitation.
  • the MOCVD method, the MBE method, the VPE method, and the like are preferable in that a film with favorable crystallinity can be formed because migration can occur.
  • the MOCVD method can be used more suitably in that a film having particularly good crystallinity can be obtained.
  • a single crystal group III nitride semiconductor layer is grown on the main surface of a sapphire substrate using MOCVD, a single crystal layer is epitaxially grown from the C surface, but a single crystal is formed on the main surface other than the C surface.
  • the layer does not grow epitaxially. That is, in the example described in this embodiment, when the base layer 103 made of a single crystal group III nitride semiconductor is epitaxially grown on the main surface 10 of the substrate 101 on which the buffer layer 102 is formed, it is non-parallel to the C plane.
  • a crystal does not grow from the surface 12c of the first layer, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane.
  • the base layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10, so that crystal defects such as dislocations do not occur in the crystal, so that the crystallinity is improved.
  • a properly controlled layer is used to control the base layer 103 formed on the main surface 10 of the substrate 101 so as to cover the convex portion 12 on the main surface 10, so that crystal defects such as dislocations do not occur in the crystal, so that the crystallinity is improved.
  • the substrate 101 on which the protrusions 12 are formed has a better flatness when the underlayer 103 is epitaxially grown on the main surface 10 by the MOCVD method than the substrate on which the protrusions 12 are not formed. It is difficult to stack.
  • the base layer 103 laminated on the main surface 10 of the substrate 101 on which the convex portions 12 are formed is liable to cause a tilt in the C-axis direction that deteriorates the crystallinity, a twist in the C-axis, or the like.
  • the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, the following growth conditions are used in order to obtain sufficient surface flatness and good crystallinity. It is desirable.
  • the growth pressure and the growth temperature are set as described below. Generally, when the growth pressure is lowered and the growth temperature is raised, lateral crystal growth is promoted. On the other hand, when the growth pressure is raised and the growth temperature is lowered, the facet growth mode ( ⁇ shape) is entered. Further, when the growth pressure at the initial stage of growth is increased, the half-value width (XRC-FWHM) of the X-ray rocking curve is decreased, and the crystallinity tends to be improved.
  • the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, it is preferable to change the growth pressure in two stages. That is, it is preferable to change the growth pressure until the film thickness of the underlayer 103 is about 2 ⁇ m or more (first half film formation) and after the underlayer 103 is laminated about 2 ⁇ m or more (second half film formation).
  • the growth pressure is preferably 40 kPa or more, and more preferably about 60 kPa.
  • the growth pressure When the growth pressure is set to 40 kPa or more, a facet growth mode ( ⁇ shape) is set, dislocations bend in the lateral direction, and do not penetrate the epitaxial surface. For this reason, it is presumed that by increasing the growth pressure, the dislocation is lowered and the crystallinity is improved. If the growth pressure is less than 40 kPa, the crystallinity is deteriorated and the half width (XRC-FWHM) of the X-ray rocking curve is increased, which is not preferable.
  • XRC-FWHM half width
  • the growth pressure is 40 kPa or more in the first half film formation, pits are likely to be generated on the surface of the epitaxially grown base layer 103, and sufficient surface flatness may not be obtained.
  • the growth temperature is preferably 1140 ° C. or less, and more preferably about 1120 ° C. By setting the growth temperature to 1140 ° C. or lower, the generation of pits can be sufficiently suppressed even when the growth pressure is 40 kPa or more, preferably about 60 kPa.
  • the growth pressure is preferably 40 kPa or less, more preferably about 20 kPa.
  • the base layer 103 can be formed by being doped with impurities as necessary, but undoped is preferable from the viewpoint of improving crystallinity. It is also possible to form the base layer 103 made of a group III nitride semiconductor by using a reactive sputtering method. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.
  • the stacked structure shown in FIG. 1 is obtained.
  • the base layer 103 is grown on the main surface 10 so as to cover the planar portion 11 and the convex portion 12. Since the epitaxial process is provided, crystal defects such as dislocations are not easily generated in the crystal of the base layer 103, and the base layer 103 in which the crystallinity is well controlled within an appropriate range can be formed.
  • the crystal defect which arose here is the semiconductor layer which comprises LED structure. If the light-emitting element is formed by the crystal, the internal quantum efficiency may be reduced and the leakage current may be increased.
  • the convex portion 12 made of the surface 12c that is non-parallel to the C plane is formed on the substrate 101, so that the flat portion 11 made of the C plane and the convex portion 12 are formed.
  • the main surface 10 is formed.
  • the base layer 103 is epitaxially grown on the main surface 10 of the substrate 101, crystals grow only from the planar portion 11. Therefore, the underlayer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown on the main surface 10 so as to cover the convex portions 12, and crystal defects such as dislocations do not occur in the crystal.
  • the interface between the substrate 101 and the base layer 103 is uneven via the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light. The extraction efficiency can be further improved.
  • (X-ray rocking curve half width) In the present invention, as described above, (10) of the base layer 103 in a state where the base layer 103 made of a group III nitride semiconductor is formed on the main surface 10 of the substrate 101 provided with the protrusions 12 by the epitaxial process. It is preferable that the X-ray rocking curve (XRC) half-width in the ⁇ 10) plane is 150 arcsec or more. If the X-ray rocking curve (XRC) half-value width in the (10-10) plane of the underlayer 103 is such a numerical value, the crystallinity of the underlayer 103 is well controlled within an appropriate range, and is formed thereon.
  • the LED structure 20 composed of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103.
  • MOCVD method Metal Organic Chemical Vapor Deposition
  • n-type semiconductor layer 104 is formed by sequentially laminating an n-type contact layer 104a and an n-type clad layer 104b on the base layer 103 formed by the epitaxial process using a conventionally known MOCVD method.
  • MOCVD apparatus used for forming the base layer 103 and the light-emitting layer 105 described later may be used by appropriately changing various conditions. Is possible.
  • the n-type contact layer 104a and the n-type cladding layer 104b can be formed by a reactive sputtering method.
  • the light emitting layer 105 is formed on the n-type cladding layer 104b (n-type semiconductor layer 104) by a conventionally known MOCVD method.
  • the light emitting layer 105 formed in the present embodiment has a stacked structure starting with a GaN barrier layer and ending with the GaN barrier layer. That is, seven barrier layers 105a made of GaN and six well layers 105b made of non-doped Ga 0.8 In 0.2 N are alternately stacked.
  • the light emitting layer 105 can be formed using the same film forming apparatus (MOCVD apparatus) used for forming the n-type semiconductor layer 104 described above.
  • a light emitting element that emits green light with an emission wavelength in the range of 490 to 570 nm can be configured.
  • the concentration of In contained in the well layer 105b is high, the growth temperature of the well layer 105b needs to be about 700 to 800 ° C., for example.
  • the lowering is achieved by controlling the half width.
  • the p-type semiconductor layer 106 composed of the p-type cladding layer 106a and the p-type contact layer 106b is formed on the light-emitting layer 105, that is, on the barrier layer 105a that is the uppermost layer of the light-emitting layer 105 by a conventionally known MOCVD method.
  • MOCVD method a conventionally known MOCVD method.
  • the same apparatus as the MOCVD apparatus used for forming the n-type semiconductor layer 104 and the light-emitting layer 105 can be used by appropriately changing various conditions.
  • the p-type cladding layer 106a and the p-type contact layer 106b constituting the p-type semiconductor layer 106 can be formed using a reactive sputtering method.
  • a p-type cladding layer 106a made of Al 0.1 Ga 0.9 N doped with Mg is formed on the light emitting layer 105 (the uppermost barrier layer 105a), and further, Mg A p-type contact layer 106b made of Al 0.02 Ga 0.98 N doped with is formed.
  • the same MOCVD apparatus can be used for stacking the p-type cladding layer 106a and the p-type contact layer 106b.
  • not only Mg but also zinc (Zn), for example, can be used as the p-type impurity.
  • electrodes are installed on the wafer on which the LED structure 20 is formed in the LED stacking step. Specifically, after forming a translucent positive electrode 109 at a predetermined position on the p-type semiconductor layer 106, a positive electrode bonding pad 107 is formed on each of the translucent positive electrodes 109. Also, the n-type semiconductor layer 104 is exposed by etching away a predetermined position of the LED structure 20 to form an exposed region 104c, and a negative electrode bonding pad 108 is formed in the exposed region 104c.
  • the translucent positive electrode 109 made of ITO is formed on the p-type contact layer 106b of the laminated semiconductor 10 in which each layer is formed by the above method.
  • a method for forming the translucent positive electrode 109 is not particularly limited, and the translucent positive electrode 109 can be provided by a common means well known in this technical field. Further, any structure including a conventionally known structure can be used without any limitation.
  • the material of the translucent positive electrode 109 is not limited to ITO, and can be formed using materials such as AZO, IZO, and GZO. Further, after forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
  • a positive electrode bonding pad 107 is further formed on the translucent positive electrode 109 formed on the laminated semiconductor 10.
  • the positive electrode bonding pad 107 can be formed, for example, by laminating Ti, Al, and Au materials in order from the surface side of the translucent positive electrode 109 by a conventionally known method.
  • the negative electrode bonding pad 108 when forming the negative electrode bonding pad 108, first, a part of the p-type semiconductor layer 106, the light emitting layer 105, and the n-type semiconductor layer 104 formed on the substrate 101 is removed by a method such as dry etching. The exposed region 104c of the n-type contact layer 104a is formed. Then, on this exposed region 104c, for example, each material of Ni, Al, Ti, and Au is sequentially laminated from the surface side of the exposed region 104c by a conventionally known method, thereby omitting detailed illustration.
  • the negative electrode bonding pad 108 can be formed.
  • the base width is 0.05 to 1.5 ⁇ m on the planar portion 11 made of the (0001) C plane of the substrate 101.
  • a substrate processing step of forming a plurality of convex portions 12 to form main surface 10 composed of flat portion 11 and convex portions 12 on substrate 101, and a group III nitride on main surface 10 of substrate 101 By epitaxially growing a semiconductor, an epitaxial process for forming a base layer so as to cover the planar portion 11 and the convex portion 12 and an LED structure 20 having the emission wavelength in the range of 490 to 570 nm are formed. LED lamination process.
  • the method for manufacturing a group III nitride semiconductor light emitting device it is possible to form the underlayer 103 with properly controlled crystallinity, and the LED structure 20 formed on this layer, particularly light emission.
  • the occurrence of lattice mismatch with the well layer 105b provided in the layer 105 is suppressed, and the well layer 105b (light-emitting layer 105) can be formed without causing distortion or the like.
  • the LED structure 20 exhibiting green light emission is formed, a group III nitride semiconductor light emitting device having excellent internal quantum efficiency and light extraction efficiency and having high light emission characteristics can be manufactured.
  • the group III nitride semiconductor light-emitting device of the present invention is used for the lamp of the present invention.
  • Examples of the lamp of the present invention include a combination of the group III nitride semiconductor light emitting device of the present invention and a phosphor.
  • a lamp in which a group III nitride semiconductor light emitting device and a phosphor are combined may be manufactured by means well known to those skilled in the art and may have a structure well known to those skilled in the art.
  • Conventionally, a technique for changing the emission color by combining a group III nitride semiconductor light-emitting element and a phosphor is known, and such a technique should be adopted in the lamp of the present invention without any limitation. Is possible.
  • FIG. 5 is a schematic view schematically showing an example of a lamp configured using the group III nitride semiconductor light emitting device according to the present invention.
  • the lamp 3 shown in FIG. 5 is a cannonball type, and the group III nitride semiconductor light emitting device 1 shown in FIG. 3 is used.
  • the group III nitride semiconductor light emitting device 1 is mounted. That is, the positive electrode bonding pad 107 of the group III nitride semiconductor light emitting device 1 is bonded to one of the two frames 31 and 32 (the frame 31 in FIG. 5) by the wire 33, and the negative electrode bonding pad of the light emitting device 1. 108 is bonded to the other frame 32 by a wire 34. Further, the periphery of the group III nitride semiconductor light emitting device 1 is sealed with a mold 35 made of a transparent resin.
  • the lamp of the present invention has excellent light emission characteristics.
  • the lamp of the present invention is not limited in shape and use, and can be used for any use such as a general-use bullet type, a side view type for a portable backlight, and a top view type used for a display.
  • Examples 1 and 2 A sapphire substrate having a plurality of (0001) C faces is prepared. On the (0001) C face of the sapphire substrate, “base width”, “height”, “base width / 4”, “ By forming a plurality of convex portions that satisfy the conditions of “interval between adjacent convex portions” and “presence / absence of convex surface C”, the substrates of Examples 1 and 2 and Comparative Example 1 are formed. Formed (substrate processing step). The convex portions were formed by forming a mask on a C-plane sapphire substrate having a diameter of 2 inches by a known photolithography method and etching the sapphire substrate by a dry etching method. As an exposure method, a stepper exposure method using ultraviolet light was used. In addition, a mixed gas of BCl 3 and Cl 2 was used for dry etching.
  • the convex portions of the substrates of Examples 1 and 2 and Comparative Example 1 obtained in this way have a shape in which the planar shape of the base of the convex portion is circular and the outer shape (cross-sectional area) gradually decreases toward the top. Yes, it had a bowl-like (hemispherical) shape with side surfaces curved outward.
  • a sapphire substrate having a principal surface made of a (0001) C surface without a convex portion without carrying out the substrate processing step as described above was prepared and used as a substrate of Comparative Example 2.
  • the thickness made of AlN having a single crystal structure using RF sputtering is used.
  • a 50 nm buffer layer was formed (buffer layer forming step).
  • the sputtering film forming apparatus an apparatus having a high-frequency power source and having a mechanism capable of moving the position of the magnet in the target was used.
  • a 50 nm thick buffer layer made of AlN having a single crystal structure was also formed on the main surface of the substrate of Comparative Example 2 having no protrusions using the same procedure described below.
  • a substrate having a plurality of convex portions was introduced into a chamber of a sputter deposition apparatus and heated to 500 ° C., and only nitrogen gas was introduced into the chamber at a flow rate of 15 sccm. Thereafter, the pressure in the chamber was maintained at 1 Pa, a high frequency bias of 500 W was applied to the substrate side, and the substrate was exposed to nitrogen plasma, thereby cleaning the surface of the substrate (pretreatment).
  • argon and nitrogen gas were introduced into the chamber, the pressure in the chamber was maintained at 0.5 Pa, and Ar gas was circulated at 5 sccm and nitrogen gas was circulated at 15 sccm. Under the conditions (the ratio of nitrogen to the whole gas is 75%), a high frequency bias of 2000 W is applied to the metal Al target side to start the formation of a buffer layer made of AlN on the substrate on which a plurality of convex portions are formed. It was. The growth rate was 0.08 nm / s. Note that the magnet in the target was swung both when the substrate was cleaned and when the buffer layer was formed.
  • film formation is performed for a prescribed time according to a film formation rate measured in advance, and after the buffer layer made of a 50 nm AlN layer is deposited on the substrate on which the plurality of convex portions are formed, the plasma is stopped from being generated. The substrate temperature was lowered.
  • an underlying layer made of a group III nitride semiconductor was epitaxially grown on the buffer layer thus obtained by using the low pressure MOCVD method described below (epitaxial process).
  • the substrate on which the buffer layer was formed was taken out from the sputter deposition apparatus. This substrate is introduced into a stainless steel vapor phase growth reactor used for the growth of a group III nitride semiconductor layer by MOCVD, and heated to a film formation temperature by a high frequency (RF) induction heating heater. The substrate was placed on a susceptor made of high-purity graphite for semiconductor in a reaction furnace. Thereafter, nitrogen gas was circulated in the reaction furnace to purge the reaction furnace.
  • RF high frequency
  • nitrogen gas was distribute
  • the induction heater was activated to raise the temperature of the sapphire substrate from room temperature to 500 ° C. in about 10 minutes.
  • the temperature of the substrate was kept at 500 ° C., and NH 3 gas and nitrogen gas were circulated in the reaction furnace.
  • the pressure in the vapor growth reactor was 95 kPa.
  • the temperature of the substrate was raised to 1000 ° C. over about 10 minutes, and the substrate surface was left under this temperature and pressure for 10 minutes to thermally clean the surface of the substrate. Even after the thermal cleaning was completed, the supply of nitrogen gas into the vapor phase growth reactor was continued.
  • the temperature of the substrate was raised to 1120 ° C. in a hydrogen atmosphere while continuing the flow of NH 3 gas, and the pressure in the reactor was 60 kPa. Then, after confirming that the temperature of the substrate was stabilized at 1120 ° C., supply of trimethylgallium (TMG) into the vapor phase growth reactor was started, and an undoped GaN layer having a thickness of 3 ⁇ m was formed on the AlN buffer layer. Until epitaxial growth. At this time, the amount of ammonia was adjusted so that the V group (N) / III group (Ga) ratio was 600. Then, after the growth of a base layer made of 3 ⁇ m of GaN (Group III nitride semiconductor), the supply of the raw material to the reaction furnace was stopped, and the temperature of the substrate was lowered.
  • TMG trimethylgallium
  • the substrate on which the buffer layer and the underlayer were formed was taken out from the reaction furnace, and the X-ray rocking curve (XRC) half widths of the (10-10) plane and the (0002) plane of the underlayer were measured. Indicated.
  • the X-ray rocking curve (XRC) on the (0002) plane represents the flatness of the crystal.
  • the sample of Comparative Example 1 in which the base layer was formed via the buffer layer on the main surface of the substrate having the base width of the protrusions of 2 nm is the XRC half of the (10-10) plane. It can be seen that the value width is 121 arcsec, the XRC half-value width of the (0002) plane is 38 arcsec, and the crystallinity of the underlayer is greatly enhanced. Further, in the sample of Comparative Example 2 in which the base layer is formed on the main surface of the substrate on which the convex portion is not formed via the buffer layer, the XRC half-value width of the (10-10) plane is 220 arcsec and the (0002) plane. The XRC half-value width is 36 arcsec, indicating that the crystallinity of the underlayer is inferior.
  • Example 1 in which the base layer was formed on the main surface of the substrate with the base width of the convex portion being 1 ⁇ m so as to cover the convex portion through the buffer layer is the (10-10) plane
  • the XRC half width was 171 arcsec
  • the XRC half width of the (0002) plane was 40 arcsec.
  • the sample of Example 1 has a smaller XRC half-value width, that is, improved crystallinity, as compared with Comparative Example 2 in which the base layer is formed on the substrate on which no convex portion is formed.
  • the sample of Example 1 has a larger XRC half-value width, that is, lower crystallinity than Comparative Example 1 in which the base layer is formed on the substrate on which the base width is as large as 2 ⁇ m. It is apparent that the crystallinity of the underlayer is controlled by controlling the dimensions of the convex portions formed on the substrate.
  • an n-type semiconductor layer constituting an LED structure is formed on the base layer made of a group III nitride semiconductor produced by the same method as in Examples 1 and 2 and Comparative Examples 1 and 2 by the following method.
  • the light emitting layer and the p-type semiconductor layer were laminated in this order to produce a light emitting element as shown in FIG. 3 (see also FIG. 4).
  • a lamp (light emitting diode: LED) using the light emitting element as shown in FIG. 5 was manufactured using the light emitting element.
  • n-type contact layer 104a made of GaN was formed on the underlayer 103 by the same MOCVD apparatus. At this time, the n-type contact layer 104a was doped with Si. Crystal growth was performed under the same conditions as the underlayer except that SiH 4 was circulated as a Si dopant material.
  • An n-type contact layer was formed by the process as described above. That is, an AlN buffer layer 102 having a single crystal structure is formed on a substrate 101 made of sapphire whose surface is reverse-sputtered, and an undoped GaN layer (underlayer 103) having a thickness of 8 ⁇ m is formed thereon. A 2 ⁇ m Si-doped GaN layer (n-type contact layer 104a) having a carrier concentration of 5 ⁇ 10 18 cm ⁇ 3 was formed. The substrate taken out from the apparatus after film formation was colorless and transparent, and the surface of the GaN layer (here, the initial layer forming the n-type contact layer 104a) was a mirror surface.
  • n-type cladding layer 104b was stacked on the n-type contact layer 104a produced by the above procedure by MOCVD.
  • the substrate on which the n-type contact layer 104a was grown by the above procedure was introduced into an MOCVD apparatus, and then the substrate temperature was lowered to 760 ° C. with nitrogen as the carrier gas while circulating the NH 3 gas. While waiting for the temperature change in the furnace, the NH 3 gas was continuously supplied into the furnace at the same flow rate. At this time, the supply amount of SiH 4 was set while waiting for the temperature change in the furnace. That is, the amount of SiH 4 to be distributed was calculated in advance, and the amount of SiH 4 was adjusted so that the electron concentration of the Si-doped layer was 4 ⁇ 10 18 cm ⁇ 3 .
  • a calculated amount of SiH 4 gas and TMI and TEG vapor generated by bubbling are circulated into the furnace, and a layer composed of Ga 0.99 In 0.01 N is formed.
  • a layer composed of Ga 0.99 In 0.01 N was formed with a thickness of 1.7 nm and a layer made of GaN with a thickness of 1.7 nm.
  • a layer made of Ga 0.99 In 0.01 N was grown at 1.7 nm.
  • the SiH 4 flow was continued during this process.
  • an n-type cladding layer 104b having a superlattice structure of Si-doped Ga 0.99 In 0.01 N and GaN was formed.
  • the light emitting layer 105 was laminated
  • the light emitting layer 105 has a multiple quantum well structure including a barrier layer 105a made of GaN and a well layer 105b made of Ga 0.85 In 0.15 N.
  • a barrier layer 105a is first formed on an n-type cladding layer 104c having a superlattice structure of Si-doped GaInN and GaN, and Ga 0.85 In is formed on the barrier layer 105a.
  • a well layer 105b made of 0.15 N was formed.
  • a seventh barrier layer 105a is formed on the sixth stacked well layer 105b, on both sides (upper and lower) of the light emitting layer 105 having a multiple quantum well structure.
  • the barrier layer 105a is provided.
  • the light emitting layer 105 was formed by the following method.
  • the barrier layer 105a of the light emitting layer 105 was formed as follows. With the substrate temperature kept at 760 ° C., supply of TEG and SiH 4 into the furnace was started, and an initial barrier layer made of GaN doped with Si for a predetermined time was formed to 0.8 nm, and then TEG and SiH 4 Supply was stopped. Thereafter, the temperature of the susceptor was raised to 920 ° C. Then, the supply of TEG and SiH 4 into the furnace was restarted, and the 1.7 nm intermediate barrier layer was grown while the substrate temperature remained at 920 ° C., and then the supply of TEG and SiH 4 into the furnace was stopped. did.
  • the susceptor temperature is lowered to 760 ° C.
  • the supply of TEG and SiH 4 is started
  • the final barrier layer of 3.5 nm is grown
  • the supply of TEG and SiH 4 is stopped again, and the GaN Finished the growth of the barrier layer.
  • an Si-doped GaN barrier layer (barrier layer 105a) having a total film thickness of 6 nm, which is composed of an initial barrier layer, an intermediate barrier layer, and a final barrier layer, is formed. did.
  • the amount of SiH 4 was adjusted so that the Si concentration was 1 ⁇ 10 17 cm ⁇ 3 .
  • the well layer 105b of the light emitting layer 105 was formed as follows. After the growth of the GaN barrier layer (barrier layer 105a) is completed, TEG and TMI are supplied into the furnace to form a well layer, and a Ga 0.85 In 0.15 N layer having a thickness of 3 nm is formed. (Well layer 105b) was formed on barrier layer 105a. During the deposition process of the well layer 105b, the In concentration of the well layer 105b was 8%, and the substrate temperature during growth was 750 ° C. Then, after the growth of the well layer 105b made of Ga 0.85 In 0.15 N, the setting of the TEGa supply amount was changed. Subsequently, the supply of TEGa and SiH 4 was restarted, and the second barrier layer 105a was formed.
  • barrier layers 105a made of Si-doped GaN and six layers of well layers 105b made of Ga 0.85 In 0.15 N are formed alternately. did.
  • a seventh barrier layer was formed.
  • the supply of SiH 4 was stopped, and an initial barrier layer made of undoped GaN was formed.
  • the substrate temperature is raised to 920 ° C. while the supply of the TEG into the furnace is continued, and the intermediate barrier layer is grown at the substrate temperature of 920 ° C. for a specified time.
  • the supply to was stopped.
  • the substrate temperature was lowered to 760 ° C., the supply of TEG was started, and the final barrier layer was grown. Thereafter, the supply of TEG was stopped again, and the growth of the GaN barrier layer was completed.
  • a seventh barrier layer made of undoped GaN having an initial barrier layer, an intermediate barrier layer, and a final barrier layer and having a total thickness of 4 nm was formed (in the light emitting layer 105 in FIG. 4).
  • top barrier layer 105a which uses the same reference number 105a but is not doped unlike the other barrier layers.
  • a well layer having a non-uniform thickness (the first to fifth well layers 105b from the n-type semiconductor layer 104 side in FIG. 4) and a well layer having a uniform thickness (the n-type in FIG. 4).
  • Formation of p-type semiconductor layer A superlattice composed of four layers of non-doped Al 0.06 Ga 0.94 N and three layers of Mg-doped GaN stacked alternately using the same MOCVD apparatus following the above-described steps. A p-type cladding layer 106 a having a structure was formed, and a p-type contact layer 106 b made of Mg-doped GaN having a thickness of 200 nm was formed thereon to form a p-type semiconductor layer 106.
  • the p-type semiconductor layer 106 was formed by the following method.
  • the p-type cladding layer 106a of the p-type semiconductor layer 106 was formed as follows. The substrate temperature was raised to 975 ° C. while supplying NH 3 gas, and then the carrier gas was switched from nitrogen to hydrogen at this temperature. Subsequently, the substrate temperature was changed to 1050 ° C. Then, by supplying TMG and TMA into the furnace, a 2.5 nm layer made of non-doped Al 0.06 Ga 0.94 N was formed. Subsequently, without taking an interval, the TMA valve was closed and the Cp 2 Mg valve was opened, and a Mg-doped GaN layer was deposited to 2.5 nm. The above operation was repeated three times, and finally a p-type cladding layer 106a having a superlattice structure was formed by forming an undoped Al 0.06 Ga 0.94 N layer.
  • the p-type contact layer 106b of the p-type semiconductor layer 106 was formed as follows. After forming the p-type cladding layer 106a, only Cp 2 Mg and TMG were supplied into the furnace to form a p-type contact layer 106b made of 200-nm p-type GaN. This p-type contact layer exhibited p-type characteristics even without annealing for activating p-type carriers.
  • the energization of the high-frequency induction heater used to heat the substrate is stopped immediately, and at the same time, the carrier gas is switched from hydrogen to nitrogen, and NH The flow rate of 3 gases was reduced. Specifically, during the growth, the amount of NH 3 gas that had been tightened by about 14% of the volume of the total circulation gas was reduced to 0.2%. Furthermore, after maintaining for 45 seconds in this state, the flow of NH 3 gas was stopped. In this state, it was confirmed that the substrate temperature was lowered to room temperature, and the substrate on which each layer was laminated was taken out into the atmosphere.
  • the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer constituting the LED structure are arranged in this order on the base layer manufactured in the same manner as in Examples 1-2 and Comparative Examples 1-2.
  • Samples (epitaxial wafers) of Examples 3 to 4 and Comparative Examples 3 to 4 formed in the above were produced.
  • the LED epitaxial wafer produced as described above has the following laminated structure. That is, after forming an AlN layer (buffer layer 102) having a single crystal structure on a substrate 101 made of sapphire having a c-plane, an 8 ⁇ m undoped GaN layer (underlayer 103), 5 ⁇ 10 18 cm -3 of 2 ⁇ m with electron concentration Si-doped GaNn type contact layer 104a, 4 has a Si concentration of ⁇ 10 18 cm -3, the 20 layers of 1.7nm Ga 0.99 in 0.01 N And 19 layers of a cladding layer (n-type cladding layer 104b) having a superlattice structure made of 1.7 nm of GaN.
  • a six-layer Si-doped GaN barrier layer (barrier layer 105a) that starts with the GaN barrier layer and ends with the GaN barrier layer and has a layer thickness of 6 nm, and a layer thickness of 3 nm 6 non-doped Ga 0.85 In 0.15 N well layers (well layers 105b) are alternately stacked, and the uppermost barrier layer made of non-doped GaN (the light emitting layer 105 in FIG.
  • a multi-quantum well structure (light-emitting layer 105) having a top barrier layer 105a in contact with the semiconductor layer 106 is stacked.
  • a p-type cladding layer 106a composed of three layers made of 0.01 Ga 0.99 N and having a superlattice structure, and a p-type contact layer 106b composed of Mg-doped GaN with a thickness of 200 nm.
  • a p-type semiconductor layer 106 is stacked.
  • a light-emitting diode which is a kind of semiconductor light-emitting element, was fabricated by the following procedure using the substrate on which each layer to be an LED structure obtained in this way was formed (see FIG. 3).
  • a light-transmitting positive electrode made of ITO is formed on a p-type contact layer of a substrate on which each layer to be an LED structure is formed by a known photolithography technique, and Ti, Al, and Au are sequentially formed on the light-transmitting positive electrode.
  • a positive electrode bonding pad having a laminated structure was formed.
  • dry etching was performed on the portion where the positive electrode bonding pad was not formed to expose the n-type semiconductor layer where the negative electrode bonding pad was formed.
  • a negative electrode bonding pad composed of four layers of Ni, Al, Ti, and Au was formed on the exposed n-type semiconductor layer.
  • substrate with which the positive electrode bonding pad and the negative electrode bonding pad were formed was ground and grind
  • the substrate was cut into 350 ⁇ m square chips to form LED chips. This chip was placed on the lead frame so that the positive electrode bonding pad and the negative electrode bonding pad were on top, and was connected to the lead frame with a gold wire to produce a lamp (see FIG. 5).
  • the forward voltage (driving voltage Vf) when a forward current of 20 mA was passed between the p-side electrode and the n-side electrode was measured, and the p-side transparency was measured.
  • the emission wavelength WD (nm) and the emission output Po (mW) were measured through the photocathode, and the results are shown in Table 2 below.
  • the samples of Examples 3 to 4 manufactured by the manufacturing method according to the present invention have a drive voltage Vf of 3.27 to 3.30 V, and an emission wavelength WD of 538 nm to 539 nm. While exhibiting good green light emission, the light emission output Po was 8.4 to 8.7 (mW).
  • the sample of Comparative Example 3 in which the base width of the convex portion of the substrate is 2 ⁇ m requires a driving voltage Vf of 3.37 V, which is higher than the samples of Examples 3 to 4, Further, the light emission output Po is 7.9 mW, which is lower than the samples of Examples 3 to 4. Further, in the sample of Comparative Example 4 having the conventional configuration in which the convex portion is not formed on the substrate, the driving voltage Vf is 3.35 V, and the light emission output Po is 7.7 mW. Luminous properties are inferior to the sample.
  • Example 1 In the same manner as in Examples 3 to 4, a 350 ⁇ m square Group III nitride semiconductor light emitting device chip was fabricated, and the lead frame was similarly placed so that the positive electrode bonding pad and the negative electrode bonding pad were on top. The sample was placed on top and connected to a lead frame with a gold wire to prepare a light emitting device sample. At this time, a sample in which the base width of the convex portion of the substrate was 1 ⁇ m was designated as Experimental Example 1, and a sample in which the base width of the convex portion was 2 ⁇ m was designated as Experimental Example 2, and five samples were produced. The emission intensity of each sample was measured while moving the detector in the direction perpendicular to the top surface of the chip, and the measurement results are shown in the graphs of FIGS. 6A and 6B.
  • the light-emitting element chip of Experimental Example 1 in which the interval between the protrusions formed on the substrate is 1 ⁇ m has an interval between the protrusions of 2 ⁇ m as shown in the graph of FIG. 6B. It can be seen that the light emission output is higher than that of the light emitting element chip of Experimental Example 2. From this result, it was found that the light emission output of the light emitting element can be improved when the interval between the convex portions formed on the substrate is smaller.
  • the group III nitride semiconductor light-emitting device of the present invention has excellent light extraction efficiency without reducing the internal quantum efficiency of the LED structure exhibiting green light emission, and high emission intensity. It is clear that
  • the present invention it is possible to provide a group III nitride semiconductor light-emitting device having excellent light extraction efficiency, a method for manufacturing the same, and a lamp without reducing the internal quantum efficiency of the LED structure that emits green light.

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Abstract

Provided is a III nitride semiconductor light emitting element wherein an LED structure is formed on a single crystalline III nitride semiconductor layer formed on a substrate.  The substrate has a main surface, which is composed of a flat surface section composed of a (0001)C surface and a plurality of protruding sections, and a rear surface, and the width of a base portion of the protruding section is 0.05-1.5μm.  The III nitride semiconductor layer is formed on the main surface of the substrate by epitaxially growing a III nitride semiconductor to cover the flat surface section and the protruding sections.  The emission wavelength of the LED structure is within the range of 490-570nm.

Description

ＩＩＩ族窒化物半導体発光素子及びその製造方法、並びにランプGroup III nitride semiconductor light emitting device, method for manufacturing the same, and lamp
　本発明は、発光ダイオード（ＬＥＤ）構造を有し、発光波長が４９０～５７０ｎｍであるＩＩＩ族窒化物半導体発光素子、及びその製造方法、並びにランプに関する。
　本願は、２００８年５月２１日に、日本に出願された特願２００８－１３３１９９号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a group III nitride semiconductor light-emitting device having a light-emitting diode (LED) structure and an emission wavelength of 490 to 570 nm, a method for manufacturing the same, and a lamp.
This application claims priority based on Japanese Patent Application No. 2008-133199 filed in Japan on May 21, 2008, the contents of which are incorporated herein by reference.
　近年、短波長の光を発する発光素子用の半導体材料として、ＩＩＩ族窒化物半導体が注目を集めている。ＩＩＩ族窒化物半導体は、一般式ＡｌｘＧａｙＩｎｚＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｚ≦１、ｘ＋ｙ＋ｚ＝１）で表され、サファイア単結晶をはじめ種々の酸化物やＩＩＩ－Ｖ族化合物からなる基板の上に、有機金属化学気相成長法（ＭＯＣＶＤ法）や分子線エピタキシー法（ＭＢＥ法）等によって形成される。 In recent years, group III nitride semiconductors have attracted attention as semiconductor materials for light-emitting elements that emit light of short wavelengths. Group III nitride semiconductors are represented by the general formula Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1), and include various sapphire single crystals. It is formed on a substrate made of an oxide or a III-V compound by a metal organic chemical vapor deposition method (MOCVD method), a molecular beam epitaxy method (MBE method), or the like.
　ＩＩＩ族窒化物半導体を用いた一般的な発光素子の例としては、サファイア単結晶基板の上に、ＩＩＩ族窒化物半導体からなるｎ型半導体層、発光層、及びｐ型半導体層をこの順で積層したものが挙げられる。サファイア基板は絶縁体である。よってサファイア基板を用いた上記素子構造は、一般的に、ｐ型半導体層上に形成された正極とｎ型半導体層上に形成された負極とが同一面上に横方向に存在する構造となる。このようなＩＩＩ族窒化物半導体発光素子には、正極に透明電極を使用してｐ型半導体側から光を取り出すフェイスアップ方式と、正極にＡｇなどの高反射膜を使用してサファイア基板側から光を取り出すフリップチップ方式との２種類がある。 As an example of a general light emitting device using a group III nitride semiconductor, an n-type semiconductor layer, a light emitting layer, and a p type semiconductor layer made of a group III nitride semiconductor are arranged in this order on a sapphire single crystal substrate. The thing laminated | stacked is mentioned. The sapphire substrate is an insulator. Therefore, the element structure using the sapphire substrate generally has a structure in which the positive electrode formed on the p-type semiconductor layer and the negative electrode formed on the n-type semiconductor layer are present on the same plane in the lateral direction. . In such a group III nitride semiconductor light-emitting device, a face-up method in which a transparent electrode is used as a positive electrode and light is extracted from the p-type semiconductor side, and a highly reflective film such as Ag is used as a positive electrode from the sapphire substrate side. There are two types, a flip chip type that extracts light.
　このような発光素子の出力の指標として、外部量子効率が用いられる。外部量子効率が高ければ、出力の高い発光素子と言うことができる。外部量子効率は、内部量子効率と光取り出し効率とを掛け合わせた値である。内部量子効率とは、素子に注入した電流のエネルギーが発光層で光に変換される割合である。光取り出し効率とは、発光層で発生した光のうち発光素子の外部に取り出すことができる光の割合である。従って、外部量子効率を向上させるには、光取り出し効率を改善する必要がある。 External quantum efficiency is used as an index of the output of such a light emitting element. If the external quantum efficiency is high, it can be said that the light-emitting element has a high output. The external quantum efficiency is a value obtained by multiplying the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency is a rate at which the energy of current injected into the device is converted into light in the light emitting layer. The light extraction efficiency is a ratio of light that can be extracted outside the light emitting element among light generated in the light emitting layer. Therefore, in order to improve the external quantum efficiency, it is necessary to improve the light extraction efficiency.
　光取り出し効率を改善するためには、主として２つの方法がある。一つは、光取り出し面に形成される電極等による光の吸収を低減させる方法である。もう一つは、発光素子とその外部に位置する媒体との屈折率の違いによって生じる発光素子の内部への光の閉じ込めを低減させる方法である。 There are mainly two methods for improving the light extraction efficiency. One is a method of reducing light absorption by an electrode or the like formed on the light extraction surface. The other is a method of reducing the confinement of light inside the light emitting element caused by the difference in refractive index between the light emitting element and the medium located outside the light emitting element.
　発光素子の内部への光の閉じ込めを低減させる方法としては、発光素子の光取り出し面に凹凸を形成する技術が挙げられる（例えば、特許文献１参照）。
　しかしながら、機械的加工又は化学的加工によって光取り出し面に凹凸を形成した発光素子では、光取り出し面に加工を施すことで、光取り出し面を有する半導体層に負荷を掛けることになり、発光層にダメージを残してしまう。また、光取り出し面に凹凸が形成されるような条件で半導体層を成長させた発光素子では、半導体層の結晶性が劣化してしまうため、発光層が欠陥を含んだものになる。このため、光取り出し面に凹凸を形成した場合、光取り出し効率は向上するものの、内部量子効率が低下してしまい、発光強度を増加させることができないという問題がある。 As a method for reducing the confinement of light inside the light emitting element, there is a technique of forming irregularities on the light extraction surface of the light emitting element (for example, see Patent Document 1).
However, in a light emitting device in which unevenness is formed on the light extraction surface by mechanical processing or chemical processing, by processing the light extraction surface, a load is applied to the semiconductor layer having the light extraction surface. It will leave damage. In addition, in a light-emitting element in which a semiconductor layer is grown under conditions where irregularities are formed on the light extraction surface, the crystallinity of the semiconductor layer is deteriorated, so that the light-emitting layer includes a defect. For this reason, when unevenness is formed on the light extraction surface, although the light extraction efficiency is improved, there is a problem that the internal quantum efficiency is lowered and the emission intensity cannot be increased.
　一方で、ＩＩＩ族窒化物半導体発光素子として、発光波長が４９０～５７０ｎｍである緑色発光を呈する素子が、このような発光色を必要とする各分野において用いられるようになっている。一般に、発光波長が４９０ｎｍ以上の長い波長の場合には、発光色は緑色系となる。例えば、発光波長が５０５ｎｍ付近であると、信号機等に用いられるような青緑色を呈する。また、発光波長が５２５ｎｍ付近では、例えばディスプレイ等の３原色光源として用いられるような純緑色が得られる。また、発光波長が５６０ｎｍ付近であると、例えばパイロットランプ等に用いられるような黄緑色が得られ、発光波長が５７０ｎｍになると発光色が黄色に近い色調となる。このように緑色発光を得るためには、発光波長が４９０ｎｍ以上である必要がある。 On the other hand, as a group III nitride semiconductor light emitting element, an element that emits green light having an emission wavelength of 490 to 570 nm is used in various fields that require such an emission color. Generally, when the emission wavelength is a long wavelength of 490 nm or longer, the emission color is green. For example, when the emission wavelength is around 505 nm, a blue-green color used for a traffic light or the like is exhibited. Further, when the emission wavelength is in the vicinity of 525 nm, a pure green color that is used as a light source for three primary colors such as a display can be obtained. Further, when the emission wavelength is near 560 nm, a yellowish green color used for, for example, a pilot lamp is obtained, and when the emission wavelength is 570 nm, the emission color becomes a color tone close to yellow. Thus, in order to obtain green light emission, the emission wavelength needs to be 490 nm or more.
　窒化ガリウム系化合物半導体（ＩＩＩ族窒化物半導体）発光素子において、発光波長が４９０ｎｍ以上の緑色発光を得るためには、発光層に含まれる井戸層（活性層）に含有されるインジウム（Ｉｎ）の濃度を高くする必要がある。しかしながら、インジウム濃度を高めた場合には格子定数が大きくなり、発光層よりも下側に位置する下層側（基板側）の層や障壁層との格子定数の差が大きくなる。このことから発光層内部に歪みが生じ、内部量子効率の低下を招くという問題がある。また、インジウムは蒸発し易い。このため、障壁層を形成するための昇温過程において、井戸層からインジウムが蒸発し、その結果、結晶性が低下して発光層内部に歪みが生じ、内部量子効率の低下を招くという問題も発生する。 In a gallium nitride compound semiconductor (Group III nitride semiconductor) light emitting device, in order to obtain green light emission having an emission wavelength of 490 nm or more, indium (In) contained in a well layer (active layer) included in the light emitting layer is used. It is necessary to increase the concentration. However, when the indium concentration is increased, the lattice constant increases, and the difference in lattice constant between the lower layer (substrate side) layer and the barrier layer located below the light emitting layer increases. For this reason, there is a problem that distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. Moreover, indium is easy to evaporate. For this reason, in the temperature rising process for forming the barrier layer, indium evaporates from the well layer, and as a result, the crystallinity is lowered and distortion occurs in the light emitting layer, leading to a decrease in internal quantum efficiency. appear.
　近年、光取り出し効率及び結晶性の向上を目的として、光取り出し面に凹凸を形成するのではなく、サファイアからなる基板の表面に凹凸を形成し、その上にＩＩＩ族窒化物半導体層を成長させる方法が提案されている（例えば、特許文献２参照）。このような方法によれば、サファイア基板とＩＩＩ族窒化物半導体層との界面が凹凸となるので、サファイア基板とＩＩＩ族窒化物半導体層との屈折率の違いによる界面での光の乱反射により、発光素子の内部への光の閉じ込めを低減させることができ、光取り出し効率を向上させることができる。また、サファイア基板の表面に形成された凹凸により、結晶が横方向に成長するのを利用して結晶欠陥を低減させ、内部量子効率を向上させることが可能となる。 In recent years, for the purpose of improving light extraction efficiency and crystallinity, instead of forming irregularities on the light extraction surface, irregularities are formed on the surface of a substrate made of sapphire, and a group III nitride semiconductor layer is grown thereon. A method has been proposed (see, for example, Patent Document 2). According to such a method, since the interface between the sapphire substrate and the group III nitride semiconductor layer becomes uneven, due to irregular reflection of light at the interface due to the difference in refractive index between the sapphire substrate and the group III nitride semiconductor layer, Light confinement inside the light emitting element can be reduced, and light extraction efficiency can be improved. In addition, the unevenness formed on the surface of the sapphire substrate makes it possible to reduce crystal defects and improve internal quantum efficiency by utilizing the lateral growth of crystals.
　しかしながら、特許文献２に記載されたような凹凸が形成された基板を用いて、上述のような、インジウム濃度を高めた緑色発光を呈する発光層を有するＩＩＩ族窒化物半導体発光素子を構成した場合、発光層よりも下側に位置する層の結晶性が横方向成長により大きく向上するために、発光層と下層側との間の結晶性の違いがさらに大きくなる。このため、発光層と下層側との間との間の格子不整合が大きくなり、基板側のＩＩＩ族窒化物半導体層の結晶性が向上しているのにも関わらず、発光層内に大きな歪みが生じて内部量子効率が低下し、発光強度が低下するという問題があった。 However, when a group III nitride semiconductor light-emitting device having a light-emitting layer exhibiting green light emission with an increased indium concentration as described above is configured using a substrate on which irregularities as described in Patent Document 2 are formed. Since the crystallinity of the layer located below the light emitting layer is greatly improved by lateral growth, the difference in crystallinity between the light emitting layer and the lower layer side is further increased. For this reason, the lattice mismatch between the light emitting layer and the lower layer side is increased, and the crystallinity of the group III nitride semiconductor layer on the substrate side is improved, but a large amount is present in the light emitting layer. There is a problem that distortion occurs, the internal quantum efficiency decreases, and the light emission intensity decreases.
特許第２８３６６８７号公報Japanese Patent No. 2836687 特開２００２－２８０６１１号公報JP 2002-280611 A
　本発明は上記課題に鑑みてなされたものであり、緑色発光を呈するＬＥＤ構造の内部量子効率を低下させることなく、光取り出し効率に優れたＩＩＩ族窒化物半導体発光素子及びその製造方法を提供することを目的とする。
　さらに、本発明は、上記ＩＩＩ族窒化物半導体発光素子が用いられてなり、発光特性に優れたランプを提供することを目的とする。 The present invention has been made in view of the above problems, and provides a group III nitride semiconductor light-emitting device excellent in light extraction efficiency and a manufacturing method thereof without reducing the internal quantum efficiency of an LED structure that emits green light. For the purpose.
Furthermore, an object of the present invention is to provide a lamp that uses the above-mentioned group III nitride semiconductor light emitting device and has excellent light emission characteristics.
　本発明者は、上記問題を解決するために鋭意検討した結果、本発明を以下のように完成した。（[１]、[１５]及び[３１]以外は本発明の好ましい例を示す。） As a result of intensive studies to solve the above problems, the present inventor has completed the present invention as follows. (Except for [1], [15] and [31], preferred examples of the present invention are shown.)
　［１］　基板上に形成された単結晶のＩＩＩ族窒化物半導体層上にＬＥＤ構造が形成されたＩＩＩ族窒化物半導体発光素子であって、
　前記基板は、（０００１）Ｃ面からなる平面部と複数の凸部とからなる主面と、裏面とを有し、前記凸部の基部幅が０．０５～１．５μｍであり、
　前記ＩＩＩ族窒化物半導体層は、ＩＩＩ族窒化物半導体がエピタキシャル成長することによって前記基板の主面上に、前記平面部及び前記凸部を覆い形成されたものであり、
　前記ＬＥＤ構造の発光波長は４９０～５７０ｎｍの範囲であることを特徴とするＩＩＩ族窒化物半導体発光素子。
　［２］　前記凸部は、前記Ｃ面に非並行の表面により構成されることを特徴とする上記［１］に記載のＩＩＩ族窒化物半導体発光素子。
　［３］　前記凸部は、前記基部幅が０．０５～１μｍであり、高さが０．０５～１μｍの範囲であり且つ前記基部幅の１／４以上であり、隣接する前記凸部間の間隔が前記基部幅の０．５～５倍であることを特徴とする［１］又は［２］に記載のＩＩＩ族窒化物半導体発光素子。
　［４］　前記凸部が上部に向かって徐々に外形が小さくなる形状であることを特徴とする上記［１］～［３］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［５］　前記凸部が略円錐状ないし略多角錐状であることを特徴とする上記［１］～［４］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［６］　前記凸部が、前記基板のＣ面上に設けられた酸化物又は窒化物であることを特徴とする上記［１］～［５］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［７］　前記凸部が、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、ＺｎＯの何れかからなることを特徴とする上記［６］に記載のＩＩＩ族窒化物半導体発光素子。
　［８］　前記基板がサファイア基板であることを特徴とする上記［１］～［７］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。 [1] A group III nitride semiconductor light emitting device in which an LED structure is formed on a single crystal group III nitride semiconductor layer formed on a substrate,
The substrate has a main surface composed of a flat portion made of a (0001) C plane and a plurality of convex portions, and a back surface, and the base width of the convex portion is 0.05 to 1.5 μm
The group III nitride semiconductor layer is formed so as to cover the planar portion and the convex portion on the main surface of the substrate by epitaxial growth of the group III nitride semiconductor.
The group III nitride semiconductor light-emitting device characterized in that the light emission wavelength of the LED structure is in the range of 490 to 570 nm.
[2] The group III nitride semiconductor light-emitting device according to the above [1], wherein the convex portion is configured by a surface non-parallel to the C-plane.
[3] The convex portion has a base width of 0.05 to 1 μm, a height in the range of 0.05 to 1 μm, and ¼ or more of the base width, and between adjacent convex portions. The group III nitride semiconductor light-emitting device according to [1] or [2], wherein the interval is 0.5 to 5 times the base width.
[4] The group III nitride semiconductor light-emitting device according to any one of the above [1] to [3], wherein the convex portion has a shape whose outer shape gradually decreases toward the top.
[5] The group III nitride semiconductor light-emitting device according to any one of [1] to [4], wherein the convex portion has a substantially conical shape or a substantially polygonal pyramid shape.
[6] The group III nitride according to any one of [1] to [5], wherein the convex portion is an oxide or a nitride provided on the C-plane of the substrate. Semiconductor light emitting device.
[7] The group III nitride semiconductor light-emitting device according to the above [6], wherein the convex portion is made of any one of SiO 2 , Al 2 O 3 , SiN, and ZnO.
[8] The group III nitride semiconductor light-emitting device according to any one of [1] to [7], wherein the substrate is a sapphire substrate.
　［９］　前記ＬＥＤ構造は、前記基板の主面上に、ＩＩＩ族窒化物半導体から各々がなる、ｎ型半導体層、発光層及びｐ型半導体層をこの順で有することを特徴とする上記［１］～［８］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［１０］　前記ＬＥＤ構造に備えられる発光層のＩｎ濃度が７質量％以上であることを特徴とする上記［９］に記載のＩＩＩ族窒化物半導体発光素子。
　［１１］　前記基板の主面上に、多結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなり、厚さが０．０１～０．５μｍであるバッファ層がスパッタ法によって積層され、前記バッファ層上に前記ＩＩＩ族窒化物半導体層が積層されていることを特徴とする上記［１］～［１０］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［１２］　前記基板の主面上に、単結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなり、厚さが０．０１～０．５μｍであるバッファ層がスパッタ法によって積層され、前記バッファ層上に前記ＩＩＩ族窒化物半導体層が積層されていることを特徴とする上記［１］～［１０］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［１３］　前記ｎ型半導体層にｎ型クラッド層を含むとともに、前記ｐ型半導体層がｐ型クラッド層を含んでおり、前記ｎ型クラッド層及び前記ｐ型クラッド層の少なくとも一つが超格子構造を含むことを特徴とする上記［８］～［１２］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。
　［１４］　前記ＩＩＩ族窒化物半導体層の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることを特徴とする上記［１］～［１３］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子。 [9] The LED structure includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, each of which is made of a group III nitride semiconductor, in this order on the main surface of the substrate. [1] The group III nitride semiconductor light-emitting device according to any one of [8].
[10] The group III nitride semiconductor light-emitting device according to [9], wherein an In concentration of the light-emitting layer provided in the LED structure is 7% by mass or more.
[11] A buffer layer made of polycrystalline Al x Ga 1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm is stacked on the main surface of the substrate by sputtering. The group III nitride semiconductor light-emitting device according to any one of the above [1] to [10], wherein the group III nitride semiconductor layer is stacked on the buffer layer.
[12] A buffer layer made of single-crystal Al x Ga 1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm is stacked on the main surface of the substrate by sputtering. The group III nitride semiconductor light-emitting device according to any one of the above [1] to [10], wherein the group III nitride semiconductor layer is stacked on the buffer layer.
[13] The n-type semiconductor layer includes an n-type cladding layer, the p-type semiconductor layer includes a p-type cladding layer, and at least one of the n-type cladding layer and the p-type cladding layer has a superlattice structure. The group III nitride semiconductor light-emitting device according to any one of the above [8] to [12], comprising:
[14] Any one of [1] to [13] above, wherein a half width of an X-ray rocking curve (XRC) in the (10-10) plane of the group III nitride semiconductor layer is 150 arcsec or more. A group III nitride semiconductor light-emitting device according to item 2.
　［１５］前記　前記基板の（０００１）Ｃ面からなる平面上に、基部幅が０．０５～１．５μｍである複数の凸部を形成することにより、前記基板上に平面部と凸部とからなる主面を形成する基板加工工程と、
　前記基板の主面上に、ＩＩＩ族窒化物半導体をエピタキシャル成長させることにより、前記平面部及び前記凸部を覆う、単結晶のＩＩＩ族窒化物半導体層を形成するエピタキシャル工程と、
　前記ＩＩＩ族窒化物半導体層上に、発光波長が４９０～５７０ｎｍの範囲であるＬＥＤ構造を前記形成するＬＥＤ積層工程と、を含むことを特徴とするＩＩＩ族窒化物半導体発光素子の製造方法。
　［１６］　基板加工工程において、前記凸部の表面が、前記Ｃ面に非並行の表面により構成されるように形成することを特徴とする上記［１５］に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［１７］　前記基板加工工程において、前記基部幅が０．０５～１μｍ、高さが０．０５～１μｍの範囲であって且つ前記基部幅の１／４以上であり、隣接する前記凸部間の間隔が前記基部幅の０．５～５倍である前記凸部を形成することを特徴とする［１５］又は［１６］に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［１８］前記基板加工工程において、前記凸部として上部に向かって徐々にその外形が小さくなる形状が形成されることを特徴とする上記［１５］～［１７］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［１９］　前記基板加工工程において、前記凸部が、略円錐状ないし略多角錐状に形成されることを特徴とする上記［１５］～［１８］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２０］　前記基板がサファイア基板であることを特徴とする上記［１５］～［１９］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２１］　前記基板加工工程において、前記基板の（０００１）Ｃ面上に、ステッパー露光法、ナノインプリント法、電子ビーム（ＥＢ）露光法、レーザー露光法の内の何れかを用いてマスクパターンを形成した後、前記基板をエッチングすることによって、前記凸部が形成されることを特徴とする上記［１５］～［２０］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２２］　前記凸部を、前記基板のＣ面上に、酸化物又は窒化物から形成することを特徴とする上記［１５］～［２０］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２３］　前記凸部を、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、ＺｎＯの何れかから形成することを特徴とする上記［２２］に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 [15] By forming a plurality of convex portions having a base width of 0.05 to 1.5 μm on a plane composed of the (0001) C plane of the substrate, the plane portions and the convex portions are formed on the substrate. A substrate processing step for forming a main surface comprising:
An epitaxial step of forming a single crystal group III nitride semiconductor layer covering the planar portion and the convex portion by epitaxially growing a group III nitride semiconductor on the main surface of the substrate;
A method of manufacturing a group III nitride semiconductor light emitting device, comprising: an LED stacking step of forming an LED structure having an emission wavelength in the range of 490 to 570 nm on the group III nitride semiconductor layer.
[16] The group III nitride semiconductor light-emitting device according to [15], wherein in the substrate processing step, the surface of the convex portion is formed by a surface non-parallel to the C-plane Manufacturing method.
[17] In the substrate processing step, the base width is in the range of 0.05 to 1 μm, the height is in the range of 0.05 to 1 μm, and is ¼ or more of the base width, and between the adjacent convex portions. The method for producing a group III nitride semiconductor light-emitting device according to [15] or [16], wherein the convex portions having an interval of 0.5 to 5 times the base width are formed.
[18] The substrate processing step according to any one of [15] to [17], wherein the convex portion is formed with a shape whose outer shape gradually decreases toward the top. A method for manufacturing a group III nitride semiconductor light-emitting device.
[19] The group III nitride according to any one of [15] to [18], wherein in the substrate processing step, the convex portion is formed in a substantially conical shape or a substantially polygonal pyramid shape. For manufacturing a semiconductor light emitting device.
[20] The method for producing a group III nitride semiconductor light-emitting device according to any one of the above [15] to [19], wherein the substrate is a sapphire substrate.
[21] In the substrate processing step, a mask pattern is formed on the (0001) C surface of the substrate using one of a stepper exposure method, a nanoimprint method, an electron beam (EB) exposure method, and a laser exposure method. The method for producing a Group III nitride semiconductor light-emitting device according to any one of [15] to [20] above, wherein the convex portion is formed by etching the substrate.
[22] The group III nitride semiconductor according to any one of [15] to [20], wherein the convex portion is formed of an oxide or a nitride on the C-plane of the substrate. Manufacturing method of light emitting element.
[23] The method for producing a group III nitride semiconductor light-emitting element according to the above [22], wherein the convex portion is formed of any one of SiO 2 , Al 2 O 3 , SiN, and ZnO.
　［２４］　前記ＬＥＤ積層工程において、前記基板の主面上に、ＩＩＩ族窒化物半導体から各々なるｎ型半導体層、発光層及びｐ型半導体層をこの順で積層して前記ＬＥＤ構造が形成されることを特徴とする上記［１５］～［２３］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２５］　前記ＬＥＤ積層工程において、前記ＬＥＤ構造に備えられる発光層のＩｎ濃度が７質量％以上であることを特徴とする上記［２４］に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２６］　前記基板加工工程の後であって、前記エピタキシャル工程の前に、前記基板の主面上に多結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなる厚さ０．０１～０．５μｍのバッファ層を、スパッタ法によって積層するバッファ層形成工程が含まれることを特徴とする［１５］～［２５］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２７］　前記基板加工工程の後、前記エピタキシャル工程の前に、前記基板の主面上に単結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなる厚さ０．０１～０．５μｍのバッファ層を、スパッタ法によって積層するバッファ層形成工程が備えられていることを特徴とする上記［１５］～［２５］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２８］　前記ＬＥＤ積層工程において、前記ｎ型半導体層にｎ型クラッド層が含まれ、前記ｐ型半導体層にｐ型クラッド層が含まれ、且つ、前記ｎ型クラッド層及び前記ｐ型クラッド層の少なくとも一つが超格子構造を含む層であることを特徴とする上記［２４］～［２７］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。
　［２９］　前記エピタキシャル工程において、前記凸部を備えた前記基板の主面上に前記ＩＩＩ族窒化物半導体層を形成した後の、前記ＩＩＩ族窒化物半導体層の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることを特徴とする上記［１５］～［２８］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 [24] In the LED stacking step, the LED structure is formed by stacking an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor in this order on the main surface of the substrate. The method for producing a group III nitride semiconductor light-emitting device according to any one of the above [15] to [23], wherein
[25] The method for producing a group III nitride semiconductor light-emitting element according to the above [24], wherein, in the LED stacking step, an In concentration of a light-emitting layer provided in the LED structure is 7% by mass or more.
[26] After the substrate processing step, and before the epitaxial step, a thickness of 0.1% of the polycrystalline Al x Ga 1-x N (0 ≦ x ≦ 1) is formed on the main surface of the substrate. The group III nitride semiconductor light-emitting device according to any one of [15] to [25], wherein a buffer layer forming step of laminating a buffer layer of 01 to 0.5 μm by a sputtering method is included. Production method.
[27] After the substrate processing step and before the epitaxial step, a thickness of 0.01 to 0 made of single crystal Al x Ga 1-x N (0 ≦ x ≦ 1) on the main surface of the substrate A group III nitride semiconductor light-emitting device according to any one of the above [15] to [25], further comprising a buffer layer forming step of stacking a buffer layer of .5 μm by sputtering. Production method.
[28] In the LED stacking step, the n-type semiconductor layer includes an n-type cladding layer, the p-type semiconductor layer includes a p-type cladding layer, and the n-type cladding layer and the p-type cladding layer. The method for producing a group III nitride semiconductor light-emitting device according to any one of the above [24] to [27], wherein at least one of the layers is a layer containing a superlattice structure.
[29] X in the (10-10) plane of the group III nitride semiconductor layer after forming the group III nitride semiconductor layer on the main surface of the substrate having the convex portion in the epitaxial step. The method for producing a group III nitride semiconductor light-emitting device according to any one of the above [15] to [28], wherein the line rocking curve (XRC) half width is 150 arcsec or more.
　［３０］　上記［１５］～［２９］の何れか１項に記載の製造方法によって得られるＩＩＩ族窒化物半導体発光素子。
　［３１］　上記［１］～［１４］、及び［３０］の何れか１項に記載のＩＩＩ族窒化物半導体発光素子が用いられてなることを特徴とするランプ。 [30] A group III nitride semiconductor light-emitting device obtained by the manufacturing method according to any one of [15] to [29].
[31] A lamp comprising the group III nitride semiconductor light-emitting device according to any one of [1] to [14] and [30].
　本発明のＩＩＩ族窒化物半導体発光素子によれば、基板が、（０００１）Ｃ面からなるの平面部と複数の凸部とからなる主面と、裏面とを有するものであり、凸部の基部幅が０．０５～１．５μｍである。また、ＩＩＩ族窒化物半導体層は、基板の主面上に、前記平面部及び凸部を覆うようにＩＩＩ族窒化物半導体がエピタキシャル成長することにより形成されたものである。また、ＬＥＤ構造における発光波長は４９０～５７０ｎｍの範囲である。上記の特徴により、本発明では、ＩＩＩ族窒化物半導体層の結晶性を適正に制御することができ、この層の上にさらに積層されるＬＥＤ構造との間で格子不整合が生じるのを抑制することができる。
　また、基板の凸部が、Ｃ面に非並行の表面により構成されることにより、上記効果がより顕著となり、格別な効果が得られる。
　これらの特徴により、緑色発光を呈するＬＥＤ構造に歪み等が生じることが無く、内部量子効率の低下やリーク電流が生じるのを抑制することができるので、電気的特性に優れるとともに発光出力が高いＩＩＩ族窒化物半導体発光素子が得られる。また、基板とＩＩＩ族窒化物半導体層との界面が凹凸であるので、光の乱反射によって発光素子の内部への光の閉じ込めが低減されるため、光取り出し効率に優れたＩＩＩ族窒化物半導体発光素子を実現できる。
　さらに、本発明の発光素子は、ｎ型クラッド層及び／又はｐ型クラッド層を含み、かつｎ型クラッド層及び／又はｐ型クラッド層が超格子構造を含む層構成である場合、出力が格段に向上し、電気特性に優れた発光素子とすることができる。 According to the group III nitride semiconductor light emitting device of the present invention, the substrate has a flat surface composed of a (0001) C plane, a main surface composed of a plurality of convex portions, and a back surface. The base width is 0.05 to 1.5 μm. The group III nitride semiconductor layer is formed by epitaxially growing a group III nitride semiconductor on the main surface of the substrate so as to cover the planar portion and the convex portion. The emission wavelength in the LED structure is in the range of 490 to 570 nm. Due to the above characteristics, the present invention can appropriately control the crystallinity of the group III nitride semiconductor layer and suppress the occurrence of lattice mismatch with the LED structure further stacked on this layer. can do.
Moreover, the said effect becomes more remarkable and the exceptional effect is acquired because the convex part of a board | substrate is comprised by the surface non-parallel to C surface.
With these characteristics, there is no distortion in the LED structure that emits green light, and it is possible to suppress the decrease in internal quantum efficiency and the occurrence of leakage current, so that the electrical characteristics are excellent and the light emission output is high. A group nitride semiconductor light emitting device is obtained. In addition, since the interface between the substrate and the group III nitride semiconductor layer is uneven, light confinement inside the light emitting element is reduced due to diffused reflection of light, so that the group III nitride semiconductor light emitting with excellent light extraction efficiency is achieved. An element can be realized.
Furthermore, the light emitting device of the present invention includes an n-type cladding layer and / or a p-type cladding layer, and when the n-type cladding layer and / or the p-type cladding layer has a superlattice structure, the output is remarkably high. Thus, a light-emitting element having excellent electrical characteristics can be obtained.
　また、本発明のＩＩＩ族窒化物半導体発光素子の製造方法によれば、基板の（０００１）Ｃ面からなる平面上に、基部幅が０．０５～１．５μｍである複数の凸部が形成される。本発明の方法は、基板上に平面部と凸部とからなる主面を形成する基板加工工程と、基板の主面上にＩＩＩ族窒化物半導体をエピタキシャル成長させることにより、平面及び凸部を覆うようにＩＩＩ族窒化物半導体層を形成するエピタキシャル工程と、ＬＥＤ構造を、前記ＬＥＤ構造における発光波長を４９０～５７０ｎｍの範囲として形成するＬＥＤ積層工程と、を含んでいる。その結果、結晶性が適正に制御されたＩＩＩ族窒化物半導体層を形成することができ、この層の上に形成されるＬＥＤ構造との間で格子不整合が生じるのが抑制でき、歪み等を生じさせること無くＬＥＤ構造を形成することが可能となる。
　また、基板加工工程において、Ｃ面に対して非並行である表面により構成される凸部を形成する方法を用いることにより、上記効果がより顕著となり、格別な効果が得られる。
　これらの特徴により、緑色発光を呈するＬＥＤ構造を形成する場合においても、内部量子効率及び光取り出し効率に優れ、高い発光特性を有することができる、ＩＩＩ族窒化物半導体発光素子を製造することが可能となる。
　さらに、本発明に係るランプは、本発明のＩＩＩ族窒化物半導体発光素子が用いられるので、発光特性に優れたものとなる。 In addition, according to the method for manufacturing a group III nitride semiconductor light emitting device of the present invention, a plurality of convex portions having a base width of 0.05 to 1.5 μm are formed on the plane composed of the (0001) C plane of the substrate. Is done. In the method of the present invention, a substrate processing step for forming a main surface composed of a flat portion and a convex portion on a substrate, and a group III nitride semiconductor is epitaxially grown on the main surface of the substrate to cover the flat surface and the convex portion. Thus, an epitaxial process for forming the group III nitride semiconductor layer and an LED stacking process for forming the LED structure with an emission wavelength in the LED structure in the range of 490 to 570 nm are included. As a result, a group III nitride semiconductor layer with properly controlled crystallinity can be formed, and it is possible to suppress the occurrence of lattice mismatch with the LED structure formed on this layer, distortion, etc. It is possible to form an LED structure without causing the above.
Moreover, the said effect becomes more remarkable by using the method of forming the convex part comprised by the surface which is non-parallel with respect to C surface in a board | substrate processing process, and a special effect is acquired.
With these features, even when forming an LED structure that emits green light, it is possible to manufacture a group III nitride semiconductor light-emitting device that is excellent in internal quantum efficiency and light extraction efficiency and has high light emission characteristics. It becomes.
Furthermore, since the group III nitride semiconductor light emitting device of the present invention is used, the lamp according to the present invention has excellent light emission characteristics.
本発明に係るＩＩＩ族窒化物半導体発光素子の一例を模式的に説明する図であり、基板の主面上に、バッファ層と単結晶のＩＩＩ族窒化物半導体からなる下地層とが形成された積層構造を示す断面図である。It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and the base layer which consists of a buffer layer and a single crystal group III nitride semiconductor was formed on the main surface of a board | substrate It is sectional drawing which shows a laminated structure. 本発明に係るＩＩＩ族窒化物半導体発光素子の一例を模式的に説明する図であり、図１の要部を示す斜視図である。It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is a perspective view which shows the principal part of FIG. 本発明に係るＩＩＩ族窒化物半導体発光素子の一例を模式的に説明する図であり、図１に示す積層構造の上にＬＥＤ構造が形成された発光素子を示す断面図である。It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is sectional drawing which shows the light-emitting device in which the LED structure was formed on the laminated structure shown in FIG. 本発明に係るＩＩＩ族窒化物半導体発光素子の一例を模式的に説明する図であり、図３の要部を示す拡大断面図である。It is a figure which illustrates typically an example of the group III nitride semiconductor light-emitting device based on this invention, and is an expanded sectional view which shows the principal part of FIG. 本発明に係るＩＩＩ族窒化物半導体発光素子を用いて構成したランプの一例を模式的に説明する概略図である。It is the schematic explaining typically an example of the lamp | ramp comprised using the group III nitride semiconductor light-emitting device based on this invention. 本発明に係るＩＩＩ族窒化物半導体発光素子の実験例について説明する図であり、基板に形成された基部幅を１μｍとした場合の発光特性を示すグラフである。It is a figure explaining the experiment example of the group III nitride semiconductor light-emitting device based on this invention, and is a graph which shows the light emission characteristic when the base part width | variety formed in the board | substrate is 1 micrometer. 本発明に係るＩＩＩ族窒化物半導体発光素子の実験例について説明する図であり、基板に形成された基部幅を２μｍとした場合の発光特性を示すグラフである。It is a figure explaining the experiment example of the group III nitride semiconductor light-emitting device based on this invention, and is a graph which shows the light emission characteristic when the base part width | variety formed in the board | substrate was 2 micrometers.
　以下、本発明に係るＩＩＩ族窒化物半導体発光素子（以下、発光素子と略称することがある）及びその製造方法、並びにランプの一実施形態について、図面を適宜参照しながら説明する。しかしながら、本発明はこれら例のみに限定されるものではなく、特に問題のない限り、数、大きさ、厚さ、形状、位置などの、変更、追加、省略などをしてもよい。
　図１は、本発明に係る発光素子１の一部を説明するための図である。基板１０１の主面１０上に、バッファ層１０２と単結晶の下地層（ＩＩＩ族窒化物半導体層）１０３とが形成された積層構造を示した断面図である。図２は、図１に示す基板１０１を説明するための斜視図である。図３は、図１に示す積層構造の下地層（ＩＩＩ族窒化物半導体層）１０３上に、ＬＥＤ構造２０が形成されている、発光素子１を示す断面図である。図中、符号１０７は正極ボンディングパッドを示し、符号１０８は負極ボンディングパッドを示している。図４は、図３に示す発光素子１の内の、ｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６の断面を示す部分断面図である。 Hereinafter, a group III nitride semiconductor light emitting device (hereinafter sometimes abbreviated as a light emitting device) according to the present invention, a manufacturing method thereof, and an embodiment of a lamp will be described with reference to the drawings as appropriate. However, the present invention is not limited to these examples, and the number, size, thickness, shape, position, and the like may be changed, added, omitted, etc., as long as there is no particular problem.
FIG. 1 is a diagram for explaining a part of a light emitting device 1 according to the present invention. 1 is a cross-sectional view showing a laminated structure in which a buffer layer and a single crystal underlayer (group III nitride semiconductor layer) 103 are formed on a main surface 10 of a substrate 101. FIG. FIG. 2 is a perspective view for explaining the substrate 101 shown in FIG. FIG. 3 is a cross-sectional view showing the light-emitting element 1 in which the LED structure 20 is formed on the base layer (group III nitride semiconductor layer) 103 having the stacked structure shown in FIG. In the figure, reference numeral 107 denotes a positive electrode bonding pad, and reference numeral 108 denotes a negative electrode bonding pad. 4 is a partial cross-sectional view showing cross sections of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 in the light-emitting element 1 shown in FIG.
［ＩＩＩ族窒化物半導体発光素子］
　本発明に係る発光素子１は、図１～図４に示す一例のように概略構成されており、基板１０１上に形成された単結晶の下地層（ＩＩＩ族窒化物半導体層）１０３上に、ＬＥＤ構造２０が形成されている。基板１０１は、裏面と、（０００１）Ｃ面からなる平面部１１と、Ｃ面に非平行の表面１２ｃからなる複数の凸部１２とからなる主面１０を有する。凸部１２の基部幅は０．０５～３μｍである。下地層１０３は、基板１０１の主面１０上に、平面部１１及び凸部１２を覆うようにＩＩＩ族窒化物半導体がエピタキシャル成長することによって形成されたものである。ＬＥＤ構造２０における発光波長は４９０～５７０ｎｍの範囲である。また、この図示例においては、基板１０１上にバッファ層１０２が設けられ、このバッファ層１０２上にさらに下地層１０３が形成されている。 [Group III nitride semiconductor light emitting device]
A light-emitting element 1 according to the present invention is schematically configured as in the example shown in FIGS. 1 to 4, and is formed on a single crystal underlayer (group III nitride semiconductor layer) 103 formed on a substrate 101. An LED structure 20 is formed. The substrate 101 has a main surface 10 composed of a back surface, a flat portion 11 made of a (0001) C plane, and a plurality of convex portions 12 made of a surface 12c non-parallel to the C surface. The base width of the convex portion 12 is 0.05 to 3 μm. The underlayer 103 is formed by epitaxially growing a group III nitride semiconductor on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12. The emission wavelength in the LED structure 20 is in the range of 490 to 570 nm. In the illustrated example, a buffer layer 102 is provided on the substrate 101, and a base layer 103 is further formed on the buffer layer 102.
　本実施形態で説明される、本発明の一例である発光素子１は、図３で示されるように、一面電極型である。上述したような基板１０１上に、バッファ層１０２と、ＩＩＩ族元素としてＧａを含有するＩＩＩ族窒化物半導体からなるＬＥＤ構造（ＩＩＩ族窒化物半導体層）２０とが形成されている。発光素子１に備えられるＬＥＤ構造２０は、図３に示すように、ｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６がこの順で積層されたものである。 The light-emitting element 1 which is an example of the present invention described in the present embodiment is a single electrode type as shown in FIG. A buffer layer 102 and an LED structure (Group III nitride semiconductor layer) 20 made of a Group III nitride semiconductor containing Ga as a Group III element are formed on the substrate 101 as described above. As shown in FIG. 3, the LED structure 20 provided in the light-emitting element 1 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 stacked in this order.
　本発明のＩＩＩ族窒化物半導体発光素子は、詳細を後述するＬＥＤ構造において、発光層を構成する井戸層のインジウム（Ｉｎ）含有量を高濃度になるように制御することにより、発光波長が４９０ｎｍ以上の緑色発光を呈するものであり、より好ましくは４９０～５７０ｎｍの範囲の発光波長を呈するものである。本発明の素子は、良好な緑色発光が可能である。
　以下、発光素子１の積層構造について詳しく説明する。 The group III nitride semiconductor light-emitting device of the present invention has a light emission wavelength of 490 nm by controlling the indium (In) content of the well layer constituting the light-emitting layer to be high concentration in the LED structure described in detail later. It exhibits green light emission as described above, and more preferably exhibits an emission wavelength in the range of 490 to 570 nm. The element of the present invention can emit good green light.
Hereinafter, the laminated structure of the light emitting element 1 will be described in detail.
『基板』
（基板の材料）
　本実施形態の発光素子において、基板１０１に用いることができる材料としては、ＩＩＩ族窒化物半導体結晶が表面にエピタキシャル成長される基板材料であれば特に限定されず、各種材料を選択して用いることができる。例えば、サファイア、ＳｉＣ、シリコン、酸化亜鉛、酸化マグネシウム、酸化マンガン、酸化ジルコニウム、酸化マンガン亜鉛鉄、酸化マグネシウムアルミニウム、ホウ化ジルコニウム、酸化ガリウム、酸化インジウム、酸化リチウムガリウム、酸化リチウムアルミニウム、酸化ネオジウムガリウム、酸化ランタンストロンチウムアルミニウムタンタル、酸化ストロンチウムチタン、酸化チタン、ハフニウム、タングステン、及びモリブデン等が挙げられる。
　上記基板材料の中でも、特に、サファイアを用いることが好ましい。またサファイア基板のｃ面上に中間層（バッファ層）１０２が形成されることが望ましい。 "substrate"
(Substrate material)
In the light emitting device of the present embodiment, the material that can be used for the substrate 101 is not particularly limited as long as it is a substrate material on which a group III nitride semiconductor crystal is epitaxially grown, and various materials can be selected and used. it can. For example, sapphire, SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide Lanthanum strontium oxide aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum and the like.
Among the substrate materials, sapphire is particularly preferable. It is desirable that an intermediate layer (buffer layer) 102 be formed on the c-plane of the sapphire substrate.
　なお、上記基板材料の内、高温でアンモニアに接触することで化学的な変性を引き起こすことが知られている酸化物基板や金属基板等を用いる場合には、バッファ層１０２の使用が好ましい。例えば、アンモニアを使用せずにバッファ層１０２を成膜した後に、アンモニアを使用する方法で後述の下地層１０３を成膜する場合には、バッファ層１０２がコート層としても作用するので、基板１０１の化学的な変質を防ぐ点で効果的である。
　また、バッファ層１０２をスパッタ法で形成する事も好ましい。バッファ層１０２がスパッタ法により形成された場合、基板１０１の温度を低く抑えることが可能である。よって、高温で分解してしまう性質を持つ材料からなる基板１０１を用いた場合でも、バッファ層１０２をスパッタ法で形成することによって、基板１０１にダメージを与えることなく、基板上への各層の成膜が可能である。 In the case of using an oxide substrate or a metal substrate that is known to cause chemical modification by contact with ammonia at a high temperature, the buffer layer 102 is preferably used. For example, in the case where an underlayer 103 described later is formed by a method using ammonia after forming the buffer layer 102 without using ammonia, the buffer layer 102 also functions as a coat layer. It is effective in preventing chemical alteration.
It is also preferable to form the buffer layer 102 by sputtering. In the case where the buffer layer 102 is formed by a sputtering method, the temperature of the substrate 101 can be kept low. Therefore, even when the substrate 101 made of a material that decomposes at a high temperature is used, the formation of each layer on the substrate without damaging the substrate 101 by forming the buffer layer 102 by sputtering. A membrane is possible.
（基板の形状：平面と凸部とからなる主面）
　本実施形態で用いられる基板１０１の主面１０には、図２に示す例のように、複数の凸部１２が形成されている。基板１０１の主面１０において凸部１２の形成されていない部分は、（０００１）Ｃ面からなる平面部１１により構成されている。従って、図２及び図３に示す例のように、基板１０１の主面１０は、Ｃ面からなる平面部１１と、複数の凸部１２とから構成される。 (Substrate shape: main surface consisting of flat and convex parts)
A plurality of convex portions 12 are formed on the main surface 10 of the substrate 101 used in this embodiment, as in the example shown in FIG. A portion of the main surface 10 of the substrate 101 where the convex portion 12 is not formed is constituted by a flat portion 11 made of a (0001) C plane. Therefore, as in the example shown in FIGS. 2 and 3, the main surface 10 of the substrate 101 is composed of a flat surface portion 11 made of a C surface and a plurality of convex portions 12.
　凸部１２の表面は、図１及び図２に示すように、Ｃ面に対して非平行の表面１２ｃである。この表面１２ｃにはＣ面が現れていない。凸部１２の形状、位置、大きさや数は必要に応じて選択できるが、図１及び図２に示す凸部１２は、伏せたお椀状（半球状）の形状である。すなわち、基部１２ａの平面形状（凸部１２の底面形状）が略円形であり、凸部１２は上部に向かうほど徐々に外形（断面積）が小さくなる形状である。凸部１２の側面１２ｂは外側に向かって湾曲している。
　なお、凸部が、詳細を後述するように、サファイア以外の酸化物又は窒化物から構成される場合は、円柱形としても構わない。
　凸部１２の平面配置は、図１及び図２に示すように、碁盤目状に等間隔に配置されている。 As shown in FIGS. 1 and 2, the surface of the convex portion 12 is a surface 12 c that is non-parallel to the C plane. The C surface does not appear on the surface 12c. Although the shape, position, size, and number of the convex portions 12 can be selected as necessary, the convex portions 12 shown in FIGS. 1 and 2 have an obstructed bowl-like (hemispherical) shape. That is, the planar shape of the base 12a (the shape of the bottom surface of the convex portion 12) is substantially circular, and the convex portion 12 has a shape in which the outer shape (cross-sectional area) gradually decreases toward the top. The side surface 12b of the convex portion 12 is curved outward.
In addition, when a convex part is comprised from oxides or nitrides other than sapphire so that a detail may mention later, it is good also as a column shape.
As shown in FIGS. 1 and 2, the planar arrangement of the protrusions 12 is arranged in a grid pattern at regular intervals.
　また、図１及び図２に示す凸部１２の例では、基部幅ｄ１が０．０５～１．５μｍ、高さｈが０．０５～１μｍの範囲で、且つ基部幅ｄ１の１／４以上である。また、互いに隣接する凸部１２間の間隔ｄ２は、基部幅ｄ１の０．５～５倍である。ここで、凸部１２の基部幅ｄ１とは、凸部１２の底面（基部１２ａ）における最大の幅のことをいう。また、隣接する凸部１２との間隔ｄ２とは、凸部１２の基部１２ａの縁と、前記凸部１２に最も近接した凸部１２の基部１２ａの縁の間の最短距離をいう。 1 and 2, the base width d 1 is 0.05 to 1.5 μm, the height h is 0.05 to 1 μm, and 1 / of the base width d 1 . 4 or more. Further, the distance d 2 between the adjacent convex portions 12 is 0.5 to 5 times the base width d 1 . Here, the base width d 1 of the convex portion 12 refers to the maximum width at the bottom surface (base portion 12 a) of the convex portion 12. The distance d 2 between the adjacent convex portions 12 refers to the shortest distance between the edge of the base portion 12 a of the convex portion 12 and the edge of the base portion 12 a of the convex portion 12 closest to the convex portion 12.
　互いに隣接する凸部１２間の間隔ｄ２は、基部幅ｄ１の０．５～５倍であることが好ましい。互いに隣接する凸部１２間の間隔ｄ２が基部幅ｄ１の０．５倍未満であると、その上にｎ型半導体層１０４（半導体層３０）が形成される下地層１０３をエピタキシャル成長する際に、Ｃ面からなる平面部１１上からの結晶成長が促進され難くなり、凸部１２を下地層１０３で完全に埋め込むことが難しくなり、また、下地層１０３の表面１０３ａの平坦性が十分に得られない場合がある。従って、前記のような条件で凸部１２を埋めた下地層１０３上にさらにＬＥＤ構造をなす半導体層の結晶を形成した場合、この結晶にはピットが多く形成されてしまい、形成されたＩＩＩ族窒化物半導体発光素子の出力や電気特性等の悪化につながる場合がある。一方で、凸部１２間の間隔ｄ２が基部幅ｄ１の５倍を超えると、基板１０１を用いてＩＩＩ族窒化物半導体発光素子を形成した場合に、基板１０１と、基板１０１上に形成されたＩＩＩ族窒化物半導体層との界面での光の乱反射の機会が減少し、光の取り出し効率を十分に向上させることができなくなる場合がある。 The distance d 2 between the convex portions 12 adjacent to each other is preferably 0.5 to 5 times the base width d 1 . If the interval d 2 between the convex portions 12 adjacent is less than 0.5 times the base width d 1 from each other, when epitaxially growing a base layer 103 of n-type semiconductor layer 104 (semiconductor layer 30) is formed thereon In addition, it is difficult to promote crystal growth from the C-plane flat portion 11, and it becomes difficult to completely fill the convex portion 12 with the underlayer 103, and the flatness of the surface 103 a of the underlayer 103 is sufficiently high. It may not be obtained. Therefore, when a semiconductor layer crystal having an LED structure is further formed on the base layer 103 in which the convex portion 12 is buried under the above-described conditions, a lot of pits are formed in the crystal, and the formed group III In some cases, the output and electrical characteristics of the nitride semiconductor light emitting device may be deteriorated. On the other hand, when the distance d 2 between the protrusions 12 exceeds 5 times the base width d 1 , the substrate 101 is formed on the substrate 101 when the group III nitride semiconductor light emitting device is formed using the substrate 101. In some cases, the chance of irregular reflection of light at the interface with the group III nitride semiconductor layer is reduced, and the light extraction efficiency cannot be sufficiently improved.
　基部幅ｄ１は０．０５～１．５μｍであることが好ましい。基部幅ｄ１が０．０５μｍ未満であると、基板１０１を用いてＩＩＩ族窒化物半導体発光素子を形成した場合に、光を乱反射させる効果が十分に得られない場合がある。また、基部幅ｄ１が１．５μｍを超えると、凸部１２を完全に埋めて下地層１０３をエピタキシャル成長させることが困難になる場合がある。また、平坦性及び結晶性の良好な下地層が形成できたとしても、下地層と発光層との間の歪みが大きくなり、内部量子効率の低下を招く可能性がある。
　また、基部幅ｄ１は、上記範囲内ならば、より小さい構成とすればするほど、発光素子の発光出力がさらに向上する効果が得られる。
　基部幅ｄ１は０．０５～１μｍとされることがより好ましい。 The base width d 1 is preferably 0.05 to 1.5 μm. When the base width d 1 is less than 0.05 μm, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be obtained sufficiently. On the other hand, if the base width d 1 exceeds 1.5 μm, it may be difficult to completely fill the convex portion 12 and epitaxially grow the base layer 103. Further, even if an underlayer with good flatness and crystallinity can be formed, the distortion between the underlayer and the light-emitting layer may increase, leading to a decrease in internal quantum efficiency.
In addition, if the base width d 1 is within the above range, the light emission output of the light emitting element can be further improved as the configuration is made smaller.
The base width d 1 is more preferably 0.05 to 1 μm.
　凸部１２の高さｈは０．０５～１μｍであることが好ましい。凸部１２の高さｈが０．０５μｍ未満であると、基板１０１を用いてＩＩＩ族窒化物半導体発光素子を形成した場合に、光を乱反射させる効果が十分に得られない場合がある。また、凸部１２の高さｈが１μｍを超えると、凸部１２を埋めて下地層１０３をエピタキシャル成長することが困難になり、下地層１０３の表面１４ａの平坦性が十分に得られない場合がある。 The height h of the convex portion 12 is preferably 0.05 to 1 μm. When the height h of the convex portion 12 is less than 0.05 μm, when a group III nitride semiconductor light emitting device is formed using the substrate 101, the effect of irregularly reflecting light may not be sufficiently obtained. In addition, if the height h of the convex portion 12 exceeds 1 μm, it may be difficult to epitaxially grow the base layer 103 by filling the convex portion 12, and the flatness of the surface 14a of the base layer 103 may not be sufficiently obtained. is there.
　また、凸部１２の高さｈは基部幅ｄ１の１／４以上であることが好ましい。より好ましくは１／２以上であって１／１以下である。凸部１２の高さｈが基部幅ｄ１の１／４未満であると、基板１０１を用いてＩＩＩ族窒化物半導体発光素子を形成した場合の光を乱反射させる効果や、光の取り出し効率を向上させる効果が十分に得られない場合がある。 The height h of the convex portion 12 is preferably 1/4 or more base portion width d 1. More preferably, it is ½ or more and 1/1 or less. When the height h of the convex portion 12 is less than ¼ of the base width d 1 , the effect of irregularly reflecting light when the substrate 101 is used to form a group III nitride semiconductor light-emitting device and the light extraction efficiency are improved. The effect of improving may not be obtained sufficiently.
　凸部１２の形状は、図１及び図２に示す例に限定されるものではなく、Ｃ面に非平行の表面から構成されるものであれば、いかなる形状であってもよい。例えば、基部の平面形状が略多角形であり、上部に向かって徐々に外形が小さくなる形状であってもよく、側面１２が外側に向かって湾曲する形状であってもよい。また、凸部１２の形状は、略円錐状や、側面幅が上部に向かって徐々に小さくなる略多角錐状であってもよい。側面は外側に向かって張り出していてもよい。また、側面の傾斜角度は、多段階に、例えば２段階的に変化する形状であってもよい。また、凸部が、詳細を後述するように、サファイア以外の酸化物又は窒化物から構成される場合は、円柱形としても良い。
　また、凸部１２の平面配置も、図１及び図２に示す例（碁盤目状）に限定されるものではなく、等間隔に配置されてもよいし、等間隔でない配置であってもよい。また、凸部１２の平面配置は、四角形状であってもよいし、三角形状であってもよいし、ランダムであってもよい。 The shape of the convex part 12 is not limited to the example shown in FIG.1 and FIG.2, and what kind of shape may be sufficient if it is comprised from the surface non-parallel to C surface. For example, the planar shape of the base may be substantially polygonal, and the outer shape may gradually decrease toward the top, or the side surface 12 may be curved outward. Moreover, the shape of the convex part 12 may be a substantially conical shape or a substantially polygonal pyramid whose side width gradually decreases toward the top. The side surface may protrude outward. Further, the side surface inclination angle may be a shape that changes in multiple stages, for example, in two stages. Moreover, when a convex part is comprised from oxides or nitrides other than sapphire so that a detail may mention later, it is good also as a column shape.
Further, the planar arrangement of the protrusions 12 is not limited to the example shown in FIGS. 1 and 2 (a grid pattern), and may be arranged at equal intervals or may be arranged at non-equal intervals. . Further, the planar arrangement of the convex portions 12 may be a quadrangular shape, a triangular shape, or a random shape.
　なお、本実施形態おいて、基板１０１上に設けられる凸部１２は、詳細を後述する製造方法により、基板１０１をエッチングすることによって形成することができる。しかしながら、製造方法はこれには限定されない。例えば、基板上に、凸部をなす別の材料を基板１０１のＣ面上に堆積させることによって凸部を形成してもよい。上記基板上に凸部をなす別の材料を堆積させる方法としては、例えば、スパッタ法、蒸着法、及びＣＶＤ法等の各方法を用いることができる。また、凸部をなす材料としては、酸化物や窒化物等の、基板の材料とほぼ同等の屈折率を有する材料を用いることが好ましい。基板がサファイア基板の場合には、例えば、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、及びＺｎＯ等を用いることができる。 In the present embodiment, the convex portion 12 provided on the substrate 101 can be formed by etching the substrate 101 by a manufacturing method described in detail later. However, the manufacturing method is not limited to this. For example, the convex portion may be formed by depositing another material forming the convex portion on the C surface of the substrate 101 on the substrate. As a method for depositing another material for forming a convex portion on the substrate, for example, a sputtering method, a vapor deposition method, a CVD method, or the like can be used. Further, as the material forming the convex portion, it is preferable to use a material having a refractive index substantially equal to the material of the substrate, such as an oxide or a nitride. When the substrate is a sapphire substrate, for example, SiO 2 , Al 2 O 3 , SiN, ZnO, or the like can be used.
　本発明においては、基板１０１を、平面部１１及び凸部１２からなる主面１０が備えられた上記構成としたことにより、基板１０１と、詳細を後述する下地層１０３との界面は、バッファ層１０２を介して凹凸とされる。このため、凹凸によって光の乱反射によって発光素子の内部への光の閉じ込めが低減され、光取り出し効率に優れた発光素子１が実現できる。また、基板１０１を上記構成としたことにより、下地層１０３の結晶性が適正に制御できるので、後述のＬＥＤ構造２０に備えられる発光層１０５（井戸層１０５ｂ）と下地層１０３との間に格子不整合が生じるのが抑制される。これにより、発光層１０５に備えられる井戸層１０５ｂのＩｎ濃度を高濃度として、緑色発光を呈する発光素子１を構成する場合であっても、井戸層１０５ｂに歪み等が生じるのが抑制される。従って、内部量子効率に優れ、高い発光出力を備えるとともに、リーク電流の発生が抑制されて電気的特性に優れる、発光素子１を実現することができる。 In the present invention, since the substrate 101 has the above-described configuration including the main surface 10 including the flat portion 11 and the convex portion 12, the interface between the substrate 101 and the underlayer 103, which will be described in detail later, is a buffer layer. Concavities and convexities are formed through 102. For this reason, confinement of light inside the light emitting element due to irregular reflection of light due to the unevenness is reduced, and the light emitting element 1 having excellent light extraction efficiency can be realized. Further, since the substrate 101 has the above-described structure, the crystallinity of the base layer 103 can be appropriately controlled, so that a lattice is formed between the light emitting layer 105 (well layer 105b) provided in the LED structure 20 described later and the base layer 103. Inconsistencies are prevented from occurring. Thereby, even when the In concentration of the well layer 105b provided in the light emitting layer 105 is set to a high concentration to constitute the light emitting element 1 that emits green light, the occurrence of distortion or the like in the well layer 105b is suppressed. Accordingly, it is possible to realize the light emitting device 1 that has excellent internal quantum efficiency, has a high light emission output, and is excellent in electrical characteristics by suppressing generation of leakage current.
『バッファ層』
　本発明においては、基板１０１の主面１０上にバッファ層１０２を形成し、その上に、後述の下地層１０３を形成することが好ましい。
　バッファ層１０２は、ＡｌＸＧａ１－ＸＮ（０≦ｘ≦１）の組成で基板１０１上に積層される。例えばバッファ層は、Ｖ族元素を含むガスと金属材料とをプラズマで活性化して反応させる反応性スパッタ法によって形成することができる。本実施形態のような、プラズマ化した金属原料を用いた方法で成膜された膜は、配向が得られ易いという作用がある。 "Buffer layer"
In the present invention, it is preferable to form the buffer layer 102 on the main surface 10 of the substrate 101 and form an underlayer 103 described later on the buffer layer 102.
The buffer layer 102 is stacked on the substrate 101 with a composition of Al X Ga 1-X N (0 ≦ x ≦ 1). For example, the buffer layer can be formed by a reactive sputtering method in which a gas containing a group V element and a metal material are activated and reacted with plasma. A film formed by a method using a plasma metal raw material as in this embodiment has an effect that alignment is easily obtained.
　バッファ層１０２は、基板１０１と下地層１０３との格子定数の違いを緩和し、その結果、基板１０１のＣ面上にＣ軸配向した単結晶層が形成することを容易にする働きがある。従って、基板上に形成されたバッファ層１０２の上に単結晶のＩＩＩ族窒化物半導体層（下地層１０３）を積層すると、バッファ層なしの場合と比較して、より結晶性に優れた下地層１０３が形成できる。なお、本実施形態では、基板１０１と下地層１０３の間にバッファ層１０２を形成することが最も好ましいが、バッファ層を省略した構成とすることも可能である。 The buffer layer 102 has a function of alleviating the difference in lattice constant between the substrate 101 and the base layer 103 and, as a result, easily forming a C-axis oriented single crystal layer on the C plane of the substrate 101. Therefore, when a single-crystal group III nitride semiconductor layer (underlayer 103) is stacked on the buffer layer 102 formed on the substrate, the underlayer has better crystallinity than the case without the buffer layer. 103 can be formed. In the present embodiment, it is most preferable to form the buffer layer 102 between the substrate 101 and the base layer 103, but a configuration in which the buffer layer is omitted may be employed.
（バッファ層の組成）
　本実施形態では、バッファ層１０２が、上記ＡｌＸＧａ１－ＸＮ（０≦ｘ≦１）の組成であることが好ましく、ＡｌＮであることがより好ましい。一般に、基板上に積層させるバッファ層としては、Ａｌを含有する組成であることが好ましく、一般式ＡｌＸＧａ１－ＸＮ（０≦ｘ≦１）で表されるＩＩＩ族窒化物化合物であれば、如何なる材料も用いることができる。さらに、Ｖ族としてＡｓやＰが含有される組成とすることもできる。バッファ層が、ＡｌＧａＮの組成でである場合、Ａｌの組成が５０％以上であることがより好ましい。
　また、バッファ層１０２を構成する材料としては、ＩＩＩ族窒化物半導体と同じ結晶構造を有するものを用いることができるが、格子の長さが後述の下地層を構成するＩＩＩ族窒化物半導体に近いものが好ましく、特に周期表のＩＩＩａ族元素の窒化物が好適である。 (Composition of buffer layer)
In the present embodiment, the buffer layer 102 preferably has a composition of Al X Ga 1-X N (0 ≦ x ≦ 1), and more preferably AlN. In general, the buffer layer laminated on the substrate preferably has a composition containing Al, and may be a group III nitride compound represented by the general formula Al X Ga 1-X N (0 ≦ x ≦ 1). Any material can be used. Furthermore, it can also be set as the composition containing As and P as V group. When the buffer layer has an AlGaN composition, the Al composition is more preferably 50% or more.
In addition, as a material constituting the buffer layer 102, a material having the same crystal structure as that of the group III nitride semiconductor can be used, but the length of the lattice is close to that of the group III nitride semiconductor constituting the underlayer described later. And nitrides of group IIIa elements of the periodic table are particularly preferred.
（バッファ層の結晶構造）
　バッファ層をなすＩＩＩ族窒化物の結晶は、六方晶系の結晶構造を持ち、成膜条件をコントロールすることにより、単結晶膜とすることができる。また、ＩＩＩ族窒化物の結晶は、上記成膜条件をコントロールすることにより、六角柱を基本とした集合組織からなる柱状結晶（多結晶）とすることも可能である。なお、ここで説明する柱状結晶とは、隣接する結晶粒との間に結晶粒界を形成して隔てられており、それ自体は縦断面形状として柱状になっている結晶のことをいう。 (Crystal structure of buffer layer)
The group III nitride crystal forming the buffer layer has a hexagonal crystal structure, and can be formed into a single crystal film by controlling the film formation conditions. Further, the group III nitride crystal can be formed into a columnar crystal (polycrystal) having a texture based on a hexagonal column by controlling the film forming conditions. Note that the columnar crystal described here is a crystal which is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape.
　バッファ層１０２は、単結晶構造であることが、バッファ機能の面から好ましい。上述したように、ＩＩＩ族窒化物の結晶は六方晶系の結晶を有し、六角柱を基本とした組織を形成する。ＩＩＩ族窒化物の結晶は、成膜条件等を制御することにより、上方向に成長した結晶だけではなく、面内方向にも成長した結晶を成膜することが可能である。上述のような単結晶構造を有するバッファ層１０２を基板１０１上に成膜した場合、バッファ層１０２のバッファ機能が有効に作用する。このため、その上に成膜されるＩＩＩ族窒化物半導体の層は、良好な配向性及び結晶性を持つ結晶膜となる。 The buffer layer 102 preferably has a single crystal structure from the viewpoint of the buffer function. As described above, the group III nitride crystal has a hexagonal crystal and forms a structure based on a hexagonal column. By controlling the film forming conditions and the like for the group III nitride crystal, it is possible to form a crystal grown not only in the upward direction but also in the in-plane direction. When the buffer layer 102 having the single crystal structure as described above is formed over the substrate 101, the buffer function of the buffer layer 102 effectively operates. Therefore, the group III nitride semiconductor layer formed thereon is a crystal film having good orientation and crystallinity.
（バッファ層の膜厚）
　バッファ層１０２の膜厚は、０．０１～０．５μｍの範囲であることが好ましい。バッファ層１０２の膜厚を上記範囲とすることにより、良好な配向性を有し、かつ、バッファ層１０２上にＩＩＩ族窒化物半導体からなる各層を成膜する際に、コート層として有効に機能するバッファ層１０２が得られる。バッファ層１０２の膜厚が０．０１μｍ未満であると、上述したコート層としての充分な機能が得られず、また、基板１０１と下地層１０３との間の格子定数の違いを緩和するバッファ作用が充分に得られない場合がある。また、０．５μｍを超える膜厚でバッファ層１０２を形成した場合、バッファ作用やコート層としての機能には変化が無いのにも関わらず成膜処理時間が長くなり、生産性が低下する場合がある。また、バッファ層１０２の膜厚は、０．０２～０．１μｍの範囲であることがより好ましい。 (Buffer layer thickness)
The thickness of the buffer layer 102 is preferably in the range of 0.01 to 0.5 μm. By setting the thickness of the buffer layer 102 in the above range, it has good orientation and functions effectively as a coating layer when each layer made of a group III nitride semiconductor is formed on the buffer layer 102. The buffer layer 102 is obtained. When the film thickness of the buffer layer 102 is less than 0.01 μm, a sufficient function as the above-described coat layer cannot be obtained, and the buffer function that alleviates the difference in lattice constant between the substrate 101 and the base layer 103. May not be sufficiently obtained. In addition, when the buffer layer 102 is formed with a film thickness exceeding 0.5 μm, the film formation processing time is prolonged and the productivity is lowered although there is no change in the buffer function and the function as the coat layer. There is. The thickness of the buffer layer 102 is more preferably in the range of 0.02 to 0.1 μm.
『ＩＩＩ族窒化物半導体層（下地層）』
　本発明の発光素子１に備えられる下地層（ＩＩＩ族窒化物半導体層）１０３は、上述したようにＩＩＩ族窒化物半導体からなり、従来公知のＭＯＣＶＤ法によってバッファ層１０２上に積層して成膜することができる。また、本例で説明する下地層１０３は、上述したように、基板１０１の主面１０上に、バッファ層１０２を介して、平面部１１及び凸部１２を覆うようにＩＩＩ族窒化物半導体がエピタキシャル成長することによって形成される。 "Group III nitride semiconductor layer (underlayer)"
The underlayer (group III nitride semiconductor layer) 103 provided in the light emitting device 1 of the present invention is made of a group III nitride semiconductor as described above, and is laminated on the buffer layer 102 by a conventionally known MOCVD method. can do. In addition, as described above, the base layer 103 described in this example is formed of a group III nitride semiconductor on the main surface 10 of the substrate 101 via the buffer layer 102 so as to cover the planar portion 11 and the convex portion 12. It is formed by epitaxial growth.
（下地層の材料）
　下地層１０３の材料としては、例えば、下地層１０３として、ＡｌｘＧａｙＩｎｚＮ（０≦ｘ≦１、０≦ｙ≦１、０≦ｚ≦１、ｘ＋ｙ＋ｚ＝１）を用いることができる。ＡｌｙＧａ１―ｙＮ層（０≦ｙ≦１、好ましくは０≦ｙ≦０．５、さらに好ましくは０≦ｙ≦０．１）を下地層１０３として用いることが、結晶性の良好な下地層１０３を形成できる点でより好ましい。
　下地層１０３の材料は、上述したように、バッファ層１０２と異なる材料を用いても良いが、バッファ層１０２と同じ材料を用いることも可能である。 (Underlayer material)
As the material of the base layer 103, for example, Al x Ga y In z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used as the base layer 103. . The use of an Al y Ga 1-y N layer (0 ≦ y ≦ 1, preferably 0 ≦ y ≦ 0.5, more preferably 0 ≦ y ≦ 0.1) as the base layer 103 provides good crystallinity. It is more preferable in that the underlayer 103 can be formed.
As described above, a material different from that of the buffer layer 102 may be used as the material of the base layer 103, but the same material as that of the buffer layer 102 may be used.
　下地層１０３は、必要に応じて、ｎ型不純物が１×１０１７～１×１０１９個／ｃｍ３の範囲内でドープされた構成としても良いが、アンドープ（＜１×１０１７個／ｃｍ３）の構成とすることもできる。アンドープの方が良好な結晶性を維持できる点で好ましい。
　基板１０１が導電性である場合には、下地層１０３にドーパントをドープして導電性とすることにより、発光素子の上下に電極を設けて使用することができる。一方、基板１０１に絶縁性の材料を用いる場合には、発光素子の同じ面に正極及び負極の各電極が設けられたチップ構造をとることになる。よってこの場合、下地層１０３はドープしない結晶とした方が、結晶性が良好となるので好ましい。
　下地層１０３にドープされるｎ型不純物としては、特に限定されないが、例えば、Ｓｉ、ＧｅおよびＳｎ等が挙げられ、好ましくはＳｉおよびＧｅが挙げられる。 The underlayer 103 may have a configuration in which n-type impurities are doped in the range of 1 × 10 17 to 1 × 10 19 atoms / cm 3 as necessary, but may be undoped (<1 × 10 17 atoms / cm 3). 3 ). Undoped is preferable in that good crystallinity can be maintained.
In the case where the substrate 101 is conductive, the base layer 103 is doped with a dopant so that the substrate 101 is conductive, whereby electrodes can be provided above and below the light emitting element. On the other hand, when an insulating material is used for the substrate 101, a chip structure in which the positive electrode and the negative electrode are provided on the same surface of the light-emitting element is employed. Therefore, in this case, it is preferable that the base layer 103 be an undoped crystal because crystallinity is improved.
The n-type impurity doped in the base layer 103 is not particularly limited, and examples thereof include Si, Ge, and Sn, and preferably Si and Ge.
（下地層の厚さ）
　下地層１０３の厚さは、１～８μｍの範囲とすることが、結晶性の良好な下地層が得られる点で好ましく、２～５μｍの範囲とすることが、成膜に要する工程時間を短縮でき、生産性が向上する点でより好ましい。
　また、図１に示す下地層１０３の最大厚さＨは、基板１０１の凸部１２の高さｈの２倍以上とすることが、表面１０３ａの平坦な下地層１０３が得られるため好ましい。下地層１０３の最大厚さＨが、凸部１２の高さｈの２倍より小さいと、凸部１２を覆うように成長した下地層１０３の表面１０３ａの平坦性が不充分となり、その結果、下地層１０３上に積層され、ＬＥＤ構造２０を構成する各層の結晶性が低下する虞がある。 (Underlayer thickness)
The thickness of the underlayer 103 is preferably in the range of 1 to 8 μm, from the viewpoint of obtaining an underlayer with good crystallinity, and in the range of 2 to 5 μm shortens the process time required for film formation. This is more preferable in terms of productivity.
In addition, it is preferable that the maximum thickness H of the base layer 103 illustrated in FIG. 1 is not less than twice the height h of the convex portion 12 of the substrate 101 because a flat base layer 103 having a surface 103a can be obtained. If the maximum thickness H of the base layer 103 is smaller than twice the height h of the convex portion 12, the flatness of the surface 103a of the base layer 103 grown so as to cover the convex portion 12 becomes insufficient. There is a possibility that the crystallinity of each layer which is laminated on the underlayer 103 and constitutes the LED structure 20 is lowered.
（下地層のＸ線ロッキングカーブ半値幅）
　本発明の発光素子１では、下地層１０３の（１０－１０）面のＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることが好ましい。下地層１０３のＸＲＣ半値幅が１５０ａｒｃｓｅｃ以上であれば、下地層１０３の結晶性が高くなり過ぎず適正範囲に制御されるので、表面１０３ａ上に積層されるＬＥＤ構造２０、特に発光層１０５に備えられる井戸層１０５ｂ、に歪等が生じることが無く、良好な結晶層となる。 (Half width of X-ray rocking curve of underlayer)
In the light emitting device 1 of the present invention, it is preferable that the X-ray rocking curve (XRC) half width of the (10-10) plane of the underlayer 103 is 150 arcsec or more. If the XRC half width of the underlayer 103 is 150 arcsec or more, the crystallinity of the underlayer 103 does not become too high and is controlled within an appropriate range. Therefore, the LED structure 20, particularly the light emitting layer 105, laminated on the surface 103 a is prepared. The well layer 105b is free from distortion and becomes a good crystal layer.
　通常、下地層の（１０－１０）面のＸＲＣ半値幅は結晶性の指標となり、この数値が小さいほど下地層の結晶性が高いことを示す。また、半値幅はその上に形成されるＬＥＤ構造の結晶性に影響を与えることから、出来る限り小さな数値とすることで発光素子全体の結晶性を高める方法がこれまで採用されてきている。しかしながら、本発明のような発光波長が４９０～５７０ｎｍの緑色発光を呈する発光素子においては、発光素子に備えられる井戸層のＩｎ濃度を高濃度とする必要があり、この場合には、井戸層の格子定数が大きくなる。このため、結晶性が非常に高められた下地層と井戸層との間での格子不整合が大きくなり、井戸層に歪み等の欠陥が生じてしまう問題がある。
　本発明では、下地層１０３の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅を１５０ａｒｃｓｅｃ以上、より好ましくは１７０ａｒｃｓｅｃ以上、に規定することで、下地層１０３の結晶性が適正範囲として良好に制御される。これにより、緑色発光を得るため、ＬＥＤ構造２０に備えられる発光層１０５の井戸層１０５ｂのＩｎ濃度を高めた場合であっても、下地層１０３と井戸層１０５ｂとの間で大きな格子不整合が生じるのが抑制される。従って、井戸層１０５ｂに歪み等の欠陥が生じるのが抑制され、内部量子効率が低下することが無いので、高い発光出力を有する発光素子１が実現できる。 Usually, the XRC half-width of the (10-10) plane of the underlayer is an index of crystallinity, and the smaller this value, the higher the crystallinity of the underlayer. In addition, since the half-value width affects the crystallinity of the LED structure formed thereon, a method of increasing the crystallinity of the entire light-emitting element by setting the value as small as possible has been employed. However, in a light emitting element that emits green light with an emission wavelength of 490 to 570 nm as in the present invention, it is necessary to increase the In concentration of the well layer provided in the light emitting element. Lattice constant increases. For this reason, there is a problem in that lattice mismatch between the underlayer and the well layer with extremely high crystallinity is increased, and defects such as strain are generated in the well layer.
In the present invention, by setting the X-ray rocking curve (XRC) half-value width in the (10-10) plane of the underlayer 103 to 150 arcsec or more, more preferably 170 arcsec or more, the crystallinity of the underlayer 103 is set within an appropriate range. Well controlled. Thereby, in order to obtain green light emission, even when the In concentration of the well layer 105b of the light emitting layer 105 provided in the LED structure 20 is increased, there is a large lattice mismatch between the base layer 103 and the well layer 105b. It is suppressed from occurring. Accordingly, the occurrence of defects such as strain in the well layer 105b is suppressed, and the internal quantum efficiency is not lowered, so that the light emitting element 1 having a high light emission output can be realized.
　下地層１０３のＸＲＣ半値幅は、上述した基板１０１に形成される凸部１２の基部幅ｄ１により、適正に制御することが可能である。例えば、基板１０１の凸部１２の基部幅ｄ１を１μｍとした場合には、下地層１０３のＸＲＣ半値幅は１５０～２００ａｒｃｓｅｃ程度となる。なお基部幅ｄ１を本発明の好ましい範囲にしておくと、半値幅は１５０ａｒｃｓｅｃ以上となりやすい。
　一方、基板に凸部を形成せずに、Ｃ面のみからなる主面上に下地層を形成した場合には、光取り出し効率が低下するため好ましくない。また、基板の凸部の基部幅を２μｍとした場合には、下地層のＸＲＣ半値幅は１００ａｒｃｓｅｃ以上１５０ａｒｃｓｅｃ未満程度となり、下地層の結晶性が非常に高められた状態となる。しかしながら、このような結晶性の非常に高い下地層上に、上層として高濃度でＩｎを含有する井戸層を形成した場合には、下地層と井戸層との間の格子不整合が大きくなり、上述のように、井戸層に歪み等の結晶欠陥が生じてしまう。
　このため、本発明においては、下地層１０３の（１０－１０）面のＸＲＣ半値幅を１５０ａｒｃｓｅｃ以上とすることが、下地層１０３の結晶性を適正に制御する点から好ましい。なお、下地層のＸＲＣ半値幅が２５０ａｒｃｓｅｃを超えると結晶性が低下し過ぎるので、２５０ａｒｃｓｅｃ以下となるように制御することが好ましい。 The XRC half width of the underlayer 103 can be appropriately controlled by the base width d 1 of the convex portion 12 formed on the substrate 101 described above. For example, when the base width d 1 of the convex portion 12 of the substrate 101 is 1 μm, the XRC half width of the base layer 103 is about 150 to 200 arcsec. If the base width d 1 is kept within the preferred range of the present invention, the half width tends to be 150 arcsec or more.
On the other hand, it is not preferable to form a base layer on the main surface consisting only of the C-plane without forming a convex portion on the substrate because the light extraction efficiency is lowered. Further, when the base width of the convex portion of the substrate is 2 μm, the XRC half-value width of the underlayer is about 100 arcsec or more and less than 150 arcsec, and the crystallinity of the underlayer is greatly enhanced. However, when a well layer containing In at a high concentration is formed as an upper layer on such a highly crystalline underlayer, the lattice mismatch between the underlayer and the well layer increases, As described above, crystal defects such as strain are generated in the well layer.
Therefore, in the present invention, it is preferable that the XRC half-value width of the (10-10) plane of the underlayer 103 is 150 arcsec or more from the viewpoint of controlling the crystallinity of the underlayer 103 appropriately. In addition, since crystallinity will fall too much when the XRC half value width of a base layer exceeds 250 arcsec, it is preferable to control so that it may become 250 arcsec or less.
　なお、本発明者等が鋭意研究した結果、上述のような下地層１０３上に、後述のｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６からなるＬＥＤ構造２０を積層した場合、ｐ型半導体層１０６側における（１０－１０）面のＸＲＣ半値幅についても、下地層１０３と同様の傾向のデータとなることが明らかとなっている。このため、本発明においては、結晶性を表す指標として下地層の（１０－１０）面のＸＲＣ半値幅を用いている。 In addition, as a result of intensive studies by the present inventors, when an LED structure 20 including an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106, which will be described later, is stacked on the base layer 103 as described above, p It has been clarified that the XRC half-value width of the (10-10) plane on the side of the mold semiconductor layer 106 has the same tendency as that of the base layer 103. Therefore, in the present invention, the XRC half width of the (10-10) plane of the underlayer is used as an index representing crystallinity.
『ＬＥＤ構造』　
　ＬＥＤ構造２０は、各々がＩＩＩ族窒化物半導体からなるｎ型半導体層１０４と発光層１０５とｐ型半導体層１０６とを有する。このようなＬＥＤ構造２０の各層を、ＭＯＣＶＤ法で形成することにより、より結晶性の高い層を得る事ができる。 "LED structure"
The LED structure 20 includes an n-type semiconductor layer 104, a light-emitting layer 105, and a p-type semiconductor layer 106 each made of a group III nitride semiconductor. By forming each layer of such an LED structure 20 by MOCVD, a layer with higher crystallinity can be obtained.
「ｎ型半導体層」
　ｎ型半導体層１０４は、通常ｎ型コンタクト層１０４ａとｎ型クラッド層１０４ｂとから構成される。ｎ型コンタクト層１０４ａはｎ型クラッド層１０４ｂを兼ねることも可能である。 "N-type semiconductor layer"
The n-type semiconductor layer 104 is generally composed of an n-type contact layer 104a and an n-type cladding layer 104b. The n-type contact layer 104a can also serve as the n-type cladding layer 104b.
　ｎ型コンタクト層１０４ａは、負極を設けるための層である。ｎ型コンタクト層１０４ａは、ＡｌｘＧａ１－ｘＮ層（０≦ｘ＜１、好ましくは０≦ｘ≦０．５、さらに好ましくは０≦ｘ≦０．１）から構成されることが好ましい。また、ｎ型コンタクト層１０４ａにはｎ型不純物がドープされていることが好ましく、ｎ型不純物を１×１０１７～１×１０２０／ｃｍ３、好ましくは１×１０１８～１×１０１９／ｃｍ３の濃度で含有すると、負極との良好なオーミック接触の維持の点で好ましい。ｎ型不純物としては、特に限定されないが、例えば、Ｓｉ、ＧｅおよびＳｎ等が挙げられ、好ましくはＳｉおよびＧｅが挙げられる。 The n-type contact layer 104a is a layer for providing a negative electrode. The n-type contact layer 104a is preferably composed of an Al x Ga 1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). . The n-type contact layer 104a is preferably doped with an n-type impurity, and the n-type impurity is preferably 1 × 10 17 to 1 × 10 20 / cm 3 , preferably 1 × 10 18 to 1 × 10 19 /. Containing at a concentration of cm 3 is preferable in terms of maintaining good ohmic contact with the negative electrode. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably Si and Ge are mentioned.
　ｎ型コンタクト層１０４ａの膜厚は、０．５～５μｍであることが好ましく、１～３μｍの範囲に設定することがより好ましい。ｎ型コンタクト層１０４ａの膜厚が上記範囲にあると、半導体の結晶性が良好に維持される。 The film thickness of the n-type contact layer 104a is preferably 0.5 to 5 μm, and more preferably set to a range of 1 to 3 μm. When the film thickness of the n-type contact layer 104a is in the above range, the crystallinity of the semiconductor is maintained well.
　ｎ型コンタクト層１０４ａと発光層１０５との間には、ｎ型クラッド層１０４ｂを設けることが好ましい。ｎ型クラッド層１０４ｂは、発光層１０５へのキャリアの注入とキャリアの閉じ込めを行なう層である。ｎ型クラッド層１０４ｂはＡｌＧａＮや、ＧａＮ、及びＧａＩｎＮなどで形成することが可能である。また、これらをヘテロ接合した構造や、複数回積層した超格子構造としてもよい。ｎ型クラッド層１０４ｂをＧａＩｎＮで形成する場合には、発光層１０５のＧａＩｎＮのバンドギャップよりも、ｎ型クラッド層１０４ｂのバンドギャップを大きくすることが望ましいことは言うまでもない。 It is preferable to provide an n-type cladding layer 104b between the n-type contact layer 104a and the light emitting layer 105. The n-type cladding layer 104b is a layer that injects carriers into the light emitting layer 105 and confines carriers. The n-type cladding layer 104b can be formed of AlGaN, GaN, GaInN, or the like. Further, a structure in which these are heterojunctioned or a superlattice structure in which a plurality of layers are laminated may be used. Needless to say, when the n-type cladding layer 104b is formed of GaInN, it is desirable to make the band gap of the n-type cladding layer 104b larger than the band gap of GaInN of the light emitting layer 105.
　ｎ型クラッド層１０４ｂの膜厚は、特に限定されないが、好ましくは０．００５～０．５μｍであり、より好ましくは０．００５～０．１μｍである。ｎ型クラッド層１０４ｂのｎ型ドープ濃度は１×１０１７～１×１０２０／ｃｍ３が好ましく、より好ましくは１×１０１８～１×１０１９／ｃｍ３である。ドープ濃度がこの範囲であると、良好な結晶性の維持および素子の動作電圧低減の点で好ましい。 The film thickness of the n-type cladding layer 104b is not particularly limited, but is preferably 0.005 to 0.5 μm, and more preferably 0.005 to 0.1 μm. The n-type doping concentration of the n-type cladding layer 104b is preferably 1 × 10 17 to 1 × 10 20 / cm 3 , more preferably 1 × 10 18 to 1 × 10 19 / cm 3 . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.
　なお、ｎ型クラッド層１０４ｂを、超格子構造を含む層とする場合には、詳細な図示を省略するが、１００オングストローム以下の膜厚を有したＩＩＩ族窒化物半導体からなるｎ側第１層と、前記ｎ側第１層と組成が異なるとともに１００オングストローム以下の膜厚を有したＩＩＩ族窒化物半導体からなるｎ側第２層とが積層された構造を含むｎ型クラッド層１０４ｂであっても良い。また、ｎ型クラッド層１０４ｂは、ｎ側第１層とｎ側第２層とが交互に繰返し積層された構造を含んだものであってもよい。また、好ましくは、前記ｎ側第１層又はｎ側第２層の何れかが、活性層（発光層１０５）に接する構成とすれば良い。 When the n-type cladding layer 104b is a layer including a superlattice structure, a detailed illustration is omitted, but an n-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less. And an n-type cladding layer 104b including a structure in which an n-side second layer made of a group III nitride semiconductor having a composition different from that of the n-side first layer and having a thickness of 100 angstroms or less is laminated. Also good. The n-type cladding layer 104b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. Preferably, either the n-side first layer or the n-side second layer is in contact with the active layer (light-emitting layer 105).
　上述のようなｎ側第１層及びｎ側第２層の組成としては、例えば、Ａｌを含むＡｌＧａＮ系（単にＡｌＧａＮと記載することがある）、Ｉｎを含むＧａＩｎＮ系（単にＧａＩｎＮと記載することがある）、またはＧａＮの組成とすることができる。また、ｎ側第１層及びｎ側第２層の構造は、ＧａＩｎＮ／ＧａＮの交互構造、ＡｌＧａＮ／ＧａＮの交互構造、ＧａＩｎＮ／ＡｌＧａＮの交互構造、組成の異なるＧａＩｎＮ／ＧａＩｎＮの交互構造（本発明における“組成の異なる”との説明は、各元素組成比が異なることを指し、以下同様である）、組成の異なるＡｌＧａＮ／ＡｌＧａＮの交互構造であってもよい。本発明においては、ｎ側第１層及びｎ側第２層は、ＧａＩｎＮ／ＧａＮの交互構造又は組成の異なるＧａＩｎＮ／ＧａＩｎＮであることが好ましい。 Examples of the composition of the n-side first layer and the n-side second layer as described above include, for example, AlGaN-based Al (sometimes simply referred to as AlGaN) and GaInN-based (including simply InGa). Or a composition of GaN. The n-side first layer and the n-side second layer have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, a GaInN / AlGaN alternating structure, and a GaInN / GaInN alternating structure having a different composition (the present invention). The description of “different compositions” in FIG. 4 indicates that the elemental composition ratios are different, and the same applies hereinafter), and may be AlGaN / AlGaN alternating structures having different compositions. In the present invention, the n-side first layer and the n-side second layer are preferably GaInN / GaInN having different GaInN / GaN structures or different compositions.
　上記超格子層であるｎ側第１層及びｎ側第２層は、それぞれ６０オングストローム以下であることが好ましく、それぞれ４０オングストローム以下であることがより好ましく、それぞれ１０オンストローム～４０オングストロームの範囲であることが最も好ましい。超格子層を形成するｎ側第１層とｎ側第２層のそれぞれの膜厚が１００オングストローム超だと、結晶欠陥が入りやすく好ましくない。 The n-side first layer and the n-side second layer, which are superlattice layers, are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Most preferably it is. If the thickness of each of the n-side first layer and the n-side second layer forming the superlattice layer exceeds 100 angstroms, crystal defects are likely to occur, which is not preferable.
　上記ｎ側第１層及びｎ側第２層は、それぞれドープした構造であってもよく、また、ドープ構造／未ドープ構造の組み合わせであってもよい。ドープされる不純物としては、上記材料組成に対して従来公知のものを、何ら制限無く適用できる。例えば、ｎ型クラッド層として、ＧａＩｎＮ／ＧａＮの交互構造、又は組成の異なるＧａＩｎＮ／ＧａＩｎＮの交互構造であるｎ側第１層及びｎ側第２層の組み合わせを用いた場合には、不純物としてＳｉが好適である。また、上述のようなｎ側超格子多層膜は、ＧａＩｎＮやＡｌＧａＮ、ＧａＮで代表される同じ組成を用いながら、ドーピングを適宜ＯＮ、ＯＦＦしながら、多層構造を作製してもよい。
　上述のように、ｎ型クラッド層１０４ｂを、超格子構造を含む層構成とすることで、発光出力が格段に向上し、電気特性に優れた発光素子１とすることが可能となる。 The n-side first layer and the n-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure. As the impurity to be doped, conventionally known impurities can be applied to the material composition without any limitation. For example, when an n-type cladding layer is formed of an alternate structure of GaInN / GaN or a combination of an n-side first layer and an n-side second layer having an alternate structure of GaInN / GaInN having different compositions, Si as an impurity. Is preferred. In addition, the n-side superlattice multilayer film as described above may be formed in a multilayer structure using the same composition typified by GaInN, AlGaN, and GaN while appropriately turning ON / OFF doping.
As described above, when the n-type cladding layer 104b has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting element 1 having excellent electric characteristics can be obtained.
「発光層」
　ｎ型半導体層１０４の上に積層される発光層１０５としては、単一量子井戸構造あるいは多重量子井戸構造などの発光層１０５が挙げられる。図４に示すような量子井戸構造の井戸層としては、例えば、青色発光を呈する構成とする場合には、通常、Ｇａ１－ｙＩｎｙＮ（０＜ｙ＜０．０４）である組成のＩＩＩ族窒化物半導体が用いられるが、本発明のような緑色発光を呈する井戸層１０５ｂの場合には、Ｇａ１－ｙＩｎｙＮ（０．０７＜ｙ＜０．２０）等、インジウムの組成が高められたものが用いられる。 "Light emitting layer"
Examples of the light emitting layer 105 stacked on the n-type semiconductor layer 104 include a light emitting layer 105 having a single quantum well structure or a multiple quantum well structure. As a well layer having a quantum well structure as shown in FIG. 4, for example, in the case of a structure exhibiting blue light emission, a composition having a composition of Ga 1-y In y N (0 <y <0.04) is usually used. Although a group III nitride semiconductor is used, in the case of the well layer 105b exhibiting green light emission as in the present invention, the composition of indium such as Ga 1-y In y N (0.07 <y <0.20) is used. The one with increased is used.
　本発明のような多重量子井戸構造の発光層１０５の場合には、上記Ｇａ１－ｙＩｎｙＮを井戸層１０５ｂとし、井戸層１０５ｂよりバンドギャップエネルギーが大きいＡｌｘＧａ１－ｘＮ（０≦ｚ＜０．３）を障壁層１０５ａとすることが好ましい。
　また、井戸層１０５ｂおよび障壁層１０５ａには、設計により不純物をドープしても、又はしなくてもよい。 In the case of the light emitting layer 105 having the multiple quantum well structure as in the present invention, the Ga 1-y In y N is used as the well layer 105b, and Al x Ga 1-x N (0 ≦ z <0.3) is preferably the barrier layer 105a.
Further, the well layer 105b and the barrier layer 105a may or may not be doped with impurities depending on the design.
　また、井戸層１０５ｂの膜厚は、例えば量子効果の得られる程度の膜厚、すなわち１～１０ｎｍとすることができ、より好ましくは２～６ｎｍとすると発光出力の点で好ましい。 The film thickness of the well layer 105b can be, for example, a film thickness at which a quantum effect can be obtained, that is, 1 to 10 nm, and more preferably 2 to 6 nm from the viewpoint of light emission output.
　ＩＩＩ族窒化物半導体発光素子の発光色を緑色発光とするためには、発光波長が４９０ｎｍ以上である必要がある。また、良好な緑色発光を得るためには、発光波長が４９０～５７０ｎｍの範囲であることがより好ましい。
　このため、本発明の発光素子１においては、発光層１０５を形成する井戸層１０５ｂのＩｎ組成比を７％以上とすることが好ましい。井戸層１０５ｂのＩｎ濃度がこの範囲であれば、発光波長が４９０～５７０ｎｍの良好な緑色発光が得られる。 In order for the group III nitride semiconductor light emitting device to emit green light, the emission wavelength needs to be 490 nm or more. In order to obtain good green light emission, the emission wavelength is more preferably in the range of 490 to 570 nm.
For this reason, in the light emitting element 1 of the present invention, the In composition ratio of the well layer 105b forming the light emitting layer 105 is preferably 7% or more. If the In concentration of the well layer 105b is within this range, good green light emission with an emission wavelength of 490 to 570 nm can be obtained.
　本発明に係る発光素子１は、井戸層１０５ｂのＩｎ濃度が上述したような高濃度であり、上記範囲の発光波長であることで、緑色発光するものである。このように、緑色発光を目的として、発光層１０５に含まれる井戸層１０５ｂを高いＩｎ濃度で構成した場合、下側の層である下地層１０３の結晶性が適正範囲を超えて高められると、井戸層と下地層との間で格子不整合が大きくなり、井戸層に歪み等の欠陥が生じてしまう問題がある。このため、従来の緑色発光する発光素子のように、単に井戸層のＩｎ濃度を高めるのみの構成では、井戸層の結晶欠陥に伴って内部量子効率が低下するため、発光強度が低いものとなってしまう。 The light emitting element 1 according to the present invention emits green light when the In concentration of the well layer 105b is as high as described above and the emission wavelength is in the above range. Thus, for the purpose of green light emission, when the well layer 105b included in the light emitting layer 105 is configured with a high In concentration, when the crystallinity of the underlying layer 103, which is the lower layer, is increased beyond the appropriate range, There is a problem in that lattice mismatch increases between the well layer and the base layer, and defects such as strain occur in the well layer. For this reason, in the configuration in which the In concentration of the well layer is simply increased as in the conventional light emitting element that emits green light, the internal quantum efficiency is reduced due to crystal defects in the well layer, and thus the emission intensity is low. End up.
　通常では、井戸層及び発光層全体の結晶性を向上させることを目的とした場合、発光層が積層されるｎ型半導体層や下地層の結晶性を可能な限り高めておくことが考えられる。しかしながら、本発明者等が鋭意研究したところ、単に発光層が積層されるｎ型半導体層や下地層の結晶性を高めただけでは、井戸層のＩｎ濃度が高濃度とされる発光素子においては、ｎ型半導体層や下地層と、発光層（井戸層）との間の格子定数の不整合が一層大きくなることがわかった。このため、井戸層に歪み等の欠陥が生じ、内部量子効率が低下するのに伴って、発光出力が低下してしまうことが明らかとなった。 Usually, for the purpose of improving the crystallinity of the entire well layer and the light emitting layer, it is conceivable to increase the crystallinity of the n-type semiconductor layer and the base layer on which the light emitting layer is laminated as much as possible. However, as a result of diligent research by the present inventors, in a light-emitting element in which the In concentration of the well layer is made high by simply increasing the crystallinity of the n-type semiconductor layer or the underlayer on which the light-emitting layer is laminated. It has been found that the lattice constant mismatch between the light emitting layer (well layer) and the n-type semiconductor layer or the underlying layer is further increased. For this reason, it became clear that defects such as strain occurred in the well layer and the light emission output decreased as the internal quantum efficiency decreased.
　本発明においては、上述のように、まず、基板１０１を、平面部１１と凸部１２とからなる主面１０及びその裏面を有し、凸部１２の基部幅を０．０５～１．５μｍの範囲となるように構成し、この基板１０１の主面１０上に、単結晶のＩＩＩ族窒化物半導体がエピタキシャル成長してなる下地層１０３を、平面部１１及び凸部１２を覆うように設ける。後述の製造方法において詳細を説明するが、サファイアからなる基板の主面に単結晶のＩＩＩ族窒化物半導体層をエピタキシャル成長させる場合、Ｃ面からはＣ軸方向に配向した単結晶がエピタキシャル成長しやすく、Ｃ面以外の主面上からはエピタキシャル成長が生じにくいという傾向がある。従って、本実施形態で説明する例においては、バッファ層１０２の形成された基板１０１の主面１０上に、単結晶のＩＩＩ族窒化物半導体からなる下地層１０３をエピタキシャル成長させると、Ｃ面に非平行の表面１２ｃからは結晶が成長せず、（０００１）Ｃ面からなる平面部１１からのみＣ軸方向に配向した結晶がエピタキシャル成長する。このため、基板１０１の主面１０に形成される下地層１０３は、主面１０上において凸部１２を覆うようにエピタキシャル成長し、結晶中に転位等の結晶欠陥を生じないため、結晶性が適正に制御された層となる。 In the present invention, as described above, first, the substrate 101 has the main surface 10 composed of the flat portion 11 and the convex portion 12 and the back surface thereof, and the base width of the convex portion 12 is 0.05 to 1.5 μm. A base layer 103 formed by epitaxially growing a single crystal group III nitride semiconductor is provided on the main surface 10 of the substrate 101 so as to cover the flat portion 11 and the convex portion 12. Although details will be described in the manufacturing method described later, when a single-crystal group III nitride semiconductor layer is epitaxially grown on the main surface of a substrate made of sapphire, a single crystal oriented in the C-axis direction is easily epitaxially grown from the C-plane, There is a tendency that epitaxial growth hardly occurs from the main surface other than the C-plane. Therefore, in the example described in this embodiment, when the base layer 103 made of a single crystal group III nitride semiconductor is epitaxially grown on the main surface 10 of the substrate 101 on which the buffer layer 102 is formed, the non-surface is formed on the C plane. A crystal does not grow from the parallel surface 12c, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane. Therefore, the underlying layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10 and does not cause crystal defects such as dislocations in the crystal. It becomes a controlled layer.
　そして、上述のように結晶性が適正範囲で良好に制御された下地層１０３の上に、ＬＥＤ構造２０を構成する各層を形成することにより、高いＩｎ濃度とされて緑色発光を呈する井戸層１０５ｂを形成した場合であっても、下地層１０３と井戸層１０５ｂとの間に、格子不整合が生じるのが抑制される。これにより、井戸層１０５ｂに歪み等の結晶欠陥が生じることがなく、内部量子効率の低下やリーク電流が生じるのを抑制することができ、電気的特性に優れるとともに発光出力が高い発光素子１とすることが可能となる。 Then, by forming each layer constituting the LED structure 20 on the base layer 103 whose crystallinity is well controlled in an appropriate range as described above, the well layer 105b exhibiting green light emission with a high In concentration. Even when the layer is formed, the occurrence of lattice mismatch between the base layer 103 and the well layer 105b is suppressed. Thereby, crystal defects such as strain do not occur in the well layer 105b, it is possible to suppress a decrease in internal quantum efficiency and a leak current, and the light emitting device 1 having excellent electrical characteristics and high light emission output. It becomes possible to do.
「ｐ型半導体層」
　ｐ型半導体層１０６は、通常、ｐ型クラッド層１０６ａおよびｐ型コンタクト層１０６ｂから構成される。また、ｐ型コンタクト層１０６ｂがｐ型クラッド層１０６ａを兼ねることも可能である。 "P-type semiconductor layer"
The p-type semiconductor layer 106 is generally composed of a p-type cladding layer 106a and a p-type contact layer 106b. The p-type contact layer 106b can also serve as the p-type cladding layer 106a.
　ｐ型クラッド層１０６ａは、発光層１０５へのキャリアの閉じ込めとキャリアの注入を行なう層である。ｐ型クラッド層１０６ａの組成としては、発光層１０５のバンドギャップエネルギーより大きくなる組成であって、発光層１０５へのキャリアの閉じ込めができるものであれば特に限定されない。好ましくは、ＡｌｘＧａ１－ｘＮ（０＜ｘ≦０．４）のものが好ましい組成として挙げられる。ｐ型クラッド層１０６ａがこのようなＡｌＧａＮからなると、発光層へのキャリアの閉じ込めの点で好ましい。ｐ型クラッド層１０６ａの膜厚は、特に限定されないが、好ましくは１～４００ｎｍであり、より好ましくは５～１００ｎｍである。ｐ型クラッド層１０６ａのｐ型ドープ濃度は、１×１０１８～１×１０２１／ｃｍ３が好ましく、より好ましくは１×１０１９～１×１０２０／ｃｍ３である。ｐ型ドープ濃度が上記範囲であると、結晶性を低下させることなく良好なｐ型結晶が得られる。
　また、ｐ型クラッド層１０６ａは、複数回積層した超格子構造としてもよい。 The p-type cladding layer 106 a is a layer that performs confinement of carriers and injection of carriers in the light emitting layer 105. The composition of the p-type cladding layer 106 a is not particularly limited as long as the composition is larger than the band gap energy of the light emitting layer 105 and can confine carriers in the light emitting layer 105. A preferable composition is Al x Ga 1-x N (0 <x ≦ 0.4). When the p-type cladding layer 106a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer. The film thickness of the p-type cladding layer 106a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm. The p-type doping concentration of the p-type cladding layer 106a is preferably 1 × 10 18 to 1 × 10 21 / cm 3 , more preferably 1 × 10 19 to 1 × 10 20 / cm 3 . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
The p-type cladding layer 106a may have a superlattice structure in which a plurality of layers are stacked.
　なお、ｐ型クラッド層１０６ａを、超格子構造を含む層とする場合には、詳細な図示は省略するが、１００オングストローム以下の膜厚を有したＩＩＩ族窒化物半導体からなるｐ側第１層と、前記ｐ側第１層と組成が異なるとともに１００オングストローム以下の膜厚を有したＩＩＩ族窒化物半導体からなるｐ側第２層とが積層された構造を含むｐ型クラッド層１０６ａであっても良い。また、ｐ側第１層とｐ側第２層とが交互に繰返し積層された構造を含んだｐ型クラッド層１０６ａであっても良い。 When the p-type cladding layer 106a is a layer including a superlattice structure, a detailed illustration is omitted, but a p-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less. A p-type cladding layer 106a including a structure in which a p-side second layer made of a group III nitride semiconductor having a composition different from that of the p-side first layer and having a thickness of 100 angstroms or less is laminated. Also good. Alternatively, the p-type cladding layer 106a may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.
　上述のようなｐ側第１層及びｐ側第２層の組成は、それぞれ異なる組成であってよく、例えば、ＡｌＧａＮ、ＧａＩｎＮ又はＧａＮの内の何れの組成であっても良い。またｐ側第１層及びｐ側第２層の構造は、ＧａＩｎＮ／ＧａＮの交互構造、ＡｌＧａＮ／ＧａＮの交互構造、又はＧａＩｎＮ／ＡｌＧａＮの交互構造であっても良い。本発明においては、ｐ側第１層及びｐ側第２層は、ＡｌＧａＮ／ＡｌＧａＮ又はＡｌＧａＮ／ＧａＮの交互構造であることが好ましい。 The composition of the p-side first layer and the p-side second layer as described above may be different compositions, for example, any composition of AlGaN, GaInN, or GaN. The p-side first layer and the p-side second layer may have a GaInN / GaN alternating structure, an AlGaN / GaN alternating structure, or a GaInN / AlGaN alternating structure. In the present invention, the p-side first layer and the p-side second layer preferably have an AlGaN / AlGaN or AlGaN / GaN alternating structure.
　上記ｐ側第１層及びｐ側第２層の超格子層は、それぞれ６０オングストローム以下であることが好ましく、それぞれ４０オングストローム以下であることがより好ましく、それぞれ１０オングストローム～４０オングストロームの範囲であることが最も好ましい。超格子層を形成するｐ側第１層とｐ側第２層のそれぞれの膜厚が１００オングストローム超だと、結晶欠陥等を多く含む層となり、好ましくない。 The superlattice layers of the p-side first layer and the p-side second layer are each preferably 60 angstroms or less, more preferably 40 angstroms or less, and each in the range of 10 angstroms to 40 angstroms. Is most preferred. If the thickness of each of the p-side first layer and the p-side second layer forming the superlattice layer exceeds 100 angstroms, it becomes a layer containing many crystal defects and the like, which is not preferable.
　上記ｐ側第１層及びｐ側第２層は、それぞれドープした構造であっても良く、また、ドープ構造／未ドープ構造の組み合わせであっても良い。ドープされる不純物としては、上記材料組成に対して従来公知のものを、何ら制限無く適用できる。例えば、ｐ型クラッド層として、ＡｌＧａＮ／ＧａＮの交互構造又は組成の異なるＡｌＧａＮ／ＡｌＧａＮの交互構造のものを用いた場合には、不純物としてＭｇが好適である。また、上述のようなｐ側超格子多層膜は、組成がＧａＩｎＮやＡｌＧａＮ、あるいはＧａＮのように同じであっても、ドーピングを適宜ＯＮ、ＯＦＦする事により、多層構造を作製できる。
　上述のように、ｐ型クラッド層１０５ａを、超格子構造を含む層構成とすることで、発光出力が格段に向上し、電気特性に優れた発光素子１とすることが可能となる。 The p-side first layer and the p-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure. As the impurity to be doped, conventionally known impurities can be applied to the material composition without any limitation. For example, when an AlGaN / GaN alternating structure or an AlGaN / AlGaN alternating structure having a different composition is used as the p-type cladding layer, Mg is suitable as the impurity. Further, even if the p-side superlattice multilayer film as described above has the same composition as GaInN, AlGaN, or GaN, a multilayer structure can be produced by appropriately turning ON / OFF doping.
As described above, when the p-type cladding layer 105a has a layer structure including a superlattice structure, the light emission output is remarkably improved and the light emitting device 1 having excellent electric characteristics can be obtained.
　ｐ型コンタクト層１０６ｂは、正極を設けるための層である。ｐ型コンタクト層１０６ｂは、ＡｌｘＧａ１－ｘＮ（０≦ｘ≦０．４）の組成である事が好ましい。Ａｌ組成が上記範囲であると、良好な結晶性の維持およびｐオーミック電極との良好なオーミック接触が可能である点で好ましい。ｐ型コンタクト層１０６ｂがｐ型不純物（ドーパント）を１×１０１８～１×１０２１／ｃｍ３の濃度、好ましくは５×１０１９～５×１０２０／ｃｍ３の濃度で含有していると、良好なオーミック接触の維持、クラック発生の防止、及び良好な結晶性の維持の点で好ましい。ｐ型不純物としては、特に限定されないが、例えば好ましくはＭｇが挙げられる。ｐ型コンタクト層１０６ｂの膜厚は、特に限定されないが、０．０１～０．５μｍが好ましく、より好ましくは０．０５～０．２μｍである。ｐ型コンタクト層１０６ｂの膜厚がこの範囲であると、発光出力の点で好ましい。 The p-type contact layer 106b is a layer for providing a positive electrode. The p-type contact layer 106b preferably has a composition of Al x Ga 1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity is maintained and good ohmic contact with the p ohmic electrode is possible. The p-type contact layer 106b contains a p-type impurity (dopant) at a concentration of 1 × 10 18 to 1 × 10 21 / cm 3 , preferably 5 × 10 19 to 5 × 10 20 / cm 3 . From the viewpoint of maintaining good ohmic contact, preventing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned. The thickness of the p-type contact layer 106b is not particularly limited, but is preferably 0.01 to 0.5 μm, and more preferably 0.05 to 0.2 μm. When the film thickness of the p-type contact layer 106b is within this range, it is preferable in terms of light emission output.
「電極」
　図５に示されるように、透光性導電酸化膜層からなる透光性正極１０９が、ｐ型半導体層１０６と接するように設けられる。正極ボンディングパッド１０７は、透光性正極１０９上の一部に設けられている。
　透光性正極１０９は、ＩＴＯ（Ｉｎ２Ｏ３－ＳｎＯ２）、ＡＺｎＯ（ＺｎＯ－Ａｌ２Ｏ３）、ＩＺｎＯ（Ｉｎ２Ｏ３－ＺｎＯ）、及びＧＺＯ（ＺｎＯ－Ｇａ２Ｏ３）から選ばれる少なくとも一種類を含んだ材料を、この技術分野でよく知られた慣用の手段で設けることによって得られる。また、透光性正極１０９の構造も、従来公知の構造を含めて如何なる構造のものも、何ら制限なく用いることができる。透光性正極１０９は、ｐ型半導体層１０６上のほぼ全面を覆うように形成しても構わないし、隙間を開けて格子状や樹形状に形成しても良い。透光性正極１０９を形成した後に、合金化や透明化を目的とした熱アニールを施す場合もあるが、施さなくても構わない。 "electrode"
As shown in FIG. 5, a translucent positive electrode 109 made of a translucent conductive oxide film layer is provided in contact with the p-type semiconductor layer 106. The positive electrode bonding pad 107 is provided on a part of the translucent positive electrode 109.
The translucent positive electrode 109 is selected from ITO (In 2 O 3 —SnO 2 ), AZnO (ZnO—Al 2 O 3 ), ISnO (In 2 O 3 —ZnO), and GZO (ZnO—Ga 2 O 3 ). Provided by a conventional means well known in the art. Moreover, the structure of the translucent positive electrode 109 can be used without any limitation, including a conventionally known structure. The translucent positive electrode 109 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 106, or may be formed in a lattice shape or a tree shape with a gap. After forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
　正極ボンディングパッド１０７は、回路基板やリードフレーム等との電気接続のために設けられる。正極ボンディングパッドとしては、Ａｕ、Ａｌ、ＮｉおよびＣｕ等を用いた各種構造が周知であり、これら周知の材料や構造を何ら制限無く用いることができる。 The positive electrode bonding pad 107 is provided for electrical connection with a circuit board, a lead frame or the like. As the positive electrode bonding pad, various structures using Au, Al, Ni, Cu and the like are well known, and these known materials and structures can be used without any limitation.
　正極ボンディングパッド１０７の厚さは、１００～１５００ｎｍの範囲内であることが好ましい。また、ボンディングパッドの特性上、厚さが大きい方が、ボンダビリティーが高くなるため、正極ボンディングパッド１０７の厚さは３００ｎｍ以上とすることがより好ましい。 The thickness of the positive electrode bonding pad 107 is preferably in the range of 100 to 1500 nm. Further, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 107 is more preferably 300 nm or more.
　一方、負極ボンディングパッド１０８は、ＬＥＤ構造２０のｎ型半導体層１０４に接するように形成される。このため、負極ボンディングパッド１０８を形成する際には、発光層１０５およびｐ型半導体層１０６の一部を除去してｎ型半導体層１０４のｎ型コンタクト層を露出させ、この上に負極ボンディングパッド１０８を設置する。 Meanwhile, the negative electrode bonding pad 108 is formed in contact with the n-type semiconductor layer 104 of the LED structure 20. For this reason, when forming the negative electrode bonding pad 108, the light emitting layer 105 and the p-type semiconductor layer 106 are partially removed to expose the n-type contact layer of the n-type semiconductor layer 104, and the negative electrode bonding pad is formed thereon. 108 is installed.
　負極ボンディングパッド１０８としては、各種組成や構造が周知であり、これら周知の組成や構造を何ら制限無く用いることができ、この技術分野でよく知られた慣用の手段で設けることができる。 As the negative electrode bonding pad 108, various compositions and structures are well known, and these well known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.
　以上説明したような、本発明に係るＩＩＩ族窒化物半導体発光素子１では、基板１０１が、（０００１）Ｃ面からなる平面部１１と複数の凸部１２とからなる主面１０を有し、凸部１２の基部幅ｄ１が０．０５～１．５μｍであり、下地層（ＩＩＩ族窒化物半導体層）１０３は、基板１０１の主面１０上に、平面部１１及び凸部１２を覆うようにＩＩＩ族窒化物半導体がエピタキシャル成長して形成されたものである。また、ＬＥＤ構造２０は、発光波長が４９０～５７０ｎｍの範囲である構成である。これらの特徴により、下地層１０３の結晶性が適正に制御されるので、この上に積層されるＬＥＤ構造２０との間で格子不整合が生じるのを抑制することができる。これにより、緑色発光を呈するＬＥＤ構造２０、特に発光層１０５に備えられる井戸層１０５ｂに歪み等が生じることが無く、内部量子効率の低下やリーク電流が生じるのを抑制することができるので、電気的特性に優れるとともに発光出力が高い発光素子１が得られる。また、基板１０１と下地層１０３との界面が、バッファ層１０２を介して凹凸とされることで、光の乱反射によって発光素子の内部への光の閉じ込めが低減されるため、光取り出し効率に優れた発光素子１が実現できる。またさらに、本発明においては、ｎ型クラッド層１０４ｂ及び／又はｐ型クラッド層１０５ａを、超格子構造を含む層構成とすることで出力が格段に向上し、電気特性に優れた発光素子１とすることができる。 In the group III nitride semiconductor light-emitting device 1 according to the present invention as described above, the substrate 101 has the principal surface 10 composed of the planar portion 11 composed of the (0001) C plane and the plurality of convex portions 12. The base width d 1 of the convex portion 12 is 0.05 to 1.5 μm, and the base layer (group III nitride semiconductor layer) 103 covers the planar portion 11 and the convex portion 12 on the main surface 10 of the substrate 101. Thus, the group III nitride semiconductor is formed by epitaxial growth. The LED structure 20 has a configuration in which the emission wavelength is in the range of 490 to 570 nm. Due to these characteristics, the crystallinity of the underlayer 103 is appropriately controlled, so that it is possible to suppress the occurrence of lattice mismatch with the LED structure 20 stacked thereon. As a result, the LED structure 20 that emits green light, in particular, the well layer 105b included in the light emitting layer 105 is not distorted, and it is possible to suppress a decrease in internal quantum efficiency and a leakage current. The light emitting device 1 having excellent optical characteristics and high light emission output can be obtained. In addition, since the interface between the substrate 101 and the base layer 103 is uneven through the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light, so that light extraction efficiency is excellent. The light emitting device 1 can be realized. Furthermore, in the present invention, the n-type cladding layer 104b and / or the p-type cladding layer 105a has a layer structure including a superlattice structure, whereby the output is remarkably improved and the light emitting device 1 having excellent electrical characteristics is provided. can do.
［ＩＩＩ族窒化物半導体発光素子の製造方法］
　本発明に係るＩＩＩ族窒化物半導体発光素子の製造方法は、基板１０１上に単結晶の下地層（ＩＩＩ族窒化物半導体層）１０３を形成し、前記下地層１０３上にＬＥＤ構造２０を形成する方法である。上記方法には、基板１０１の（０００１）Ｃ面からなる平面部１１上に、基部幅が０．０５～３μｍである複数の凸部１２を形成することにより、基板１０１上に平面部１１と凸部１２とからなる主面１０を形成する基板加工工程と、基板１０１の主面１０上にＩＩＩ族窒化物半導体をエピタキシャル成長させることにより、平面部１１及び凸部１２を覆うようにして下地層１０３を形成するエピタキシャル工程と、前記下地層１０３上に、前記発光波長が４９０～５７０ｎｍの範囲であるＬＥＤ構造２０を形成するＬＥＤ積層工程とが含まれる。
　以下、本発明の製造方法に備えられる各工程について詳しく説明する。 [Method for Producing Group III Nitride Semiconductor Light-Emitting Device]
In the method for manufacturing a group III nitride semiconductor light emitting device according to the present invention, a single crystal underlayer (group III nitride semiconductor layer) 103 is formed on a substrate 101, and an LED structure 20 is formed on the underlayer 103. Is the method. In the above method, a plurality of convex portions 12 having a base width of 0.05 to 3 μm are formed on the flat portion 11 made of the (0001) C surface of the substrate 101, thereby forming the flat portion 11 on the substrate 101. Substrate processing step for forming main surface 10 composed of convex portion 12 and a base layer so as to cover flat portion 11 and convex portion 12 by epitaxially growing a group III nitride semiconductor on main surface 10 of substrate 101 And an LED stacking process for forming the LED structure 20 having the emission wavelength in the range of 490 to 570 nm on the underlayer 103.
Hereinafter, each process with which the manufacturing method of this invention is equipped is demonstrated in detail.
『基板加工工程』
　図２は、図１の模式図に示す積層構造を製造する工程の一例を説明するための図である。具体的には、本実施形態の製造方法において用意される基板１０１を示す斜視図である。この基板１０１は、Ｃ面からなる平面部１１と、Ｃ面上に形成される複数の凸部１２とからなる主面１０を有してなる。以下、図２に示すような基板１０１を加工する方法の一例を説明する。 "Board processing process"
FIG. 2 is a diagram for explaining an example of a process for manufacturing the laminated structure shown in the schematic diagram of FIG. 1. Specifically, it is a perspective view showing a substrate 101 prepared in the manufacturing method of the present embodiment. The substrate 101 has a main surface 10 composed of a flat surface portion 11 composed of a C surface and a plurality of convex portions 12 formed on the C surface. Hereinafter, an example of a method for processing the substrate 101 as shown in FIG. 2 will be described.
　基板加工工程では、例えば、サファイア基板の（０００１）Ｃ面上に、Ｃ面に非平行の表面からなる複数の凸部１２を形成することにより、Ｃ面からなる平面部１１と凸部１２とからなる主面１０を有する基板１０１を製造する。このような基板加工工程は、例えば、基板１０１上における凸部１２の平面配置となるようにマスクを基板１０１上に形成するパターニング工程と、前記パターニング工程によって形成されたマスクを使って基板１０１をエッチングして凸部１２を形成するエッチング工程とを備えた方法であってもよい。 In the substrate processing step, for example, by forming a plurality of convex portions 12 having a surface non-parallel to the C plane on the (0001) C plane of the sapphire substrate, the plane portion 11 and the convex portion 12 having the C plane are formed. A substrate 101 having a main surface 10 made of is manufactured. Such a substrate processing step includes, for example, a patterning step for forming a mask on the substrate 101 so as to have a planar arrangement of the convex portions 12 on the substrate 101, and a substrate 101 using the mask formed by the patterning step. And a method including an etching step of forming the convex portion 12 by etching.
　本実施形態において、複数の凸部１２を形成する基板材料として、（０００１）Ｃ面を表面とするサファイア単結晶のウェーハが用いられる。ここで（０００１）Ｃ面を表面とする基板には、基板の面方位に（０００１）方向から±３°の範囲でオフ角が付与された基板も含まれる。また、Ｃ面に非平行の表面とは、（０００１）Ｃ面から±３°の範囲内にはない表面であることを意味する。 In this embodiment, a sapphire single crystal wafer having a (0001) C plane as a surface is used as a substrate material for forming the plurality of convex portions 12. Here, the substrate having the (0001) C plane as the surface includes a substrate in which an off angle is given in the range of ± 3 ° from the (0001) direction in the plane direction of the substrate. Further, the surface that is not parallel to the C plane means a surface that is not within a range of ± 3 ° from the (0001) C plane.
　前記パターニング工程は、一般的なフォトリソグラフィー法で行なうことができる。基板加工工程において形成する凸部１２の、基部１２ａの基部幅ｄ１は１．５μｍ以下であることが好ましい。このため、基板１０１の表面全面を均一にパターニングするためには、フォトリソグラフィー法の中でも、ステッパー露光法を用いることが好ましい。しかしながら、１μｍ以下の基部幅ｄ１である凸部１２のパターンを形成する場合には高価なステッパー装置が必要であり、高コストとなる。このため、凸部幅ｄ１が１μｍ以下であるマスクパターンを形成する場合には、光ディスクの分野で使用されているレーザー露光法、もしくはナノインプリント法、あるいは電子ビーム（ＥＢ）露光法等を用いることが好ましい。 The patterning process can be performed by a general photolithography method. Of the convex portions 12 be formed in the substrate processing process, the base width d 1 of the base portion 12a is preferably at 1.5μm or less. Therefore, in order to uniformly pattern the entire surface of the substrate 101, it is preferable to use a stepper exposure method among photolithography methods. However, when forming the pattern of the convex part 12 having a base width d 1 of 1 μm or less, an expensive stepper device is required, resulting in high cost. Therefore, when forming a mask pattern having a convex width d 1 of 1 μm or less, a laser exposure method, a nanoimprint method, an electron beam (EB) exposure method, or the like used in the field of optical discs is used. Is preferred.
　エッチング工程において基板をエッチングする方法としては、ドライエッチング法やウェットエッチング法が挙げられる。しかしながら、エッチング方法としてウェットエッチング法を用いる場合には、基板１０１の結晶面が露出されるため、Ｃ面に非平行の表面１２ｃからなる凸部１２を形成することが困難となる。このため、エッチング工程においては、ドライエッチング法を用いることが好ましい。 Examples of the method for etching the substrate in the etching process include a dry etching method and a wet etching method. However, when the wet etching method is used as the etching method, since the crystal plane of the substrate 101 is exposed, it is difficult to form the convex portion 12 formed of the surface 12c that is non-parallel to the C plane. For this reason, it is preferable to use a dry etching method in an etching process.
　Ｃ面に非平行の表面１２ｃにより構成される凸部１２は、例えば、上述したパターニング工程で形成されたマスクが消失するまで基板１０１をドライエッチングすることにより、形成することが出来る。より具体的にいえば、例えば、基板１０１上にレジストを形成し、その後所定の形状にパターニングする。その後、オーブン等を用いて１１０℃で３０分の熱処理を行なうポストベークにより、所定の形状のレジストの側面をテーパ状とする。次いで、横方向のエッチングを促進させる所定の条件で、レジストが消失するまでドライエッチングを行なうことにより、凸部１２を形成することができる。 The convex part 12 constituted by the surface 12c non-parallel to the C plane can be formed, for example, by dry etching the substrate 101 until the mask formed in the patterning process described above disappears. More specifically, for example, a resist is formed on the substrate 101 and then patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, the convex portion 12 can be formed by performing dry etching under predetermined conditions that promote lateral etching until the resist disappears.
　また、Ｃ面に非平行の表面１２ｃにより構成される凸部１２は、マスクを使って基板をドライエッチングした後、再度マスクを剥離して基板１０１をドライエッチングする方法を用いて形成することも出来る。より具体的にいえば、例えば、基板１０１上にレジストを形成し、所定の形状にパターニングする。この後、オーブン等を用いて１１０℃で３０分の熱処理を行なうポストベークにより、所定の形状のレジストの側面をテーパ状とする。次いで、横方向のエッチングを促進させる所定の条件でドライエッチングを行ない、レジストが消失する前にドライエッチングを中断する。その後、レジストを剥離してドライエッチングを再開し、所定量のエッチングを行なうことにより、凸部１２を形成することができる。このような方法で形成された凸部１２は、高さ寸法の面内均一性に優れたものとなる。 Further, the convex portion 12 constituted by the surface 12c non-parallel to the C-plane may be formed by using a method in which the substrate is dry-etched using a mask and then the mask is removed again and the substrate 101 is dry-etched. I can do it. More specifically, for example, a resist is formed on the substrate 101 and patterned into a predetermined shape. Thereafter, the side surface of the resist having a predetermined shape is tapered by post-baking in which heat treatment is performed at 110 ° C. for 30 minutes using an oven or the like. Next, dry etching is performed under a predetermined condition that promotes lateral etching, and the dry etching is interrupted before the resist disappears. Thereafter, the resist 12 is removed, dry etching is resumed, and a predetermined amount of etching is performed, whereby the convex portion 12 can be formed. The convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension.
　また、エッチング方法としてウェットエッチング法を用いる場合には、ドライエッチング法と組み合わせることにより、Ｃ面に非平行の表面１２ｃにより構成される凸部１２を形成することができる。
　ウェットエッチングとしては、例えば、基板１０１がサファイア単結晶からなるものである場合、２５０℃以上の高温とした燐酸と硫酸との混酸等を用いることにより、ウェットエッチングすることができる。
　ウェットエッチング法とドライエッチング法と組み合わせた方法としては、例えば、マスクが消失するまで基板１０１をドライエッチングした後、高温の酸を用いて所定量のウェットエッチングを行なう方法により、凸部１２を形成することができる。このような方法を用いて凸部１２を形成することにより、凸部１２の側面を構成する斜面に結晶面が露出され、再現性よく凸部１２の側面を構成する斜面の角度を形成することができる。また、主面１０に良好な結晶面を再現性よく露出させることができる。
　また、ウェットエッチング法とドライエッチング法と組み合わせたその他の方法としては、例えば、ＳｉＯ２等の酸に対して耐性を有する材料からなるマスクを形成してウェットエッチングを行なった後、マスクを剥離し、横方向のエッチングを促進させるための所定の条件でドライエッチングを行なう方法でも、凸部１２を形成することができる。このような方法で形成された凸部１２は、高さ寸法の面内均一性に優れたものとなる。また、このような方法を用いて凸部１２を形成した場合においても、再現性よく凸部１２の側面を構成する斜面の角度を形成することができる。
　また、凸部を酸化物もしくは窒化物で形成する場合には、基板上に材料を堆積させた後、ナノインプリント等の方法でパターニングされたマスクを形成させ、ドライエッチングもしくはウェットエッチングにより凸部を形成する方法とすることができる。 Further, when the wet etching method is used as the etching method, the convex portion 12 constituted by the surface 12c non-parallel to the C plane can be formed by combining with the dry etching method.
For example, when the substrate 101 is made of a sapphire single crystal, the wet etching can be performed by using a mixed acid of phosphoric acid and sulfuric acid at a high temperature of 250 ° C. or higher.
As a method of combining the wet etching method and the dry etching method, for example, after the substrate 101 is dry etched until the mask disappears, the convex portion 12 is formed by performing a predetermined amount of wet etching using a high-temperature acid. can do. By forming the convex portion 12 using such a method, the crystal plane is exposed on the slope constituting the side surface of the convex portion 12, and the angle of the slope constituting the side surface of the convex portion 12 is formed with good reproducibility. Can do. Further, a good crystal plane can be exposed to the main surface 10 with good reproducibility.
In addition, as another method in combination with the wet etching method and the dry etching method, for example, a mask made of a material resistant to an acid such as SiO 2 is formed and wet etching is performed, and then the mask is peeled off. The convex portion 12 can also be formed by a method of performing dry etching under a predetermined condition for promoting lateral etching. The convex part 12 formed by such a method is excellent in in-plane uniformity of the height dimension. Moreover, even when the convex part 12 is formed using such a method, the angle of the slope which comprises the side surface of the convex part 12 can be formed with sufficient reproducibility.
In addition, when the convex part is formed of oxide or nitride, after depositing a material on the substrate, a mask patterned by a method such as nanoimprinting is formed, and the convex part is formed by dry etching or wet etching. It can be a method to do.
　なお、本実施形態の製造方法においては、凸部を形成する方法としてエッチング法を用い、基板をエッチングする例を挙げて説明したが、本発明は上記方法に限定されるものではない。例えば、上述したように、基板上に凸部を構成する材料を堆積させることにより、凸部を形成する方法とすることも可能であり、適宜選択して採用することができる。 In addition, in the manufacturing method of this embodiment, although the example which etches a board | substrate using the etching method as a method of forming a convex part was demonstrated, this invention is not limited to the said method. For example, as described above, it is possible to adopt a method of forming a convex portion by depositing a material constituting the convex portion on the substrate, and the method can be appropriately selected and adopted.
『バッファ層形成工程』
　次に、バッファ層形成工程では、上記方法によって準備された基板１０１の主面１０上に、図１や図３に示されるようなバッファ層１０２を積層する。
　本実施形態で説明する例では、基板加工工程の後、エピタキシャル工程の前にバッファ層形成工程を行なうことにより、基板１０１の主面１０上に図１に示すようなバッファ層１０２を積層する。
　また、本発明においては、上述したようにバッファ層を省略した構成とすることも可能であり、この場合にはバッファ層形成工程を行なわなくても良い。 "Buffer layer formation process"
Next, in the buffer layer forming step, a buffer layer 102 as shown in FIGS. 1 and 3 is laminated on the main surface 10 of the substrate 101 prepared by the above method.
In the example described in this embodiment, the buffer layer 102 as shown in FIG. 1 is stacked on the main surface 10 of the substrate 101 by performing a buffer layer forming step after the substrate processing step and before the epitaxial step.
In the present invention, as described above, the buffer layer may be omitted. In this case, the buffer layer forming step may not be performed.
「基板の前処理」
　本実施形態では、基板１０１をスパッタ装置のチャンバ内に導入した後、バッファ層１０２を形成する前に、プラズマ処理による逆スパッタ等の方法を用いて前処理を行うことが望ましい。具体的には、基板１０１をＡｒやＮ２のプラズマ中に曝す事によって、表面を整えることができる。例えば、ＡｒガスやＮ２ガスなどのプラズマを基板１０１表面に作用させる逆スパッタにより、基板１０１表面に付着した有機物や酸化物を除去することができる。この場合、基板１０１とチャンバとの間に電圧を印加すれば、プラズマ粒子が効率的に基板１０１に作用する。このような前処理を基板１０１に施すことにより、その後の工程で、基板１０１の表面全面にわたってバッファ層１０２を成膜することができ、その上に成膜されるＩＩＩ族窒化物半導体からなる膜の結晶性を高めることが可能となる。また、基板１０１には、上述のような逆スパッタによる前処理を行なう前に、湿式の前処理を施すことがより好ましい。 "Pretreatment of substrate"
In this embodiment, after introducing the substrate 101 into the chamber of the sputtering apparatus and before forming the buffer layer 102, it is desirable to perform pretreatment using a method such as reverse sputtering by plasma treatment. Specifically, the surface can be prepared by exposing the substrate 101 to Ar or N 2 plasma. For example, organic matter and oxide attached to the surface of the substrate 101 can be removed by reverse sputtering in which plasma such as Ar gas or N 2 gas is applied to the surface of the substrate 101. In this case, if a voltage is applied between the substrate 101 and the chamber, the plasma particles efficiently act on the substrate 101. By applying such pretreatment to the substrate 101, the buffer layer 102 can be formed over the entire surface of the substrate 101 in the subsequent steps, and a film made of a group III nitride semiconductor formed thereon It becomes possible to increase the crystallinity. Further, it is more preferable that the substrate 101 is subjected to a wet pretreatment before the pretreatment by reverse sputtering as described above.
　また、基板１０１への前処理としては、Ｎ＋、（Ｎ２）＋などのイオン成分と、Ｎラジカル、Ｎ２ラジカルなどの電荷を持たないラジカル成分とが混合された雰囲気で行なわれる、プラズマ処理で行なうことが好ましい。
　基板の表面から有機物や酸化物等のコンタミを除去する際に、例えば、イオン成分等を単独で基板表面に供給した場合には、エネルギーが強すぎて基板表面にダメージを与えてしまい、基板上に成長させる結晶の品質を低下させてしまう問題がある。本実施形態においては、基板１０１への前処理を、上述のようなイオン成分とラジカル成分とが混合された雰囲気で行なわれるプラズマ処理を用いた方法とすることが好ましい、その結果、基板１０１に適度なエネルギーを持つ反応種を作用させることにより、基板１０１表面にダメージを与えずにコンタミ等の除去を行なうことが可能となる。このような効果が得られるメカニズムとしては、イオン成分の割合が少ないプラズマを用いることで基板１０１表面に与えるダメージが抑制されることと、基板１０１表面にプラズマを作用させることによって効果的にコンタミを除去できること等が考えられる。 In addition, as the pretreatment for the substrate 101, plasma is performed in an atmosphere in which ion components such as N + and (N 2 ) + and radical components having no charge such as N radicals and N 2 radicals are mixed. It is preferable to carry out by processing.
When removing contaminants such as organic substances and oxides from the surface of the substrate, for example, if an ionic component or the like is supplied to the substrate surface alone, the energy is too strong and the substrate surface is damaged, There is a problem in that the quality of the crystal to be grown is lowered. In the present embodiment, it is preferable that the pretreatment on the substrate 101 is a method using plasma treatment performed in an atmosphere in which an ionic component and a radical component are mixed as described above. By allowing a reactive species having an appropriate energy to act, it is possible to remove contamination and the like without damaging the surface of the substrate 101. As a mechanism for obtaining such an effect, damage caused to the surface of the substrate 101 is suppressed by using plasma with a small proportion of ion components, and contamination is effectively performed by causing plasma to act on the surface of the substrate 101. It can be considered that it can be removed.
「バッファ層の成膜」
　基板１０１に前処理を行なった後、基板１０１上に、反応性スパッタ法により、ＡｌＸＧａ１－ＸＮ（０≦Ｘ≦１）である組成のバッファ層１０２を成膜する。反応性スパッタ法によって単結晶構造を有するバッファ層１０２を形成する場合、スパッタ装置のチャンバ内の窒素原料と不活性ガスの合計流量に対する窒素原料の流量の比を、５０～１００％の範囲となるように制御することが好ましく、７５％程度とすることがより好ましい。
　また、柱状結晶（多結晶）構造を有するバッファ層１０２を形成する場合には、スパッタ装置のチャンバ内の窒素原料と不活性ガスの合計流量に対する窒素原料の流量の比を、１～５０％の範囲となるように制御することが好ましく、２５％程度とすることがより好ましい。 "Deposition of buffer layer"
After performing the pretreatment to the substrate 101 on the substrate 101 by a reactive sputtering method, forming an Al X Ga 1-X N ( 0 ≦ X ≦ 1) buffer layer 102 of the composition it is. When the buffer layer 102 having a single crystal structure is formed by the reactive sputtering method, the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is in the range of 50 to 100%. It is preferable to control so that it is about 75%.
When the buffer layer 102 having a columnar crystal (polycrystalline) structure is formed, the ratio of the flow rate of the nitrogen source to the total flow rate of the nitrogen source and the inert gas in the chamber of the sputtering apparatus is 1 to 50%. It is preferable to control to be within the range, and more preferably about 25%.
　バッファ層１０２は、上述した反応性スパッタ法に限らず、例えば、ＭＯＣＶＤ法を用いて形成することも可能である。しかしながら、基板１０１の主面１０には凸部１２が形成されているため、ＭＯＣＶＤ法でバッファ層を形成した場合、主面１０で原料ガスの流れが乱れてしまう虞がある。このようなＭＯＣＶＤ法に対し、反応性スパッタ法は原料粒子の直進性が高いので、主面１０の形状に影響を受けずに均一なバッファ層１０２を積層することが可能である。従って、バッファ層１０２は、反応性スパッタ法を用いて形成することが好ましい。 The buffer layer 102 is not limited to the reactive sputtering method described above, and can be formed using, for example, the MOCVD method. However, since the convex portion 12 is formed on the main surface 10 of the substrate 101, the flow of the source gas may be disturbed on the main surface 10 when the buffer layer is formed by the MOCVD method. In contrast to the MOCVD method, the reactive sputtering method has a high degree of straightness of the raw material particles, so that the uniform buffer layer 102 can be stacked without being affected by the shape of the main surface 10. Therefore, the buffer layer 102 is preferably formed using a reactive sputtering method.
『エピタキシャル工程及びＬＥＤ積層工程』
　上記バッファ層形成工程の後、図１や図３に示すように、基板１０１の主面１０上に形成されたバッファ層１０２上に、単結晶のＩＩＩ族窒化物半導体をエピタキシャル成長させて、主面１０を覆うように下地層（ＩＩＩ族窒化物半導体層）１０３を形成するエピタキシャル工程を行なう。
　また、エピタキシャル工程においてＩＩＩ族窒化物半導体からなる下地層１０３を形成した後、ＬＥＤ積層工程において、下地層１０３上に、ｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６の各層からなるＬＥＤ構造２０を形成する。
　なお、本実施形態においては、それぞれＩＩＩ族窒化物半導体を用いて各層を成膜するエピタキシャル工程及びＬＥＤ積層工程について、両工程に共通する構成の説明を、一部、省略することがある。 "Epitaxial process and LED stacking process"
After the buffer layer forming step, as shown in FIGS. 1 and 3, a single crystal group III nitride semiconductor is epitaxially grown on the buffer layer 102 formed on the main surface 10 of the substrate 101. An epitaxial process is performed to form a base layer (group III nitride semiconductor layer) 103 so as to cover 10.
In addition, after the base layer 103 made of a group III nitride semiconductor is formed in the epitaxial process, the LED stacking process includes the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103. An LED structure 20 is formed.
In the present embodiment, the description of the configuration common to both processes may be partially omitted for the epitaxial process and the LED stacking process in which each layer is formed using a group III nitride semiconductor.
　本発明において、下地層１０３、ｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６を形成する際の窒化ガリウム系化合物半導体（ＩＩＩ族窒化物半導体）の成長方法は特に限定されない。反応性スパッタ法、ＭＯＣＶＤ（有機金属化学気相成長法）、ＨＶＰＥ（ハイドライド気相成長法）、ＭＢＥ（分子線エピタキシー法）等、窒化物半導体を成長させることが知られている全ての方法を適用できる。
これらの方法の内、ＭＯＣＶＤ法では、例えば、キャリアガスとして水素（Ｈ２）または窒素（Ｎ２）、ＩＩＩ族原料であるＧａ源としてトリメチルガリウム（ＴＭＧ）またはトリエチルガリウム（ＴＥＧ）、Ａｌ源としてトリメチルアルミニウム（ＴＭＡ）またはトリエチルアルミニウム（ＴＥＡ）、Ｉｎ源としてトリメチルインジウム（ＴＭＩ）またはトリエチルインジウム（ＴＥＩ）、Ｖ族原料であるＮ源としてアンモニア（ＮＨ３）、ヒドラジン（Ｎ２Ｈ４）などを用いることができる。また、ドーパントとしては、ｎ型にはＳｉ原料としてモノシラン（ＳｉＨ４）またはジシラン（Ｓｉ２Ｈ６）を利用でき、またＧｅ原料としてゲルマンガス（ＧｅＨ４）や、テトラメチルゲルマニウム（（ＣＨ３）４Ｇｅ）やテトラエチルゲルマニウム（（Ｃ２Ｈ５）４Ｇｅ）等の有機ゲルマニウム化合物を利用できる。ＭＢＥ法では、元素状のゲルマニウムもドーピング源として利用できる。ｐ型にはＭｇ原料としては、例えばビスシクロペンタジエニルマグネシウム（Ｃｐ２Ｍｇ）またはビスエチルシクロペンタジエニルマグネシウム（ＥｔＣｐ２Ｍｇ）を用いることができる。
　また、上述したような窒化ガリウム系化合物半導体は、Ａｌ、ＧａおよびＩｎ以外に他のＩＩＩ族元素を含有することができ、必要に応じてＧｅ、Ｓｉ、Ｍｇ、Ｃａ、Ｚｎ、及びＢｅ等のドーパント元素を含有することができる。さらに、意図的に添加した元素に限らず、成膜条件等に依存して必然的に含まれる不純物、並びに原料、反応管材質に含まれる微量不純物を含む場合もある。
　本発明においては、上記各方法の中でも、結晶性の良好な膜が得られる点からＭＯＣＶＤ法を用いることが好ましく、本実施形態では、エピタキシャル工程及びＬＥＤ積層工程においてＭＯＣＶＤ法を用いた例について説明する。 In the present invention, the growth method of the gallium nitride compound semiconductor (group III nitride semiconductor) when forming the base layer 103, the n-type semiconductor layer 104, the light emitting layer 105, and the p-type semiconductor layer 106 is not particularly limited. All methods known to grow nitride semiconductors such as reactive sputtering, MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), etc. Applicable.
Among these methods, in the MOCVD method, for example, hydrogen (H 2 ) or nitrogen (N 2 ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source as a group III source, and as an Al source Trimethylaluminum (TMA) or triethylaluminum (TEA), trimethylindium (TMI) or triethylindium (TEI) as the In source, ammonia (NH 3 ), hydrazine (N 2 H 4 ), etc. as the N source that is a group V source Can be used. Moreover, as a dopant, monosilane (SiH 4 ) or disilane (Si 2 H 6 ) can be used as a Si raw material for the n-type, and germane gas (GeH 4 ) or tetramethyl germanium ((CH 3 ) as a Ge raw material. Organic germanium compounds such as 4 Ge) and tetraethyl germanium ((C 2 H 5 ) 4 Ge) can be used. In the MBE method, elemental germanium can also be used as a doping source. For the p-type, for example, biscyclopentadienyl magnesium (Cp 2 Mg) or bisethylcyclopentadienyl magnesium (EtCp 2 Mg) can be used as the Mg raw material.
Further, the gallium nitride compound semiconductor as described above can contain other group III elements in addition to Al, Ga, and In, and can contain Ge, Si, Mg, Ca, Zn, and Be as necessary. A dopant element can be contained. Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.
In the present invention, among the above methods, the MOCVD method is preferably used from the viewpoint of obtaining a film having good crystallinity. In the present embodiment, an example using the MOCVD method in the epitaxial process and the LED stacking process will be described. To do.
「エピタキシャル工程（下地層の形成）」
　エピタキシャル工程では、図１に示すように、基板１０１上に形成されたバッファ層１０２の上に、下地層１０３を、従来公知のＭＯＣＶＤ法を用いて、基板１０１の主面１０をなす平面部１１及び凸部１２を覆うようにして形成する。 "Epitaxial process (underlayer formation)"
In the epitaxial process, as shown in FIG. 1, a base layer 103 is formed on a buffer layer 102 formed on a substrate 101 by using a conventionally known MOCVD method, and a planar portion 11 that forms the main surface 10 of the substrate 101. And it forms so that the convex part 12 may be covered.
（成膜条件）
　本実施形態の製造方法では、ＭＯＣＶＤ法を用いて下地層１０３を形成している。しかしながら、下地層１０３を積層する方法としては特に限定されず、転位のループ化を生じさせることができる結晶成長方法であれば、何ら制限なく用いることができる。特に、ＭＯＣＶＤ法やＭＢＥ法、ＶＰＥ法等は、マイグレーションを生じさせることができるため、結晶性の良好な膜を形成することが可能となる点で好適である。中でも、ＭＯＣＶＤ法は、特に結晶性の良好な膜を得ることができる点で、より好適に用いることができる。 (Deposition conditions)
In the manufacturing method of the present embodiment, the underlayer 103 is formed using the MOCVD method. However, the method for stacking the base layer 103 is not particularly limited, and any crystal growth method that can cause dislocation looping can be used without any limitation. In particular, the MOCVD method, the MBE method, the VPE method, and the like are preferable in that a film with favorable crystallinity can be formed because migration can occur. Among these, the MOCVD method can be used more suitably in that a film having particularly good crystallinity can be obtained.
　例えば、ＭＯＣＶＤ法を用いてサファイア基板の主面に単結晶のＩＩＩ族窒化物半導体層を成長させると、Ｃ面からは単結晶層がエピタキシャル成長するが、Ｃ面以外の主面上には単結晶層がエピタキシャル成長しないという特性がある。つまり、本実施形態で説明する例では、バッファ層１０２の形成された基板１０１の主面１０上に、単結晶のＩＩＩ族窒化物半導体からなる下地層１０３をエピタキシャル成長させると、Ｃ面に非平行の表面１２ｃからは結晶が成長せず、（０００１）Ｃ面からなる平面部１１からのみＣ軸方向に配向した結晶がエピタキシャル成長する。これにより、基板１０１の主面１０に形成される下地層１０３は、主面１０上において凸部１２を覆うようにエピタキシャル成長するので、結晶中に転位等の結晶欠陥を生じないため、結晶性が適正に制御された層となる。 For example, when a single crystal group III nitride semiconductor layer is grown on the main surface of a sapphire substrate using MOCVD, a single crystal layer is epitaxially grown from the C surface, but a single crystal is formed on the main surface other than the C surface. The layer does not grow epitaxially. That is, in the example described in this embodiment, when the base layer 103 made of a single crystal group III nitride semiconductor is epitaxially grown on the main surface 10 of the substrate 101 on which the buffer layer 102 is formed, it is non-parallel to the C plane. A crystal does not grow from the surface 12c of the first layer, and a crystal oriented in the C-axis direction grows epitaxially only from the flat portion 11 made of the (0001) C plane. As a result, the base layer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown so as to cover the convex portion 12 on the main surface 10, so that crystal defects such as dislocations do not occur in the crystal, so that the crystallinity is improved. A properly controlled layer.
　凸部１２の形成された基板１０１は、凸部１２の形成されていない基板と比較して、主面１０に下地層１０３をＭＯＣＶＤ法でエピタキシャル成長した場合に、平坦性の良好な下地層１０３を積層することが困難である。また、凸部１２の形成された基板１０１の主面１０に積層された下地層１０３は、結晶性を悪化させるＣ軸方向の傾き（チルト）やＣ軸のねじれ（ツイスト）等が生じやすい。このため、凸部１２の形成された基板１０１の主面１０に下地層１０３をＭＯＣＶＤ法でエピタキシャル成長させる場合、十分な表面平坦性や良好な結晶性を得るために、以下に示す成長条件とすることが望ましい。 The substrate 101 on which the protrusions 12 are formed has a better flatness when the underlayer 103 is epitaxially grown on the main surface 10 by the MOCVD method than the substrate on which the protrusions 12 are not formed. It is difficult to stack. In addition, the base layer 103 laminated on the main surface 10 of the substrate 101 on which the convex portions 12 are formed is liable to cause a tilt in the C-axis direction that deteriorates the crystallinity, a twist in the C-axis, or the like. Therefore, when the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, the following growth conditions are used in order to obtain sufficient surface flatness and good crystallinity. It is desirable.
　凸部１２の形成された基板１０１の主面１０に下地層１０３をＭＯＣＶＤ法でエピタキシャル成長させる場合には、成長圧力および成長温度を以下に説明するような条件とすることが好ましい。
　一般に、成長圧力を低くして成長温度を高くすると、横方向の結晶成長が促進され、一方で、成長圧力を高くして成長温度を低くすると、ファセット成長モード（△形状）になる。また、成長初期の成長圧力を高くすると、Ｘ線ロッキングカーブの半値幅（ＸＲＣ－ＦＷＨＭ）が小さくなり、結晶性が向上する傾向がある。 When the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, it is preferable that the growth pressure and the growth temperature are set as described below.
Generally, when the growth pressure is lowered and the growth temperature is raised, lateral crystal growth is promoted. On the other hand, when the growth pressure is raised and the growth temperature is lowered, the facet growth mode (Δ shape) is entered. Further, when the growth pressure at the initial stage of growth is increased, the half-value width (XRC-FWHM) of the X-ray rocking curve is decreased, and the crystallinity tends to be improved.
　以上の事から、凸部１２の形成された基板１０１の主面１０上に下地層１０３をＭＯＣＶＤ法でエピタキシャル成長させる場合には、成長圧力を２段階に変化させることが好ましい。すなわち、下地層１０３の膜厚が２μｍ程度以上になるまで（前半成膜）と、下地層１０３を２μｍ程度以上積層した後（後半成膜）とで、成長圧力を変化させることが好ましい。
　成長圧力は前半成膜においては、４０ｋＰａ以上とすることが好ましく、６０ｋＰａ程度とすることがより好ましい。成長圧力を４０ｋＰａ以上とすると、ファセット成長モード（△形状）になり、転位が横方向に屈曲し、エピタキシャル表面に貫通しない。このため、成長圧力を高くする事で、低転位化され、結晶性が良好となると推定される。成長圧力を４０ｋＰａ未満とすると、結晶性が悪化し、Ｘ線ロッキングカーブの半値幅（ＸＲＣ－ＦＷＨＭ）が大きくなるため好ましくない。 From the above, when the base layer 103 is epitaxially grown by the MOCVD method on the main surface 10 of the substrate 101 on which the convex portions 12 are formed, it is preferable to change the growth pressure in two stages. That is, it is preferable to change the growth pressure until the film thickness of the underlayer 103 is about 2 μm or more (first half film formation) and after the underlayer 103 is laminated about 2 μm or more (second half film formation).
In the first half film formation, the growth pressure is preferably 40 kPa or more, and more preferably about 60 kPa. When the growth pressure is set to 40 kPa or more, a facet growth mode (Δ shape) is set, dislocations bend in the lateral direction, and do not penetrate the epitaxial surface. For this reason, it is presumed that by increasing the growth pressure, the dislocation is lowered and the crystallinity is improved. If the growth pressure is less than 40 kPa, the crystallinity is deteriorated and the half width (XRC-FWHM) of the X-ray rocking curve is increased, which is not preferable.
　しかしながら前半成膜において、成長圧力を４０ｋＰａ以上とすると、エピタキシャル成長させた下地層１０３の表面にピットが発生しやすくなり、十分な表面平坦性が得られない場合がある。
このため、成長圧力を４０ｋＰａ以上とする場合、成長温度を１１４０℃以下とすることが好ましく、１１２０℃程度とすることがより好ましい。成長温度を１１４０℃以下とすることで、成長圧力を４０ｋＰａ以上、好ましくは６０ｋＰａ程度とした場合であっても、ピットの発生を十分に抑制できる。 However, if the growth pressure is 40 kPa or more in the first half film formation, pits are likely to be generated on the surface of the epitaxially grown base layer 103, and sufficient surface flatness may not be obtained.
For this reason, when the growth pressure is 40 kPa or more, the growth temperature is preferably 1140 ° C. or less, and more preferably about 1120 ° C. By setting the growth temperature to 1140 ° C. or lower, the generation of pits can be sufficiently suppressed even when the growth pressure is 40 kPa or more, preferably about 60 kPa.
　また、後半成膜においては、成長圧力を４０ｋＰａ以下とすることが好ましく、２０ｋＰａ程度とすることがより好ましい。後半成膜において成長圧力を４０ｋＰａ以下とすることで、横方向の結晶成長を促進することができ、表面平坦性に優れた下地層１０３が得られる。 In the latter half film formation, the growth pressure is preferably 40 kPa or less, more preferably about 20 kPa. By setting the growth pressure to 40 kPa or less in the latter half film formation, the lateral crystal growth can be promoted, and the base layer 103 having excellent surface flatness can be obtained.
　なお、下地層１０３には、必要に応じて、不純物をドープして成膜することができるが、アンドープとすることが、結晶性が向上する点から好ましい。
　また、反応性スパッタ法を用いてＩＩＩ族窒化物半導体からなる下地層１０３を成膜することも可能である。スパッタ法を用いる場合には、ＭＯＣＶＤ法やＭＢＥ法等と比較して、装置を簡便な構成とすることが可能となる。 Note that the base layer 103 can be formed by being doped with impurities as necessary, but undoped is preferable from the viewpoint of improving crystallinity.
It is also possible to form the base layer 103 made of a group III nitride semiconductor by using a reactive sputtering method. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.
　以上説明したようなエピタキシャル工程により、図１に示す積層構造が得られる。
　本発明に係るＩＩＩ族窒化物半導体発光素子の製造方法では、上述したような基板加工工程に次いで、主面１０上に、平面部１１及び凸部１２を覆うようにして下地層１０３を成長させるエピタキシャル工程を備えているので、下地層１０３の結晶中に転位などの結晶欠陥が生じにくく、結晶性が適正な範囲で良好に制御された下地層１０３が形成できる。 By the epitaxial process as described above, the stacked structure shown in FIG. 1 is obtained.
In the method for manufacturing a group III nitride semiconductor light-emitting device according to the present invention, after the substrate processing step as described above, the base layer 103 is grown on the main surface 10 so as to cover the planar portion 11 and the convex portion 12. Since the epitaxial process is provided, crystal defects such as dislocations are not easily generated in the crystal of the base layer 103, and the base layer 103 in which the crystallinity is well controlled within an appropriate range can be formed.
　ここで、例えば、凸部の表面にＣ面が存在する場合、凸部の形成された基板上に単結晶のＩＩＩ族窒化物半導体をエピタキシャル成長させると、凸部の表面に存在するＣ面と、凸部の形成されていない領域のＣ面とから結晶が成長することになる。この場合、凸部の表面から成長した結晶と、凸部の形成されていない領域から成長した結晶とが合体した部分に転位などの結晶欠陥が発生しやすく、結晶性の良好なＩＩＩ族窒化物半導体が得られにくい。ここで生じた結晶欠陥は、ＩＩＩ族窒化物半導体からなる下地層の上に、ｎ型半導体層、発光層、ｐ型半導体層からなるＬＥＤ構造を形成した場合、ＬＥＤ構造を構成する半導体層の結晶に引き継がれ、発光素子を形成した場合における内部量子効率の低下やリーク電流の増大の原因となる虞がある。 Here, for example, when a C-plane exists on the surface of the convex portion, when a single crystal group III nitride semiconductor is epitaxially grown on the substrate on which the convex portion is formed, the C-plane existing on the surface of the convex portion, A crystal grows from the C-plane of the region where no convex portion is formed. In this case, a crystal defect such as dislocation is likely to occur in a portion where the crystal grown from the surface of the convex portion and the crystal grown from the region where the convex portion is not formed, and the group III nitride having good crystallinity It is difficult to obtain a semiconductor. When the LED structure which consists of an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer is formed on the base layer which consists of a group III nitride semiconductor, the crystal defect which arose here is the semiconductor layer which comprises LED structure. If the light-emitting element is formed by the crystal, the internal quantum efficiency may be reduced and the leakage current may be increased.
　これに対し、本発明では、上述したように、基板１０１上にＣ面に非平行の表面１２ｃからなる凸部１２を形成することにより、Ｃ面からなる平面部１１と凸部１２とからなる主面１０を形成する。その結果、基板１０１の主面１０に下地層１０３のエピタキシャル成長を行った場合、平面部１１からのみ結晶が成長する。従って、基板１０１の主面１０に形成される下地層１０３は、主面１０上において凸部１２を覆うようにエピタキシャル成長し、結晶中に転位などの結晶欠陥を生じない。
　また、基板１０１と下地層１０３との界面が、バッファ層１０２を介して凹凸とされることで、光の乱反射によって発光素子の内部への光の閉じ込めが低減されるため、発光素子１の光取り出し効率をより向上させることが可能となる。 On the other hand, in the present invention, as described above, the convex portion 12 made of the surface 12c that is non-parallel to the C plane is formed on the substrate 101, so that the flat portion 11 made of the C plane and the convex portion 12 are formed. The main surface 10 is formed. As a result, when the base layer 103 is epitaxially grown on the main surface 10 of the substrate 101, crystals grow only from the planar portion 11. Therefore, the underlayer 103 formed on the main surface 10 of the substrate 101 is epitaxially grown on the main surface 10 so as to cover the convex portions 12, and crystal defects such as dislocations do not occur in the crystal.
In addition, since the interface between the substrate 101 and the base layer 103 is uneven via the buffer layer 102, light confinement inside the light-emitting element is reduced due to irregular reflection of light. The extraction efficiency can be further improved.
（Ｘ線ロッキングカーブ半値幅）
　本発明では、上述したように、エピタキシャル工程により、凸部１２を備えた基板１０１の主面１０上にＩＩＩ族窒化物半導体からなる下地層１０３を形成した状態での、下地層１０３の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることが好ましい。下地層１０３の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅がこのような数値であれば、下地層１０３の結晶性が適正範囲で良好に制御され、この上に形成されるＬＥＤ構造２０と間で格子不整合が生じるのを抑制できる。従って、後述のＬＥＤ積層工程において、井戸層１０５ｂにインジウム（Ｉｎ）を高濃度で添加し、高温で成長させた場合であっても、井戸層１０５ｂに歪み等の結晶欠陥が生じるのを抑制することが可能となる。 (X-ray rocking curve half width)
In the present invention, as described above, (10) of the base layer 103 in a state where the base layer 103 made of a group III nitride semiconductor is formed on the main surface 10 of the substrate 101 provided with the protrusions 12 by the epitaxial process. It is preferable that the X-ray rocking curve (XRC) half-width in the −10) plane is 150 arcsec or more. If the X-ray rocking curve (XRC) half-value width in the (10-10) plane of the underlayer 103 is such a numerical value, the crystallinity of the underlayer 103 is well controlled within an appropriate range, and is formed thereon. It is possible to suppress a lattice mismatch between the LED structure 20 and the LED structure 20. Accordingly, in the later-described LED stacking step, even when indium (In) is added to the well layer 105b at a high concentration and grown at a high temperature, the occurrence of crystal defects such as strain in the well layer 105b is suppressed. It becomes possible.
「ＬＥＤ積層工程」
　次に、ＬＥＤ積層工程において、上記エピタキシャル工程の後、図３に示すように、下地層１０３の上に、ｎ型半導体層１０４、発光層１０５及びｐ型半導体層１０６の各層からなるＬＥＤ構造２０を、従来公知のＭＯＣＶＤ法を用いて積層する。 "LED lamination process"
Next, in the LED stacking step, after the epitaxial step, as shown in FIG. 3, the LED structure 20 composed of the n-type semiconductor layer 104, the light-emitting layer 105, and the p-type semiconductor layer 106 on the base layer 103. Are stacked using a conventionally known MOCVD method.
（ｎ型半導体層の形成）
　上記エピタキシャル工程で形成された下地層１０３の上に、従来公知のＭＯＣＶＤ法を用いて、ｎ型コンタクト層１０４ａ及びｎ型クラッド層１０４ｂを順次積層することにより、ｎ型半導体層１０４を形成する。ｎ型コンタクト層１０４ａ及びｎ型クラッド層１０４ｂを形成する成膜装置としては、上述の下地層１０３や後述の発光層１０５の成膜に用いるＭＯＣＶＤ装置を、各種条件を適宜変更して用いることが可能である。また、ｎ型コンタクト層１０４ａ及びｎ型クラッド層１０４ｂを反応性スパッタ法で形成することも可能である。 (Formation of n-type semiconductor layer)
An n-type semiconductor layer 104 is formed by sequentially laminating an n-type contact layer 104a and an n-type clad layer 104b on the base layer 103 formed by the epitaxial process using a conventionally known MOCVD method. As a film forming apparatus for forming the n-type contact layer 104a and the n-type clad layer 104b, the MOCVD apparatus used for forming the base layer 103 and the light-emitting layer 105 described later may be used by appropriately changing various conditions. Is possible. Further, the n-type contact layer 104a and the n-type cladding layer 104b can be formed by a reactive sputtering method.
（発光層の形成）
　次いで、ｎ型クラッド層１０４ｂ（ｎ型半導体層１０４）上に、発光層１０５を、従来公知のＭＯＣＶＤ法によって形成する。本実施形態で形成する発光層１０５は、図４に例示するように、ＧａＮ障壁層に始まりＧａＮ障壁層に終わる積層構造を有している。すなわち、ＧａＮからなる７層の障壁層１０５ａと、ノンドープのＧａ０．８Ｉｎ０．２Ｎからなる６層の井戸層１０５ｂとを交互に積層して形成されている。また、本実施形態の製造方法では、上述したｎ型半導体層１０４の成膜に用いる成膜装置（ＭＯＣＶＤ装置）と同じものを使用して発光層１０５を成膜することができる。 (Formation of light emitting layer)
Next, the light emitting layer 105 is formed on the n-type cladding layer 104b (n-type semiconductor layer 104) by a conventionally known MOCVD method. As illustrated in FIG. 4, the light emitting layer 105 formed in the present embodiment has a stacked structure starting with a GaN barrier layer and ending with the GaN barrier layer. That is, seven barrier layers 105a made of GaN and six well layers 105b made of non-doped Ga 0.8 In 0.2 N are alternately stacked. In the manufacturing method of this embodiment, the light emitting layer 105 can be formed using the same film forming apparatus (MOCVD apparatus) used for forming the n-type semiconductor layer 104 described above.
　本発明では、井戸層１０５ｂに含有されるＩｎの濃度を、例えば７質量％以上の高濃度とすることにより、発光波長が４９０～５７０ｎｍの範囲の緑色発光を呈する発光素子を構成できる。このように、井戸層１０５ｂに含有されるＩｎを高濃度とした場合、井戸層１０５ｂの成長温度を、例えば７００～８００℃程度とする必要がある。本発明の製造方法では、このような高い成長温度を用いて井戸層１０５ｂを成膜し、Ｉｎ組成が低下することによって結晶性の低下が生じた場合であっても、半値幅のコントロールによって下地層１０３との間での格子不整合が抑制されるので、井戸層１０５に歪み等の結晶欠陥が生じるのを防止することができる。これにより、内部量子効率の低下が抑制され、高い発光出力を備えた発光素子を製造することが可能となる。 In the present invention, by setting the concentration of In contained in the well layer 105b to a high concentration of, for example, 7% by mass or more, a light emitting element that emits green light with an emission wavelength in the range of 490 to 570 nm can be configured. As described above, when the concentration of In contained in the well layer 105b is high, the growth temperature of the well layer 105b needs to be about 700 to 800 ° C., for example. In the manufacturing method of the present invention, even when the well layer 105b is formed using such a high growth temperature and the crystallinity is lowered due to the decrease in the In composition, the lowering is achieved by controlling the half width. Since lattice mismatch with the ground layer 103 is suppressed, crystal defects such as strain can be prevented from occurring in the well layer 105. Thereby, the fall of internal quantum efficiency is suppressed and it becomes possible to manufacture the light emitting element provided with the high light emission output.
（ｐ型半導体層の形成）
　次いで、発光層１０５上、つまり、発光層１０５の最上層となる障壁層１０５ａの上に、ｐ型クラッド層１０６ａ及びｐ型コンタクト層１０６ｂからなるｐ型半導体層１０６を、従来公知のＭＯＣＶＤ法を用いて形成する。ｐ型半導体層１０６の形成には、ｎ型半導体層１０４及び発光層１０５の形成に用いるＭＯＣＶＤ装置と同じ装置を、各種条件を適宜変更して用いることが可能である。また、ｐ型半導体層１０６を構成するｐ型クラッド層１０６ａ及びｐ型コンタクト層１０６ｂを、反応性スパッタ法を用いて形成することも可能である。 (Formation of p-type semiconductor layer)
Next, the p-type semiconductor layer 106 composed of the p-type cladding layer 106a and the p-type contact layer 106b is formed on the light-emitting layer 105, that is, on the barrier layer 105a that is the uppermost layer of the light-emitting layer 105 by a conventionally known MOCVD method. Use to form. For the formation of the p-type semiconductor layer 106, the same apparatus as the MOCVD apparatus used for forming the n-type semiconductor layer 104 and the light-emitting layer 105 can be used by appropriately changing various conditions. In addition, the p-type cladding layer 106a and the p-type contact layer 106b constituting the p-type semiconductor layer 106 can be formed using a reactive sputtering method.
　本実施形態では、まず、ＭｇをドープしたＡｌ０．１Ｇａ０．９Ｎからなるｐ型クラッド層１０６ａを発光層１０５（最上層の障壁層１０５ａ）上に形成し、さらにその上に、ＭｇをドープしたＡｌ０．０２Ｇａ０．９８Ｎからなるｐ型コンタクト層１０６ｂを形成する。この際、ｐ型クラッド層１０６ａ及びｐ型コンタクト層１０６ｂの積層には、同じＭＯＣＶＤ装置を用いることができる。なお、上述したように、ｐ型不純物としては、Ｍｇのみならず、例えば亜鉛（Ｚｎ）等も同様に用いることができる。 In the present embodiment, first, a p-type cladding layer 106a made of Al 0.1 Ga 0.9 N doped with Mg is formed on the light emitting layer 105 (the uppermost barrier layer 105a), and further, Mg A p-type contact layer 106b made of Al 0.02 Ga 0.98 N doped with is formed. At this time, the same MOCVD apparatus can be used for stacking the p-type cladding layer 106a and the p-type contact layer 106b. As described above, not only Mg but also zinc (Zn), for example, can be used as the p-type impurity.
『電極の形成』
　次に、ＬＥＤ積層工程おいてＬＥＤ構造２０が形成されたウェーハに対し、図３に例示するように、電極を設置する。具体的には、ｐ型半導体層１０６上の所定の位置に透光性正極１０９を形成した後、前記透光性正極１０９の各々の上に正極ボンディングパッド１０７を形成する。またＬＥＤ構造２０の所定の位置をエッチング除去することにより、ｎ型半導体層１０４を露出させて露出領域１０４ｃを形成し、前記露出領域１０４ｃに負極ボンディングパッド１０８を形成する。 "Formation of electrodes"
Next, as illustrated in FIG. 3, electrodes are installed on the wafer on which the LED structure 20 is formed in the LED stacking step. Specifically, after forming a translucent positive electrode 109 at a predetermined position on the p-type semiconductor layer 106, a positive electrode bonding pad 107 is formed on each of the translucent positive electrodes 109. Also, the n-type semiconductor layer 104 is exposed by etching away a predetermined position of the LED structure 20 to form an exposed region 104c, and a negative electrode bonding pad 108 is formed in the exposed region 104c.
「透光性正極の形成」
　まず、上記方法によって各層が形成されてなる積層半導体１０のｐ型コンタクト層１０６ｂ上に、ＩＴＯからなる透光性正極１０９を形成する。
　透光性正極１０９の形成方法としては、特に限定されず、この技術分野でよく知られた慣用の手段で設けることができる。また、その構造も、従来公知の構造を含めて如何なる構造のものも何ら制限なく用いることができる。 "Formation of translucent cathode"
First, the translucent positive electrode 109 made of ITO is formed on the p-type contact layer 106b of the laminated semiconductor 10 in which each layer is formed by the above method.
A method for forming the translucent positive electrode 109 is not particularly limited, and the translucent positive electrode 109 can be provided by a common means well known in this technical field. Further, any structure including a conventionally known structure can be used without any limitation.
　また、上述したように、透光性正極１０９の材料は、ＩＴＯには限定されず、ＡＺＯ、ＩＺＯ、及びＧＺＯ等の材料を用いて形成することが可能である。また、透光性正極１０９を形成した後、合金化や透明化を目的とした熱アニールを施す場合もあるが、施さなくても構わない。 Further, as described above, the material of the translucent positive electrode 109 is not limited to ITO, and can be formed using materials such as AZO, IZO, and GZO. Further, after forming the translucent positive electrode 109, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.
「正極ボンディングパッド及び負極ボンディングパッドの形成」
　次いで、積層半導体１０上に形成された透光性正極１０９上に、さらに、正極ボンディングパッド１０７を形成する。この正極ボンディングパッド１０７は、例えば、透光性正極１０９の表面側から順に、Ｔｉ、Ａｌ、及びＡｕの各材料を、従来公知の方法で積層することによって形成することができる。 “Formation of positive and negative bonding pads”
Next, a positive electrode bonding pad 107 is further formed on the translucent positive electrode 109 formed on the laminated semiconductor 10. The positive electrode bonding pad 107 can be formed, for example, by laminating Ti, Al, and Au materials in order from the surface side of the translucent positive electrode 109 by a conventionally known method.
　また、負極ボンディングパッド１０８を形成する際は、まず、基板１０１上に形成されたｐ型半導体層１０６、発光層１０５及びｎ型半導体層１０４の一部をドライエッチング等の方法によって除去することにより、ｎ型コンタクト層１０４ａの露出領域１０４ｃを形成する。そして、この露出領域１０４ｃ上に、例えば、露出領域１０４ｃ表面側から順に、Ｎｉ、Ａｌ、Ｔｉ、及びＡｕの各材料を従来公知の方法で積層することにより、詳細な図示を省略する４層構造の負極ボンディングパッド１０８を形成することができる。 Further, when forming the negative electrode bonding pad 108, first, a part of the p-type semiconductor layer 106, the light emitting layer 105, and the n-type semiconductor layer 104 formed on the substrate 101 is removed by a method such as dry etching. The exposed region 104c of the n-type contact layer 104a is formed. Then, on this exposed region 104c, for example, each material of Ni, Al, Ti, and Au is sequentially laminated from the surface side of the exposed region 104c by a conventionally known method, thereby omitting detailed illustration. The negative electrode bonding pad 108 can be formed.
　以上説明したような、本発明に係るＩＩＩ族窒化物半導体発光素子の製造方法には、基板１０１の（０００１）Ｃ面からなる平面部１１上に、基部幅が０．０５～１．５μｍである複数の凸部１２を形成することにより、基板１０１上に平面部１１と凸部１２とからなる主面１０を形成する、基板加工工程と、基板１０１の主面１０上にＩＩＩ族窒化物半導体をエピタキシャル成長させることにより、平面部１１及び凸部１２を覆うようにして下地層を形成するエピタキシャル工程と、ＬＥＤ構造２０を、前記発光波長が４９０～５７０ｎｍの範囲であるＬＥＤ構造２０を形成するＬＥＤ積層工程と、が備えられている。本発明に係るＩＩＩ族窒化物半導体発光素子の製造方法によれば、結晶性が適正に制御された下地層１０３を形成することができ、この層の上に形成されるＬＥＤ構造２０、特に発光層１０５に備えられる井戸層１０５ｂとの間で格子不整合が生じるのが抑制され、歪み等を生じさせること無く井戸層１０５ｂ（発光層１０５）を形成することが可能となる。これにより、緑色発光を呈するＬＥＤ構造２０を形成する場合においても、内部量子効率及び光取り出し効率に優れ、高い発光特性を有するＩＩＩ族窒化物半導体発光素子を製造することが可能となる。 In the method for manufacturing a group III nitride semiconductor light-emitting device according to the present invention as described above, the base width is 0.05 to 1.5 μm on the planar portion 11 made of the (0001) C plane of the substrate 101. A substrate processing step of forming a plurality of convex portions 12 to form main surface 10 composed of flat portion 11 and convex portions 12 on substrate 101, and a group III nitride on main surface 10 of substrate 101 By epitaxially growing a semiconductor, an epitaxial process for forming a base layer so as to cover the planar portion 11 and the convex portion 12 and an LED structure 20 having the emission wavelength in the range of 490 to 570 nm are formed. LED lamination process. According to the method for manufacturing a group III nitride semiconductor light emitting device according to the present invention, it is possible to form the underlayer 103 with properly controlled crystallinity, and the LED structure 20 formed on this layer, particularly light emission. The occurrence of lattice mismatch with the well layer 105b provided in the layer 105 is suppressed, and the well layer 105b (light-emitting layer 105) can be formed without causing distortion or the like. As a result, even when the LED structure 20 exhibiting green light emission is formed, a group III nitride semiconductor light emitting device having excellent internal quantum efficiency and light extraction efficiency and having high light emission characteristics can be manufactured.
［ランプ］
　本発明のランプには、本発明のＩＩＩ族窒化物半導体発光素子が用いられる。
　本発明のランプとしては、例えば、本発明のＩＩＩ族窒化物半導体発光素子と蛍光体とを組み合わせたものを挙げることができる。ＩＩＩ族窒化物半導体発光素子と蛍光体とを組み合わせたランプは、当業者周知の手段によって製造し、当業者周知の構成としても良い。また、従来より、ＩＩＩ族窒化物半導体発光素子と蛍光体と組み合わせることによって発光色を変える技術が知られており、本発明のランプにおいてもこのような技術を何ら制限されることなく採用することが可能である。 [lamp]
The group III nitride semiconductor light-emitting device of the present invention is used for the lamp of the present invention.
Examples of the lamp of the present invention include a combination of the group III nitride semiconductor light emitting device of the present invention and a phosphor. A lamp in which a group III nitride semiconductor light emitting device and a phosphor are combined may be manufactured by means well known to those skilled in the art and may have a structure well known to those skilled in the art. Conventionally, a technique for changing the emission color by combining a group III nitride semiconductor light-emitting element and a phosphor is known, and such a technique should be adopted in the lamp of the present invention without any limitation. Is possible.
　図５は、本発明に係るＩＩＩ族窒化物半導体発光素子を用いて構成したランプの一例を模式的に示した概略図である。図５に示すランプ３は、砲弾型のものであり、図３に示すＩＩＩ族窒化物半導体発光素子１が用いられている。図５に示すようにＩＩＩ族窒化物半導体発光素子１は実装される。すなわち、ＩＩＩ族窒化物半導体発光素子１の正極ボンディングパッド１０７がワイヤー３３により２本のフレーム３１、３２の内の一方（図５ではフレーム３１）に接着されており、発光素子１の負極ボンディングパッド１０８がワイヤー３４により他方のフレーム３２に接着されている。また、ＩＩＩ族窒化物半導体発光素子１の周辺は、透明な樹脂からなるモールド３５で封止されている。 FIG. 5 is a schematic view schematically showing an example of a lamp configured using the group III nitride semiconductor light emitting device according to the present invention. The lamp 3 shown in FIG. 5 is a cannonball type, and the group III nitride semiconductor light emitting device 1 shown in FIG. 3 is used. As shown in FIG. 5, the group III nitride semiconductor light emitting device 1 is mounted. That is, the positive electrode bonding pad 107 of the group III nitride semiconductor light emitting device 1 is bonded to one of the two frames 31 and 32 (the frame 31 in FIG. 5) by the wire 33, and the negative electrode bonding pad of the light emitting device 1. 108 is bonded to the other frame 32 by a wire 34. Further, the periphery of the group III nitride semiconductor light emitting device 1 is sealed with a mold 35 made of a transparent resin.
　本発明のランプは、本発明のＩＩＩ族窒化物半導体発光素子１が用いられているので、優れた発光特性を備えたものとなる。
　なお、本発明のランプは、形状や用途に制限はなく、一般用途の砲弾型、携帯のバックライト用途のサイドビュー型、表示器に用いられるトップビュー型等いかなる用途にも用いることができる。 Since the group III nitride semiconductor light emitting device 1 of the present invention is used, the lamp of the present invention has excellent light emission characteristics.
The lamp of the present invention is not limited in shape and use, and can be used for any use such as a general-use bullet type, a side view type for a portable backlight, and a top view type used for a display.
　次に、本発明のＩＩＩ族窒化物半導体発光素子を、実施例及び比較例を示してより詳細に説明するが、本発明はこれらの実施例にのみ限定されるものではない。 Next, the group III nitride semiconductor light-emitting device of the present invention will be described in more detail with reference to examples and comparative examples, but the present invention is not limited only to these examples.
［実施例１～２、比較例１～２］
　複数の（０００１）Ｃ面を有するサファイア基板を用意し、サファイア基板の（０００１）Ｃ面上に、表１に示すような「基部幅」、「高さ」、「基部幅／４」、「隣接する凸部間の間隔」及び「凸部表面Ｃ面の有無」の条件を満たす複数の凸部を、以下に示す方法によって形成することにより、実施例１～２及び比較例１の基板を形成した（基板加工工程）。凸部は、直径２インチのＣ面サファイア基板に公知のフォトリソグラフィー法でマスクを形成し、ドライエッチング法でサファイア基板をエッチングすることにより、形成した。なお、露光法として、紫外光を用いたステッパー露光法を用いた。また、ドライエッチングにはＢＣｌ３とＣｌ２の混合ガスを用いた。 [Examples 1 and 2, Comparative Examples 1 and 2]
A sapphire substrate having a plurality of (0001) C faces is prepared. On the (0001) C face of the sapphire substrate, “base width”, “height”, “base width / 4”, “ By forming a plurality of convex portions that satisfy the conditions of “interval between adjacent convex portions” and “presence / absence of convex surface C”, the substrates of Examples 1 and 2 and Comparative Example 1 are formed. Formed (substrate processing step). The convex portions were formed by forming a mask on a C-plane sapphire substrate having a diameter of 2 inches by a known photolithography method and etching the sapphire substrate by a dry etching method. As an exposure method, a stepper exposure method using ultraviolet light was used. In addition, a mixed gas of BCl 3 and Cl 2 was used for dry etching.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　このようにして得られた実施例１～２及び比較例１の基板の凸部は、凸部の基部の平面形状が円形で、上部に向かって徐々に外形（断面積）が小さくなる形状であり、側面が外側に向かって湾曲したお椀状（半球状）の形状であった。 The convex portions of the substrates of Examples 1 and 2 and Comparative Example 1 obtained in this way have a shape in which the planar shape of the base of the convex portion is circular and the outer shape (cross-sectional area) gradually decreases toward the top. Yes, it had a bowl-like (hemispherical) shape with side surfaces curved outward.
　また、上述のような基板加工工程を実施せず、凸部の無い、（０００１）Ｃ面からなる主面を有するサファイア基板を準備し、比較例２の基板とした。 In addition, a sapphire substrate having a principal surface made of a (0001) C surface without a convex portion without carrying out the substrate processing step as described above was prepared and used as a substrate of Comparative Example 2.
　次に、以下に詳細に示す方法で、実施例１～２及び比較例１の複数の凸部が形成された基板の主面に、ＲＦスパッタ法を用いて単結晶構造を有するＡｌＮからなる厚さ５０ｎｍバッファ層を形成した（バッファ層形成工程）。この際、スパッタ成膜装置としては、高周波式の電源を備え、ターゲット内でマグネットの位置を動かすことが可能な機構を有するものを使用した。また、以下に述べる同様の手順を用いて、凸部の無い比較例２の基板の主面上にも、単結晶構造を有するＡｌＮからなる厚さ５０ｎｍバッファ層を形成した。 Next, on the main surface of the substrate on which the plurality of convex portions of Examples 1 and 2 and Comparative Example 1 are formed by the method described in detail below, the thickness made of AlN having a single crystal structure using RF sputtering is used. A 50 nm buffer layer was formed (buffer layer forming step). At this time, as the sputtering film forming apparatus, an apparatus having a high-frequency power source and having a mechanism capable of moving the position of the magnet in the target was used. In addition, a 50 nm thick buffer layer made of AlN having a single crystal structure was also formed on the main surface of the substrate of Comparative Example 2 having no protrusions using the same procedure described below.
　まず、複数の凸部の形成された基板を、スパッタ成膜装置のチャンバ内へ導入して５００℃まで加熱し、チャンバ内に窒素ガスだけを１５ｓｃｃｍの流量で導入した。この後、チャンバ内の圧力を１Ｐａに保持して、基板側に５００Ｗの高周波バイアスを印加して基板を窒素プラズマに曝することで、基板の表面を洗浄した（前処理）。 First, a substrate having a plurality of convex portions was introduced into a chamber of a sputter deposition apparatus and heated to 500 ° C., and only nitrogen gas was introduced into the chamber at a flow rate of 15 sccm. Thereafter, the pressure in the chamber was maintained at 1 Pa, a high frequency bias of 500 W was applied to the substrate side, and the substrate was exposed to nitrogen plasma, thereby cleaning the surface of the substrate (pretreatment).
　続いて、基板の温度を５００℃に保ったまま、チャンバ内にアルゴンおよび窒素ガスを導入し、チャンバ内の圧力を０．５Ｐａに保ち、かつ、Ａｒガスを５ｓｃｃｍ、窒素ガスを１５ｓｃｃｍ流通させた条件（ガス全体に対する窒素の比は７５％）で、２０００Ｗの高周波バイアスを金属Ａｌターゲット側に印加し、複数の凸部の形成された基板上に、ＡｌＮからなるバッファ層を成膜を開始させた。成長レートは０．０８ｎｍ／ｓであった。なお、ターゲット内のマグネットは、基板洗浄の際もバッファ層成膜の際も揺動させておいた。そして、予め測定した成膜速度に従って規定した時間の間、成膜を行い、５０ｎｍのＡｌＮ層からなるバッファ層が複数の凸部の形成された基板上に堆積した後、プラズマを立てるのを止め、基板温度を低下させた。 Subsequently, while maintaining the substrate temperature at 500 ° C., argon and nitrogen gas were introduced into the chamber, the pressure in the chamber was maintained at 0.5 Pa, and Ar gas was circulated at 5 sccm and nitrogen gas was circulated at 15 sccm. Under the conditions (the ratio of nitrogen to the whole gas is 75%), a high frequency bias of 2000 W is applied to the metal Al target side to start the formation of a buffer layer made of AlN on the substrate on which a plurality of convex portions are formed. It was. The growth rate was 0.08 nm / s. Note that the magnet in the target was swung both when the substrate was cleaned and when the buffer layer was formed. Then, film formation is performed for a prescribed time according to a film formation rate measured in advance, and after the buffer layer made of a 50 nm AlN layer is deposited on the substrate on which the plurality of convex portions are formed, the plasma is stopped from being generated. The substrate temperature was lowered.
　次に、このようにして得られたバッファ層上に、以下に示す減圧ＭＯＣＶＤ法を用いてＩＩＩ族窒化物半導体からなる下地層をエピタキシャル成長させた（エピタキシャル工程）。
　まず、スパッタ成膜装置からバッファ層が形成された基板を取り出した。この基板を、ＭＯＣＶＤ法によるＩＩＩ族窒化物半導体層の成長のために使用されるステンレス鋼製の気相成長反応炉内に導入し、高周波（ＲＦ）誘導加熱式ヒータで成膜温度に加熱される、反応炉内の半導体用高純度グラファイト製のサセプタ（ｓｕｓｃｅｐｔｏｒ）上に前記基板を載置した。その後、前記反応炉内に窒素ガスを流通し、反応炉内をパージした。 Next, an underlying layer made of a group III nitride semiconductor was epitaxially grown on the buffer layer thus obtained by using the low pressure MOCVD method described below (epitaxial process).
First, the substrate on which the buffer layer was formed was taken out from the sputter deposition apparatus. This substrate is introduced into a stainless steel vapor phase growth reactor used for the growth of a group III nitride semiconductor layer by MOCVD, and heated to a film formation temperature by a high frequency (RF) induction heating heater. The substrate was placed on a susceptor made of high-purity graphite for semiconductor in a reaction furnace. Thereafter, nitrogen gas was circulated in the reaction furnace to purge the reaction furnace.
　そして、気相成長反応炉内に窒素ガスを８分間に亘って流通させた。この後、誘導加熱式ヒータを作動させて、サファイア基板の温度を約１０分間で室温から５００℃に昇温した。その後、基板の温度を５００℃に保ち、ＮＨ３ガスおよび窒素ガスを反応炉内に流通させた。気相成長反応炉内の圧力は９５ｋＰａとした。続いて、基板の温度を約１０分間かけて１０００℃まで昇温させ、この温度及び圧力下で１０分間放置して、基板の表面をサーマルクリーニング（ｔｈｅｒｍａｌ　ｃｌｅａｎｉｎｇ）した。サーマルクリーニングの終了後も、気相成長反応炉内への窒素ガスの供給は継続させた。 And nitrogen gas was distribute | circulated over 8 minutes in the vapor phase growth reaction furnace. Thereafter, the induction heater was activated to raise the temperature of the sapphire substrate from room temperature to 500 ° C. in about 10 minutes. Thereafter, the temperature of the substrate was kept at 500 ° C., and NH 3 gas and nitrogen gas were circulated in the reaction furnace. The pressure in the vapor growth reactor was 95 kPa. Subsequently, the temperature of the substrate was raised to 1000 ° C. over about 10 minutes, and the substrate surface was left under this temperature and pressure for 10 minutes to thermally clean the surface of the substrate. Even after the thermal cleaning was completed, the supply of nitrogen gas into the vapor phase growth reactor was continued.
　その後、ＮＨ３ガスの流通を続けながら水素雰囲気中で、基板の温度を１１２０℃に昇温させ、また、反応炉内の圧力は６０ｋＰａとした。そして、基板の温度が１１２０℃で安定したのを確認した後、気相成長反応炉内へのトリメチルガリウム（ＴＭＧ）の供給を開始し、ＡｌＮバッファ層上にアンドープのＧａＮ層を３μｍの膜厚までエピタキシャル成長させた。このとき、アンモニアの量はＶ族（Ｎ）／ＩＩＩ族（Ｇａ）比が６００となるように調節した。そして、３μｍのＧａＮ（ＩＩＩ族窒化物半導体）からなる下地層を成長後、反応炉への原料の供給を停止し、基板の温度を低下させた。 Thereafter, the temperature of the substrate was raised to 1120 ° C. in a hydrogen atmosphere while continuing the flow of NH 3 gas, and the pressure in the reactor was 60 kPa. Then, after confirming that the temperature of the substrate was stabilized at 1120 ° C., supply of trimethylgallium (TMG) into the vapor phase growth reactor was started, and an undoped GaN layer having a thickness of 3 μm was formed on the AlN buffer layer. Until epitaxial growth. At this time, the amount of ammonia was adjusted so that the V group (N) / III group (Ga) ratio was 600. Then, after the growth of a base layer made of 3 μm of GaN (Group III nitride semiconductor), the supply of the raw material to the reaction furnace was stopped, and the temperature of the substrate was lowered.
　その後、反応炉からバッファ層及び下地層の形成された基板を取り出し、下地層の（１０－１０）面及び（０００２）面のＸ線ロッキングカーブ（ＸＲＣ）半値幅を測定し、上記表１に示した。なお（０００２）面のＸ線ロッキングカーブ（ＸＲＣ）は結晶の平坦性を表す。 Thereafter, the substrate on which the buffer layer and the underlayer were formed was taken out from the reaction furnace, and the X-ray rocking curve (XRC) half widths of the (10-10) plane and the (0002) plane of the underlayer were measured. Indicated. The X-ray rocking curve (XRC) on the (0002) plane represents the flatness of the crystal.
　表１に示すように、凸部の基部幅が２ｎｍとされた基板の主面上にバッファ層を介して下地層が形成された比較例１のサンプルは、（１０－１０）面のＸＲＣ半値幅が１２１ａｒｃｓｅｃ、（０００２）面のＸＲＣ半値幅が３８ａｒｃｓｅｃであり、下地層の結晶性が非常に高められていることがわかる。
　また、凸部の形成されていない基板の主面上にバッファ層を介して下地層が形成された比較例２のサンプルは、（１０－１０）面のＸＲＣ半値幅が２２０ａｒｃｓｅｃ、（０００２）面のＸＲＣ半値幅が３６ａｒｃｓｅｃであり、下地層の結晶性が劣っていることがわかる。 As shown in Table 1, the sample of Comparative Example 1 in which the base layer was formed via the buffer layer on the main surface of the substrate having the base width of the protrusions of 2 nm is the XRC half of the (10-10) plane. It can be seen that the value width is 121 arcsec, the XRC half-value width of the (0002) plane is 38 arcsec, and the crystallinity of the underlayer is greatly enhanced.
Further, in the sample of Comparative Example 2 in which the base layer is formed on the main surface of the substrate on which the convex portion is not formed via the buffer layer, the XRC half-value width of the (10-10) plane is 220 arcsec and the (0002) plane. The XRC half-value width is 36 arcsec, indicating that the crystallinity of the underlayer is inferior.
　また、凸部の基部幅が１μｍとされた基板の主面上に、バッファ層を介して凸部を覆うように下地層が形成された実施例１のサンプルは、（１０－１０）面のＸＲＣ半値幅が１７１ａｒｃｓｅｃ、（０００２）面のＸＲＣ半値幅が４０ａｒｃｓｅｃであった。実施例１のサンプルは、凸部の形成されていない基板上に下地層が形成された比較例２に比べ、ＸＲＣ半値幅が小さい、すなわち結晶性が高められている。一方、基部幅が２μｍと大きな凸部が形成された基板上に下地層が形成された比較例１に比べると実施例１のサンプルは、ＸＲＣ半値幅が大きい、すなわち結晶性が低めとなっており、基板に形成された凸部の寸法を制御することにより、下地層の結晶性が制御されることが明らかである。 In addition, the sample of Example 1 in which the base layer was formed on the main surface of the substrate with the base width of the convex portion being 1 μm so as to cover the convex portion through the buffer layer is the (10-10) plane The XRC half width was 171 arcsec, and the XRC half width of the (0002) plane was 40 arcsec. The sample of Example 1 has a smaller XRC half-value width, that is, improved crystallinity, as compared with Comparative Example 2 in which the base layer is formed on the substrate on which no convex portion is formed. On the other hand, the sample of Example 1 has a larger XRC half-value width, that is, lower crystallinity than Comparative Example 1 in which the base layer is formed on the substrate on which the base width is as large as 2 μm. It is apparent that the crystallinity of the underlayer is controlled by controlling the dimensions of the convex portions formed on the substrate.
　また、凸部の基部幅が１．５ｎｍとされた基板の主面上に、バッファ層を介して凸部を覆うように下地層が形成された実施例２のサンプルにおいては、（１０－１０）面のＸＲＣ半値幅が１５２ａｒｃｓｅｃ、（０００２）面のＸＲＣ半値幅が３６ａｒｃｓｅｃであった。実施例２のサンプルは、実施例１のサンプルに比べて（１０－１０）面のＸＲＣ半値幅が小さく、結晶性が高いことがわかるが、本発明の規定範囲（１５０ａｒｃｓｅｃ以上）を満たすものであった。 In addition, in the sample of Example 2 in which the base layer was formed on the main surface of the substrate with the base width of the convex portion being 1.5 nm so as to cover the convex portion via the buffer layer, (10-10 ) Plane XRC half width was 152 arcsec, and (0002) plane XRC half width was 36 arcsec. The sample of Example 2 has a smaller (10-10) plane XRC half-value width and higher crystallinity than the sample of Example 1, but satisfies the specified range (150 arcsec or more) of the present invention. there were.
［実施例３～４、比較例３～４］
　次に、上記実施例１～２及び比較例１～２と同様の方法で作製したＩＩＩ族窒化物半導体からなる下地層上に、以下に示す方法により、ＬＥＤ構造を構成するｎ型半導体層、発光層、ｐ型半導体層の各層をこの順で積層して、図３（図４も参照）に示すような発光素子を作製した。さらに、発光素子を用いて、図５に示すような発光素子が用いられるランプ（発光ダイオード：ＬＥＤ）を作製した。 [Examples 3 to 4, Comparative Examples 3 to 4]
Next, an n-type semiconductor layer constituting an LED structure is formed on the base layer made of a group III nitride semiconductor produced by the same method as in Examples 1 and 2 and Comparative Examples 1 and 2 by the following method. The light emitting layer and the p-type semiconductor layer were laminated in this order to produce a light emitting element as shown in FIG. 3 (see also FIG. 4). Further, a lamp (light emitting diode: LED) using the light emitting element as shown in FIG. 5 was manufactured using the light emitting element.
「ｎ型コンタクト層の形成」
　下地層１０３の形成に引き続いて、同じＭＯＣＶＤ装置によってＧａＮからなるｎ型コンタクト層１０４ａを下地層１０３上に形成した。この際、ｎ型コンタクト層１０４ａにはＳｉをドープした。結晶成長は、Ｓｉのドーパント原料としてＳｉＨ４を流通させた以外は、下地層と同じ条件によって行った。 “Formation of n-type contact layer”
Subsequent to the formation of the underlayer 103, an n-type contact layer 104a made of GaN was formed on the underlayer 103 by the same MOCVD apparatus. At this time, the n-type contact layer 104a was doped with Si. Crystal growth was performed under the same conditions as the underlayer except that SiH 4 was circulated as a Si dopant material.
　以上説明したような工程により、ｎ型コンタクト層を形成した。すなわち、表面に逆スパッタを施したサファイアからなる基板１０１上に、単結晶組織を持つＡｌＮのバッファ層１０２を形成し、その上にアンドープで８μｍの膜厚のＧａＮ層（下地層１０３）と、５×１０１８ｃｍ－３のキャリア濃度を持つ２μｍのＳｉドープＧａＮ層（ｎ型コンタクト層１０４ａ）を形成した。
成膜後に装置内から取り出した基板は無色透明であり、ＧａＮ層（ここではｎ型コンタクト層１０４ａをなす初期層）の表面は鏡面であった。 An n-type contact layer was formed by the process as described above. That is, an AlN buffer layer 102 having a single crystal structure is formed on a substrate 101 made of sapphire whose surface is reverse-sputtered, and an undoped GaN layer (underlayer 103) having a thickness of 8 μm is formed thereon. A 2 μm Si-doped GaN layer (n-type contact layer 104a) having a carrier concentration of 5 × 10 18 cm −3 was formed.
The substrate taken out from the apparatus after film formation was colorless and transparent, and the surface of the GaN layer (here, the initial layer forming the n-type contact layer 104a) was a mirror surface.
「ｎ型クラッド層の形成」
　上記手順で作製したｎ型コンタクト層１０４ａ上に、ＭＯＣＶＤ法により、ｎ型クラッド層１０４ｂを積層した。
　まず、上記手順でｎ型コンタクト層１０４ａを成長させた基板をＭＯＣＶＤ装置に導入した後、ＮＨ３ガスを流通させながら、キャリアガスを窒素として、基板温度を７６０℃へ低下させた。炉内の温度の変更を待つ間、ＮＨ３ガスはそのままの流量で炉内へ供給し続けた。
　この時、炉内の温度の変更を待つ間に、ＳｉＨ４の供給量を設定した。すなわち、流通させるＳｉＨ４の量については事前に計算を行い、Ｓｉドープ層の電子濃度が４×１０１８ｃｍ－３となるようにＳｉＨ４の量を調整した。 “Formation of n-type cladding layer”
An n-type cladding layer 104b was stacked on the n-type contact layer 104a produced by the above procedure by MOCVD.
First, the substrate on which the n-type contact layer 104a was grown by the above procedure was introduced into an MOCVD apparatus, and then the substrate temperature was lowered to 760 ° C. with nitrogen as the carrier gas while circulating the NH 3 gas. While waiting for the temperature change in the furnace, the NH 3 gas was continuously supplied into the furnace at the same flow rate.
At this time, the supply amount of SiH 4 was set while waiting for the temperature change in the furnace. That is, the amount of SiH 4 to be distributed was calculated in advance, and the amount of SiH 4 was adjusted so that the electron concentration of the Si-doped layer was 4 × 10 18 cm −3 .
　次いで、アンモニアをチャンバ内に流通させながら、計算された量のＳｉＨ４ガスと、バブリングによって発生させたＴＭＩ及びＴＥＧの蒸気を炉内へ流通させ、Ｇａ０．９９Ｉｎ０．０１Ｎからなる層を１．７ｎｍの厚さで、またＧａＮからなる層を１．７ｎｍの厚さで、各々成膜した。このような成膜処理を１９サイクル繰り返した後、最後に、Ｇａ０．９９Ｉｎ０．０１Ｎからなる層を１．７ｎｍで成長させた。また、この工程処理を行なっている間は、ＳｉＨ４の流通を継続した。これにより、ＳｉドープのＧａ０．９９Ｉｎ０．０１ＮとＧａＮの超格子構造からなるｎ型クラッド層１０４ｂを形成した。 Next, while ammonia is circulated in the chamber, a calculated amount of SiH 4 gas and TMI and TEG vapor generated by bubbling are circulated into the furnace, and a layer composed of Ga 0.99 In 0.01 N is formed. Was formed with a thickness of 1.7 nm and a layer made of GaN with a thickness of 1.7 nm. After 19 cycles of such a film forming process, finally, a layer made of Ga 0.99 In 0.01 N was grown at 1.7 nm. Further, the SiH 4 flow was continued during this process. As a result, an n-type cladding layer 104b having a superlattice structure of Si-doped Ga 0.99 In 0.01 N and GaN was formed.
「発光層の形成」
　次いで、上記手順で作製したｎ型クラッド層１０４ｂ上に、ＭＯＣＶＤ法によって発光層１０５を積層した。
　発光層１０５は、ＧａＮからなる障壁層１０５ａと、Ｇａ０．８５Ｉｎ０．１５Ｎからなる井戸層１０５ｂとから構成される、多重量子井戸構造を有する。この発光層１０５の形成にあたっては、ＳｉドープのＧａＩｎＮとＧａＮの超格子構造からなるｎ型クラッド層１０４ｃ上に、まず、障壁層１０５ａを形成し、この障壁層１０５ａ上に、Ｇａ０．８５Ｉｎ０．１５Ｎからなる井戸層１０５ｂを形成した。さらに、このような積層手順を６回繰り返した後、６番目に積層した井戸層１０５ｂ上に、７番目の障壁層１０５ａを形成し、多重量子井戸構造を有する発光層１０５の両側（上下）に、障壁層１０５ａを配した構造とした。
　 `` Formation of light emitting layer ''
Subsequently, the light emitting layer 105 was laminated | stacked by MOCVD method on the n-type clad layer 104b produced in the said procedure.
The light emitting layer 105 has a multiple quantum well structure including a barrier layer 105a made of GaN and a well layer 105b made of Ga 0.85 In 0.15 N. In forming the light emitting layer 105, a barrier layer 105a is first formed on an n-type cladding layer 104c having a superlattice structure of Si-doped GaInN and GaN, and Ga 0.85 In is formed on the barrier layer 105a. A well layer 105b made of 0.15 N was formed. Further, after repeating such a stacking procedure six times, a seventh barrier layer 105a is formed on the sixth stacked well layer 105b, on both sides (upper and lower) of the light emitting layer 105 having a multiple quantum well structure. The barrier layer 105a is provided.
　詳細には、以下の方法によって発光層１０５を形成した。まず、発光層１０５の障壁層１０５ａを次のように形成した。基板温度は７６０℃のままで、ＴＥＧとＳｉＨ４の炉内への供給を開始し、所定の時間ＳｉをドープしたＧａＮからなる初期障壁層を０．８ｎｍ形成し、その後、ＴＥＧとＳｉＨ４の供給を停止した。その後、サセプタの温度を９２０℃に昇温した。そして、ＴＥＧとＳｉＨ４の炉内への供給を再開し、基板温度９２０℃のままで、さらに、１．７ｎｍの中間障壁層の成長を行い、その後、ＴＥＧとＳｉＨ４の炉内供給を停止した。続いて、サセプタ温度を７６０℃に下げ、ＴＥＧとＳｉＨ４の供給を開始し、さらに、３．５ｎｍの最終障壁層の成長を行い、その後、再びＴＥＧとＳｉＨ４の供給を停止して、ＧａＮ障壁層の成長を終了した。上述のような３段階の成膜処理により、初期障壁層、中間障壁層、及び最終障壁層の３層からなる、総膜厚が６ｎｍである、ＳｉドープＧａＮ障壁層（障壁層１０５ａ）を形成した。ＳｉＨ４の量は、Ｓｉ濃度が１×１０１７ｃｍ－３になるように調整された。 Specifically, the light emitting layer 105 was formed by the following method. First, the barrier layer 105a of the light emitting layer 105 was formed as follows. With the substrate temperature kept at 760 ° C., supply of TEG and SiH 4 into the furnace was started, and an initial barrier layer made of GaN doped with Si for a predetermined time was formed to 0.8 nm, and then TEG and SiH 4 Supply was stopped. Thereafter, the temperature of the susceptor was raised to 920 ° C. Then, the supply of TEG and SiH 4 into the furnace was restarted, and the 1.7 nm intermediate barrier layer was grown while the substrate temperature remained at 920 ° C., and then the supply of TEG and SiH 4 into the furnace was stopped. did. Subsequently, the susceptor temperature is lowered to 760 ° C., the supply of TEG and SiH 4 is started, the final barrier layer of 3.5 nm is grown, and then the supply of TEG and SiH 4 is stopped again, and the GaN Finished the growth of the barrier layer. By the three-stage film forming process as described above, an Si-doped GaN barrier layer (barrier layer 105a) having a total film thickness of 6 nm, which is composed of an initial barrier layer, an intermediate barrier layer, and a final barrier layer, is formed. did. The amount of SiH 4 was adjusted so that the Si concentration was 1 × 10 17 cm −3 .
　発光層１０５の井戸層１０５ｂを次のように形成した。上記ＧａＮ障壁層（障壁層１０５ａ）の成長終了後、ＴＥＧとＴＭＩを炉内へ供給して、井戸層の成膜処理を行ない、３ｎｍの膜厚を成すＧａ０．８５Ｉｎ０．１５Ｎ層（井戸層１０５ｂ）を障壁層１０５ａ上に形成した。井戸層１０５ｂの成膜処理の際、井戸層１０５ｂのＩｎ濃度は８％とし、また、成長時の基板温度を７５０℃とした。
　そして、Ｇａ０．８５Ｉｎ０．１５Ｎからなる井戸層１０５ｂの成長終了後は、ＴＥＧａの供給量の設定を変更した。
　引き続いて、ＴＥＧａおよびＳｉＨ4の供給を再開し、２層目の障壁層１０５ａの形成を行なった。 The well layer 105b of the light emitting layer 105 was formed as follows. After the growth of the GaN barrier layer (barrier layer 105a) is completed, TEG and TMI are supplied into the furnace to form a well layer, and a Ga 0.85 In 0.15 N layer having a thickness of 3 nm is formed. (Well layer 105b) was formed on barrier layer 105a. During the deposition process of the well layer 105b, the In concentration of the well layer 105b was 8%, and the substrate temperature during growth was 750 ° C.
Then, after the growth of the well layer 105b made of Ga 0.85 In 0.15 N, the setting of the TEGa supply amount was changed.
Subsequently, the supply of TEGa and SiH 4 was restarted, and the second barrier layer 105a was formed.
　上述のような手順を６回繰り返すことにより、交互に積層された、６層のＳｉドープＧａＮからなる障壁層１０５ａと、６層のＧａ０．８５Ｉｎ０．１５Ｎからなる井戸層１０５ｂを形成した。 By repeating the above procedure six times, six layers of barrier layers 105a made of Si-doped GaN and six layers of well layers 105b made of Ga 0.85 In 0.15 N are formed alternately. did.
　そして、６層目のＧａ０．９２Ｉｎ０．０８Ｎからなる井戸層１０５ｂを形成した後、引き続いて、７層目の障壁層の形成を行った。
　７層目の障壁層の形成処理においては、まず、ＳｉＨ４の供給を停止し、アンドープＧａＮからなる初期障壁層を形成した。この後、ＴＥＧの炉内への供給を続けたままで基板温度を９２０℃に昇温し、この基板温度９２０℃にて、規定の時間で中間障壁層の成長を行ない、その後、ＴＥＧの炉内への供給を停止した。続いて、基板温度を７６０℃に下げ、ＴＥＧの供給を開始し、最終障壁層の成長を行った。その後、再びＴＥＧの供給を停止し、ＧａＮ障壁層の成長を終了した。
　これら方法により、初期障壁層、中間障壁層及び最終障壁層の３層からなり、総膜厚が４ｎｍのアンドープＧａＮからなる７層目の障壁層を形成した（図４における発光層１０５の内の最上層の障壁層１０５ａを参照。なお最上層の障壁層は同じ参照番号１０５ａを使用しているものの、その他の障壁層と異なりドープされていない）。 Then, after forming a sixth well layer 105b made of Ga 0.92 In 0.08 N, a seventh barrier layer was formed.
In the formation process of the seventh barrier layer, first, the supply of SiH 4 was stopped, and an initial barrier layer made of undoped GaN was formed. Thereafter, the substrate temperature is raised to 920 ° C. while the supply of the TEG into the furnace is continued, and the intermediate barrier layer is grown at the substrate temperature of 920 ° C. for a specified time. The supply to was stopped. Subsequently, the substrate temperature was lowered to 760 ° C., the supply of TEG was started, and the final barrier layer was grown. Thereafter, the supply of TEG was stopped again, and the growth of the GaN barrier layer was completed.
By these methods, a seventh barrier layer made of undoped GaN having an initial barrier layer, an intermediate barrier layer, and a final barrier layer and having a total thickness of 4 nm was formed (in the light emitting layer 105 in FIG. 4). (See top barrier layer 105a, which uses the same reference number 105a but is not doped unlike the other barrier layers).
　以上の手順にて、厚さが不均一な井戸層（図４におけるｎ型半導体層１０４側から１～５層目の井戸層１０５ｂ）と、厚さが均一な井戸層（図４におけるｎ型半導体層１０４側から６層目の井戸層１０５ｂを参照）を含んだ多重量子井戸構造の発光層１０５を形成した。 Through the above procedure, a well layer having a non-uniform thickness (the first to fifth well layers 105b from the n-type semiconductor layer 104 side in FIG. 4) and a well layer having a uniform thickness (the n-type in FIG. 4). A light emitting layer 105 having a multiple quantum well structure including a sixth well layer 105b from the semiconductor layer 104 side was formed.
「ｐ型半導体層の形成」
　上述の各工程に引き続き、同じＭＯＣＶＤ装置を用いて、交互に積層された、４層のノンドープのＡｌ０．０６Ｇａ０．９４Ｎと、３層のＭｇをドープしたＧａＮと、からなる超格子構造を持つｐ型クラッド層１０６ａを成膜し、更に、その上に膜厚が２００ｎｍのＭｇドープＧａＮからなるｐ型コンタクト層１０６ｂを成膜し、ｐ型半導体層１０６とした。 “Formation of p-type semiconductor layer”
A superlattice composed of four layers of non-doped Al 0.06 Ga 0.94 N and three layers of Mg-doped GaN stacked alternately using the same MOCVD apparatus following the above-described steps. A p-type cladding layer 106 a having a structure was formed, and a p-type contact layer 106 b made of Mg-doped GaN having a thickness of 200 nm was formed thereon to form a p-type semiconductor layer 106.
　詳細には、ｐ型半導体層１０６を以下の方法によって形成した。
　まずｐ型半導体層１０６のｐ型クラッド層１０６ａを次のように形成した。
　ＮＨ３ガスを供給しながら基板温度を９７５℃へ昇温した後、この温度でキャリアガスを窒素から水素に切り替えた。続いて、基板温度を１０５０℃に変更した。そして、炉内へＴＭＧとＴＭＡを供給することにより、ノンドープのＡｌ０．０６Ｇａ０．９４Ｎからなる層２.５ｎｍを成膜した。引き続き、インターバルを取らずに、ＴＭＡのバルブを閉じてＣｐ２Ｍｇのバルブを開け、ＭｇをドープしたＧａＮの層を２．５ｎｍ成膜した。
　以上のような操作を３回繰り返し、最後にアンドープＡｌ０．０６Ｇａ０．９４Ｎの層を形成することにより、超格子構造よりなるｐ型クラッド層１０６ａを形成した。 Specifically, the p-type semiconductor layer 106 was formed by the following method.
First, the p-type cladding layer 106a of the p-type semiconductor layer 106 was formed as follows.
The substrate temperature was raised to 975 ° C. while supplying NH 3 gas, and then the carrier gas was switched from nitrogen to hydrogen at this temperature. Subsequently, the substrate temperature was changed to 1050 ° C. Then, by supplying TMG and TMA into the furnace, a 2.5 nm layer made of non-doped Al 0.06 Ga 0.94 N was formed. Subsequently, without taking an interval, the TMA valve was closed and the Cp 2 Mg valve was opened, and a Mg-doped GaN layer was deposited to 2.5 nm.
The above operation was repeated three times, and finally a p-type cladding layer 106a having a superlattice structure was formed by forming an undoped Al 0.06 Ga 0.94 N layer.
　次にｐ型半導体層１０６のｐ型コンタクト層１０６ｂを以下のように形成した。ｐ型クラッド層１０６ａを形成した後、Ｃｐ２ＭｇとＴＭＧのみを炉内へ供給して、２００ｎｍのｐ型ＧａＮよりなるｐ型コンタクト層１０６ｂを形成した。このｐ型コンタクト層は、ｐ型キャリアを活性化するためのアニール処理を行なわなくてもｐ型特性を示した。 Next, the p-type contact layer 106b of the p-type semiconductor layer 106 was formed as follows. After forming the p-type cladding layer 106a, only Cp 2 Mg and TMG were supplied into the furnace to form a p-type contact layer 106b made of 200-nm p-type GaN. This p-type contact layer exhibited p-type characteristics even without annealing for activating p-type carriers.
　ｐ型コンタクト層の気相成長を終了させた後には、直ちに基板を加熱するために利用していた高周波誘導加熱式ヒータへの通電を停止すると同時に、キャリアガスを水素から窒素へと切り替え、ＮＨ３ガスの流量を低下させた。具体的には、成長中には全流通ガス量のうち体積にして約１４％を締めていたＮＨ３ガスの量を０．２％まで下げた。更に、この状態で４５秒保持した後、ＮＨ３ガスの流通を停止した。この状態で、基板温度が室温まで降温したのを確認して、各層が積層された基板を大気中に取り出した。
　このようにして、実施例１～２及び比較例１～２と同様の方法で作製した下地層上に、ＬＥＤ構造を構成するｎ型半導体層、発光層、ｐ型半導体層の各層をこの順で形成した、実施例３～４及び比較例３～４のサンプル（エピタキシャルウェーハ）を作製した。 After completing the vapor phase growth of the p-type contact layer, the energization of the high-frequency induction heater used to heat the substrate is stopped immediately, and at the same time, the carrier gas is switched from hydrogen to nitrogen, and NH The flow rate of 3 gases was reduced. Specifically, during the growth, the amount of NH 3 gas that had been tightened by about 14% of the volume of the total circulation gas was reduced to 0.2%. Furthermore, after maintaining for 45 seconds in this state, the flow of NH 3 gas was stopped. In this state, it was confirmed that the substrate temperature was lowered to room temperature, and the substrate on which each layer was laminated was taken out into the atmosphere.
In this manner, the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer constituting the LED structure are arranged in this order on the base layer manufactured in the same manner as in Examples 1-2 and Comparative Examples 1-2. Samples (epitaxial wafers) of Examples 3 to 4 and Comparative Examples 3 to 4 formed in the above were produced.
　上述のようにして作製したＬＥＤ用のエピタキシャルウェーハは、以下の積層構造を有する。すなわち、ｃ面を有するサファイアからなる基板１０１上に、単結晶構造を有するＡｌＮ層（バッファ層１０２）を形成した後、基板１０１側から順に、８μｍのアンドープＧａＮ層（下地層１０３）、５×１０１８ｃｍ－３の電子濃度を持つ２μｍのＳｉドープＧａＮｎ型コンタクト層１０４ａ、４×１０１８ｃｍ－３のＳｉ濃度を有し、２０層の１．７ｎｍのＧａ０．９９Ｉｎ０．０１Ｎと１９層の１．７ｎｍのＧａＮからなる超格子構造を有するクラッド層（ｎ型クラッド層１０４ｂ）が積層される。またクラッド層上にはさらに、ＧａＮ障壁層に始まってＧａＮ障壁層に終わり、かつ、層厚が６ｎｍとされた６層のＳｉドープのＧａＮ障壁層（障壁層１０５ａ）と、層厚が３ｎｍとされた６層のノンドープのＧａ０．８５Ｉｎ０．１５Ｎ井戸層（井戸層１０５ｂ）とが交互に積層されており、さらにノンドープのＧａＮからなる最上位障壁層（図４における発光層１０５の内、半導体層１０６と接する最上層の障壁層１０５ａを参照）を有する、多重量子井戸構造（発光層１０５）が積層される。さらに発光層１０５上には、互いに交互に積層された、膜厚が２．５ｎｍのノンドープＡｌ０．０６Ｇａ０．９４Ｎからなる４つの層と、膜厚が２．５ｎｍのＭｇドープＡｌ０．０１Ｇａ０．９９Ｎからなり超格子構造を有する３つの層とから構成されるｐ型クラッド層１０６ａと、及び、膜厚が２００ｎｍのＭｇドープＧａＮからなるｐ型コンタクト層１０６ｂとから構成されるｐ型半導体層１０６が積層されている。　 The LED epitaxial wafer produced as described above has the following laminated structure. That is, after forming an AlN layer (buffer layer 102) having a single crystal structure on a substrate 101 made of sapphire having a c-plane, an 8 μm undoped GaN layer (underlayer 103), 5 × 10 18 cm -3 of 2μm with electron concentration Si-doped GaNn type contact layer 104a, 4 has a Si concentration of × 10 18 cm -3, the 20 layers of 1.7nm Ga 0.99 in 0.01 N And 19 layers of a cladding layer (n-type cladding layer 104b) having a superlattice structure made of 1.7 nm of GaN. Further, on the clad layer, a six-layer Si-doped GaN barrier layer (barrier layer 105a) that starts with the GaN barrier layer and ends with the GaN barrier layer and has a layer thickness of 6 nm, and a layer thickness of 3 nm 6 non-doped Ga 0.85 In 0.15 N well layers (well layers 105b) are alternately stacked, and the uppermost barrier layer made of non-doped GaN (the light emitting layer 105 in FIG. A multi-quantum well structure (light-emitting layer 105) having a top barrier layer 105a in contact with the semiconductor layer 106 is stacked. Furthermore, four layers of non-doped Al 0.06 Ga 0.94 N having a thickness of 2.5 nm and Mg-doped Al 0 having a thickness of 2.5 nm, which are alternately stacked on each other, are stacked on the light-emitting layer 105. A p-type cladding layer 106a composed of three layers made of 0.01 Ga 0.99 N and having a superlattice structure, and a p-type contact layer 106b composed of Mg-doped GaN with a thickness of 200 nm. A p-type semiconductor layer 106 is stacked.
　次いで、このようにして得られたＬＥＤ構造となる各層が形成された基板を用いて、以下に示す手順で、半導体発光素子の一種である発光ダイオード（ＬＥＤ）を作製した（図３を参照）。
　まず、公知のフォトリソグラフィー技術によって、ＬＥＤ構造となる各層が形成された基板のｐ型コンタクト層上に、ＩＴＯからなる透光性正極と、この透光性正極上にＴｉ、Ａｌ及びＡｕを順に積層した構造を持つ正極ボンディングパッドを形成した。
　続いて、正極ボンディングパッドが形成されていない部分にドライエッチングを行い、負極ボンディングパッドが形成される部分であるｎ型半導体層を露出させた。続いて、露出したｎ型半導体層上に、Ｎｉ、Ａｌ、Ｔｉ及びＡｕの４層よりなる負極ボンディングパッドを形成した。 Next, a light-emitting diode (LED), which is a kind of semiconductor light-emitting element, was fabricated by the following procedure using the substrate on which each layer to be an LED structure obtained in this way was formed (see FIG. 3). .
First, a light-transmitting positive electrode made of ITO is formed on a p-type contact layer of a substrate on which each layer to be an LED structure is formed by a known photolithography technique, and Ti, Al, and Au are sequentially formed on the light-transmitting positive electrode. A positive electrode bonding pad having a laminated structure was formed.
Subsequently, dry etching was performed on the portion where the positive electrode bonding pad was not formed to expose the n-type semiconductor layer where the negative electrode bonding pad was formed. Subsequently, a negative electrode bonding pad composed of four layers of Ni, Al, Ti, and Au was formed on the exposed n-type semiconductor layer.
　そして、正極ボンディングパッド及び負極ボンディングパッドが形成された基板の裏面を研削及び研磨してミラー状の面とした。次いで、この基板を３５０μｍ角の正方形のチップに切断し、ＬＥＤのチップとした。
　このチップを、正極ボンディングパッド及び負極ボンディングパッドが上になるようにリードフレーム上に載置し、金線でリードフレームに結線することによってランプ（図５参照）を作製した。 And the back surface of the board | substrate with which the positive electrode bonding pad and the negative electrode bonding pad were formed was ground and grind | polished, and it was set as the mirror-shaped surface. Next, the substrate was cut into 350 μm square chips to form LED chips.
This chip was placed on the lead frame so that the positive electrode bonding pad and the negative electrode bonding pad were on top, and was connected to the lead frame with a gold wire to produce a lamp (see FIG. 5).
　そして、上述のようにして作製したランプにおいて、ｐ側電極およびｎ側電極の電極間に２０ｍＡの順方向電流を流した際の順方向電圧（駆動電圧Ｖｆ）を測定するとともに、ｐ側の透光性正極を通して発光波長ＷＤ（ｎｍ）及び発光出力Ｐｏ（ｍＷ）を測定し、結果を下記表２に示した。 In the lamp manufactured as described above, the forward voltage (driving voltage Vf) when a forward current of 20 mA was passed between the p-side electrode and the n-side electrode was measured, and the p-side transparency was measured. The emission wavelength WD (nm) and the emission output Po (mW) were measured through the photocathode, and the results are shown in Table 2 below.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　表２に示すように、本発明に係る製造方法によって作製された実施例３～４のサンプルは、駆動電圧Ｖｆが３．２７～３．３０Ｖであり、また、発光波長ＷＤが５３８ｎｍ～５３９ｎｍで良好な緑色発光を呈するとともに、発光出力Ｐｏが８．４～８．７（ｍＷ）であった。 As shown in Table 2, the samples of Examples 3 to 4 manufactured by the manufacturing method according to the present invention have a drive voltage Vf of 3.27 to 3.30 V, and an emission wavelength WD of 538 nm to 539 nm. While exhibiting good green light emission, the light emission output Po was 8.4 to 8.7 (mW).
　これに対して、基板の凸部の基部幅が２μｍとされた比較例３のサンプルは、駆動電圧Ｖｆが３．３７Ｖと、実施例３～４のサンプルに比べて高い駆動電圧を必要とし、また、発光出力Ｐｏが７．９ｍＷと、実施例３～４のサンプルに比べて低出力となっている。
　また、基板に凸部を形成しなかった従来の構成を有する比較例４のサンプルは、駆動電圧Ｖｆが３．３５Ｖであり、また、発光出力Ｐｏが７．７ｍＷと、実施例３～４のサンプルに比べて発光特性が劣っている。 In contrast, the sample of Comparative Example 3 in which the base width of the convex portion of the substrate is 2 μm requires a driving voltage Vf of 3.37 V, which is higher than the samples of Examples 3 to 4, Further, the light emission output Po is 7.9 mW, which is lower than the samples of Examples 3 to 4.
Further, in the sample of Comparative Example 4 having the conventional configuration in which the convex portion is not formed on the substrate, the driving voltage Vf is 3.35 V, and the light emission output Po is 7.7 mW. Luminous properties are inferior to the sample.
［実験例１及び２］
　上記実施例３～４と同様の方法で、３５０μｍ角の正方形とされたＩＩＩ族窒化物半導体発光素子のチップを作製し、同様に、正極ボンディングパッド及び負極ボンディングパッドが上になるようにリードフレーム上に載置し、金線でリードフレームに結線し、発光素子サンプルを作製した。この際、基板の凸部の基部幅を１μｍとしたサンプルを実験例１とし、また、凸部の基部幅を２μｍとしたサンプルを実験例２として、各々５個のサンプルを作製した。
　そして、これら各サンプルの発光強度を、チップ上面に対して垂直方向に検知器を移動させながら測定し、この測定結果を図６Ａ、６Ｂのグラフに示した。 [Experimental Examples 1 and 2]
In the same manner as in Examples 3 to 4, a 350 μm square Group III nitride semiconductor light emitting device chip was fabricated, and the lead frame was similarly placed so that the positive electrode bonding pad and the negative electrode bonding pad were on top. The sample was placed on top and connected to a lead frame with a gold wire to prepare a light emitting device sample. At this time, a sample in which the base width of the convex portion of the substrate was 1 μm was designated as Experimental Example 1, and a sample in which the base width of the convex portion was 2 μm was designated as Experimental Example 2, and five samples were produced.
The emission intensity of each sample was measured while moving the detector in the direction perpendicular to the top surface of the chip, and the measurement results are shown in the graphs of FIGS. 6A and 6B.
　図６Ａのグラフに示すように、基板に形成された凸部間の間隔が１μｍとされた実験例１の発光素子チップは、図６Ｂのグラフに示すような凸部間の間隔が２μｍとされた実験例２の発光素子チップに比べ、発光出力が高くなっていることがわかる。この結果より、基板に形成される凸部間の間隔がより小さいほうが、発光素子の発光出力を向上できることが明らかとなった。 As shown in the graph of FIG. 6A, the light-emitting element chip of Experimental Example 1 in which the interval between the protrusions formed on the substrate is 1 μm has an interval between the protrusions of 2 μm as shown in the graph of FIG. 6B. It can be seen that the light emission output is higher than that of the light emitting element chip of Experimental Example 2. From this result, it was found that the light emission output of the light emitting element can be improved when the interval between the convex portions formed on the substrate is smaller.
　上記各実施例及び実験例の結果により、本発明のＩＩＩ族窒化物半導体発光素子が、緑色発光を呈するＬＥＤ構造の内部量子効率を低下させることなく、光取り出し効率に優れており、高い発光強度を備えていることが明らかである。 According to the results of the above examples and experimental examples, the group III nitride semiconductor light-emitting device of the present invention has excellent light extraction efficiency without reducing the internal quantum efficiency of the LED structure exhibiting green light emission, and high emission intensity. It is clear that
　本発明によれば、緑色発光を呈するＬＥＤ構造の内部量子効率を低下させることなく、光取り出し効率に優れたＩＩＩ族窒化物半導体発光素子及びその製造方法並びにランプを提供できる。 According to the present invention, it is possible to provide a group III nitride semiconductor light-emitting device having excellent light extraction efficiency, a method for manufacturing the same, and a lamp without reducing the internal quantum efficiency of the LED structure that emits green light.
１　ＩＩＩ族窒化物半導体発光素子
　３　ランプ
　１０　主面
　１１　平面
　１２　凸部
　１２ａ　凸部の基部
　１２ｂ　凸部の側面
　１２ｃ　表面
　２０　ＬＥＤ構造
　３１、３２　フレーム
　３３、３４　ワイヤー
　３５　モールド
　１０１　基板
　１０２　バッファ層
　１０３　下地層（ＩＩＩ族窒化物半導体層）
　１０３ａ　下地層１０３の表面
　１０４　ｎ型半導体層
　１０４ａ　ｎ型コンタクト層
　１０４ｂ　ｎ型クラッド層
　１０４ｃ　露出領域
　１０５　発光層
　１０５ａ　障壁層
　１０５ｂ　井戸層
　１０６　ｐ型半導体層
　１０６ａ　ｐ型クラッド層
　１０６ｂ　ｐ型コンタクト層
　１０７　正極ボンディングパッド
　１０８　負極ボンディングパッド
　１０９　透光性正極 DESCRIPTION OF SYMBOLS 1 Group III nitride semiconductor light emitting element 3 Lamp 10 Main surface 11 Plane 12 Convex part 12a Convex part base 12b Convex part side surface 12c Surface 20 LED structure 31, 32 Frame 33, 34 Wire 35 Mold 101 Substrate 102 Buffer layer 103 Bottom Formation (Group III nitride semiconductor layer)
103a Surface of the underlayer 103 104 n-type semiconductor layer 104a n-type contact layer 104b n-type cladding layer 104c exposed region 105 light-emitting layer 105a barrier layer 105b well layer 106 p-type semiconductor layer 106a p-type cladding layer 106b p-type contact layer 107 positive electrode Bonding pad 108 Negative electrode bonding pad 109 Translucent positive electrode

Claims (31)

  1. 　基板上に形成された単結晶のＩＩＩ族窒化物半導体層上にＬＥＤ構造が形成されたＩＩＩ族窒化物半導体発光素子であって、
    　前記基板は、（０００１）Ｃ面からなる平面部と複数の凸部とからなる主面と、裏面とを有し、前記凸部の基部幅が０．０５～１．５μｍであり、
    　前記ＩＩＩ族窒化物半導体層は、ＩＩＩ族窒化物半導体がエピタキシャル成長することによって前記基板の主面上に、前記平面部及び前記凸部を覆い形成されたものであり、
    　前記ＬＥＤ構造の発光波長は４９０～５７０ｎｍの範囲であることを特徴とするＩＩＩ族窒化物半導体発光素子。     A group III nitride semiconductor light emitting device in which an LED structure is formed on a single crystal group III nitride semiconductor layer formed on a substrate,
    The substrate has a main surface composed of a flat portion made of a (0001) C plane and a plurality of convex portions, and a back surface, and the base width of the convex portion is 0.05 to 1.5 μm
    The group III nitride semiconductor layer is formed so as to cover the planar portion and the convex portion on the main surface of the substrate by epitaxial growth of the group III nitride semiconductor.
    The group III nitride semiconductor light-emitting device characterized in that the light emission wavelength of the LED structure is in the range of 490 to 570 nm.
  2. 　前記凸部は、前記Ｃ面に非並行の表面により構成されることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 2. The group III nitride semiconductor light-emitting element according to claim 1, wherein the convex portion is configured by a surface non-parallel to the C-plane.
  3. 　前記凸部は、前記基部幅が０．０５～１μｍであり、高さが０．０５～１μｍの範囲であり且つ前記基部幅の１／４以上であり、隣接する前記凸部間の間隔が前記基部幅の０．５～５倍であることを特徴とする請求項１記載のＩＩＩ族窒化物半導体発光素子。 The convex portion has a base width of 0.05 to 1 μm, a height in the range of 0.05 to 1 μm and a quarter or more of the base width, and an interval between the adjacent convex portions. 2. The group III nitride semiconductor light emitting device according to claim 1, wherein the width is 0.5 to 5 times the base width.
  4. 　前記凸部が上部に向かって徐々に外形が小さくなる形状であることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 The group III nitride semiconductor light-emitting device according to claim 1, wherein the convex portion has a shape in which an outer shape gradually decreases toward an upper portion.
  5. 　前記凸部が略円錐状ないし略多角錐状であることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 2. The group III nitride semiconductor light emitting device according to claim 1, wherein the convex portion has a substantially conical shape or a substantially polygonal pyramid shape.
  6. 　前記凸部が、前記基板のＣ面上に設けられた酸化物又は窒化物であることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 2. The group III nitride semiconductor light-emitting device according to claim 1, wherein the convex portion is an oxide or a nitride provided on a C-plane of the substrate.
  7. 　前記凸部が、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、ＺｎＯの何れかからなることを特徴とする請求項６に記載のＩＩＩ族窒化物半導体発光素子。 The group III nitride semiconductor light-emitting element according to claim 6, wherein the convex portion is made of any one of SiO 2 , Al 2 O 3 , SiN, and ZnO.
  8. 　前記基板がサファイア基板であることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 The group III nitride semiconductor light-emitting device according to claim 1, wherein the substrate is a sapphire substrate.
  9. 　前記ＬＥＤ構造は、前記基板の主面上に、ＩＩＩ族窒化物半導体から各々がなる、ｎ型半導体層、発光層及びｐ型半導体層をこの順で有することを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 2. The LED structure according to claim 1, wherein an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, each of which is made of a group III nitride semiconductor, are arranged in this order on the main surface of the substrate. Group III nitride semiconductor light-emitting device.
  10. 　前記ＬＥＤ構造に備えられる発光層のＩｎ濃度が７質量％以上であることを特徴とする請求項９に記載のＩＩＩ族窒化物半導体発光素子。 The group III nitride semiconductor light-emitting device according to claim 9, wherein the light-emitting layer provided in the LED structure has an In concentration of 7% by mass or more.
  11. 　前記基板の主面上に、多結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなり、厚さが０．０１～０．５μｍであるバッファ層がスパッタ法によって積層され、前記バッファ層上に前記ＩＩＩ族窒化物半導体層が積層されていることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 A buffer layer made of polycrystalline Al x Ga 1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm is laminated on the main surface of the substrate by sputtering, The group III nitride semiconductor light-emitting device according to claim 1, wherein the group III nitride semiconductor layer is stacked on a buffer layer.
  12. 　前記基板の主面上に、単結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなり、厚さが０．０１～０．５μｍであるバッファ層がスパッタ法によって積層され、前記バッファ層上に前記ＩＩＩ族窒化物半導体層が積層されていることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 A buffer layer made of single-crystal Al x Ga 1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 to 0.5 μm is laminated on the main surface of the substrate by sputtering, The group III nitride semiconductor light-emitting device according to claim 1, wherein the group III nitride semiconductor layer is stacked on a buffer layer.
  13. 　前記ｎ型半導体層がｎ型クラッド層を含むとともに、前記ｐ型半導体層がｐ型クラッド層を含んでおり、前記ｎ型クラッド層及び前記ｐ型クラッド層の少なくとも一つが、超格子構造を含むことを特徴とする請求項９に記載のＩＩＩ族窒化物半導体発光素子。 The n-type semiconductor layer includes an n-type cladding layer, the p-type semiconductor layer includes a p-type cladding layer, and at least one of the n-type cladding layer and the p-type cladding layer includes a superlattice structure. The group III nitride semiconductor light-emitting device according to claim 9.
  14. 　前記ＩＩＩ族窒化物半導体層の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることを特徴とする請求項１に記載のＩＩＩ族窒化物半導体発光素子。 2. The group III nitride semiconductor light-emitting device according to claim 1, wherein an X-ray rocking curve (XRC) half-value width in the (10-10) plane of the group III nitride semiconductor layer is 150 arcsec or more.
  15. 前記　前記基板の（０００１）Ｃ面からなる平面上に、基部幅が０．０５～１．５μｍである複数の凸部を形成することにより、前記基板上に平面部と凸部とからなる主面を形成する基板加工工程と、
    　前記基板の主面上に、ＩＩＩ族窒化物半導体をエピタキシャル成長させることにより、前記平面部及び前記凸部を覆う、単結晶のＩＩＩ族窒化物半導体層を形成するエピタキシャル工程と、
    　前記ＩＩＩ族窒化物半導体層上に、発光波長が４９０～５７０ｎｍの範囲であるＬＥＤ構造を前記形成するＬＥＤ積層工程と、を含むことを特徴とするＩＩＩ族窒化物半導体発光素子の製造方法。     A plurality of convex portions having a base width of 0.05 to 1.5 μm are formed on a plane composed of the (0001) C surface of the substrate, thereby forming a main portion composed of the planar portion and the convex portions on the substrate. A substrate processing step for forming a surface;
    An epitaxial step of forming a single crystal group III nitride semiconductor layer covering the planar portion and the convex portion by epitaxially growing a group III nitride semiconductor on the main surface of the substrate;
    A method of manufacturing a group III nitride semiconductor light emitting device, comprising: an LED stacking step of forming an LED structure having an emission wavelength in the range of 490 to 570 nm on the group III nitride semiconductor layer.
  16. 　前記基板加工工程において、前記凸部の表面が、前記Ｃ面に非並行の表面により構成されるように形成することを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 The method of manufacturing a group III nitride semiconductor light-emitting device according to claim 15, wherein in the substrate processing step, the surface of the convex portion is formed by a surface non-parallel to the C-plane. .
  17. 　前記基板加工工程において、前記基部幅が０．０５～１μｍ、高さが０．０５～１μｍの範囲であって且つ前記基部幅の１／４以上であり、隣接する前記凸部間の間隔が前記基部幅の０．５～５倍である前記凸部を形成することを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 In the substrate processing step, the base width is in the range of 0.05 to 1 μm, the height is in the range of 0.05 to 1 μm, and is ¼ or more of the base width, and the spacing between the adjacent convex portions is The method of manufacturing a group III nitride semiconductor light-emitting device according to claim 15, wherein the convex part having a width of 0.5 to 5 times the base part width is formed.
  18. 前記基板加工工程において、前記凸部として、上部に向かって徐々にその外形が小さくなる形状が形成されることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 16. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 15, wherein in the substrate processing step, a shape is formed as the convex portion, the outer shape of which gradually decreases toward the top.
  19. 　前記基板加工工程において、前記凸部が、略円錐状ないし略多角錐状に形成されることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 16. The method for manufacturing a group III nitride semiconductor light emitting device according to claim 15, wherein, in the substrate processing step, the convex portion is formed in a substantially conical shape or a substantially polygonal pyramid shape.
  20. 　前記基板がサファイア基板であることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 15, wherein the substrate is a sapphire substrate.
  21. 　前記基板加工工程において、前記基板の（０００１）Ｃ面上に、ステッパー露光法、ナノインプリント法、電子ビーム（ＥＢ）露光法、レーザー露光法の内の何れかを用いてマスクパターンを形成した後、前記基板をエッチングすることによって、前記凸部が形成されることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 In the substrate processing step, on the (0001) C surface of the substrate, after forming a mask pattern using any one of a stepper exposure method, a nanoimprint method, an electron beam (EB) exposure method, and a laser exposure method, The method for manufacturing a group III nitride semiconductor light emitting device according to claim 15, wherein the convex portion is formed by etching the substrate.
  22. 　前記凸部を、前記基板のＣ面上に、酸化物又は窒化物から形成することを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 15, wherein the convex portion is formed of an oxide or a nitride on the C-plane of the substrate.
  23. 　前記凸部を、ＳｉＯ２、Ａｌ２Ｏ３、ＳｉＮ、及びＺｎＯの何れかから形成することを特徴とする請求項２２に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 23. The method for manufacturing a group III nitride semiconductor light-emitting element according to claim 22, wherein the convex portion is formed of any one of SiO 2 , Al 2 O 3 , SiN, and ZnO.
  24. 　前記ＬＥＤ積層工程において、前記基板の主面上に、ＩＩＩ族窒化物半導体から各々なるｎ型半導体層、発光層及びｐ型半導体層をこの順で積層して、前記ＬＥＤ構造が形成されることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 In the LED stacking step, the LED structure is formed by stacking an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a group III nitride semiconductor in this order on the main surface of the substrate. The method for producing a group III nitride semiconductor light-emitting device according to claim 15.
  25. 　前記ＬＥＤ積層工程において、前記ＬＥＤ構造に備えられる発光層のＩｎ濃度が７質量％以上であることを特徴とする請求項２４に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 25. The method for manufacturing a group III nitride semiconductor light-emitting element according to claim 24, wherein, in the LED stacking step, an In concentration of a light-emitting layer provided in the LED structure is 7% by mass or more.
  26. 　前記基板加工工程の後であって、前記エピタキシャル工程の前に、前記基板の主面上に多結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなる厚さ０．０１～０．５μｍのバッファ層を、スパッタ法によって積層するバッファ層形成工程が含まれることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 After the substrate processing step and before the epitaxial step, a thickness of 0.01 to 0 made of polycrystalline Al x Ga 1-x N (0 ≦ x ≦ 1) is formed on the main surface of the substrate. 16. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 15, further comprising a buffer layer forming step of stacking a buffer layer of .5 μm by a sputtering method.
  27. 　前記基板加工工程の後、前記エピタキシャル工程の前に、前記基板の主面上に単結晶のＡｌｘＧａ１－ｘＮ（０≦ｘ≦１）からなる厚さ０．０１～０．５μｍのバッファ層を、スパッタ法によって積層するバッファ層形成工程が備えられていることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 After the substrate processing step and before the epitaxial step, a thickness of 0.01 to 0.5 μm made of single crystal Al x Ga 1-x N (0 ≦ x ≦ 1) is formed on the main surface of the substrate. 16. The method for producing a group III nitride semiconductor light-emitting device according to claim 15, further comprising a buffer layer forming step of laminating the buffer layer by a sputtering method.
  28. 　前記ＬＥＤ積層工程において、前記ｎ型半導体層にｎ型クラッド層が含まれ、前記ｐ型半導体層にｐ型クラッド層が含まれ、且つ、前記ｎ型クラッド層及び前記ｐ型クラッド層の少なくとも一つが超格子構造を含む層であることを特徴とする請求項２４に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 In the LED stacking step, the n-type semiconductor layer includes an n-type cladding layer, the p-type semiconductor layer includes a p-type cladding layer, and at least one of the n-type cladding layer and the p-type cladding layer. 25. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 24, wherein one of the layers includes a superlattice structure.
  29. 　前記エピタキシャル工程において、前記凸部を備えた前記基板の主面上に前記ＩＩＩ族窒化物半導体層を形成した後の、前記ＩＩＩ族窒化物半導体層の（１０－１０）面におけるＸ線ロッキングカーブ（ＸＲＣ）半値幅が１５０ａｒｃｓｅｃ以上であることを特徴とする請求項１５に記載のＩＩＩ族窒化物半導体発光素子の製造方法。 In the epitaxial step, an X-ray rocking curve on the (10-10) plane of the group III nitride semiconductor layer after forming the group III nitride semiconductor layer on the main surface of the substrate having the convex portion 16. The method for producing a group III nitride semiconductor light-emitting device according to claim 15, wherein the (XRC) half width is 150 arcsec or more.
  30. 　請求項１５に記載の製造方法によって得られるＩＩＩ族窒化物半導体発光素子。 A group III nitride semiconductor light-emitting device obtained by the manufacturing method according to claim 15.
  31. 　請求項１に記載のＩＩＩ族窒化物半導体発光素子が用いられてなることを特徴とするランプ。 A lamp comprising the group III nitride semiconductor light-emitting device according to claim 1.
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