WO2009078220A1 - Sram cell circuit and method for driving the same - Google Patents

Sram cell circuit and method for driving the same Download PDF

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Publication number
WO2009078220A1
WO2009078220A1 PCT/JP2008/069512 JP2008069512W WO2009078220A1 WO 2009078220 A1 WO2009078220 A1 WO 2009078220A1 JP 2008069512 W JP2008069512 W JP 2008069512W WO 2009078220 A1 WO2009078220 A1 WO 2009078220A1
Authority
WO
WIPO (PCT)
Prior art keywords
inverter
control transistor
read
circuit
driving
Prior art date
Application number
PCT/JP2008/069512
Other languages
French (fr)
Japanese (ja)
Inventor
Toshihiro Sekigawa
Yohei Matsumoto
Masakazu Hioki
Takashi Kawanami
Tadashi Nakagawa
Hanpei Koike
Original Assignee
National Institute Of Advanced Industrial Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute Of Advanced Industrial Science And Technology filed Critical National Institute Of Advanced Industrial Science And Technology
Publication of WO2009078220A1 publication Critical patent/WO2009078220A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

There is provided a SRAM circuit in which restrictions on transistor sizes occurring when ensuring a write operation and a read operation are controlled, the number of transistors in use is reduced, and use of a dedicated read line is eliminated. In the SRAM circuit, to configure a positive feedback circuit, the output node (Q202) of a first inverter (202) is connected to the input node (I204) of a second inverter (204) and a feedback control transistor (220) connects between the output node (Q204) of the second inverter (204) and the input node (I202) of the first inverter (202). After bringing the feedback control transistor (220) into a non-conduction state to disconnect the positive feedback circuit, either a write control transistor (222) or a read control transistor (224) is brought into a conduction state, thereby bringing the SRAM circuit into a write state or a read state.
PCT/JP2008/069512 2007-12-19 2008-10-28 Sram cell circuit and method for driving the same WO2009078220A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-326777 2007-12-19
JP2007326777A JP5083889B2 (en) 2007-12-19 2007-12-19 SRAM cell circuit and driving method thereof

Publications (1)

Publication Number Publication Date
WO2009078220A1 true WO2009078220A1 (en) 2009-06-25

Family

ID=40795339

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/069512 WO2009078220A1 (en) 2007-12-19 2008-10-28 Sram cell circuit and method for driving the same

Country Status (2)

Country Link
JP (1) JP5083889B2 (en)
WO (1) WO2009078220A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177636B1 (en) 2014-05-09 2015-11-03 International Business Machines Corporation 8T based SRAM cell and related method
JP2017532710A (en) * 2014-09-27 2017-11-02 クアルコム，インコーポレイテッド 7-transistor static random access memory bit cell with reduced read disturb
JP2019144539A (en) * 2018-02-20 2019-08-29 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
US10943326B2 (en) 2018-02-20 2021-03-09 Seiko Epson Corporation Electro-optical device and electronic apparatus

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5382886B2 (en) * 2009-07-29 2014-01-08 独立行政法人産業技術総合研究所 SRAM cell
JP6604374B2 (en) * 2017-12-26 2019-11-13 セイコーエプソン株式会社 Electro-optical device and electronic apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128091A (en) * 1982-01-25 1983-07-30 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
JPS63285794A (en) * 1987-05-18 1988-11-22 Ricoh Co Ltd Static random access memory device
JPH06103781A (en) * 1992-09-21 1994-04-15 Sharp Corp Memory cell circuit
JP2006059523A (en) * 2004-08-23 2006-03-02 Seiko Epson Corp Memory cell
JP2006286100A (en) * 2005-03-31 2006-10-19 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940395A (en) * 1982-08-31 1984-03-06 Toshiba Corp Storage circuit
JPH04298893A (en) * 1991-01-04 1992-10-22 Toshiba Corp Semiconductor storage device
JPH087571A (en) * 1994-04-20 1996-01-12 Hitachi Ltd Gate circuit, semiconductor integrated circuit, semiconductor storage circuit and semiconductor integrated circuit device using them, information processing device using them
JPH10222985A (en) * 1998-03-09 1998-08-21 Hitachi Ltd Semiconductor storage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128091A (en) * 1982-01-25 1983-07-30 Nippon Telegr & Teleph Corp <Ntt> Memory circuit
JPS63285794A (en) * 1987-05-18 1988-11-22 Ricoh Co Ltd Static random access memory device
JPH06103781A (en) * 1992-09-21 1994-04-15 Sharp Corp Memory cell circuit
JP2006059523A (en) * 2004-08-23 2006-03-02 Seiko Epson Corp Memory cell
JP2006286100A (en) * 2005-03-31 2006-10-19 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177636B1 (en) 2014-05-09 2015-11-03 International Business Machines Corporation 8T based SRAM cell and related method
JP2017532710A (en) * 2014-09-27 2017-11-02 クアルコム，インコーポレイテッド 7-transistor static random access memory bit cell with reduced read disturb
JP2019144539A (en) * 2018-02-20 2019-08-29 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
US10943326B2 (en) 2018-02-20 2021-03-09 Seiko Epson Corporation Electro-optical device and electronic apparatus
US11367162B2 (en) 2018-02-20 2022-06-21 Seiko Epson Corporation Electro-optical device and electronic apparatus
US11983795B2 (en) 2018-02-20 2024-05-14 Seiko Epson Corporation Electro-optical device and electronic apparatus

Also Published As

Publication number Publication date
JP5083889B2 (en) 2012-11-28
JP2009151844A (en) 2009-07-09

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