WO2009033968A1

WO2009033968A1 - System and method for data transfer

Info

Publication number: WO2009033968A1
Application number: PCT/EP2008/061458
Authority: WO
Inventors: Wolfgang Klausberger; Stefan Abeling; Axel Kochale; Johann Maas
Original assignee: Thomson Licensing
Priority date: 2007-09-13
Filing date: 2008-09-01
Publication date: 2009-03-19

Abstract

The present invention relates to a method (300) of transferring data in a data storage system (100) having a memory device (110, 112, 114, 116) that is configured to be accessed via direct memory access bursts, and to the pertaining system (100). A method (300) in accordance with the invention comprises initialising (304) the memory device (110, 112, 114, 116), and employing a burst length that varies depending on a characteristic of the memory device (110, 112, 114, 116).

Description

System and Method for Data Transfer

The present invention relates to data transactions in storage arrays of data storage systems. In particular, the invention relates to the field of mass storage devices in which multiple storage units may be implemented using different device technologies.

Read and write operations in high-speed data storage systems are often performed by DMA burst transfers. State of the art in computer systems is a negotiation process between a host and a hard disk drive or HDD to determine a longest possible burst length that the target can handle for read and write operations. The longest possible burst length is typically limited by the first-in first-out memory buffer or FIFO implementation in the HDD or other storage device.

U.S. Patent Application Publication No. 20040255093 to Forrer, et al. purports to disclose a method and system in which a hardware platform such as a disk drive is formatted to the largest block length for which it is desired to perform a read or write operation. Using commands, data can be accessed from the drive in any block length that is equal to or less than the formatted block length.

U.S. Patent Application Publication No. 20040054856 to Drescher, et al. purports to disclose a method for configuring a memory with I/O support. The aim of the disclosure is to guarantee a processor and functional units that function in time- critical conditions the appropriate priority for data access, using simple programs. To this end, an input memory area which the unit can only write into and which the processor unit can only read out of and an output memory area which the unit can only read out of and which the processor unit can only write into are specified in the processor.

U.S. Patent No. 6,701 ,387 to Pannel, et al. purports to disclose a method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA controller to a multiprocessor system mesh. A bridge between the device controller and the mesh is described that buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

U.S. Patent No. 6,473,814 to Lyons, et al. purports to disclose a method and system for choosing an optimal PCI adapter burst length. The optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.

Japanese Patent Application Publication No. 2000222344 to Yasushi purports to disclose an improvement related to the efficiency of data communicating operation by determining the transfer size of reception DMA on the basis of a reception speed when the kind of communication is decided as reception and setting the determined reception DMA transfer size. The kind of communication is decided according to whether or not DCS 3-2 is received; when the DCS 3-2 is received, DCS 3-2 indicating a reception speed determined according to a receivable communication speed of DIS 3-1 and a transmittable communication speed of a transmission device is received and reception speed data of the DCS 3-2 is stored in a random access memory or RAM. On the basis of the reception speed data, a data table stored in a read only memory or ROM is referred to and the reception DMA transfer side is set as reception DMA transfer buffer size in a dynamic direct memory access controller through a data bus.

U.S. Patent No. 6,256,684 to Klein purports to disclose a method and system for increasing the rate of data transfer between a PC-based computer and an IDE/ATA-compliant hard drive. Synchronous data transfer is employed in a manner that retains full compatibility with the existing IDE/ATA standard.

U.S. Patent No. 5,721 ,954 to Shrock, et al. purports to disclose a SCSI-2-and- DMA processor that has on a single integrated circuit a SCSI-2 interface for a SCSI-2 data bus that is at least two bytes wide and a DMA interface for a system data bus that is at least two bytes wide. This integrated circuit has an set of control registers and an on-chip processor such that the transfers involving SCSI- 2 data transfers involving data words that have a width of at least two bytes can be processed and completed without burdening the remainder of the system. Substantially all that is needed of the system processor is to download a very compact control program and then begin performing transfers between this integrated circuit and system RAM. The on-chip processor allows chaining of random length blocks of contiguous address data by using a chain mode of transfer which also pairs up any odd residue with a portion of the first word of the next block in the chain using on-chip processing.

U.S. Patent No. 4,658,349 to Tabata, et al. purports to disclose a direct memory access control circuit equipped with a first register for storing the top address of a memory area, a second register for storing the bottom address of that memory area, a comparison circuit for comparing the current address used for memory access with the bottom address stored in the second register, and a control circuit for replacing the current address. The current address is to be subsequently used for memory access, with the top address stored in the first register when coincidence is detected by the comparison circuit.

A system and method that improves the performance of DMA transfers in a highspeed data recording workflow is desired.

A method in accordance with the present invention is recited in claim 1. The method relates to transferring data in a data storage system having a memory device that is configured to be accessed via direct memory access bursts. In particular, the method comprises initialising the memory device, and employing a burst length that varies depending on a characteristic of the memory device.

A data storage system in accordance with the present invention is recited in claim 6. The data storage system comprises a memory device configured to be accessed via direct memory access bursts. The data storage system also comprises a direct memory access unit that employs a burst length that varies depending on a characteristic of the memory device.

In a data storage system according to the present invention, the characteristic upon which the burst length varies may comprise a device type. In such a data storage system, the device type may either be a hard disk drive or a solid state drive.

According to the invention, a burst length for the memory device may be selected from a set of predefined burst lengths, each of the predefined burst lengths corresponding to a particular type of memory device. Further in accordance with the present invention, a performance test may be performed on the memory device to determine the burst length to use for a data transfer to the memory device.

A preferred embodiment of the present invention is described with reference to the accompanying drawings. The preferred embodiment merely exemplifies the invention. Plural possible modifications are apparent to the skilled person. The gist and scope of the present invention is defined in the appended claims of the present application.

Fig. 1 is a block diagram of a data storage system in accordance with an exemplary embodiment of the present invention.

Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.

Fig. 3 is a process flow diagram that shows a method in accordance with an exemplary embodiment of the present invention.

In high-speed mass storage devices, overall throughput performance of the storage devices is likely to be more important than just the FIFO implementation. Performance tests with different example device technologies, e.g. hard disk drives, also referred to as HDDs, in comparison to solid state drives, also referred to as SSDs, have revealed that an optimized data throughput may be obtained using a different burst length for each drive technology. The optimized burst length for each drive technology may sometimes be smaller than the above- mentioned longest possible burst length for that drive technology.

In an exemplary embodiment of the present invention, data burst length for DMA transfers are adapted to optimize the performance in a high-speed data recording workflow depending on the drive technology of a particular storage system. The device type of the installed disks in a particular data storage system may be indicated, for example, by involved hardware/software units. In accordance with an exemplary embodiment of the present invention, the burst length for DMA transactions may be set to a particular value depending on the device type of the drives that are installed in the system. In one exemplary embodiment, the DMA burst length is set to a specific value that has shown the best performance in previous throughput measurements. The skilled person will appreciate that an exemplary embodiment of the present invention results in a burst length that is adapted to the type or technology of the particular memory devices in a data storage system. Moreover, the burst length may be chosen or adapted for the express purpose of optimizing overall data storage system throughput. The use of adapted burst lengths for DMA transfers in accordance with an exemplary embodiment of the present invention improves the performance of real-time mass storage solutions depending on the specific drive technology employed by the system.

The data storage system shown in Fig. 1 is generally referred to by the reference number 100. The data storage system 100 comprises a plurality of BusDhver modules, including a first BusDriver module 102, a second BusDhver module 104, a third BusDriver module 106 and a fourth BusDriver module 108. Each of the four BusDriver modules 102, 104, 106, 108 performs the function of managing the operation of a plurality of storage devices such as ATA/ATAPI controlled storage devices, which are shown as Device#0,...,Device#15 in Fig. 1. For example, the first BusDriver module 102 manages the operation of a first group of controlled storage devices 110. Similarly, the second BusDriver module 104 manages the operation of a second group of controlled storage devices 112. The third BusDriver module 106 manages the operation of a third group of controlled storage devices 114. Finally, the fourth BusDriver 108 manages the operation of a fourth group of controlled storage devices 116. The skilled person will appreciate that, collectively, the first group of controlled storage devices 110, the second group of controlled storage devices 112, the third group of controlled storage devices 114, and the fourth group of controlled storage devices 116 may comprise a RAID storage array.

Each of the BusDriver modules 102, 104, 106, 108 comprises a general BusDriver controller, a Parallel Input Output unit, and a Direct Memory Access or DMA unit for each of the four storage devices it controls. In Fig. 1 , each Parallel Input Output unit is identified with a label in the form of PIO#n. Each DMA unit is identified with a label in the form of DMA#n. The BusDriver controller associated with a first one of the first group of controlled storage devices 110 is identified by the reference number 118 in Fig. 1. The PIO unit associated with the first one of the first group of controlled storage devices 110 is identified by the reference number 120 in Fig. 1. The DMA unit associated with the first one of the first group of controlled storage devices 110 is identified by the reference number 122 in Fig. 1. The remaining BusDriver controllers, PIO units and DMA units are not assigned separate reference numbers in Fig. 1 for clarity. The skilled person will appreciate that an exemplary one of the BusDriver modules 102, 104, 106, 108 is controlled by a system controller FPGA with an embedded software processor system not shown in Fig. 1.

In the exemplary data storage system 100, each of the four groups of controlled storage devices 110, 112, 114, 116 comprises four controlled storage devices. Accordingly, the exemplary data storage system 100 controls a total of 16 devices. The skilled person will appreciate that other exemplary embodiments of the present invention may comprise configurations involving greater or smaller numbers of storage devices depending on design considerations for each individual system. Each of the exemplary BusDriver modules 102, 104, 106 and 108 comprises a separate control path and data path. Each control path initiates upcoming transactions like commands or the like. The control paths may be implemented, for example, as a serial communication interface, such as an I2C bus. Each data path may comprise a real-time data path having a data bus and strobe signals for data transfer. In Fig. 1 , the first BusDriver module 102 comprises a control path 124 and a data path 132. The second BusDriver module 104 comprises a control path 126 and a data path 134. The third BusDriver module 106 comprises a control path 128 and a data path 136. Finally, the fourth BusDriver module 108 comprises a control path 130 and a data path 138.

A system controller of the data storage system 100 initiates transfers of data in so-called clusters by sending register values for the cluster size, the cluster start address and the related command, namely "read" or "write", via one of the control paths 124, 126, 128, 130 to a respective one of the BusDriver controllers. Registers that hold the status of finished transfers are accessible to be read out by the system controller. This process will also be used to read the information about the data transfer performance of each single disk.

In the exemplary embodiment shown in Fig. 1 , each of the respective BusDriver controllers 102, 104, 106, 108 supports its four associated DMA units in order to handle DMA transfers between the system controller and the attached groups of controlled storage devices 110, 112, 114, 116. In an exemplary embodiment of the present invention, transfers are done according to the UDMA concept of the ATA interface. Per default the BusDriver controllers 102, 104, 106, 108 initiate read/write transfers as 64-KB bursts, which typically leads to the best data transaction performance in case of installed hard disk drives. As set forth below, performance of the system is optimized by adapting the burst length used to perform DMA transfers based on the technology type and/or operating protocol of the drives that comprise the groups of controlled storage devices 110, 112, 114, 116. Fig. 2 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention. The state diagram is generally referred to by the reference number 200. The state diagram 200 shows, in state-diagram format, an exemplary method of operation for a state machine that improves the performance of a data storage system. In particular, a state machine that operates according to Fig. 2 adaptively optimizes a burst length for DMA transfers based on a characteristic of the particular memory devices of the data storage system 100.

Prior to beginning operation, a system controller, which is denoted as Power PC or PPC in Fig. 2, is in an idle state 202. The system controller initiates a transfer by delivering a cluster size to be used, for exemple, up to 16 MB per device, and the sector start address to be used, via an associated one of the control paths 124, 126, 128, 130. At state 204, certain PPC register values denoted as "PPC Registers" in Fig. 2 are read, and an interrupt is delivered to the system controller to signal the initialisation of the storage devices.

At state 206, information about the technology or type of the storage devices associated with a DMA transfer is acquired. In an exemplary embodiment of the present invention, the BusDriver modules 102, 104, 106, 108 each have hardware or software that is adapted to determine a characteristic such as the technology or device type of the installed memory devices. In particular, the first BusDriver module 102 is adapted to determine the technology or type of the first group of controlled storage devices 110 and so on for the remaining BusDriver modules 104, 106 and 108.

The skilled person will appreciate that many different methods for determining the type or technology of the storage devices may be employed in accordance with an exemplary embodiment of the present invention. For example, the model number of the drives may be analyzed after reading Identify Device Information resulting from an Identify Device command. An Identify Device command may, for example, be part of the boot process. Alternatively, when reconfigurations may occur, it may be appropriate to repeat the Identify Device command in suitable intervals.

In an exemplary embodiment of the present invention, the allocated DMA burst length for all further or subsequent actions or transactions is stored in a register. At state 208, the current burst length is obtained from the register in which it is stored so that the current adaptive burst length may be used for the upcoming DMA transfer.

The lower half of the state diagram 200 exhibits a loop structure, where the transfer of the cluster is performed in the form of a sequence of burst transfers. Each of the burst transfers employs the DMA burst length value from the DMA burst length register. In this context, the cluster size is being used locally in the sense of "remaining cluster size" until the entire transaction is completed.

At state 210, the cluster size and address is determined. This determination involves, for example, incrementing the previously-used address or start address by the burst length and decrementing the cluster size by the burst length.

If the cluster size is determined zero, as shown at state 212, this indicates that the DMA transaction has completed. Accordingly, the system controller returns to the idle state 202.

If, at state 210, the cluster size is determined to be greater than zero, as shown at state 214, this is taken as an indication that there is data still to be transferred to complete the transaction. Moreover, a new DMA burst transfer is initiated at state 216. During the DMA transaction, the state machine is in a DMA_control state 218. After the burst transfer, a new iteration occurs whenever the attached group of storage devices is ready as a whole. This is symbolically indicated as an HDD group ready state 220 in Fig. 2. The skilled person will appreciate that the idea of waiting until a group of storage devices is ready is applicable not only to HDD storage devices, but any suitable storage device that may be employed in a digital storage system such as the digital storage system 100. When the associated storage devices are ready, the state machine iterates the loop by again calculating the cluster size remaining to be transferred and the address, as shown at state 210.

Fig. 3 is a process flow diagram that shows a method of employing adaptive burst lengths for different types of memory devices in a data storage system 100. The method is generally referred to by the reference number 300. The skilled person will appreciate that the method 300 may be implemented by a data storage system such as the data storage system 100, which has a memory device that is adapted to be accessed via DMA bursts. The skilled person will additionally appreciate that the method 300 may be performed by a state machine operating according to the state diagram 200 shown in Fig. 2.

At step 302, the method begins. At step 304, the data storage system 100 initialises the memory device. A burst length that varies depending on a characteristic of the memory device is employed for a DMA burst, as shown at step 306. At step 308, the method ends.

In one exemplary embodiment of the present invention, the DMA burst length is automatically adapted to the installed drive or device technology to achieve the optimal real-time data throughput in streaming mode, for instance by using 64- KB-bursts in for a HDD storage device and 256-KB-bursts for a SSD storage device. In such an exemplary embodiment, a set of predefined burst lengths may be stored in a table, each of the predefined burst lengths corresponding to a particular type of storage device. A burst length appropriate to a particular storage device type may be selected from the table automatically when the type of storage device is identified, as shown at state 206 in Fig. 2.

In an alternative embodiment, the system controller or PPC software conducts a performance test with the installed drives to evaluate the individually optimal burst length. In that case, the PPC software may overwrite any predefined burst length that may be contained in the DMA burst length register. In yet another alternative embodiment, separate burst lengths are maintained for read transfers versus for write transfers. Correspondingly, separate registers are used, holding a DMA_read_burst_length and a DMA_write_burst_length.

The skilled person will appreciate that combining any of the above-recited features of the present invention together may be desirable.

Claims

1. Method (300) of transferring data in a data storage system (100) having a memory device (110, 112, 114, 116) that is configured to be accessed via direct memory access bursts, the method (300) comprising:

- initialising (304) the memory device (110, 112, 114, 116); and

- employing a burst length that varies depending on a characteristic of the memory device (110, 112, 114, 116).

2. Method (300) according to claim 1 , wherein the characteristic comprises a device type.

3. Method (300) according to claim 2, wherein the device type is either a hard disk drive or a solid state drive.

4. Method (300) according to claim 1 , comprising selecting a burst length for the memory device (110, 112, 114, 116) from a set of predefined burst lengths, each of the predefined burst lengths corresponding to a particular type of memory device (110, 112, 114, 116).

5. Method (300) according to claim 1 , comprising performing a performance test on the memory device (110, 112, 114, 116) to determine the burst length to use for a data transfer to the memory device (110, 112, 114, 116).

6. Data storage system (100), comprising:

- a memory device (110, 112, 114, 116) configured to be accessed via direct memory access bursts; and

- a direct memory access unit (122) that employs a burst length that varies depending on a characteristic of the memory device (110, 112, 114, 116).

7. Data storage system (100) according to claim 6, wherein the characteristic comprises a device type.

8. Data storage system (100) according to claim 7, wherein the device type is either a hard disk drive or a solid state drive.

9. Data storage system (100) according to claim 6, wherein the direct memory access unit (122) selects a burst length for the memory device (110, 112, 114, 116) from a set of predefined burst lengths, each of the predefined burst lengths corresponding to a particular type of memory device (110, 112, 114, 116).

10. Data storage system (100) according to claim 6, wherein the direct memory access unit (122) performs a performance test on the memory device (110, 112, 114, 116) to determine the burst length to use for a data transfer to the memory device (110, 112, 114, 116).