WO2009020670A1

WO2009020670A1 - Method and system for generating software code

Info

Publication number: WO2009020670A1
Application number: PCT/US2008/050590
Authority: WO
Inventors: Kiak Wei Khoo; Kambiz Homayounfar
Original assignee: Phybit Pte. Ltd.
Priority date: 2008-01-09
Filing date: 2008-01-09
Publication date: 2009-02-12

Abstract

Method and system for a real-time software language development tool are provided. The development tool includes a host computer communicatively coupled to a target processor, a high level language compiler including a parser configured to receive a high level language instruction, direct a mathematical function portion of the instruction to a back end code generator, the back-end code generator communicatively coupled to a high level language library corresponding to the high level language for the target processor, and direct a non mathematical function to an embedded high level language engine. The development tool includes a real-time bridge communicatively coupled to the back-end code generator and the target processor wherein the high-level language compiler is configured to port a portion of the high-level language code to the target processor through the back-end code generator and the real-time bridge.

Description

METHOD AND SYSTEM FOR GENERATING SOFTWARE CODE

BACKGROUND OF THE INVENTION

[0001] This invention relates generally to embedded programmable processors and, more particularly, to providing a framework for a smooth transition of a design formulated in a high-level language to an implementation on an embedded processor.

[0002] An embedded software development cycle 100 typically includes three major stages as illustrated in Figure 1. Cycle 100 shown in Figure 1 is iterative, meaning each stage is repeated whenever verification fails.

[0003] Embedded software development cycle 100 is initiated with a proof of concept 102 using a high-level language such as MATLAB for Windows, a commercially available mathematical analysis program from The Mathwork, Inc., Natick, Massachusetts. This allows the developers to initially develop algorithms independent of the programming language of the finally implemented algorithm. A system analysis and verification stage 104 determines software performance. Final implementation 106 on a target embedded processor, such as a digital signal processor (DSP), is typically done using C or assembly languages. Transition from the high- level language code to C or Assembly, is done manually and is often a complex, error-prone and tedious process.

[0004] An inability to execute high-level language functions in the target processor prevents the designer from incremental porting of high-level language code to C or Assembly code. Designers therefore are faced with either translating all of their high level language code to C or Assembly and then performing full system testing on the target processor (sometimes referred to as whole system testing), or translating individual parts and performing unit testing. In whole system testing, the designer must have a clear understanding of the algorithm for a precise translation of the code. Whole system testing is often complex and time consuming and delays the unit testing. Translation and testing of individual parts during unit testing introduces risks whereby although each part may work individually; they may not function accurately in the whole system.

BRIEF DESCRIPTION OF THE INVENTION

[0005] In one embodiment, a real-time software language development tool includes a host computer communicatively coupled to a target processor and a high level language compiler including a parser configured to receive a high level language instruction The compiler is further configured to direct a mathematical function portion of the instruction to a back end code generator wherein the back-end code generator is communicatively coupled to a high level language library corresponding to the high level language for the target processor. The compiler is further configured to direct a non-mathematical function to an embedded high-level language engine. The development tool includes a real-time bridge communicatively coupled to the back-end code generator and the target processor wherein the high-level language compiler is configured to port a portion of the high- level language code to the target processor through the back-end code generator and the real-time bridge.

[0006] In another embodiment, a method of embedded software development includes receiving a high-level language code by a compiler and parsing a first numerical function portion of the code to a code generator. The method further includes translating the first numerical function portion to a language code specific to a target embedded processor using the code generator, porting the translated code to the target embedded processor through a real-time bridge, and executing the translated code on the target embedded processor.

[0007] In yet another embodiment, an electronic design automation system includes a compiler configured to incrementally port a portion of a high level language code to a target processor code such that only a predetermined portion of the high level language code is ported to a target processor, a code generator configured to translate the high level language code to the target processor code, and a real-time bridge communicatively coupled to the code generator and the target processor, wherein the compiler is configured to port a portion of the high level language code to the target processor through the code generator and the real-time bridge.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a flow chart of a known method of an embedded software development cycle;

[0009] Figure 2 is a schematic block diagram of a high level language code to embedded processor specific code translation system in accordance with an exemplary embodiment of the present invention; and

[0010] Figure 3 is a software architecture layered diagram in accordance with the embodiment of the present invention shown in Figure 2.

DETAILED DESCRIPTION OF THE INVENTION

[0011] The following detailed description illustrates embodiments of the invention by way of example and not by way of limitation. It is contemplated that the invention has general application to analytical and methodical embodiments of authoring software code for embedded programmable processors that accelerate the software development cycle in industrial, commercial, and residential applications.

[0012] As used herein, an element or step recited in the singular and proceeded with the word "a" or "an" should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to "one embodiment" of the present invention are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0013] Figure 2 is a schematic block diagram of a high-level language code to embedded processor specific code translation system 200 in accordance with an exemplary embodiment of the present invention. In the exemplary embodiment, system 200 executes on a host computer 201. Host computer 201 includes a high-level language compiler 202 that includes a front-end parser 204 and a back-end code generator 206. Front-end parser 204 is communicatively coupled to a high-level language engine 208 such as a MATLAB engine. Back-end code generator 206 is communicatively coupled to a high-level language library 210 such as a MATLAB library. In the exemplary embodiment, high-level language library 210 comprises a set of library functions corresponding to each of the high- level language functions of high-level language engine 208 optimized for a specific target processor 212. Code generator 206 is further communicatively coupled to target processor 212 through a real-time bridge 214, which comprises a dedicated high-speed link between the host computer 201 and a target processor emulation board 216. Real-Time Bridge 214 includes a Real-Time Bridge Driver 216 that can be in the form of, for example, but not limited to, a USB driver, a Serial Port Driver or a PCI-based user-defined port driver depending on the type of connection. Real-Time Bridge 214 also includes a Real-Time Bridge Kernel Driver 218 comprising a small kernel code that resides in a memory (not shown) of target processor 212. Real-Time Bridge Kernel Driver 218 acts as a communication operating system for target processor 212.

[0014] During operation, an instruction 222 entered by a user is parsed by front-end parser 204. Front-end parser 204 directs a mathematical function portion of instruction 222 to back end Code Generator 206 and a non-mathematical function to embedded high-level language engine 208. The non-mathematical function, for example but not limited to, graph plotting or disk operations, is executed in host computer 201. The mathematical function, for example, a sine, cosine, LU decomposition, or other function is translated to the target high level language code from back end Code Generator 206. This generated code is then transmitted to target processor 212 for execution via Real-Time Bridge 214. The result is transmitted back to host computer 201 via Real-Time Bridge 214. A command from debugger 224 such as a register data acquisition and a memory data acquisition is transmitted directly to Real-Time Bridge 214.

[0015] Real-Time Bridge (RTB), which is a dedicated high-speed link between host computer 201 and target processor emulation board 216, together with the target processor optimized high-level language library 210 enable the execution of the high-level language code on target processor 212.

[0016] Figure 3 is a software architecture layered diagram 300 in accordance with an embodiment of the present invention shown in Figure 2. As described above, Front End Parser 204 of high-level language compiler 202 not only parses the syntax of instruction 222 but also acts as a dispatcher depending on a type of instruction 222. High-level language compiler 202 dispatches a non-mathematical function to embedded high-level language engine 208 for execution. High level language compiler 202 dispatches a mathematical function to back end Code Generator 206. Code Generator 206 uses high-level language library 210 to generate the corresponding C code for target processor 212. Debugger 224 provides commonly used debugging commands, for example, but not limited to step, go, stop, read/write registers, and read/write memories. Real-Time Bridge Driver 216 continuously monitors the port for data sent from the target board as well as dispatching data to target processor board 220. Real-Time Bridge Kernel Driver 218 includes an interrupt driven kernel code to facilitate utilizing a minimum amount of processor cycles. In the exemplary embodiment, the kernel code is relatively very small, for example, approximately 100-200 words, and typically uses a relatively small portion of the total system resource.

[0017] System 200 permits an incremental porting of high-level language code to the target processor code. With high-level language Compiler 202, Debugger 224, and Real-Time Bridge 214, a designer is able to port only a certain portion of the high-level language code to the target processor and leave the rest of the code intact. The designer is able to perform a system verification by executing the ported code in target processor 212 while executing the remaining code in host computer 201. Front End Parser 204 functions as a sequence controller in addition to a command/instruction dispatcher. The incremental porting process facilitates ensuring a stability, optimization, and a correctness of the target code.

[0018] The term processor, as used herein, refers to central processing units, microprocessors, microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASIC), logic circuits, and any other circuit or processor capable of executing the functions described herein.

[0019] As used herein, the terms "software" and "firmware" are interchangeable, and include any computer program stored in memory for execution by processor 212, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are exemplary only, and are thus not limiting as to the types of memory usable for storage of a computer program.

[0020] As will be appreciated based on the foregoing specification, the above-described embodiments of the disclosure may be implemented using computer programming or engineering techniques including computer software, firmware, hardware or any combination or subset thereof, wherein the technical effect is for an incremental porting of high level language code to the target processor code such that only a certain portion of the high level language code is ported to the target processor and the remaining code remains intact on the host computer. A system verification is performed by executing the ported code in the target processor while executing the remaining code on the host computer. Any such resulting program, having computer-readable code means, may be embodied or provided within one or more computer-readable media, thereby making a computer program product, i.e., an article of manufacture, according to the discussed embodiments of the disclosure. The computer readable media may be, for example, but is not limited to, a fixed (hard) drive, diskette, optical disk, magnetic tape, semiconductor memory such as read-only memory (ROM), and/or any transmitting/receiving medium such as the Internet or other communication network or link. The article of manufacture containing the computer code may be made and/or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0021] The above-described embodiments of a method and system of authoring software code for embedded programmable processors provides a cost- effective and reliable means for providing a framework for a smooth transition of a design formulated in a high level language to an implementation on an embedded processor. More specifically, the methods and systems described herein facilitate incremental porting of high-level language code to the target processor code. In addition, the above-described methods and systems facilitate porting only a certain portion of the high-level language code to the target processor and leaving the remaining code intact. As a result, the methods and systems described herein facilitate automatically authoring software code with a high-level language for embedded programmable processors in a cost-effective and reliable manner.

[0022] While the disclosure has been described in terms of various specific embodiments, it will be recognized that the disclosure can be practiced with modification within the spirit and scope of the claims.

Claims

WHAT IS CLAIMED IS:

1. A real-time software language development tool comprising a host computer communicatively coupled to a target processor, said development tool comprising:

a high-level language compiler including a parser configured to:

receive a high-level language instruction;

direct a mathematical function portion of the instruction to a back end code generator, said back-end code generator communicatively coupled to a high level language library corresponding to the high level language for the target processor; and

direct a non-mathematical function to an embedded high level language engine; and

a real-time bridge communicatively coupled to said back-end code generator and the target processor wherein said high-level language compiler is configured to port a portion of the high-level language code to the target processor through said back-end code generator and said real-time bridge.

2. A development tool in accordance with Claim 1 wherein said parser is communicatively coupled to a high-level language engine.

3. A development tool in accordance with Claim 1 wherein said high level language compiler is configured to incremental port a portion of a high level language code to a processor specific code such that high level language functions are executed in the target processor.

4. A development tool in accordance with Claim 1 wherein said high-level language library comprises a set of library functions corresponding to each of the high-level language functions of said high-level language engine that are optimized for said target processor.

5. A development tool in accordance with Claim 1 wherein said real-time bridge comprises a dedicated high-speed link between said high-level language compiler and said target processor.

6. A development tool in accordance with Claim 5 wherein said real-time bridge comprises a real-time bridge driver and a real-time bridge kernel driver.

7. A development tool in accordance with Claim 6 wherein said real-time bridge driver comprises at least one of a USB driver, a Serial Port Driver, and a PCI-based user-defined port driver.

8. A development tool in accordance with Claim 6 wherein said real-time bridge kernel driver comprises a communication operating system for said target processor that resides in a memory of said target processor.

9. A development tool in accordance with Claim 1 wherein the non-mathematical function comprises at least one of a graph plotting function and a disk operation executed on said host computer.

10. A development tool in accordance with Claim 1 wherein the mathematical function comprises at least one of a sine, a cosine, and a LU decomposition that is translated to the target language code,

11. A development tool in accordance with Claim 1 wherein said back-end code generator is configured to transmit the code comprising the mathematical function to said target processor via said Real-Time Bridge for execution on said target processor.

12. A development tool in accordance with Claim 1 wherein said back-end code generator is configured to receive a result from said target processor through said Real-Time Bridge.

13. A method of embedded software development comprising:

receiving a high level language code by a compiler; parsing a first numerical function portion of the code to a code generator;

translating said first numerical function portion to a language code specific to a target embedded processor using the code generator;

porting the translated code to the target embedded processor through a real-time bridge; and

executing the translated code on the target embedded processor.

14. A method in accordance with Claim 13 wherein verifying a performance of the translated code comprises executing the translated code in said target processor while executing the remaining code the host computer.

15. A method in accordance with Claim 13 wherein porting the translated code comprises incrementally porting high level language code to the target processor code such that only a predetermined portion of the high level language code is ported to the target processor and the remaining code remains intact on the host computer.

16. A method in accordance with Claim 13 further comprising:

parsing a second non-numerical function portion of the code to a host processor;

17. A method in accordance with Claim 13 further comprising:

returning a result of the execution through the real-time bridge to the complier; and

verifying a performance of the translated code.

18. An electronic design automation system comprising: a compiler configured to incrementally port a portion of a high level language code to a target processor code such that only a predetermined portion of the high level language code is ported to a target processor; a code generator configured to translate the high level language code to the target processor code; and a real-time bridge communicatively coupled to the code generator and the target processor wherein said compiler is configured to port a portion of the high- level language code to the target processor through said code generator and said realtime bridge.

19. A system in accordance with Claim 18 further comprising a debugger communicatively coupled to said real time bridge, said debugger configured to transmit debugger commands directly to said real time bridge.

20. A system in accordance with Claim 18 wherein said compiler comprises a parser communicatively coupled to a high-level language engine.

21. A system in accordance with Claim 20 wherein said parser is further configured to: receive a high-level language instruction;

direct a non-mathematical function to an embedded high-level language engine

22. A system in accordance with Claim 18 wherein said code generator is communicatively coupled to a high level language library corresponding to the high level language for the target processor, said library comprising a set of library functions corresponding to each of the high level language functions of said high level language engine that are optimized for said target processor.

23. A system in accordance with Claim 18 wherein said real-time bridge comprises a dedicated high-speed link between said high-level language compiler and said target processor.

24. A system in accordance with Claim 18 wherein said code generator is configured to transmit the code comprising the mathematical function to said target processor via said Real-Time Bridge for execution on said target processor.