WO2008155418A1

WO2008155418A1 - Multiple spreading/despreading of spread-spectrum signals by multiple spreading sequences

Info

Publication number: WO2008155418A1
Application number: PCT/EP2008/057897
Authority: WO
Inventors: Martin Opitz; Thomas Reisinger
Original assignee: Continental Automotive Gmbh
Priority date: 2007-06-21
Filing date: 2008-06-20
Publication date: 2008-12-24
Also published as: DE102007028732A1

Abstract

The invention relates to a method for despreading a received spread-spectrum signal (c), wherein the despreading takes place in at least two stages. Each stage comprises the following step: generating a correlator signal by correlating a spread-spectrum signal (c, corN,..., cor2) having a spread sequence (sN,...,s1), and at least one stage comprising the following steps: decimation of the correlator signal (corN, cor(N-1),..., cor1) by a factor corresponding to the length of the spread sequence (sN,..., s1), and/or deciding on the basis of the correlator signal whether a certain symbol has been received.

Description

Multiple spreading / despreading of spread spectrum signals by multiple spreading sequences

The invention relates to a method for wireless communication with at least one peripheral unit and in particular a spread spectrum method with multiple spreading / despreading of the data transmission signal by means of multiple spreading sequences.

Especially in motor vehicles, a large number of functions are already triggered or controlled via remote controls. Usually, a radio link in license-free frequency bands is used for the transmission from and to the motor vehicle. For vehicle access and, for example, engine startup, these are so-called "remote keyless entry" systems (RKE systems, for example), such as those used for centralized radio interlocking, for example This is done mitteis integrated in a Fahrzeuσschlüssel, battery-powered radio control, which is also used in addition to the locking and unlocking of the doors and the boot also the theft protection and the immobilizer accordingly activated or Other functions, such as the convenient opening and closing of windows, sunroofs, sliding doors or tailgates, can also be integrated in the car.Another comfort function and safety feature is the activation of the vehicle's apron lighting One cares in the. Key Integrated so-called emergency button that triggers an audible and visual alarm on the vehicle when pressed.

Depending on the requirements, such RKE systems work with unidirectional or bidirectional communication in the wide area shared ISM frequencies. Other features include secure data transmission with optionally increased security, a challenge-response authentication method (bidirectional) and low energy consumption. In addition, further applications allow one

Personalization of the functions of a RKE system to selected persons. The range of such RKS systems is usually up to 100 m.

Another radio communication based system is the so-called PASE system. PASE stands for PAssive Start and Entry and describes a keyless access and start system. In this keyless vehicle access system, the driver only has to carry an identification transmitter (ID) with him and gets access to the vehicle by simply touching the door handle. As soon as the driver is inside the vehicle, the engine can be started by pressing a button. If the driver leaves the vehicle, the PASE system locks the vehicle either automatically or at the push of a button. The driver's identification card replaces conventional mechanical or radio controlled keys to provide maximum comfort and ease of use for the driver. Again, there is the possibility of personalization on selected persons and it is usually a multi-channel bidirectional data transmission is used, which also takes place wirelessly and encrypted, for example in the field of shared ISM frequencies worldwide.

In addition, systems with additional functions such as the transmission of status information are also establishing themselves in the field of motor vehicles today. Such systems generally operate over longer ranges, typically several hundred meters. Examples are the so-called Telestart, d. H. a motor start from greater distances, or the

Remote control of a parking heater, automatic air conditioning and so on. Further examples of the use of radio links with longer ranges than those described in the RKE and PASE systems refer to the motor vehicle from a long distance retrievable status information, such as the current closed state, the current interior temperature and results of technical system checks (technology check). A transmission of alarm messages is desirable over a longer distance.

All functions that require wireless data transmission over long distances are also summarized under the term "long-range applications." One goal for long-range applications is to make data transmission or communication bidirectional over distances of at least 600 m In order to achieve the goal of data transmission over greater distances and the associated high sensitivity in signal reception, it is customary in the prior art to carry out the data transmission of the useful signals at a low data rate the so-called spread spectrum method using the spread spectrum technique.

The idea of Spread Spectrum Communication is already several decades old. Whereas at the beginning of the development demands for interference- and eavesdropping-proof communication, in particular for the military application area, were in the foreground, the advantages of robust transmission in frequency-selective channels and easy-to-implement variable data transmission rates also became increasingly important, so that the band spread technology has evolved into a leading technology for satellite and mobile communications in the context of the growing availability of high-performance hardware.

Spread spectrum arrangements are characterized by a transmission bandwidth which is substantially larger than the bandwidth of the information to be transmitted. This code-based spreading of a data signal before its transmission is achieved by multiplying the data signal by a fixed bit sequence (pseudorandom number) of higher bit rate, the so-called chip rate. In this way, a spread in the modulated high-frequency spectrum is achieved while maintaining the net data rate. The demodulation of such a spread spectrum signal essentially takes place by correlation of the received signal with a copy of the so-called spread signal used in the transmitter for spreading. A fundamental component of a spread spectrum arrangement are pseudo-random sequences whose autocorrelation function is in

With respect to a receiver-side despreading of the spread data signal has ideal properties.

In this case, for example, a data signal to be transmitted d (k) of the data rate D (kbit / sec) with a so-called

Spreading sequence s (1) multiplied by a length m. The resulting spread data signal or chip signal c (l) with c (1) = d (k) ^• s (1) has the m-fold, also referred to as chip rate data rate of the original data rate D. In this case, k denotes the bit clock and 1 the chip clock of an arrangement for band spreading. With the aid of this spread data signal, a high-frequency carrier signal is arbitrarily modulated (AM, FM, PSK, etc.). This multiplication of the original data rate to the chip data rate results in a broadening or spreading of the frequency range required for radio transmission.

As a consequence, a so-called spreading gain G results, which is calculated according to the formula G = 10 -LOG (m). The broader the spread of the frequency band is selected for the information transmission, the less susceptible to interference data transmission, especially for narrow-band interference signals. As a result, broadband transmission signals can nevertheless be generated with a low user data rate. Especially in the US, this is a prerequisite to meet the criteria of the FCC (Federal

Communications Commission) for spread spectrum transmission in the 902 MHz band, which is a prerequisite for using a higher transmission power. By the low Payload or due to the large Spreizgewinns the desired high sensitivity remains. Due to the higher transmission power limits and the high sensitivity, ranges of a "long-range" radio transmission can be realized. At the same time, spreading also provides some protection against unauthorized interception in cases where critical data, such as identification codes, is to be transmitted.

If the spreading gain G or the spectral range to be used or the robustness to interfering signals are specified, the required length m of the spreading sequence results from one or more of these requirements. Previous arrangements use a single spreading sequence to multiply the data signal once. This results in the available spreading gain, the spectrum spread, etc. In order to achieve the largest possible spreading gain, the longest possible spreading sequences s (1) must be used. However, this disadvantageously results in an increased effort for despreading the transmitted data signal on the receiver side of such an arrangement. This increased complexity is evident, for example, in the number of elements required for a correlator for despreading the data signal, such as delay elements, logic operation elements and storage registers for the spread sequences.

An alternative spread spectrum method also frequently used in the prior art is the frequency hopping spread spectrum. In the frequency hopping method, the carrier frequency of the signal is suddenly varied in discrete steps, that is to say narrowband but on many different However, this method has the disadvantage that the requirement of accidental use of a minimum number of channels results in long polling cycles, ie the transmitter must first transmit until the receiver is all in question for the data transmission This has been the case with battery-operated bidirectional Tional Funkubertragungsanordnungen, such as the above-mentioned F? T 2ycz.2rc ^ a significantly increased and thus undesirable power requirements of the battery-powered radio key result.

The object of the present invention is to specify a spread spectrum method for wireless communication in which the most varied requirements are largely met.

The object is achieved by a spread spectrum method according to claim 1. refinements and developments of the inventive concept are the subject of dependent claims.

The object is achieved in particular by a spread spectrum method for wireless bidirectional communication with multiple spreading / despreading of the data signal with the aid of shortened spreading sequence lengths and with at least one corresponding correlator on the respective receiver side of the bidirectional radio transmission arrangement.

The invention will be explained in more detail with reference to the exemplary embodiments illustrated in the figures of the drawings, wherein like elements are provided with the same reference numerals. It shows:

FIG. 1 is a block diagram showing a general structure of a despreading correlator of the prior art;

Figure 2 is a flowchart showing the process of spreading and despreading a data signal according to the prior art;

FIG. 3 shows a block diagram of a structure of a correlator required for despreading in the case of binary input signals and despreading in baseband; FIG. 4 is a block diagram of embodiments (a), (b) and (c) for generating the baseband modulation signal;

Figure 5 is a block diagram showing an embodiment of the structure of a despreading correlator in the case of a multiple spread input signal;

FIG. 6 is a flowchart showing a sequence of despreading by the correlator according to FIG. 5;

FIG. 7 is a flowchart showing three exemplary embodiments of the invention

Despreading by three further embodiments of correlators;

Figure 8 is a block diagram of an alternative embodiment of the structure of a despreading correlator in the case of a final logical value decision;

FIG. 9 shows in a table a general representation of the calculation rule for the number of elements required in a correlator;

FIG. 10 shows in a block diagram an exemplary embodiment of the structure of the correlator used for despreading according to FIG. 8 for the case of a successive logic value decision;

FIG. 11 is a table showing the calculation rules for the number of elements required in a successive logic value decision correlator;

FIG. 12 shows in a table the calculation specifications for the number of times in a correlator with successive logic value decision or final the logic value decision and double spreading or despreading required elements;

FIG. 13 shows in a table the number of elements required in a correlator with successive logic value decision or concluding logic value decision and 225-fold spreading or despreading;

FIG. 14 shows a diagram of the autocorrelation function of a data signal which has once been spread or despread with a ZigBee spreading sequence; and

FIG. 15 shows a diagram of the autocorrelation function of a data signal which is twice spread or despread using a ZigBee spreading sequence.

As described above, in order to obtain the greatest possible spreading gain G, it is necessary to use long spreading sequences (spread sequence length m) which result in a high outlay on the receiver-side despreading of the transmitted data signal. It is now proposed not to achieve the spreading gain in the desired size by a single spreading or despreading (with the spreading sequence length m) but by an N-fold spreading or despreading of the data signal with the aid of correspondingly shorter spreading sequence lengths of the lengths ni, n ₂ , ... n _N. In this case, the total effective spreading sequence length n _{ges is} calculated to n _ges = ni ^• n ₂ * ... * n _N. In this way, a power, silicon and register-saving implementation of the despreading can be achieved in an ASIC at greatly increased Spreizgewinn.

15 bit or 15 chip spreading sequences have already been implemented in various other embodiments by ASICS. The exemplary embodiments shown below offer approximately 15 times the approximate cost of despreading in an ASIC Performance in terms of spreading profit. For example, the 15-bit ZigBee spreading sequence is used twice. This will also ensure compatibility with future ZigBee applications. ZigBee describes a new industry standard for the networking of devices and sensors or for wireless communication and control in almost all areas (see IEEE Working Group 802.15.4).

Typical areas of application for ZigBee include home networking, automation and safety technology in facility management and machine-to-machine communication (M2M). Due to the technical functionality and the comparatively low costs, ZigBee can be used to build completely wireless, infrastructure-independent device and sensor networks. The ZigBee standard supports

Data rates of 20, 40 and 250 kBit / s in the frequency ranges 868 MHz, 915 MHz and 2.4 GHz, respectively. The connection to ZigBee is instantaneous, while it takes up to 3 seconds for Bluetooth applications. Also, the number of components in a ZigBee network with more than 250 is significantly less limited than with Bluetooth (7 components). Furthermore, the ZigBee standard is particularly suitable against the background of low energy consumption compared to WLAN or Bluetooth, which is particularly advantageous for battery-powered devices, for example.

There are also plans for applications where a spectral bandwidth of at least 50OkHz can be used with up to 1 watt transmission power. The high bandwidth can only be achieved with relatively high chip data rates

(> 25OkChip / sec). At the same time, however, as described above, can not be dispensed with the high sensitivity, which offers a low net data rate of the data signal to be transmitted. The invention now achieves the ranges necessary for long-range applications.

As already mentioned above, in spread spectrum arrangements according to the prior art, a data signal d (k) of the data rate D (kbit / sec) multiplied by a so-called spreading sequence s (1) of a length m (s (l ... m)). The resulting spread data signal or chip signal c (l) with c (l) = d (k) -s (l) has m times the data rate of the original data rate D, also referred to as the chip rate (spread). In this case, k denotes the bit clock and 1 the chip clock of an arrangement for band spreading.

On the receiver side, a corresponding despreading of the received data signal is carried out based on this one spreading sequence s (l... M). For this purpose, the received signal r (l) digitized with the resolution bit width b is correlated with the spreading sequence s (l... M) in a receiving-side correlator. As a result, correlation sums in the chip clock cor (1) result. The signal cor (k) is obtained from this by synchronized down-clocking, and the despread signal d (k) is obtained by a subsequent decision ("0" or "1"). The synchronization for the down-clocking and the decision can in principle be exchanged in the order.

FIG. 1 shows a block diagram of a corresponding correlator according to the prior art. In this case, FIG. 1 includes m-1 delay elements Z ₁ , Z ₂ ,..., Z _m _i, m multipliers Mi, M ₂ ,..., M _m , a summer Σ, an arrangement 1 for downsampling and a Decision unit 2. According to FIG. 1, the received signal r (1, b) digitized with the resolution bit width b is correlated with the spreading sequence s (1... M). In this case, r (l, b) is multiplied by the value s (l) of the spreading sequence s (l... M) and the result is fed to the summer Σ, the signal r (l, b) delayed by the delay element Z ₁ is also included multiplied by the value s (2) of the spreading sequence s (l... m) and the result is fed to the summer Σ. The signal r (1, b), which is further delayed by the delay elements Z ₂ , is multiplied by the value s (3) of the spreading sequence s (1... M) and the result is fed to the summer Σ. These steps are repeated in the correlator of Figure 1, to the over all m-1 delay elements Z _1, Z _2, ..., Z _m _ i delayed signal r (l, b) multiplied by the value s (m) of the spreading sequence s (l ... m) and also this result is fed to the summer Σ.

The result of the summation of the individual signal components 1 to m of the multipliers Mi, M ₂ ,..., M _m in the summer Σ leads according to FIG. 1 to the signal cor (1) which is downsampled by the arrangement 1 into the Signal cor (k) is transferred. As a result of the subsequent processing in the decision unit 2 (decision), the desired despread bit signal d (k) obtained by a decision in bit values "0" or "1" corresponds to the original data signal fed into the transmitting unit and to be transmitted.

It should be noted at this point that a spread or despreading of the data signal does not have to be in the baseband and accordingly the spreading or despreading of the data signal also does not have to be done with binary signals. Furthermore, the spreaders or despreaders illustrated here are merely exemplary embodiments of correlators, so that the necessary synchronization of the signals for down-clocking can be implemented in any desired manner.

The entire sequence of an exemplary spreading and despreading of a data signal is shown in simplified form in the form of a flowchart in FIG. According to FIG. 2, digitized chips of the chip rate 1 are generated from a data signal to be transmitted with the aid of a spreading sequence of length m. In a receiver-side correlator, this bit sequence is correlated in clock 1 with the spreading sequence (sequence s) of length m (see FIG. 1). By subsequent synchronized down-sampling (compare arrangement 1 in FIG. 1), a data signal with the original bit rate k = 1 / m is restored. By means of a subsequent decision unit "decision" (compare decision unit 2 according to FIG. 1), the bits ("0" or "1") of the original data signal d (k) are restored. The frequency spreading method used is also referred to as the Direct Sequence Spread Spectrum (DSSS) method. This method is also used in wireless LANs according to the IEEE 802.11 standard.

For the special case of binary input signals (signal d (k)) and a despreading in the baseband, the user data are linked by Exklusiv-Or (EXOR) with a predetermined sequence (spreading sequence) and then modulated to the bandwidth.

The spreading sequence used represents a bit sequence. If this spreading sequence has, for example, 8 bits or chips, each bit of the data signal to be transmitted must be linked to this spreading sequence EXOR. For an exemplary

Spread sequence or chipping sequence of 1 1 0 0 0 1 1 1 results accordingly for the transmission of a data signal d (k) consisting of a "1" and a "0" following signal:

In such a case, therefore, the spread data set with the bit sequence 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 1 is transmitted.

In order to restore the original data signal d (k) from this spread and transmitted data signal, the despreading in the baseband according to the prior art, for example, with the aid of a correlator illustrated in FIG. 3, is carried out for the specified special case of binary input signals and spreading as described above.

The correlator according to FIG. 3 again comprises the delay elements Zi, Z ₂ ,..., Z _m _i known from FIG. 1 and one

Summer Σ. In contrast to FIG. 1, FIG. 3 also comprises m negated exclusive OR arrangements negEXORi, negEXOR2,... NeGEXOR _m and m memory register 3 for the spreading sequence, and an ne further negated exclusive-OR (negEXOR) arrangement 4. According to Figure 3, the binary received signal c (l, 2) is in turn correlated with the spreading sequence s (l ... m). In this case, c (l, 2) is associated with the value s (l) of the spreading sequence s (l... M) negatively connected with exclusive-or (negEXORi) and the result is fed to the summer Σ; the signal c (l, 2) delayed by the delay element Z ₁ with the value s (2) of the spreading sequence s (l... m) negates exclusive-or (negEXOR2) and supplies the result to the summer Σ; the further delayed signal c (l, 2) via the delay element Z ₂ with the value s (3) of the spreading sequence s (l... m) negates exclusive-or (negEXORs) and supplies the result to the summer Σ. These steps are repeated in the correlator according to FIG. 3 until the binary signal c (l, 2) delayed over all m-1 delay elements Z ₁ , Z ₂ ,..., Z _m _i has the value s (m) of the spreading sequence s (l ... m) negated exclusive-or (negEXOR _m ) linked and this result is fed to the summer Σ.

The result of the summation of the individual signal components 1 to m of the m negated exclusive-OR (negEXOR) arrangements ne- gEXORi, negEXOR2... NegEXOR _m is stored in the m memory registers 3. Device 4 acts as a decider by combining the MSB from memory register 3 with the logical value "1" via the negated exclusive-or (negEXOR) arrangement, resulting in the desired binary logic values "0" and "1" of the original binary data signal For the construction of such a correlator for processing data signals spread with the factor m, the following number of components are required: m-1 delay elements Z ₁ , Z ₂ ... Z _m _i, m + 1 negated exclusive-or (negEXOR) arrangements , m memory register 3 and a summer Σ for m bits.

It will now be explained how the described one-time spreading or despreading with a spreading sequence of length m can be replaced by an N-times spreading or despreading with spreading sequences of the lengths ni, n ₂ ,... _{N N.} The individual spreading sequences are denoted by Si (I... Ni), S ₂ (I... N ₂ ),... _N (l... _{N N} ). Where n _tot the calculation rule n _ges ₂ ^• ... ^•% applies to the entire Spreizlänge = ni ^• n. For a simple comparison with a conventional spreading or despreading, it is also possible to choose n _ges = m. To generate the modulation signal in the baseband, the two arrangements illustrated in FIGS. 4a, 4b and 4c can be used by way of example.

Figure 4a comprises N multipliers Mi, M ₂ , ..., M _N. In this case, according to an embodiment of a method or an arrangement for spreading a data signal with N spreading sequences, the original data signal d (k) is multiplied by a spreading sequence sl (II) via a first multiplier Mi. The signal c (11) resulting from this multiplication is multiplied by a second multiplier M ₂ with a spreading sequence s 2 (12), which produces the signal c (12). This process is continued using a total of N multipliers Mi, M ₂ ... M _N until a signal c (IN-I), which emerges from the preceding multiplier M _N -i, is used with the last multiplier M _N Spreading sequence sN (lN) is multiplied and the final, multiple-spread signal c (ln) results.

FIG. 4 b shows how this principle can be used to expand an existing ZigBee architecture or hardware for a long-range application (data rate exemplary 1 kbit / s): The ZigBee hardware expects input data with 40 kbit / s. s and spreads these with the Zig-Bee spreading sequence s2 of length 15, resulting in a transmission signal with 600 kchip / s. The long-range data are previously spread with a spread sequence sl of length 40, resulting in the actual long-range data rate of lkbit / s, a ZigBee-compliant input signal with 40 kchip / s. Overall, the long-range signal was thus spread by the factor 40 * 15 = 600. The selection of the spreading sequence sl is carried out so that a given bit rate is spread to 40 kchip / s. Basically, this principle can be reversed: So it may be advantageous to choose sl = s2. For the above Example would be the long-range sequence equal to the Zig-Bee sequence (length 15), and the total spreading factor would be 15 * 15 = 225. Since the ZigBee hardware dictates the final chip rate, the result is a long-range data rate of 2.67 kbit / s (= 600 kchip / s / 225).

According to FIG. 4c, a second embodiment also comprises N multipliers Mi, M ₂ ... M _N. In this case, to spread a data signal with N spreading sequences, first the spreading sequences sl (II), s2 (12)... SN (IN) are multiplied by themselves. This takes place starting with the multiplication of the spreading sequences sl (II) and s2 (12) via the multiplier Mi (see FIG. 4c below). The result of this multiplication is subsequently multiplied by the multiplier M ₂ with the third spreading sequence s3 (13). This process is continued for the further spreading sequences until the last spreading sequence sN (IN) is multiplied by the multiplication action of all preceding spreading sequences via the multiplier M _N -i. This multiplication of all spreading sequences sl (II), s2 (12),..., SN (IN) by itself (output signal of the multiplier M _N -i) is then multiplied by the data signal d (k), whereby the spread signal c (FIG. In this case, both the method according to Figure 4a and the method according to Figure 4c for spreading a data signal with N spreading sequences to the same output signals c (ln).

In order to perform a despreading of a data signal spread using the methods according to FIGS. 4 a or 4 c at the receiver end, a correlator may also be used, as is shown by way of example in FIG. However, then such a correlator has to be designed to a Spreizfolgenlänge, which as described above from the individual lengths of the spreading codes in accordance with n _tot = ni * n is ₂ -...- n _N calculated. FIG. 5 shows by way of example how the despreading of the received data signal can also be achieved by an arrangement of N simplified correlators, which in total require a smaller number of components than a conventional correlator for a spread sequence length n _tot . FIG. 5 comprises N separate correlators Ki to K _N. In this case, the correlator Ki comprises n-1 delay elements Z _N , i, Z _N , 2,..., Z _{S | n} _i, each having a time delay z ^"1 of one sampling interval, n multipliers Mi, M2,. .., M _n and a summer Σ. According to figure 5, the digitized reception signal in correlator c Kl (l, b = bθ) correlated with the spreading sequence sN (l ... nN). Here, c (l, b = bθ ) multiplied by the value sN (l) of the spreading sequence sN (l ... nN) via the multiplier Mi, and the result is fed to the summer Σ, which is supplied via the

Delay Z _N , 1 delayed signal c (l, b = bθ) is multiplied by the multiplier M ₂ with the value sN (2) of the spreading sequence sN (l ... nN) and fed the result to the summer Σ, which via the Delay Z _N , ₂ further delayed signal c (l, b = bθ) is multiplied by the value sN (3) of the spreading sequence sN (l ... nN) and fed the result to the summer Σ. These steps are repeated in the correlator Ki in accordance with Figure 5, until the all the n-1 delay elements Z _N, 1, Z is _N, ₂ ... Z _N, ni c each having a time delay Z ^"1 verzö- siege signal (l , b = bθ) is multiplied by the value sN (nN) of the spreading sequence sN (l ... nN) and this result is also fed to the summer Σ.

The result of the summation of the individual signal components 1 to n of the multipliers Mi, M ₂ ... M _n in the summer Σ leads according to FIG. 5 to an output signal of the correlator Ki with the chip rate 1, which is made available to the subsequent correlator K ₂ as an input signal becomes. In this case, the correlator K ₂ n-1 delay Z _N _i, i, Z _N _i, ₂ ... Z _N _i, _n _i each with a time delay z ^{~ nN} , n multipliers Mi, M ₂ ... M _n and a summer Σ. According to FIG. 5, the correlator K ₂ correlates the output signal of the correlator Ki with the spreading sequence s (NI) (1... NN). In this case, the output signal of the correlator Ki multiplied by the multiplier Mi with the value s (N-1) (1) of the spreading sequence s (NI) (1 ... nN) and the

The result is fed to the summer Σ, which via the delay element Z _N -i, 1 delayed output signal of the correlator Ki is the multiplier M ₂ with the value s (NI) (2) of the Spreading sequence s (NI) (1 ... nN) is multiplied and the result is fed to the summer Σ, which via the delay elements Z _N -i, ₂ further delayed output of the correlator K ₁ with the value s (NI) (3) the spreading sequence s (NI) (1 ... nN) multiplied and the result is fed to the summer Σ. These steps are repeated in the correlator K ₂ according to Figure 5, until the all the n-1 delay elements Z _N -i, i, -i _N Z ₂ ... Z _N i, ni, each having a time delay Z ^{~ nN} delayed output signal of the correlator Ki multiplied by the value s (NI) (n (NI)) of the spreading sequence S (NI) (I ... nN) and this result is also fed to the summer Σ. The result of the summation of the individual signal components 1 to n of the multipliers Mi, M ₂ ... M _n in the summer Σ in the correlator K ₂ leads according to FIG. 5 to an output signal of the correlator K ₂ with the chip rate 1, that of the subsequent correlator K ₃ (not shown) is provided as an input signal.

This process described for the correlators Ki and K ₂ is continued in correspondingly executed correlators K ₃ to K _N - ₁ until the output signal of the correlator K _N - ₁ (not shown) is made available to the last correlator K _{N of} the arrangement according to FIG becomes. As in all previous steps, this output signal of the correlator K _N -i has the chip rate 1. The final correlator K _N of the row 1 to N of correlators comprises n-1 delay elements Zi, _1, _{Zi, 2} ... _Zi, _i _n each having a time delay z ^{~ (nN +} - ^• - ^{+ n2)} _r n multipliers Mi, M ₂ ,..., M _n , a summer Σ, an arrangement 1 for down-sampling and a decider 2. According to FIG. 5, in the correlator K _N, the output signal of the correlator K _N -1 with the spreading sequence sl (FIG. l ... nl) correlates. In this case, the output signal of the correlator K _N -1 multiplied by the multiplier Mi with the value sl (l) of the spreading sequence sl (l ... nl) and the result is fed to the summer Σ, which delayed over the delay element Zi, 1

Output of the correlator K _N -1 is multiplied by the multiplier M ₂ with the value sl (2) of the spreading sequence sl (l ... nl) and the result is fed to the summer Σ, the via the delay elements Z ₁ , ₂ further delayed output signal of the correlator K _N -i is multiplied by the value sl (3) of the spreading sequence sl (l ... nl) and the result is fed to the summer Σ.

These steps are repeated in the correlator K _{N in} accordance with FIG. 5 until the time delay for all the n-1 delay elements Zi, i, Zi, ₂ ,..., Zi, _n -i, each with a time delay _z ^{~ (nN +} '' ^{- + n2)} delayed output signal of the correlator K _{N is} multiplied by the value sl (nl) of the spreading sequence sl (l ... nl) and this result is also fed to the summer Σ The result of the summation of the individual signal components 1 to n of the multiplier Mi, M ₂ ... M _n in the summer Σ in the correlator K _N leads according to Figure 5 to an output signal of the correlator K _N with the chip rate 1, by the arrangement 1 for synchronized down-sampling in a signal with the original clock frequency of As a result of the subsequent processing in the decision unit 2, the desired despread bit signal d (k) is obtained by a decision in bit "0" or bit "1", which is the original input to the transmitting unit fed and to be transmitted data signal corresponds.

The procedure in accordance with FIG. 5 corresponds to a depletion of the transmitted data signal in the reverse order of spreading in the transmitter of a radio transmission arrangement, whereby in the correlators Ki to K _N also the spreading sequences used to spread the data signal are applied in reverse order to despreading. By this division into N individual correlators Ki to K _N on the receiver side, there is a saving in the number of multipliers required compared to a single conventional correlator. The exemplary embodiment of the despreading of a data signal according to FIG. 5 leads to the same result as the despreading of a data signal with a conventional correlator if the data signal to be transmitted has a single spreading sequence Si (ni)... _N (n _N ) of length m = ni * n ₂ -...- n _N would be spread. According to the procedure illustrated in FIG. 5, the correlation values of the individual spreading sequences extracted in the correlators Ki to K _N -i are respectively forwarded to the subsequent (partial) correlator, without a decision on a logical bit value "0" or "0 being made here. 1 "is hit. The chip clock 1 is retained in these cases. Only after the last partial correlator is the clock clock clocked down to the original bit clock (see arrangement 1 according to FIG. 5). Subsequently, the decision Bit = "0" or "1" is made in the decision unit 2 based on the sum of all correlation values. The sequence of downclocking and decision in binary logic values is again interchangeable, without this having an effect on the result of the arrangement according to FIG.

FIG. 6 shows in a flowchart in a clear form the course of the despreading by the multi-stage correlator according to FIG. 5. As described above, the effective total spread length of the spread of the data signal to be transmitted is calculated as m = ni ^• n2 *. n _N. The signal received on the receiver side is correlated stepwise in reverse order with the spreading sequences used in accordance with the spreading. According to FIG. 6, the received digital chip signal with the chip rate 1 is made available to the first correlator Ki with an incoming bit width bθ. The incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator Ki. In the correlator Ki, there is no oversampling of the signal to be processed (oversampling = 1). In correlator Ki, the here first despreading sequence sN (last spreading sequence in the case of signal spreading) with the spreading sequence length nN is used (compare correlator Ki according to FIG. 5). After correlation with the despreading sequence sN (compare correlator Ki according to FIG. 5), the output signal of the correlator Ki results in corN (1, bl) with the chip rate 1 and the outgoing bit width bl. This overclocked by the correlator Ki signal corN (l, bl) with the chip rate 1 and the bit width ld (bO-nN) = bl is subsequently forwarded to the second correlator K2. The incoming and the outgoing clock chip or the chip rate be for the correlator K2 respectively 1. In the correlator K ₂ oversampling of the signal to be processed is held (oversampling = nN). Furthermore, in the correlator K _2, the second despreading here is s (NI) (penultimate spreading sequence for the signal spreading) with the Spreizfol- gene length n (NI) is applied (see correlator K ₂ according to Figure 5). The output signal of the correlator K ₂ is obtained in this way after correlation with the despreading sequence s (NI) (compare correlator K ₂ according to FIG. 5) to cor (NI) (1, b2) with the chip rate 1 and the outgoing bit width b2. This process is subsequently repeated stepwise via the correlators K ₃ to K _N - ₁ with corresponding input signals cor from the preceding correlators and corresponding bit widths, oversampling, spreading sequences and spreading sequence lengths and the chip rate 1 until, as the output signal of the correlator K _N -1, the output signal cor2 (1, b (NI)) with the chip rate 1 and the bit width b (NI) is available.

This over-sampled signal cor2 (1, b (NI)) overclocked by the correlator K _N -1 with the chip rate 1 and the bit width Id (b (N-2) -n 2) = b (N 1) is shown in FIG passed on to the last correlator K _N (ld (...) is the dual logarithm, the result rounded up to the next larger number of bits). The incoming and the outgoing clock chip or the chip rate be for the correlator K _N, respectively 1. In the correlator K _N, oversampling of the signal to be processed is held (oversampling = n _N-n (N-1) -...- n ₂ ). Furthermore, the last despreading sequence s1 (first spreading sequence in the case of signal spreading) with the spreading sequence length n1 is used in correlator K _N (compare correlator K ₂ according to FIG. 5). The output signal of the correlator K _N results in this way after the correlation with the despreading sequence sl (see Correlator K _N according to FIG. 5) to corl (1, b _N ) with the chip rate 1 and the outgoing bit width b _N.

Only after the last partial correlator K _N the chip clock is clocked down via the arrangement 1 synchronized to the original bit clock (compare arrangement 1 according to FIG. 5). The result is a correlation signal corl (k, b _N ) of the original bit rate k of the data signal to be transmitted. Subsequently, the decision is made in the decision unit 2 based on the sum of all correlation values

Bit = 0 or 1, resulting in the final and desired output d (k, 1) of the original bit rate k and bit width 1. The sequence of downclocking and decision is again interchangeable, without this having an effect on the result of the arrangement according to FIGS. 5 and 6.

There are several methods for synchronization for downclocking. In the case of the method presented here, it is advantageous, under the objective of a fast and / or simple synchronization, to set up the synchronization on the basis of only one or fewer subsequences.

Starting from the exemplary correlator according to FIG. 5 with final downsampling of the chip rate and concluding decision into logical bit values "0" and "1", further embodiments of correlators with a stepwise correlation are derived below. These include stepwise correlators with final separation into logical bit values "0" and "1", in which a down-sampling of the chip rate is performed after each partial correlator (successive down-clocking) so that no overclocked data signal is fed to the respective subsequent correlator (see below) Figure 7a). Furthermore, the following alternative embodiments include

Correlators with only a final down-clocking of the chip rate, in which after each partial correlator a decision is made in logical bit values "0" and "1" (sukzes- sive decision), so that an IBit of broad chip signal with overclocking is made available to the respective subsequent correlator (see the following FIG. 7b).

Further alternative embodiments of correlators include sub-correlators in which the respective subsequent sub-correlators are provided with a 1-bit-wide chip signal without overclocking. This means that after each partial correlator, a down-clocking of the chip signal and a decision in logical bit values "0" and

"1" is taken, whereby the order of down-clocking and decision has no influence on the resulting output signal of the respective Teilorrorrelators the despreading arrangement (see the following Figure 7b).

FIG. 7 shows in a flowchart in a clear form the course of the despreading by multistage correlators. Here, FIG. 7a shows the sequence of despreading of a data signal by stepwise correlators with final decision into logical bit values "0" and "1", with down-sampling of the chip rate being carried out after each partial correlator (successive down-clocking), so that the respectively following correlator is not over-clocked Data signal is supplied. According to FIG. 7a, the received digital chip signal with the chip rate 1 is made available to the first correlator Ki with an incoming bit width b = bθ.

The incoming and the outgoing chip clock or the chip rate are respectively 1 = 10 for the correlator Ki. In the correlator Ki, there is no oversampling of the signal to be processed (oversampling = 1). In correlator Ki, the first despreading sequence sN (last spreading sequence in the signal spreading) with the spreading sequence length nN is used here (compare correlator Ki according to FIG. 5). The output signal of the correlator Ki results after correlation with the despreading sequence sN (compare correlator Ki according to FIG. 5) to corN (10, bl) with the chip rate 10 and the outgoing bit width bl. This signal corN (10, bl) with the chip rate 10 generated by the correlator Ki is converted in the following arrangement 1 for down-sampling into a signal corN (II, bl) with the chip rate 10 / nN and subsequently forwarded to the second correlator K ₂ , The incoming and the outgoing chip clock or the chip rate are respectively 1 / nN = 11 for the correlator K _2. In the correlator K ₂ , no oversampling of the signal to be processed takes place (oversampling = 1). WEI terhin is in correlator K _{2 is} the second frequency here Entspreizungsse- s (NI) (penultimate spreading sequence for the signal spread) with the Spreizfolgenlänge n (NI) is applied (see correlator K ₂ according to Figure 5).

The output signal of the correlator K ₂ results on this

Way after correlation with the despreading sequence s (N-1) (compare correlator K ₂ according to Figure 5) to cor (NI) (11, b2) with the chip rate 11 and the outgoing bit width b2. Subsequently, this output signal is converted in the following arrangement 1 for down-clocking in a signal cor (NI) (12, b2) with the chip rate ll / n _N = 12 This process is subsequently stepwise through the correlators K ₃ to K _N _ i with corresponding Input signals cor from the previous correlators and corresponding bit widths, oversampling, spreading sequences and spreading sequence lengths and down-clocks in arrangements 1 are repeated until the input signal for the correlator K _{N is} the signal cor2 (1 (NI), b (NI)) Chip rate 1 (N-2) / (NI) and the bit width b (NI) is available.

This signal cor2 (1 (NI), b (NI)) provided by the correlator K _N -i with the chip rate 1 (N-2) / (NI) and the bit width b (NI) becomes according to FIG. 7a below the last correlator K _N forwarded. The incoming and the outgoing chip clock or the chip rate are respectively 1 (N-2) / (NI) = 1 (NI) for the correlator K _N. In correlator K _N no oversampling of the signal to be processed takes place (oversampling = 1). Furthermore, in correlator K _N the here last despreading sequence sl (first spreading sequence in the signal spreading) with the spreading sequence length nl applied (see correlator K2 according to Figure 5). The output signal of the correlator K _N results in this way after correlation with the despreading sequence sl (see correlator K _N according to Figure 5) to corl (1 (NI), bN) with the chip rate 1 (NI) and the outgoing bit width bN. After this last partial correlator K _N , the chip clock is re-clocked via the arrangement 1 and thus down-converted to the original bit clock (compare arrangement 1 according to FIG. 5).

The result is a correlation signal corl (lN = k, bN) with the original bit rate k of the data signal to be transmitted. Subsequently, the decision Bit = 0 or 1 is made in the decision unit 2 based on the sum of all correlation values, resulting in the final and desired output signal d (k, 1) of the original bit rate k and the bit width 1. In this case, the sequence of down-clocking and decision after the last corrector K _{N is} again interchangeable, without this having an influence on the result of the arrangement according to FIG. 7 a.

FIG. 7b shows the sequence of the despreading of a data signal by means of stepwise correlators with final downshifting after the last partial correlator, whereby after each

Partial correlator a decision in logical bit values "0" and "1" is performed (successive decision), so that the respective subsequent correlator an overclocked chip data signal is fed with IBit width. According to FIG. 7b, the received digital chip signal with the chip rate 1 is made available to the first correlator Ki with an incoming bit width b = bθ. The incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator Ki.

In the correlator Ki no oversampling of the signal to be processed takes place (oversampling = 1). In correlator Ki, the first despreading sequence sN (last spreading sequence) frequency in the signal spreading) with the spreading sequence length nN applied (see correlator Ki according to Figure 5). The output signal of the correlator Ki results after correlation with the despreading sequence sN (compare correlator Ki according to FIG. 5) to corN (1, bl) with the chip rate 1 and the outgoing bit width ld (nN-bO) = bl.

This signal corN (1, bl) with the chip rate 1 generated by the correlator Ki becomes in the subsequent decision unit (decision in logical bit values "0" and "1") a signal corN (1, 1) with the chip rate 1 and the bit width 1 converted and subsequently forwarded to the second correlator K ₂ . The incoming and the outgoing clock chip or the chip rate be ₂ K for the correlator in each case 1. In correlator K ₂ oversampling of the signal to be processed is held (oversampling = nN). Furthermore, in the correlator K _2, the second despreading is applied here s (NI) (penultimate spreading sequence for the signal spreading) with the Spreizfolgenlänge n (NI) (see correlator K ₂ according to Figure 5).

The output signal of the correlator K ₂ results in this way after correlation with the despreading sequence s (N-1) (compare correlator K ₂ according to Figure 5) to cor (NI) (1, b2) with the chip rate 1 and the outgoing bit width b2.

Subsequently, this output signal is converted in the following decision unit 2 (decision into logical bit values "0" and "1") into a signal cor (NI) (1, 1) with the chip rate 1 and the bit width 1. This process is subsequently repeated stepwise via the correlators K ₃ to K _N -i with corresponding input signals cor from the preceding correlators and corresponding incoming and outgoing bit widths, O-sampling, spreading sequences and spreading sequence lengths and decisions in arrangements 2 until as input signal for the correlator K _N the signal cor2 (1, 1) with the chip rate 1 and the bit width 1 is available. This signal cor2 (1, 1) with the chip rate 1 and the bit width 1 made available by the correlator K _N -i is subsequently forwarded to the last correlator K _N according to FIG. 7b. The incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K _N. In the correlator K _N no oversampling of the signal to be processed takes place (oversampling = 1). Furthermore, the last despreading sequence s1 (first spreading sequence in the case of signal spreading) with the spreading sequence length n1 is used in the correlator K _N (compare correlator K ₂ according to FIG. 5). The output signal of the correlator K _N results in this way, after the correlation with the despreading sequence sl (compare correlator K _N according to Figure 5) to corl (1, bN) with the chip rate 1 and the outgoing bit width ld (nl-l) = bN ,

Subsequently, the output signal of the correlator K _{N is converted} in the following decision unit 2 (decision into logical bit values "0" and "1") into a signal corl (1, bN) with the chip rate 1 and the bit width bN. After this last decider 2, the chip clock is clocked down via the arrangement 1 to the original bit clock (compare arrangement 1 according to FIG. 5). As a result, there results an output signal d (k, 1) of the original bit rate k and the bit width 1 of the data signal to be transmitted. In this case, the sequence of down-clocking and decision after the last correlator K _{N is} again interchangeable, without this having an influence on the result of the arrangement according to FIG. 7b.

FIG. 7c shows the sequence of despreading of a spread data signal or chip signal by stepwise correlators, whereby after each partial correlator a decision is made in logical bit values "0" and "1" (successive decision) and after each partial correlator a downclocking of the output signal is carried out (successively Downclocking), so that the respective subsequent correlator, a non-overclocked chip data signal is supplied with IBit width. Here are the decision and the Down-clocking is interchangeable after each correlator in the order, without affecting the final signal provided to the subsequent correlator.

According to FIG. 7c, the received digital chip signal with the chip rate 1 is made available to the first correlator Ki with an incoming bit width b = bθ. The incoming and the outgoing chip clock or the chip rate are respectively 1 = 10 for the correlator Ki. In the correlator Ki, no oversampling of the signal to be processed takes place (over sampling = 1). The incoming bit rate is b = bθ. In correlator Ki, the first despreading sequence sN (last spreading sequence in the case of signal spreading) with the spreading sequence length nN is used (compare correlator Ki according to FIG. 5). The output signal of the correlator Ki results after correlation with the despreading sequence sN (compare correlator Ki according to FIG. 5) to corN (10, bl) with the chip rate 10 and the outgoing bit width ld (nN-bO) = bl.

This signal corN (10, bl) with the chip rate 1 generated by the correlator Ki is converted in the following arrangement 1 for down-sampling to a signal corN (II, bl) with the chip rate 10 / nN. In the following decision unit 2 (decision in logical bit values "0" and "1") this is

Signal corN (ll, bl) is converted into a signal corN (l, 1) with the chip rate 11 and the bit width 1 and subsequently forwarded to the second correlator K ₂ . The incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K _2. In the correlator K ₂ , no oversampling of the signal to be processed takes place (oversampling = D).

Furthermore, in the correlator K ₂ here the second depletion sequence s (NI) (penultimate spreading sequence in the signal spreading) with the spreading sequence length n (NI) is used (compare correlator K ₂ according to FIG. 5). The output signal of the correlator K ₂ results in this way according to the Kor- relation with the despreading sequence s (NI) (compare correlator K ₂ according to FIG. 5) to cor (NI) (11, b2) with the chip rate 11 and the outgoing bit width Id (n (NI) -1) = b2. This signal cor (NI) (11, b2) with the chip rate 1 generated by the correlator Ki is used in the following arrangement 1 for down-clocking into a signal cor (NI) (12, b2) with the chip rate 11 / n (NI ) transformed.

In the following decision unit 2 (decision in logical bit values "0" and "1"), this signal cor (N-1) (12, b2) in a signal cor (NI) (12, 1) with the chip rate 11 / n (NI) and the bit width 1 converted and subsequently forwarded to the third correlator K3. In this case, the sequence of down-clocking and decision after the correlator is in turn interchangeable, without this having an influence on the result of the arrangement according to FIG. 7c. The described process is subsequently performed stepwise via the correlators K ₃ to K _N - ₁ with corresponding input signals cor from the preceding correlators and corresponding incoming and outgoing chip rates, bit widths, oversampling,

Spreading sequences, spreading sequence lengths, downtuning in arrangements 1 and decisions in arrangements 2 are repeated until, as input signal for the correlator K _N, the signal cor2 (1 (n-1), 1) with the chip rate l (N-2) / (nl) and the bit width 1 is available.

This signal cor2 (l (nl), 1) provided by the correlator K _N - ₁ with the chip rate l (N-2) / (nl) and the bit width 1 is subsequently forwarded to the last correlator K _N according to FIG , The incoming and the outgoing chip clock or the chip rate are respectively 1 for the correlator K _N. In the correlator K _N no oversampling of the signal to be processed takes place (oversampling = 1). Furthermore, in correlator K _N, the last sequence of despreading s 1 (first spreading sequence in the case of signal spreading) with the spreading sequence length n _{1 is} used here (compare correlator K ₂ according to FIG. 5). The output signal of the correlator K _N results in this way after correlation with the despreading sequence sl (see correlator K _N according to Figure 5) to corl (1 (NI), bN) with the chip rate 1 and the outgoing bit width ld (nl-l ) = bN. This signal corl (1 (N-1), bN) generated by the correlator Ki at the chip rate 1 (NI) is converted in the following arrangement 1 for down-clocking into a signal corl (IN, bN) at the chip rate IN, this being Chip rate of the original bit rate k of the non-spread data signal corresponds. In the following decision unit 2 (decision in logical bit values "0" and "1"), this signal corl (lN, bN) is converted into a signal d (k, 1) with the bit rate k and the bit width 1.

The result is a desired output signal d (k, 1) corresponding to the original data signal with the original bit rate k and the bit width 1 of the data signal to be transmitted. In this case, the sequence of downclocking and decision after the last correlator K _{N is} again interchangeable, without this having an influence on the result of the arrangement according to FIG. 7c.

Starting from the exemplary embodiments for receiving correlators according to FIGS. 7a, 7b and 7c, two-stage embodiments of correlators (application of 2 spreading sequences to the data signal) for the cases concluding decision are subsequently converted into logical bit values "0" and "1" and final Down-clocking of the output signal or successive decision in logical bit values "0" and "1" and final down-clocking of the output signal described.

The embodiment of an exemplary two-stage correlator shown in FIG. 8 is suitable for the despreading of binary signals in the baseband after the signal demodulation. Another special feature of the embodiment illustrated in FIG. 8 is that two identical spreading sequences s (l)... S (n) of length n are used to spread the data signal to be transmitted. nals and for the receiver-side despreading be used in the correlator of Figure 8. The despreading further takes place using a final decision in logical bit values "0" and "1" and a final down-clocking of the output signal.

Figure 8 comprises n-1 delay elements Zi, i, Zi, 2, ..., Zi, _n _i each having a time delay z ^"1 and a summer Σi. Figure 8 further comprises n negated exclusive-or (negEXOR) arrangements negEXORi , i, negEXORi, 2 ••• negEXORi, _n and a SpeI ^¬ cherregisteranordnung 3 the length Id (n) bits. These components constitute the first stage of two-stage correlator shown in FIG 8. Further, includes the embodiment of Figure 8, n-1 delay elements Z ₂ , 1, Z ₂ , ₂ , ■■■, Z ₂ , _n _i, each with a time delay z ^{~ n} and n associated memory register arrangements S ₂ , i, S ₂ , 2, ..., S ₂ , _n the length Id (n) bit and a summer Σ _second Further, provided n negated exclusive or (negEXOR) arrangements negEXOR _2, i, negEXOR _2, _2, ..., negEXOR _2, _n and a memory register array 4 of the length ld (nn) bit and another negated exclusive-OR (negEXOR) arrangement 5. According to Figure 8, the binary received signal in the first Partial correlator with the spreading sequence s (l ... n) correlated.

In this case, the binary input signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-or (negEXORi, i) linked and the result is fed to the summer Σi, which delayed over the delay element Zi, 1 Input signal is negated with the value s (2) of the spreading sequence s (l ... n) Exclusive OR (negEXORi, ₂ ) linked and the result supplied to the summer Σi, via the delay element Zi, ₂ further delayed input signal is the value s (3) of the spreading sequence s (l ... n) negates exclusive-or (negEXORi, 3) and the result is fed to the summer Σi. These steps are repeated in the first Teilkorrelator according to Figure 8 until the all the n-1 delay elements Zi, 1, Zi, ₂ ... Zi, _n _i delayed binary input signal with the value of s (n) of the spreading sequence s (l. .. n) negated exclusive-or (negEXORi, _n ) is linked and also this result is supplied to the summer Σi. The Result of the summation of the individual signal components 1 to n of the n negated exclusive-or (negEXOR) arrangements negE-XORi, i, negEXORi, 2 ••• negEXORi, _n is stored in the Speicherregisteran ^¬ order 3 of length Id (n) bit.

Furthermore, according to FIG. 8, the result of the summation of the first partial correlator in the second partial correlator is in turn correlated with the spreading sequence s (l... N). For this purpose, the contents of the storage register arrangement 3 of the first Teilkorre- lators in the storage register arrangement S2, i of the second

Subcorrelator transmitted and from there the first delay Z ₂ , _l and the first negated exclusive-or (negEXOR) arrangements negEXOR2, i provided for further processing. In this case, the binary signal with the value s (l) of the spreading sequence s (l... N) is negated exclusive-or (negE

XOR ₂ , i) and the result is fed to the summer Σ ₂ , the signal delayed by the delay element Z ₂ , ₁ is transmitted to the storage register arrangement S ₂ , ₂ and is multiplied by the value s (2) of the spreading sequence s (l .. n) negates exclusive-OR (negEXOR ₂ , ₂ ) linked and the result supplied to the summer Σi, via the delay element Z ₂ , ₂ further delayed signal is transmitted to the storage register arrangement S ₂ , ₃ and from there with the value s (3) the spreading sequence s (l... N) negates exclusive-or (negEXORi, 3) and the result is fed to the summer Σ ₂ .

These steps are repeated in the second partial correlator according to FIG. 8 until the binary signal with the value s (n) delayed over all n-1 delay elements Z ₂ , 1, Z ₂ , 2,..., Z ₂ , _n -i the spreading sequence s (l ... n) negated exclusive-or (negEXOR ₂ , _n ) is linked and this result is the summer Σ _{2 is} supplied. The result of the summation of the individual signal components 1 to n of the n negated exclusive-OR (negEXOR) arrangements negEXOR ₂ , i, negEXOR ₂ , ₂ ,..., NegEXOR ₂ , _n becomes in the memory register arrangement 4 of length ld (nn) bits stored. With the aid of the negated exclusive-OR (negEXOR) arrangement 5, finally, in the second partial correlator according to FIG. 8, a final decision is made in logical bit values "0" and The necessary down-sampling to the original bit clock of the data signal takes place subsequently (not shown in FIG. 8), as shown in the embodiments of correlators described above. In the case of a successive down-sampling, the corresponding reduction of the chip rate by the preceding partial spreading factor would have to be inserted into the embodiment according to FIG. 8 (compare, for example, FIGS. 7a and 7c).

In this case, the possible embodiments of a two-stage correlator according to FIG. 8 differ for the cases of final down-clocking or successive down-clocking (downsampling after each sub-stage) with regard to the number of components required for implementation, such as delay elements. FIG. 9 shows a tabulation of the components required for a two-stage correlator according to FIG. 8 for the two mentioned embodiments of the down-clocking with final decision in binary values (logic values "0" and "1") the two embodiments differ only in the number of delay elements (z ^"1 ) required for the realization.

For a two-stage correlator with a spreading factor m = nn is the number of delay elements (z ^"1) for an embodiment with a final down-sampler (n-1) ^• 1 + n ^• Id (n)) and in the embodiment with successive down-sampler (n- 1) • (l + ld (n)) The number of logic elements required for the two-stage correlator according to FIG. 8 (neg EXOR) is n • (1 + ld (n)) +1 in both cases, the number of required The storage register for the spreading sequence s (l ... n) is n and the summer Σi adds over a width of n bits, the summer Σ2 adds bits over a width of n-ld (n). FIG. 10 shows an embodiment of a two-stage correlator for the case of the successive decision in binary logic values "0" and "1" after each sub-stage of the correlator. Figure 10 comprises n-1 delay elements Zi, i, Zi, 2, ..., Zi, _n _i each having a time delay z ^"1 and a summer Σi. Figure 10 further comprises n negated exclusive-or (negEXOR) arrangements negEXORi , i, negEXORi, _2, ■■■, negEXORi, _n and a SpeI ^¬ cherregisteranordnung 3 the length Id (n) bits. These components constitute the first stage of two-stage correlator shown in FIG 10. Furthermore, comprising the embodiment of Figure 10 n- 1 delay elements Z ₂ , 1, Z ₂ , ₂ , ..., Z ₂ , _n _i, each having a time delay z ^{~ n} and a summer Σ _2. The exemplary embodiment according to Figure 10 furthermore comprises n negated exclusive-OR (negEXOR) arrangements negEXOR ₂ , i, negEXOR ₂ , ₂ , ..., negEXOR ₂ , _n and a memory register arrangement 4 of length

Id (n) bit and two further negated exclusive-or (negEXOR) arrangements 5 and 6.

According to FIG. 10, the binary received signal in the first partial correlator is correlated with the spreading sequence s (l... N). In this case, the binary input signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-or (negEXORi, i) linked and fed the result to the summer Σi; the delayed via the delay element Zi, 1 input signal with the value s (2) of the spreading sequence s (l ... n) negated exclusive-or (negEXORi, ₂ ) linked and fed the result to the summer Σi; the input signal with the value s (3) of the spreading sequence s (l... n) further negated via the delay element Zi, ₂ negates the exclusive-or (negEXORi, 3) and supplies the result to the summer Σi.

These steps are repeated in the first partial correlator according to FIG. 10 until the binary input signal delayed by all the n-1 delay elements Zi, 1, Zi, 2,..., Zi, _n -i has the value s (n) of the spreading sequence s (l ... n) negated exclusive-or (ne- gEXORi, _n ) is linked and this result is fed to the summer Σi. The result of the summation of the individual signal components 1 to n of the n negated exclusive-or (n gEXOR) arrangements negEXORi, i, negEXORi, ₂ , ..., negEXORi, _n are stored in the memory register arrangement 3 of length Id (n) bits.

Subsequently, using the negated exclusive-OR (negEXOR) arrangement 5, before deciding the output signal of the first partial correlator to the second partial correlator, a decision is made in binary logic values "0" and "1" (successive decision in binary values). As a result, the despreading with the aid of the second spreading sequence in the second partial correlator is simplified (cf. FIG. 8). Furthermore, according to FIG. 10, the result of the summation of the first partial correlator and of the decision in binary values in the second partial correlator is in turn correlated with the spreading sequence s (1... N).

In this case, the binary signal with the value s (l) of the spreading sequence s (l ... n) is negated exclusive-OR (negEXOR2, i) linked and the result is fed to the summer Σ ₂ , via the delay element Z ₂ , i delayed signal is negated with the value s (2) of the spreading sequence s (l ... n) exclusive-or (negEXOR2,2) ver ^¬ ties and the result to the summer Σi fed, via the delay element Z ₂ , ₂ on delayed signal is negated with the value s (3) of the spreading sequence s (l ... n) exclusive-or (negEXORi, 3) and the result is fed to the summer Σ ₂ . These steps are repeated in the second partial correlator according to FIG. 10 until the binary signal with the value s (n) delayed over all n-1 delay elements Z ₂ , 1, Z ₂ , 2,..., Z ₂ , _n -i the spreading sequence s (l ... n) is negated exclusive-or (negEXOR ₂ , _n ) is linked and also this result is supplied to the summator Σ ₂ .

The result of the summation of the individual signal components 1 to n of the n negated exclusive-OR (negEXOR) arrangements negEXOR ₂ , i, negEXOR ₂ , ₂ ... NegEXOR ₂ , _n is stored in the memory register arrangement 4 of length Id (n). Bit stored. Finally, with the aid of the negated exclusive-OR (negEXOR) arrangement 6, in the second partial correlator according to FIG. 10, a decision is made in logical bit values "0" and "1", where This signal is still present in the chip clock (chips). The necessary down-clocking to the original bit clock of the data signal takes place subsequently (not shown in FIG. 10), as shown in the exemplary embodiment of correlators described above. In the case of a successive down-sampling, the corresponding reduction of the chip rate by the previous partial spreading factor would have to be inserted into the embodiment according to FIG. 10 (compare, for example, FIGS. 7a and 7c).

In this case, the possible exemplary embodiments of a two-stage correlator according to FIG. 10 again differ for the cases of final down-clocking or successive down-sampling (downsampling after each partial stage) with regard to the number of components required for the implementation, such as delay elements. FIG. 11 shows a tabulation of the components required for a two-stage correlator according to FIG. 10 for the two mentioned embodiments of the downclocking with successive decision in binary values (logic values "0" and "1").

11 that the two embodiments again differ in the number of delay elements (z ^"1 ) required for the realization, for a two-stage correlator with a spreading factor m = nn the number of delay elements (z ^{" 1} ) is for an embodiment with final down-clocking (n ² -1) and for an embodiment with successive down-clocking 2- (n-1). The number of logic elements required for the two-stage correlator according to FIG. 10 (neg EXOR) is 2-n + 2 in both cases, the number of required storage registers for the spreading sequence s (l... N) is n and both Summer Σi as well as summer Σ2 each add over a width of n bits.

This results in the two-stage correlators according to Figures 8 and 10, each with two spreading sequences s (l ... n) in view of the number of required for the realization Components (components) significant simplifications compared to a conventional single-stage correlator with a spreading factor of length m (m = nn) with the same effect. The differences in the number of component components respectively required for these embodiments are shown in general form in FIG. In this case, the illustrated numbers of components for two-stage correlators of the embodiments with successive and final decision in the binary values "0" and "l ^λ \ respectively for the cases of the final or successive down-clocking correspond to the calculation rules known from Figures 9 and 11. In comparison thereto the number of component components necessary to implement a conventional (one-stage) correlator with spreading factor m is shown in the second column of Figure 12. For a conventional correlator with a spreading factor m, the number of delay elements is (m-1) The number of logic elements required (neg EXOR) is (m + 1), the number of required storage registers for the spreading sequence s (l ... m) is m and the (single) totalizer adds over a width of m bits.

FIG. 13 shows the values for the components, as they are shown by way of example, when an expansion sequence length of m = 225 is selected for the conventional correlator, from which for the two-stage correlators according to FIGS. 8 and 10 two spreading sequences s (l .. n) of length n = 15 (m = nn = 225). As can be seen from FIG. 13, the number of delay elements for a conventional correlator (with a spreading factor of m = 225) is 224. The number of required logic elements (neg. EXOR) is 226, the number of required storage registers for the spreading sequence s (l ... m) is 225 and the (single) summer must be designed for addition over a width of 225 bits.

In comparison, a two-stage correlator using two spreading sequences s (l... N) of length 15 according to FIG. 13 in the case of a final decision in binary mode requires values "0" and "1" (see FIG. 8) and, in the event of a final down-clocking, 854 delay elements, 76 logic elements (neg. EXOR), 15 memory registers and two summers, each once across the width of 15 bits or 60 bits. The same two-stage correlator requires only 70 delay elements to implement in the case of a final decision in binary values "0" and "1" and, in the case of a successive down-clocking, again 76 logic elements (neg. EXOR), 15 memory registers and two summers the width of 15 bits or 60 bits.

In comparison, a two-stage correlator using two spreading sequences s (l... N) of length 15 according to FIG. 13 in the case of a successive decision requires binary values "0" and "1" (see FIG Case of a final down-clocking 225 delay elements, 32 logic elements (neg EXOR), 15 memory registers and two summers across the width of 15 bits each. The same two-stage correlator requires only 28 delay elements, again 32 logic elements (neg. EXOR), 15 memory registers and two summers, once in the event of a successive decision in binary values "0" and "1" and in the case of a successive down-clocking the width of 15 bits or 60 bits.

It can be seen from the table of exemplary embodiments in FIG. 13 that for a two-stage correlator both in the case of the final and the successive decision in binary values "0" and "1", a significant saving of logic elements compared to a conventional single-stage correlator, Memory registers and in the addition width results. The necessary number of delay elements differs considerably for the cases of final and successive down-clocking. In the case of the final decision in binary values "0" and "1", there is a saving only for the embodiment using the successive down-clocking to delay elements over the embodiment of a conventional correlator.

A considerable saving in the number of components is obtained according to FIG. 13, for example for a two-stage correlator with a successive decision in binary values "0" and "1" and successive down-clocking. In this case, such a savings potential compared to a conventional correlator does not relate solely to the number of required modules, such as delay elements, logic elements and memory registers, but as a result also to the power savings for operating such an inventive arrangement or, for example, the processing speed.

The embodiments shown form only a small part of a variety of implementation options. The despreading of the signals does not have to take place, as shown by way of example, in the baseband after demodulation. A despreading can be carried out in a corresponding manner in every other subarea of a receiver, for example also before the demodulation at the intermediate frequency or high frequency level. Furthermore, any other spreading sequences which satisfy the required autocorrelation properties can be used. It is not necessary to use identical spreading sequences of the same length for spreading or despreading the data signals in multistage correlators, as shown in the examples. The resolution of 1 bit in the data signal shown here by way of example is also not defined, so that any resolution and processing bandwidths can be used.

The trade-off that the use of two equal (concatenated) spreading sequences entails is a deterioration in the quality of the autocorrelation function. this has

Effects on the spectral properties of the spread signal and may have implementation-dependent disadvantages, especially in the synchronization. Figure 14 shows the autocorrelation function of a simple, 511-bit PRBS-9 spreading sequence, which has optimum despreading characteristics with respect to a noisy message channel. In the upper diagram, FIG. 14 shows the autocorrelation function over a range of bit positions from 0 to 1000 (abscissa). The strongly pronounced maximum of the correspondences of the autocorrelation (ordinate) at bit position 511 is very clear. In the remaining range, the values of the autocorrelation function are at zero, as well as from the spread representation in FIG

14, where the abscissa covers a range from bit position 350 to bit position 550.

Figure 15 shows the autocorrelation function of a two-fold, 15-bit long (15x15) ZigBee spreading sequence, which does not have optimal despreading characteristics with respect to a noisy message channel. In the upper diagram, FIG. 15 shows the autocorrelation function over a range of bit positions from 0 to 450 (abscissa). Again, a very pronounced maximum of the matches of the autocorrelation (ordinate) at bit position 225 (effective spreading sequence length of the two-fold spreading amounts to 15-15 = 225) is very clear. In the remaining area, the values of the autocorrelation function are no longer consistently at zero, but have multiple small peaks (deterioration of the autocorrelation).

At the same time, however, it can be stated that these peaks still have a significantly lower amplitude in relation to the pronounced maximum at bit position 225, as well as from the spread representation in FIG

15, where the abscissa covers a range from bit position 200 to bit position 250.

For the optimization of the autocorrelation properties, the use of suitable non-identical subsequences offers a variety of possibilities.

Claims

claims

A method for despreading a received spread spectrum signal (c), wherein the despreading occurs in at least two stages, each stage comprising the step of:

Generating a correlator signal by correlating a spread spectrum signal (c, corN, ..., cor2) with a spreading sequence (sN, ..., sl),

and wherein at least one stage comprises the following steps:

Decimating the correlator signal (corN, cor (N-I), ..., corl) by a factor corresponding to the length of the spreading sequence (sN, ..., sl), and / or

Decide on the basis of the correlator signal whether a certain symbol has been received.

2. The method of claim 1, wherein only in the last stage, a decimation step takes place.

3. The method of claim 1, wherein a decimation step takes place in each stage.

4. The method according to any one of claims 1 to 3, wherein only in the last stage, a decision step takes place.

5. The method according to any one of claims 1 to 3, wherein in each stage a decision step takes place.

6. The method according to any one of claims 1 to 5, wherein in each stage different spreading sequences (sN, s (N-

1), ..., sl) are used.

7. The method according to any one of claims 1 to 5, wherein in each stage, the same spreading sequences (sN = s (N-I) = ... = sl) are used.

8. An apparatus for despreading a received spread spectrum signal (c) in at least two stages, each stage

a correlator for correlating a spread spectrum signal (c, corN, ..., cor2) with a spreading sequence (sN, ..., sl) and wherein at least one stage

a decimator (1) for decimating the correlator signal (corN, cor (N-I), ..., corl) by a factor corresponding to the length of the spreading sequence (sN, ..., sl), and / or

a decision maker (2) adapted to decide, based on the correlator signal, whether a particular symbol has been received.

9. Apparatus according to claim 8, wherein only the last stage comprises a decimator (1).

10. Apparatus according to claim 8, wherein each stage comprises a decimator (1).

11. Device according to one of claims 8 to 10, wherein only the last stage comprises a decision maker (2).

12. Device according to one of claims 8 to 10, wherein each stage comprises a decision maker (2).

13. Method for spreading the spectrum of a to be transmitted

Signal to obtain a spread spectrum signal in which the spreading occurs in multiple stages and each stage comprises at least the following steps: Combining an input signal with a spreading sequence (sN, s (NI), ..., sl).

14. The method of claim 13, wherein in each stage different spreading sequences (sN, s (N-I), ..., sl) are used.

15. The method of claim 13, wherein in each stage, the same spreading sequences (sN = s (N-I) = ... = sl) are used.

16. The method of claim 1 to 7, wherein the synchronization for the decimation based on only one or not all spreading sequences (sl ... sN) is carried out.