WO2008093963A1 - Method and system for controlling of peripherals - Google Patents

Abstract

A peripheral device control system and a peripheral device control method are provided. The peripheral device control system includes: a peripheral device controller generating a connection-alarming interrupt when a peripheral device is connected thereto; a first processor including a processor core connected directly to the peripheral device controller; and a path setting unit setting a connection path for connecting the peripheral device controller to one of the processor core and a second processor with reference to a predetermined value when the connection-alarming interrupt is input from the peripheral device controller. Here, the second processor communicates with the first processor and the peripheral device controller is controlled directly by one of the processor core and the second processor in which the connection path is set. Regardless of the operation of the application processor, it is possible to allow the host processor to directly control a USB device connected to a USB controller.

Description

Description

METHOD AND SYSTEM FOR CONTROLLING OF PERIPHERALS

Technical Field

[1] The present invention relates to data communication, and more particularly, to peripheral device control method and system that can allow a host processor to directly control bidirectional communication with an application processor and to communicate data with a peripheral device connected to the application processor.

[2]

Background Art

[3] With the development of information communication technologies, various electronic devices (such as portable terminals) are provided with one or more application processors performing various multimedia functions as well as a host processor performing an inherent function (such as a communication function). In general, the applicationprocessors include functional blocks that can make specific communications (such as USB communication, infrared communication, and Bluetooth), unlike the host processor. However, the functional blocks of the specific communications are disposed in the application processors and thus it is difficult for the host processor to use the functional blocks.

[4] Fig. 1 is a block diagram illustrating a system that can transmit and receive data through a USB controller disposed in the application processors.

[5] A method of allowing a host processor communicating with an applicationprocessor having a peripheral device controller therein to transmit data to an external peripheral device (such as a large-capacity storage medium and a multimedia player as the USB device) through the peripheral device controller will be described with reference to Fig. 1. Hereinafter, for the purpose of convenient explanation and understanding, it is assumed that the peripheral device controller is a USB controller and the peripheral device connected to the peripheral device controller is a USB device.

[6] The host processor 110 serves as a core processor of an arbitrary device (such as a portable terminal and a personal computer) and performs a control function of performing a control operation and of supplying power to inner elements thereof. For example, the host processor 110 of a portable terminal may be a baseband processor and the host processor 110 of a personal computer may be a central processing unit (CPU).

[7] As shown in Fig. 1, the application processor 120 includes an AP core 122 and a

USB controller 124 for connection an external USB device. When an external USB device is connected to the USB controller 124, the USB controller 124 outputs a predetermined interrupt (hereinafter, referred to as "connection-alarming interrupt" for the purpose of convenient explanation and understanding) to the AP core 122. That is, the AP core 122 can recognize that the external USB device is connected to the USB controller 124, by receiving and analyzing the connection-alarming interrupt from the USB controller 124. The USB controller 124 can recognize the connection of the USB device by means of a voltage difference generated when the external USB device is connected thereto. This is obvious to those skilled in the art and thus detailed description thereof is omitted.

[8] When the connection of the USB device is recognized by the connection- alarming interrupt, the AP core 122 performs a predetermined USB enumeration on the connected USB device. That is, the AP core 122 can assign an address to the USB device and can acquire and set a device descriptor, a configuration descriptor, an interface descriptor, a string descriptor corresponding to the maker and the device, and the like. The enumeration is obvious to those skilled in the art and thus particular description thereof is omitted. Here, the AP core 122 and the USB device connected to the USB controller 124 can communicate with each other using a predetermined USB protocol (such as a UMS (USB Mass Storage) and an MTP (Multimedia Transfer Protocol)).

[9] When the enumeration is completed, the AP core 122 can transmit and receive control signals and data to and from the connected USB device through the USB controller 124. In this way, since the USB device is connected directly to the applica- tionprocessor 120, the host processor 110 should transmit and receive control signals and data to and from the USB device by way of the application processor 120.

[10] For example, when the host processor 110 should record or read data in and from the USB device, there is a problem that the host processor 110 should transmit a command for transmitting the control signals or data to the connected USB device through the application processor 120.

[11] When the application processor 120 does not work, there is another problem that the host processor 110 cannot use the peripheral device such as the connected USB device.

[12] Since the host processor 110 is coupled to the application processor 120 through an

8-bit or 16-bit data bus, there is another problem that the host processor 120 cannot control a peripheral device controlled by 16-bit or more data.

[13] With the improvement in performance of terminals, there is a need for a high-rate data transmission to peripheral devices. Accordingly, the AP core 122 is connected to the peripheral device controller 124 through a 32-bit data bus. However, since the host processor 110 is configured to transmit and receive data and control signals through the 8-bit or 16-bit data bus, there is still another problem that the host processor 110 cannot control a high-performance peripheral device connected to the application processor 120.

[14]

Disclosure of Invention Technical Problem

[15] Therefore, an object of the invention is to provide peripheral device control method and system that can allow a host processor to directly control a peripheral device connected to a peripheral device controller connected to or disposed in an application processor regardless of an operation of the application processor.

[16] Another object of the invention is to provide peripheral device control method and system that can allow a host processor to directly control a peripheral device connected to a peripheral device controller connected to or disposed in an application processor and to transmit and receive data to and from the peripheral device without including a particular peripheral device controller.

[17] Another object of the invention is to provide peripheral device control method and system that can allow a host processor and an application processor to control and use a peripheral device controller connected to or disposed in the application processor.

[18] Another object of the invention is to provide peripheral device control method and system that can reduce the cost for manufacturing an application processor because the application process need not include a memory storing programs used to control a peripheral device controller.

[19] Another object of the invention is to provide peripheral device control method and system that can allow a host processor to directly control a high-performance peripheral device connected to an application processor.

[20] Another object of the invention is to provide peripheral device control method and system that can allow a host processor to transmit and receive data to and from a high- performance peripheral device connected to an application processor without changing the host processor.

[21] Other objects of the invention will be easily understood from the following description.

[22]

Technical Solution

[23] According to an aspect of the invention, there is provided a peripheral device control system that can allow a second processor to transmit and receive data througha peripheral device controller directly connected to a processor core included in a first processor. [24] According to an embodiment of the invention, there is provided a peripheral device control system including: a peripheral device controller generating a connection- alarming interrupt when a peripheral device is connected thereto; a first processor including a processor core connected directly to the peripheral device controller; and a path setting unit setting a connection path for connecting the peripheral device controller to one of the processor core and a second processor with reference to a predetermined value when the connection-alarming interrupt is input from the peripheral device controller. Here, the second processor may communicate with the firstprocessor and the peripheral device controller may be controlled directly by one of the processor core and the second processor in which the connection path is set.

[25] On the other hand, the peripheral device controller may be disposed in the first processor.

[26] The path setting unit may set a first connection path for connecting the second processor to the peripheral device controller when the predetermined value is a first set value, may set a second connection path for connecting the processor core to the peripheral device controller when the predetermined value is a second set value, and may output the connection-alarming interrupt to one of the first and second connection paths.

[27] Here, when the first connection path is set and the connection- alarming interrupt is input by the path setting unit, the second processor directly may control the peripheral device controller through the first connection path to transmit and receive data to and from the peripheral device. The second processor may include a driver which is a set of control commands for controlling the peripheral device controller and an application which is a set of commands for transmitting and receiving data to and from the peripheral device connected to the peripheral device controller.

[28] On the otherhand, when the second connection path is set and the connection- alarming interrupt is input by the path setting unit, the processor core may directly control the peripheral device controller through the second connection path.

[29] Here, the second processor may set a command line to the processor core to transmit and receive data to and from the peripheral device and then may transmit and receive data to and from the peripheral device through the processor core. The processor core may include a driver which is a set of control commands for controlling the peripheral device controller and the second processor may include an application which is a set of commands for transmitting and receiving data to and from the peripheral device connected to the peripheral device controller.

[30] According to another embodiment of the invention, there is provided a peripheral device control system including: a peripheral device controller connected to a peripheral device; a first processor that is connected directly to the peripheral device controller and that includes a data processing unit and a processor core; and a second processor communicating with the processor core. Here, when a control signal is input from one of the second processor and the processor core, the data processing unit may compare data transmission capability of the peripheral device controller with data transmission capability of one of the second processor and the processor core and processes and outputs data by a predetermined method, and the processor may be one of the second processor and the processor core.

[31] The peripheral device controller may be disposed in the first processor.

[32] The data transmission capability may be the number of bits simultaneously transmitted in a clock period, and the clock period may be a time for acquiring effective data.

[33] When the data transmission capabilities are equal to each other, the data processing unit may output the data without being processed.

[34] When the data transmission capabilities are not equal to each other, the data processing unit may receive recording data from the second processor for n (where n is a natural number) clock periods in accordance with the control signals for recording data input from the second processor, may convert the input recording data into m-bit (where m is a natural number) corresponding to the data transmission capability of the peripheral device controller, and may output the m-bit data to the peripheral device controller.

[35] On the other hand, when the data transmission capabilities are not equalto each other, the data processing unit may divide m-bit (where m is a natural number) data input from the peripheral device control in the unit of n bits (where n is a natural number) corresponding to the data transmission capability of the second processor in accordance with the control signals for reading data input from the second processor and may sequentially outputs the n-bit data to the second processor.

[36] According to another aspect of the invention, there is provided a method of allowing an external second processor to control a peripheral device connected thereto through a peripheral device controller connected directly to a processor core of a first processor.

[37] The method includes the steps of: allowing the peripheral device controller to generate a connection-alarming interrupt with the connection of the peripheral device; allowing a path setting unit to set a connection path for connecting one of the second processor and the processor core to the peripheral device controller with reference to a predetermined value with the inputof the connection- alarming interrupt; and allowing one of the processor and the processor core in which the connection path is set to directly control the peripheral device controller through the connection path.

[38] The step of allowing the path setting unit to set the connection path for connecting one of the second processor and the processor core to the peripheral device controller includes the steps of: allowing the path setting unit to set a first connection path between the second processor and the peripheral device controller when the set value is a first set value; allowing the path setting unit to set a second connection path between the processor core and the peripheral device controller; and outputting the connection- alarming interrupt through one of the first connection path and the second connection path.

[39] The step of directly controlling the peripheral device controller when the first connection path is set includes the steps of: allowing the second processor to directly control the peripheral device controller through the first connection path when the connection-alarming interrupt is input through the first connection path; and allowing the second processor to transmit and receive data to and from the peripheral device controller through the first connection path.

[40] The step of directly controlling the peripheral device controller when the second connection path is set includes the steps of: allowing the processor core to directly control the peripheral device controller through the second connection path when the connection-alarming interrupt is input through the second connection path; allowing the second processor to set a command line to the processor core so as to transmit and receive data to and from the peripheral device; and allowing the second processor to transmit and receive data to and from the peripheral device controller through the set command line and the processor core.

[41] According to another embodiment of the invention, there is provided a method of allowing an external second processor to control a peripheral device connected thereto through a peripheral device controller connected directly to a processor core of a first processor, the method including the steps of: allowing a data processing unit to receive data from a processor; allowing the data processing unit to compare data transmission capability of the processor with data transmission capability of the peripheral device controller; and allowing the data processing unit to process and output the input data by a predetermined method in accordance with the comparison result. Here, the processor may be one of the second processor and the processor core.

[42] The data transmission capability may be the number of bits simultaneously transmitted in a clock period, and the clock period may be a time for acquiring effective data.

[43] When the data transmission capabilities are equal to each other, the data processing unit may output the input data without being processed.

[44] When the data transmission capabilities are not equal to each other, the step of allowing the data processing unit to process and output the input data in accordance with the comparison result may include the steps of: receiving recording data from the second processor for n (where n is a natural number) clock periods in accordance with the control signal for recording data input from the second processor; converting the input recording data into m-bit (where m is a natural number) corresponding to the data transmission capability of the peripheral device controller; and outputting the converted data to the peripheral device controller.

[45] When the data transmission capabilities are not equal to each other, the step of allowing the data processing unit to process and output the input data in accordance with the comparison result may include the steps of: dividing m-bit (where m is a natural number) data input from the peripheral device control in the unit of n bits (where n is a natural number) corresponding to the data transmission capability of the second processor in accordance with the control signals for reading data input from the second processor; and sequentially outputting the divided data to the second processor.

[46]

Brief Description of the Drawings

[47] Fig. 1 is a block diagram illustrating a system that can allow data to be transmitted and received through a USB controlled of a conventional application processor.

[48] Fig. 2 is a block diagram illustrating a system that can allow a host processor to transmit and receive data through a USB controller of an application processor according to an embodiment of the invention.

[49] Fig. 3 is a flowchart illustrating a method of allowing a host processor to control a

USB controller of an application processor according to an embodiment of the invention.

[50] Fig. 4 is a block diagram illustrating a system that can allow a host processor to transmit and receive data through a USB controller of an application processor according to an embodiment of the invention.

[51] Fig. 5 is a functional block diagram illustrating of a data processing unit according to an embodiment of the invention.

[52] Fig. 6 is a flowchart illustrating a method of allowing a host processor to transmit data to a connected peripheral device through a peripheral device controller of an application processor according to an embodiment of the invention.

[53] Fig. 7 is a flowchart illustrating a method of allowing an application processor to read data from a peripheral device and to output the read data to a host processor according to an embodiment of the invention.

[54]

Mode for the Invention

[55] The objects, features, and advantages set forth above will become more apparent through the following detailed descriptions provided with reference to the ac- companying drawings.

[56] As the present invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in drawings and described in detail in the written description. However, this is not intended to limit the present invention to particular modes of practice, and it is to be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the present invention are encompassed in the present invention. In the description of the present invention, certain detailed explanations of related art are omitted when it is deemed that they may unnecessarily obscure the essence of the present invention.

[57] While such terms as "first" and "second,"etc, may be used to describe various elements, such elements must not be limited to the above terms. The above terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of rights of the present invention, and likewise a second element may be referred to as a first element. The term "and/or" encompasses both combinations of the multiplerelated items disclosed and any one item from among the multiple related items disclosed.

[58] When an element is mentioned to be "connected to" or "accessing" another element, this may mean that it is directly formed on or stacked on the other element, but it is to be understood that another element may exist in-between. On the other hand, when an element is mentioned to be "directly connected to" or "directly accessing" another element, it is to be understood that there are no other elements in-between.

[59] The terms used in the present disclosureare merely used to describe particular embodiments, and are not intended to limit the present invention. An expression used in the singular encompasses the expression of the plural, unless it has a clearly different meaning in the context. In the present application, it is to be understood that the terms such as "including" or "having, "etc., are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the specification, and are not intended to preclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof may exist or may be added.

[60] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meanings as those generally understood by those with ordinary knowledge in the field of art to which the present invention belongs. Such terms as those defined in a generally used dictionary are to be interpreted to have the meanings equal to the contextual meanings in the relevant field of art, and are not to be interpreted to have ideal or excessively formal meanings unless clearly defined in the present application.

[61] Hereinafter, exemplary embodiments of the invention will be described in detail with reference to the accompanying drawings. Like or corresponding elements are denoted by like reference numerals regardless of the drawing number and repeated description thereof is omitted.

[62] In the following description, a processor including a processor core connected directly to the peripheral device controller is a first processor and a processor intending to directly control a peripheral device controller connected directly to the processor cor e of the first processor is a second processor. The peripheral device controller may be disposed in the first processor.

[63] In the following description, it is assumed that the peripheral device controller disposed in the first processor is a USB controller and a peripheral device connected to the peripheral device controller is a USB device (such as a memory and an MP3 player).

[64] It is also assumed that the peripheral device controller connected directly to the processor core of the first processor is a device being able to transmit and receive data at a high speed and the second processor does not include the peripheral device controller being able to transmit and receive data at a high speed.

[65] For the purpose of convenient understanding and explanation, it is assumed that the first processor is an application processor, the processor core is an AP (Application Processor) core, the second processor is a host processor, and the peripheral device controller is disposed in the application processor as the first processor, but the invention is not limited to the assumption.

[66] Fig. 2 is a block diagram illustrating a system that can allow a host processor to transmit and receive data through a USB controller of an application processor according to an embodiment of the invention. Hereinafter, it will be described that the host processor 210 may or may not include a USB controller and the host processor 210 controls a USB controller 224 disposed in the application processor 220 so as to a USB device connected to the USB controller 224.

[67] Referring to Fig. 2, the system according to the inventionincludes a host processor

210, an application processor 220, and a path setting unit 230.

[68] The host processor 210 serves as a baseband processor of a portable terminal or a central processing unit (CPU) of a personal computer. That is, the host processor 210 serves to control internal elements of a device and to control or instruct operations of the elements.

[69] The host processor 210 includes a driver and an application required for performing the control of the USB controller disposed in the application processor 220 and data communication therewith.

[70] In the following description, the driver is defined as a set of control commands for controlling the USB controller 224 of the application processor 220. The applicationis defined as a set of commands for transmitting and receiving data to and from the USB device through the USB controller 224 by the use of UMS or MTP.

[71] For example, the driver may include control commands for enumeration of the USB device connected to the USB controller 224. Since a method of actually embodying the driver and the application to perform the corresponding operations is obvious to those skilled in the art, description thereof is omitted.

[72] The host processor 220 may include both the application and the driver or only the application depending on the embodying method.

[73] When the host processor includes both the application and the driver and the path setting unit 230 sets a connection path to the USB controller 224, the host processor 210 is connected to the USB controller 224 of the applicationprocessor 220 through the connection path to control the USB controller 224. The host processor 210 can transmit and receive data to and from the USB device connected to the USB controller 224.

[74] However, when the host processor 210 includes only the application, the connection path is not set between the host processor 210 and the USB controller 224 of the application processor 220 andthus the host processor cannot directly control the USB controller 224. In this case, the host processor 210 can set a command line for transmitting and receiving data to the application processor 220 and transmit and receive data to and from the USB device through the USB controller 224 of the application processor 220.

[75] In this way, by particularly disposing only the application in the host processor 210, a particular memory for installing the application may not be disposed in the application processor 220. In this case, since an expensive particular memory may not be disposed, it is possible to reduce the chip size of the application processor 220 and to reduce the manufacturing cost.

[76] The host processor 210 may include or may not include a built-in USB controller

224, but it is assumed for the purpose of convenient understanding and explanation that the built-in USB controller 224 is not provided.

[77] As shown in Fig. 2, the application processor 220 includes the AP core 222 and the

USB controller 224.

[78] Whenan external USB device is connected to the USB controller 224, the USB controller 224 generates and transmits a predetermined interrupt (referred to as "connection- alarming interrupt" for the purpose of convenient and explanation) to the path setting unit 230.

[79] The AP core 222 serves to perform a predetermined operation of the application processor 220 or to control internal functional blocks. For example, the AP core 222 can perform functions embodied in advance to operate in the application processor 220or control the elements to perform the functions. When the driver is provided, the AP core 222 is connected to the USB controller 224 and serves to receive one or more interrupts from the USB controller 224 to control the USB controller 224.

[80] The USB controller 224 is connected to the USB device to generate one or more predetermined interrupts for an operation of the USB device. Since this is obvious to those skilled in the art, description thereof is omitted.

[81] When receiving the connection-alarming interrupt from the USB controller 224, the path setting unit 230 serves to set a connection path between the USB controller 224 and one of the host processor 210 and the AP core 222 with reference to a predetermined value. The path setting unit 230 outputs the connection-alarming interrupt receivingfrom the USB controller 224 to one of the AP core 222 and the host processor 210 connected to the set connection path.

[82] Here, the set value is set to a first set value when both the driver and the application are disposed in the host processor 210 and to a second set value when only the application is disposed in the host processor 210 (that is, when the driver is disposed in the application processor 220).

[83] In an embodiment, it is assumed that both the driver and the application are disposed in the host processor 210. When a USB device is connected to the USB controller 224 of the application processor 220, the USB controller 224 generates and transmits the connection-alarming interrupt to the path setting unit 230. The path setting unit 230 analyzes the set value in response to the input connection-alarming interrupt. Since the analyzed set value is the first set value, the path setting unit 230 sets a connection path for connecting the host processor 210 and the USBcontroller 224 to each other. In order to notify the setting of the connection path, the path setting unit 230 outputs the connection- alarming interrupt input from the USB controller 224 to the host processor 210. Accordingly, the host processor 210 canrecognize the connection of the USB device to the USB controller 224 and recognize the setting of the connection path to the USB controller 224.

[84] The host processor 210 can perform a predetermined enumeration operation using the driver and directly controlthe USB controller 224 through the set connection path to transmit and receive data to and from the USB device connected to the USB controller 224.

[85] That is, when both the driver and the application are disposed in the host processor

210, the host processor 210 can directly control the USB controller 224 without using the AP core 222 of the application processor 220. In this case, it is possible to control the USB controller 224 without driving the application processor 220. Of course, power should be continuously supplied to the USB controller 224.

[86] In another embodiment, it is assumed that the host processor 210 includes only the application and the driver is disposed in the application processor 220. In this case, the set value of the path setting unit 230 is the second set value as described above. When a USB device is connected to the USB controller 224 of the application processor 220, the USB controller 224 generates and transmits connection-alarming interrupt to the path setting unit 230. The path setting unit 230 analyzes the set value in response to the input connection-alarming interrupt. Since the set value is set to the second set value, the path setting unit sets a connection path between the AP core 222 and the USB controller 224. The path setting unit 230 outputs the connection- alarming inter- ruptinput from the USB controller 224 to the AP core 222 through the set connection path. Accordingly, the AP core 222 can recognize the connection of the USB device to the USB controller 224 and recognize the setting of the connection path to the USB controller 224. The AP core 222 can perform an enumeration operation on the USB device connected to the USB controller 224 through the set connection path by the use of the driver. The AP core 222 can transmitand receive only a control signal to and from the USB controller 224 through the set connection path.

[87] In this way, when the host processor 210 intends to transmitand receive data to and from the USB device connected to the USB controller 224 after the enumeration operation, the host processor 210 can set a command line for transmitting and receiving data to and from the AP core 222. The host processor 210 can transmit and receive commands for transmitting and receiving data and data to be transmitted and received through the command line from the AP core 222. By providing the host processor 210 with only the application to perform a data transmitting and receiving function and allowing the AP core 222 to perform the control function of controlling the USB controller 224, the AP core 222 can be made to perform the function of processing the interrupt frequently generated by the USB controller 224, thereby reducing the load of the host processor 210. By providing the host processor 210 with the application requiring a relatively high-capacity memory to perform only the corresponding function, it is possible to reduce the manufacturing cost of the application processor 220 and to reduce the chip size.

[88] At the time of installing the driver and the application depending on the embodying method, the path setting unit 230 may set in advance the connection path between the USB controller 224 and one of the host processor 210 and the AP core 222. That is, since the USB controller 224 should be connected to a device (that is, the host processor 210 or the AP core 222) having the driver for control, a system manager may control the path setting unit 230 to set in advance a connection path between the device having the driver and the application and the USB controller 224. In this case, when the connection path between the USB controller 224 and one of the host processor 210 and the AP core 222 is set in advance and the path setting unit 230 receives the connection-alarming interrupt from the USB controller 224, the path setting unit 230 can serve to only transmit the connection- alarming interrupt to one of the host processor 210 and the AP core 222 through the set connection path without performing a particular connection path setting operation. That is, the path setting unit 230 can set the connection path between the USB controller 224 and the processor (that is, the host processor 210 or the AP core 222) in advance regardless of the connection of the USB device to the USB controller 224.

[89] Although it has beendescribed above that the path setting unit 230 is not included in the application processor 220, the path setting unit 230 may be included in the application processor 220. That is, it is assumed in the following description that the path setting unit 230 is not included in the host processor 210 and the application processor 220.

[90] Although it has been shown in Fig. 2 that a particular signal line for allowing the

AP core 222 and the USB controller 224 to communication with each other is not disposed (thatis, the AP core 222 communicates with the USB controller 224 through the path setting unit 230), a signal line for allowing the AP core 222 and the USB controller 224 to communicate with each other may be provided to allow the AP core 222 to directly control the USB controller 224.

[91] In another embodiment, it is assumed that the application and the driver for controlling the USB controller 224 are disposed in the AP core 222 and a file system, a memory driver, and a database are disposed in the host processor 210.

[92] For example, when a user inputs a command for recording data recorded in the USB device connected to the USB controller 224 in a storage medium of the host processor 210, the USB controller 224 generates and transmits an interrupt for recording datato the AP core 222. Then, the driver of the AP core 222 calls a command (that is, a predetermined function for recording data) for recording data by the use of the UMS. Here, the UMS may be a set of functions (that is, commands) set to record, delete, and update data in the USB storage medium and commands for managing the USB storage medium in response to the recording, the deletion, and the update of data in the USB storage medium. Since it is obvious that the UMS is used to record, delete, and update data in the USB storage medium, particular description thereof is omitted.

[93] The UMS transmits a control signal for recording data to the host processor 210 as the analysis result of the data recording commands called by the driver. Here, since the UMS is disposed in the AP core 222, it means that the AP core 222 transmits the control signal for recording data to the host processor 210.

[94] The host processor 210 receiving the control signal for recording data controls the storage medium by the use of the memorydriver. The host processor 210 can receive data to be recorded from the AP core 222, for example, in the unit of packet and can record the input data in the storage medium by the use of the memory driver. Here, it is assumed that the memory driver is a set of commands for controlling the storage medium connected to the host processor 210. Accordingly, the host processor 210 can record the received data at a position in the storage medium by the use of the commands of the memory driver.

[95] Since the method of managing the USB device by the use of the UMS and recording data in the storage medium by the use of a particular memory driver is obvious to those skilled in the art and it is also obvious to those skilled in the art that the UMS, the driver, the database, and the memory driver are embodied by particular software, description thereof is omitted.

[96] In another embodiment, it is assumed that the host processor 210 includes only the file system and the memory driver and the AP core 222 of the application processor 220 includes the application and the driver. Here, it is also assumed that the application of the AP core 222 includes the UMS, the MTP, and the database. It is also assumed that a user inputs a multimedia data reproducing command and inputs a command for reproducing data recorded in the USB device. For the purpose of convenient and explanation, it is assumed that a player for reproducing the multimedia data is a window media player. Attribute information (such as a file name, a file size, a file type, a musician, and a reproduction time) of the multimedia data is stored in the database.

[97] When a user inputs the multimedia data reproducing command to the AP core 222 through the USB controller 224, the AP core 222 analyzes the multimedia data reproducing command by the use of the installed driver. When the input command is a command for reproducing multimedia data stored in the USB data as the analysis result, the AP core 222 transmits the input command to the host processor 210 by the use of the installed MTP. First, the AP core 222 acquires the attribute informationof the multimedia data to be reproduced from the database by the use of the MTP and transmits the acquired attribute information to the host processor 210. Since the USB controller 224 reads the multimedia data to be transmitted in the unit of packet and stores the read multimedia data in its memory, the AP core 222 transmits the multimedia data recorded in the USB controller 224 to the host processor 210 by the use of the MTP. Accordingly, the host processor 210 can reproduce the multimedia data by the use of the attribute information of the multimedia data input from the AP core 222.

[98] Fig. 3 is a flowchart illustrating a method of allowing the host processor to control the USB controller of the application processor according to an embodiment of the invention. Although it is described below that the peripheral device controlled by the host processor 210 is the USB device (such as a USB memory), the invention is applicable to a case where the peripheral device includes the peripheral device controller having a built-in communication unit. However, for the purpose of convenient and explanation, it is assumed that the peripheral device is the USB device.

[99] In step 310, the USB controller 224determines whether a USB device is connected thereto. For example, the USB controller 224 can sense different voltages depending on the connection or non-connection of the USB device to recognize the connection or non-connection of the USB device. This is obvious to those skilled in the art and thus particular description thereof is omitted.

[100] When determining that a USB device is connected thereto, the USB controller 224 generates and transmits a connection- alarming interrupt to the path setting unit 230 in response to the connection of the USB device in step S315.

[101] However, when determining that a USB device is not connected thereto, the USB controller 224 waits in step 310.

[102] In step 320, the path setting unit 230 having received the connection-alarming in- terruptfrom the USB controller 224 determines whether the set value is the first set value or the second set value.

[103] When determining that the set value is the first set value, the path setting unit 230 sets the connection path between the host processor 210 and the USB controller 224 and outputs the connection- alarming interrupt to the host processor 210 in step 325.

[104] When receiving the connection-alarming interrupt from the path setting unit 230, the host processor 210 performs an enumeration operation on the USB device connected to the USB controller 224 through the set connection path in step 330.

[105] For example, the host processor 210 can set an address of the USB device connected to the USB controller 224 and can acquire and set a device descriptor, a configuration descriptor, an interface descriptor, and a string descriptor corresponding to a maker and a device. This is obvious to those skilled in the art and thus particular description thereof is omitted.

[106] When the enumeration operation of the USB device is ended, the host processor

210 can control the USB controller 224 through the set connection path by the use of the driver and can transmit and receive data to and from the USB device connected to the USB controller 224 by the use of the application in step 335.

[107] In order to clarify a difference from the invention, a conventional method will be described in brief with reference to Fig. 1. Since the driver for controlling the USB controller 124 and the application for transmitting and receiving data to and from the USB device connected to the USB controller 124 are installed in the AP core 122, the USB controller 124 generated and transmitted a connection- alarming interrupt to the AP core 122 in response to the connection of the USB device. Accordingly, the AP core 122 performed the enumeration operation, controlled the USB controller 124, and transmitted and received data to and from the USB device connected to the USB controller 124. However, when the host processor 110 does not include a built-in USB controller 124 or uses the USB controller 124 of the AP core 122 as needed, the host processor 110 could not directly control the USB controller 124.

[108] When determining in step 320 that the set value is the second set value, the path setting unit 230 sets the connection path between the AP core 222 and the USB controller 224 and outputs the connection- alarming interrupt to the AP core 222 in step 340.

[109] When receiving the connection-alarming interrupt from the path setting unit 230, the AP core 222 performs the enumeration operation on the USB device connected to the USB controller 224 through the set connection path in step 345. That is, the AP core 222 can analyze one or more interrupt input from the USB controller 224 through the set connection path and can directly control the USB controller 224 as the analysis result.

[110] When the host processor 210 intends to transmit and receive data to and from the

USB device connected to the USB controller 224, the host processor 210 sets a command line for transmitting and receiving data to and from the AP core 222 in step 350.

[I l l] In step 355, the host processor 210 transmits the command for transmitting and receiving data to the AP core 222 through the set command line. Then, the host processor 210 transmits and receives data to and from the USB device through the AP core 222 and the set command line.

[112] System and method that can allow the host processor 210 to directly control a high- performance peripheral device requiring a high data transmission rate and being connected to the application processor 220 and can transmit and receive data to and from the peripheral device without changing the host processor 210 will be described now.

[113] Fig. 4 is a block diagram illustrating a system that can allow the host processor to transmit and receive data through the USB controller of the application processor according to an embodiment of the invention.

[114] Referring to Fig. 4, the system according to the embodiment of the invention includes the host processor 210 and the application processor 220.

[115] For example, the host processor 210 serves as a baseband processor of a portable terminal or a central processing unit (CPU) of a personal computer. That is, the host processor 210 can serve to control the inner elements of a device and to control and instruct the operation of the elements.

[116] The host processor 210 is connected to the application processor 220 through a first data bus and can transmit and receive a control signal and data for controlling the USB controller 224 through the first data bus. That is, the host processor 210 transmits and receives data through the first data bus in the unit of n bits (where n is a natural number of 16 or less).

[117] The driver and the application for controlling the USB controller 224 of the application processor 220 and performing data communication are installed in the host processor 210.

[118] Depending on the embodying method, the host processor 210 may include both the driver and the application or may include only the application. In the following description, it is assumed that the host processor 210 includes both the application and the driver.

[119] The application processor 220 includes the AP core 222, the USB controller 224, a host interface unit 226, and a data processing unit 228, as shown in Fig. 4.

[120] The host interface unit 226 serves as an interface for transmitting and receiving data or control signals between the host processor 210 and the application processor 220. That is, the host interface unit 226 is connected to the host processor 210 through the first data bus and serves to output the data or the control signals received from the host processor 210 to the AP core 222 or the data processing unit 228. The host interface unit 226 serves to output the data received from the data processing unit 228 to the host processor 210.

[121] The AP core 222 serves to perform a predetermined operation of the application processor 220 or to control the inner functional blocks. For example, the AP core 222 can perform previously set functions of the application processor 220 or control the elements to perform the functions.

[122] The data processing unit 228 analyzes data transmission capabilities of a processor and the USB controller 224 in accordance with a control signal input from the processor (for example, the host processor 210 orthe AP core 222) and processes and outputs the input data in a predetermined method. Here, the data transmission capability is defined as the number of bits which can be simultaneously transmitted in a clock period. In this specification, the clock period is defined as a clock period for acquiring effective data.

[123] For example, it is assumed that the data transmission capability of the host processor 210 is 16 bits and the data transmission capability of the USB controller 224 is 32 bits. It is also assumed that the data processing unit 228 receives a control signal for recording data in the USB controller 224 from the host processor 210. The data processing unit 228 receives data (referred to as "recording data" for the purpose of convenient and explanation) in the unit of 16 bits from the host processor 210. Since the size of the input recording data is 16 bits, the data processing unit 228 receives the 16-bit data once more. That is, the data processing unit 228 receives the recording data in n clock periods (where n is a natural number), converts the input recording data into 32-bit data, and outputs the converted recording data to the USB controller 224. [124] For the purpose of convenient and explanation, the recording data input in a first clock period is referred to as "first recording data" and the recording data input in a second clock period is referred to as "second recording data". The data processing unit 228 receives the first recording data, stores the first recording data in a register, and receives the second recording data. The data processing unit 228 can convert the first recording data and the second recording data into 32-bit data and output the converted data to the USB controller 224.

[125] In another example, it is assumed that the data transmission capability of the host processor 210 is 8 bits and the data transmission capability of the USB controller 224 is 32 bits. It is also assumed that the data processing unit 228 receives a control signal for reading data to the USB controller 224 from the host processor 210. The data processing unit 228 divides the 32-bit read data input from the USB controller 224 into 8-bit data and stores the divided data. Then, the data processing unit 228 outputs the divided 8-bit data to the host processor 210 sequentially or in any order.

[126] When receiving a control signal from the AP core 222, the data processing unit 228 can output the data transmitted between the AP core 222 and the USB controller 224 without being processed. In this case, the data transmission capability of the AP core 222 is equal to the data transmission capability of the USB controller 224.

[127] In this way, the data processing unit 228 serves to compare the data transmission capabilities of the host processor 210, the AP core 222, and the USB controller 224 with each other, to process the data input to be transmitted by a predetermined method, and to outputting the processed data. The data processing unit 228 will be described below in detail with reference to Fig. 5.

[128] When an external peripheral device is connected thereto, the USB controller 224 transmits the connection-alarming interrupt to the AP core 222 and the host processor 210 through the data processing unit 228. Accordingly, the AP core 222 and the host processor 210 can recognize the connection of a peripheral device to the USB controller 224. Here, the USB controller 224 receives data and a control signal in the unit of m bits (where m is a natural number of 5 or more) and transmits and receives the data and the control signal toand from the peripheral device.

[129] Fig. 5 is a functional block diagram illustrating a data processing unit according to an embodiment of the invention.

[130] As shown in Fig. 5, the data processing unit 228 according to the invention includes a first interface unit 510, an analysis unit 520, a conversion unit 530, and a second interface unit 540.

[131] The first interface unit 510 is an interface for inputting and outputting data to and from the host processor 210 or the AP core 222. The first interface unit 510 inputsand outputs data in the unit of 8 bits or 16 bits to and from the host processor 210. The first interface unit 510 inputs and outputs data to and from the AP core 222 in the unit of 32 bits.

[132] The second interface unit 540 is an interface for inputting and outputting data between the USB controller 224 and the data processing unit 228. The second interface unit 540 inputs and outputs data in the unit of 32 bits to and from the USB controller 224.

[133] The analysis unit 520 analyzes the data transmission capability of the processor connected through the first interface unit 510 and the USB controller 224 connected through the second interface unit 540, generates a control signal corresponding to the analysis result, and outputs the generated control signal to theconversion unit 530. The data transmission capability is defined as the number of bits which can be simultaneously transmitted in a clock period as described above.

[134] That is, the analysis unit 520 serves to analyze the data transmission capability of the process (that is, one of the host processor 210 and the AP core 222) and the USB controller 224 and to control the conversion unit 530 to transmit data between the processor and the USB controller 224.

[135] For example, it is assumed that a recording control signal is input from the host processor 210, the data transmission capability of the host processor 210 is 8 bits, and the data transmission capability of the USB controller 224 is 32 bits. In this case, the analysis unit 520 controls the conversion unit 530 to receive n-times data from the host processor 210 (where the 8 -bit data is input every time), to convert the input data into 32-bit data, and to output the converted data to the peripheral device controller 228 through the second interface unit 540.

[136] Inanother example, it is assumed that a reading control signal is input from the host processor 210, the data transmission capability of the host processor 210 is 16 bits, and the data transmission capability of the USB controller 224 is 32 bits. In this case, the analysis unit 520 controls the conversion unit 530 to divide the 32-bit data input through the second interface unit 540 into 16-bit data, to store the divided 16-bit data, and to output the divided data to the host processor 210 through the first interface unit 510.

[137] Under the control of the analysis unit 520, the conversion unit 530 receives data n times (where n is a natural number) through the first interface unit 510, converts the input data into 32-bit data, and outputs the converted data to the second interface unit 540. Under the control of the analysis unit 520, the conversion unit 530 divides the 32-bit data input through the second interface unit 540 into 8-bit or 16-bit data and outputs the divided data to the host processor 210.

[138] Fig. 6 is a flowchart illustrating a method of allowing the host processor to transmit data to the peripheral device connected to the peripheral device controller of the ap- plication processor according to an embodiment of the invention. For the purpose of convenient and explanation, it is assumed that the USB controller 224 of the application processor 220 is a controller in accordance with the USB 2.0 standard and the peripheral device connected to the USB controller 224 is a USB device (for example, memory) which can transmit and receive data in accordance with the USB 2.0 standard. It is also assumed that the host processor 210 does not include a controller for connection to the USB device. It is also assumed that a peripheral device is connected to the USB controller 224, the USB controller 224 outputs the connection-alarming interrupt to the host processor 210 and the AP core 222, and the host processor 210 and the AP core 222 recognize the connection- alarming interrupt.

[139] In step 610, the data processing unit228 receives a control signal form a processor.

Here, it is assumed that the processor is one of the host processor 210 and the AP core 222 and the control signal is a recording control signal for recording data in the USB controller 224.

[140] In step 615, the data processing unit 228 compares the data transmission capability of the processor and the data transmission capability of the USB controller 224 with each other.

[141] When the data transmission capabilities are equal to each other, the data processing unit 228 outputs the data input from the processor to the USB controller 224 without being processed in step 620. Here, the data processing unit 228 can output the recording data in the unit of 32 bits to the USB controller 224.

[142] However, when the data transmissioncapabilities are not equal to each other, the data processing unit 228 receives the recording data in predetermined N (where N is a natural number) clock periods in step 625. That is, the data processing unit 228 receives the N-times recording data depending on the data transmission capability from the host processor 210.

[143] For example, when the data transmission capability of the processor is 8 bits and the data transmission capability of the USB controller 224 is 32 bits, the data processing unit receives the recording data four times in total. That is, since the data transmission capability of the processor is 8 bits, the data processing unit 228 can receive the 8-bit recording data every time. When the data transmission capability of the processor is 16 bits and the data transmissioncapability of the USB controller 224 is 32 bits, the data processing unit 228 can receive the recording data two times.

[144] In step 630, the data processing unit 228 converts the N-times input recording data into 32-bit data and outputs the converted data to the USB controller 224.

[145] Fig. 7 is a flowchart illustratinga method of allowing the application processor to read data from the connected peripheral device and to output the read data to the host processor according to an embodiment of the invention. For the purpose of convenient and explanation, it is assumed that the USB controller 224 of the application processor 220 is a controller in accordance with the USB 2.0 standard and the peripheral device connected to the USB controller 224 is a USB device (for example, a memory) which can transmit and receive data in accordance with the USB 2.0 standard. It is also assumed that the host processor 210 does not include a controller for connection to the USB device. It is also assumed that a peripheral device is connected to the USB controller 224, the USB controller 224 outputs the connection- alarming interruptto the host processor 210 and the AP core 222, and the host processor 210 and the AP core 222 recognize the connection- alarming interrupt.

[146] In step 710, the data processing unit 228 receives a reading control signal for reading data from a processor. Here, it is assumed that the processor is one of the host processor 210 and the AP core 222 and the control signal is a reading control signal for reading data from the USB controller 224.

[147] In step 715, the data processing unit 228 compares the data transmission capability of the processor with the data transmission capability of the USB controller 224. Here, the data transmission capability is defined as the number of bits of data which can be simultaneously transmitted in a clock period as described above.

[148] When the data transmission capabilities are equal to each other, the data processing unit 228 outputs 32-bit data input from the USB controller 224 to the processor without being processed in step 720.

[149] However, when the data transmissioncapabilities are not equal to each other, the data processing unit 228 divides the 32-bit data input from the USB controller 224 depending on the data transmission capability of the processor in step 725.

[150] In step 730, the data processing unit 228 outputs the divided data to the processor.

[151] Although it has been described that the peripheral device is a USB device (for example, a USB memory) for making a USB communication, the peripheral device may be a slave processor (that is, an application processor) including a peripheral device controller for controlling the peripheral device having a built-in communication function (such as Bluetooth and infrared communication), in addition to the USB device. When the peripheral device has a communication function other than the USB device, the method of allowing the host processor to directly control the peripheral device controller is the same as described above and thus particular description is omitted.

[152] Although the invention has been described with reference to the exemplary embodiments, it will be understood by those skilled in the art that the invention can be modified and changed in various formswithout departing from the spirit and scope of the invention described in the appended claims.

[153] Industrial Applicability

[154] As described above, according to the invention, it is possible to allow a host processor to directly control a USB device connected to a USB controller regardless of an operation of the application processor.

[155] According to the invention, it is possible to allow a host processor to directly control a peripheral device connected to a USB controller connected to or installed in an application processor and to transmit and receive data to and from the USB device without including a particular USB controller.

[156] According to the invention, it is possible to allow a host processor and an application processor to control and use a USB device controller connected to or installed in the application processor.

[157] According to the invention, it is possible to reduce the cost for manufacturing an application processor because the application process need not include a memory storing programs used to control a USB controller.

[158] According to the invention, it is possible to allow a host processor to directly control a high-performance peripheral device connected to an application processor and to transmit and receive data to and from the high-performance peripheral device without changing the host processor.

Claims

Claims

[1] A peripheral device control system comprising: a peripheral device controller generating a connection- alarming interrupt when a peripheral device is connected thereto; a first processor including a processor core connected directly to the peripheral device controller; and a path setting unit setting a connection path for connecting the peripheral device controller to one of the processor core and a second processor with reference to a predetermined value when the connection- alarming interrupt is input from the peripheral device controller, wherein the second processor communicateswith the first processor and the peripheral device controller is controlled directly by one of the processor core and the second processor in which the connection path is set.

[2] The peripheral device control system according to claim 1, wherein the peripheral device controller is disposed in the first processor.

[3] The peripheral device control system according to claim 1 or 2, wherein the path setting unit sets a first connection path for connecting the second processor to the peripheral device controller when the predetermined value is a first set value, sets a second connection path for connecting the processor core to the peripheral device controller when the predetermined value is a second set value, and outputs the connection- alarming interrupt to one of the first and second connection paths.

[4] The peripheral device control system according to claim 3, wherein when the first connection path is set and the connection- alarming interrupt is input by the path setting unit, the second processor directly controls the peripheral device controller through the first connection path to transmit and receive data to and from the peripheral device.

[5] The peripheral device control system accordingto claim 4, wherein the second processor includes a driver which is a set of control commands for controlling the peripheral device controller and an application which is a set of commands for transmitting and receiving data to and from the peripheral device connected to the peripheral device controller.

[6] The peripheral device control system according to claim 3, wherein when the second connection path is set and the connection-alarming interrupt is input by the path setting unit, the processor core directly controls the peripheral device controller through the second connection path.

[7] The peripheral device control system according to claim 6, wherein the second processor sets a command line to the processor core to transmit and receive data to and from the peripheral device and transmits and receives data to and from the peripheral device through the processor core.

[8] The peripheral device control system accordingto claim 7, wherein the processor core includes a driver which is a set of control commands for controlling the peripheral device controller, and wherein the second processor includes an application which is a set of commands for transmitting and receiving data to and from the peripheral device connected to the peripheral device controller.

[9] A peripheral device control system comprising: a peripheral device controller connected to a peripheral device; a first processor that is connected directly to the peripheral device controller and that includes a data processing unit and a processor core; and a second processor communicating with the processor core, wherein when a control signal is input from one of the second processor and the processor core, the data processing unit compares data transmission capability of the peripheral device controller with data transmission capability of one of the second processor and the processor core and processes and outputs data by a predetermined method, and wherein the processor is one of the secondprocessor and the processor core.

[10] The peripheral device control system according to claim 9, wherein the peripheral device controller is diposed in the first processor.

[11] The peripheral device control system according to claim 9 or 10, wherein the data transmission capability is the number of bits simultaneously transmitted in a clock period, and wherein the clock period is a time for acquiring effective data.

[12] The peripheral device control system according to claim 11, wherein when the data transmission capabilities are equal to each other, the data processing unit outputs the data without being processed.

[13] The peripheral device control system according to claim 11, wherein when the data transmission capabilities are not equal to each other, the data processing unit receives recording data from the second processor for n (where n is a natural number) clock periods in accordance with the control signals for recording data input from the second processor, converts the input recording data into m-bit (where m is a natural number) corresponding to the data transmission capability of the peripheral device controller, and outputs the m-bit data to the peripheral device controller.

[14] The peripheral device control system according to claim 11, wherein when the data transmission capabilities are not equal to each other, the data processing unit divides m-bit (where m is a natural number) data input from the peripheral device control in the unit of n bits (where n is a natural number) corresponding to the data transmission capability of the second processor in accordance with the control signals for reading data input from the second processor and sequentially outputs the n-bit data to the second processor.

[15] A method of allowing an external second processor to control a peripheral device connected thereto through a peripheral device controller connected directly to a processor core of a first processor, the method comprising the steps of: allowing the peripheral device controller to generate a connection- alarming interrupt with the connection of the peripheral device; allowing a path setting unit to set a connection path for connecting one of the second processor and the processor core to the peripheral device controller with reference to a predetermined value with the input of the connection-alarming interrupt; and allowing one of the processor and the processor core in which the connection path is set to directly control the peripheral device controller through the connection path.

[16] The method according to claim 15, wherein the step of allowing one of the processor and the processor core in which the connection path is set to directly control the peripheral device controller through the connection path includes the steps of: allowing a data processing unit, which is disposed in the first processor, to receive a control signal from one of the processor core and the second processor through the connection path; comparing data transmission capability of one of the processor core and the second processor with data transmission capability of the peripheral device controller; and processing and outputting data by a predetermined method in accordance with the comparison result.

[17] A method of allowing an external second processor to control a peripheral device connected thereto through a peripheral device controller connected directly to a processor core of a first processor, the method comprising the steps of: allowing a data processing unit to receive data from a processor; allowing the data processing unit to compare data transmission capability of the processor with data transmission capability of the peripheral device controller; and allowing the data processing unit to process and output the input data by a predetermined method in accordance with the comparison result, wherein the processor is one of the second processor and the processor core. [18] The peripheral device control method according to claim 17, wherein the data transmission capability is the number of bits simultaneously transmitted in a clock period, and wherein the clock period is a time for acquiring effective data.