WO2008062515A1

WO2008062515A1 - Semiconductor manufacturing system

Info

Publication number: WO2008062515A1
Application number: PCT/JP2006/323209
Authority: WO
Inventors: Tatsushi Iimori
Original assignee: Systemv Management Inc.,
Priority date: 2006-11-21
Filing date: 2006-11-21
Publication date: 2008-05-29
Also published as: JPWO2008062515A1; JP5075835B2

Abstract

Provided is a semiconductor manufacturing system employing a flow show system for achieving a short TAT in semiconductor manufacture in a semiconductor manufacturing facility. The semiconductor manufacturing system is provided with a plurality of bays and inter-bay transfer apparatus. The semiconductor manufacturing system is also provided with a flow shop controller having a scheduler for performing scheduling for the bays and inter-bay transfer. The bay is provided with a bay controller having a scheduler for performing scheduling for the semiconductor manufacturing apparatus and an intra-bay transfer apparatus. The flow shop controller transmits a control instruction based on the scheduling, and the bay controller transmits a control instruction based on the scheduling. The scheduling is set by having the operation rate of a lithography apparatus as reference and by calculating the number of lithography apparatuses arranged for each semiconductor manufacturing apparatus and the number of flow steps.

Description

Specification

Semiconductor manufacturing system

Technical field

The present invention relates to a semiconductor manufacturing system for realizing a short TAT (Turn-around Time) when a semiconductor is manufactured in a semiconductor manufacturing facility using a flow shop method.

Background art

[0002] A semiconductor is manufactured by executing various processing steps in a clean room of a semiconductor manufacturing facility. For each processing step in this clean room, a semiconductor manufacturing apparatus that realizes each processing is used. Conventionally, a required number of semiconductor manufacturing apparatuses that perform each process are installed by the job shop method. In other words, a conventional semiconductor manufacturing facility is equipped with a plurality of units called “pays”, each of which includes a required number of semiconductor manufacturing apparatuses that execute each process using a job shop method, and the robots are transported between the bays by a transport robot or a belt conveyor. It is manufactured by.

[0003] However, in the case of this job shop method, it is known that when a plurality of similar processing steps are repeated, the time required for transfer within the bay, transfer between bays, and standby is increased. The decline in productivity is a problem. Therefore, instead of the conventional job shop method, a semiconductor manufacturing system using a flow shop method in which each semiconductor manufacturing apparatus is installed in the order of processing steps has been proposed, and examples thereof are disclosed in Patent Documents 1 to 6 below. ing.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-26106

Patent Document 2: JP 2005-197521

Patent Document 3: Japanese Patent Laid-Open No. 2005-197500

Patent Document 4: Japanese Patent Laid-Open No. 2001-143979

Patent Document 5: Japanese Patent Application Laid-Open No. 11-145022

Patent Document 6: Japanese Patent Laid-Open No. 7-237095

Disclosure of the invention Problems to be solved by the invention

[0005] The invention disclosed in the above patent document discloses a semiconductor manufacturing system using a flow shop system, and by using this system, the problems caused by the conventional job shop system can be solved. However, even if each of these inventions is used, it cannot be said that a sufficiently short TAT can still be realized for a semiconductor production line that requires a short lot and a variety of small lots such as SOC.ヽ. Even in the inventions described in the above-mentioned patent documents, the next processing step is started by an event based on a request from each semiconductor manufacturing apparatus, so that the conveyance efficiency is poor.

That is, the processing time (TAT) is determined by the processing time in the apparatus and the transport time to the semiconductor manufacturing apparatus that performs the next processing step. Since the processing time in the equipment depends on the specifications of the semiconductor manufacturing equipment, the processing time will not be shortened unless the semiconductor manufacturing equipment is improved. However, the conveyance time can be improved. In this regard, the conventional process has an event-type processing structure based on the demands of semiconductor manufacturing equipment as described above. Therefore, when a mounting Z removal request from a certain semiconductor manufacturing equipment triggers, transportation is started. The Rukoto. Therefore, means for solving the problem that waste is still occurring in the transport time

[0007] In view of the above problems, the inventor of the present application has realized that the transport is performed by scheduling rather than the conventional event type processing in order to realize a short TAT in the flow shop type semiconductor manufacturing system. The present inventors have invented a semiconductor manufacturing system configured so that the next processing process can be started immediately on the semiconductor manufacturing apparatus.

[0008] Further, in the scheduling as described above, if all of the semiconductor manufacturing apparatuses in the semiconductor manufacturing system have the same processing capability, the standby time of the semiconductor manufacturing apparatus is set to 0 (in the semiconductor manufacturing apparatus, processing of a certain carrier) It is possible to start processing the next carrier immediately after the process is completed.) However, since there are differences in actual semiconductor manufacturing equipment, it is difficult to completely reduce the waiting time to zero. Therefore, the invention of the present application is further characterized in that scheduling is performed in a state in which the operating rate of the expensive lithography apparatus among the semiconductor manufacturing apparatuses in the semiconductor manufacturing system is most improved. [0009] The invention of claim 1 is a semiconductor manufacturing system based on a flow shop method, wherein the semiconductor manufacturing system executes a carrier transport between a plurality of semiconductor manufacturing apparatuses and the semiconductor manufacturing apparatuses. A plurality of pays each including an internal transfer device, and an inter-bay transfer device that executes transfer of carriers between the bays, and the semiconductor manufacturing system performs scheduling of the transfer between the pays and the bays. A flow shop controller having at least a scheduler for executing, and the bay has a bay controller having a scheduler for executing at least scheduling of the semiconductor manufacturing apparatus and the transfer apparatus in the bay. The flow shop controller is based on the scheduling in the scheduler. A control instruction is sent to the inter-bay transfer device, and the bay controller sends a control instruction to the semiconductor manufacturing apparatus and the intra-bay transfer device based on scheduling in the scheduler, Scheduling calculates the number of installed units and the number of flow steps for each of the semiconductor manufacturing apparatuses based on the operating rate of the lithography apparatus among the semiconductor manufacturing apparatuses, and is set based on the calculated number of installed units and the number of flow steps. It is a semiconductor manufacturing system.

By configuring as in the present invention, the semiconductor manufacturing system can be a system based on scheduling. This makes it possible to achieve a shorter TAT than the conventional event type. In addition, since the number of installations, the number of flow steps, and the like are calculated based on the lithography apparatus during this scheduling, it is possible to make maximum use of an expensive and high-throughput lithography apparatus.

[0011] In the invention of claim 2, the flow shop controller and the bay controller are one or more of the semiconductor manufacturing apparatus, the intra-bay transfer apparatus, the bay, and the inter-bay transfer apparatus. The flow shop controller receives one or more pieces of information of failure information, recovery information, and remaining processing time information, and the flow shop controller performs rescheduling at the timing of accessing the entrance of the flow shop. This is a semiconductor manufacturing system that performs rescheduling at the timing of accessing the entrance of the bay. [0012] As described above, after scheduling once, each scheduler executes rescheduling at a predetermined timing. As a result, various kinds of information can be received in real time, and it becomes possible to flexibly cope with failures of semiconductor manufacturing equipment.

The invention's effect

[0013] In the semiconductor manufacturing system based on the flow shop method of the present invention, a semiconductor manufacturing system in which a shorter TAT is realized can be realized by using a conventional scheduling method that does not use the event type. Also, because scheduling is performed, no unnecessary WiP (Work in Progress) occurs.

[0014] Further, the flow shop controller and the bay controller can perform real-time processing by performing rescheduling at each timing. And since it is real-time processing, interrupt processing can be realized in an efficient state. In short, the shortest HotLot can be realized.

Brief Description of Drawings

FIG. 1 is a diagram schematically showing an example of a semiconductor manufacturing system according to the present invention.

FIG. 2 is a diagram schematically showing an example of a semiconductor manufacturing system when a belt conveyor is used as an inter-pay transport device.

FIG. 3 is a diagram schematically showing an example of a semiconductor manufacturing system using an inter-pay buffer.

FIG. 4 is a diagram schematically showing a hierarchical relationship among a flow shop controller, a bay controller, an inter-bay transfer controller, an apparatus controller, and a bay controller according to the present invention.

FIG. 5 is a diagram schematically showing the throughput of each semiconductor manufacturing apparatus.

FIG. 6 is a diagram schematically showing a semiconductor manufacturing apparatus in order of processing steps.

FIG. 7 is a diagram schematically showing a case where an assumed operating rate is set for each semiconductor manufacturing apparatus.

FIG. 8 is a diagram schematically showing a case where a processing number ratio is set for each semiconductor manufacturing apparatus.

FIG. 9 is a diagram schematically showing a case where the throughput on the four powers for each semiconductor manufacturing apparatus is calculated.

[Figure 10] Schematic representation of the required number of semiconductor manufacturing equipment installed in order of processing steps It is a figure.

FIG. 11 is a diagram schematically showing the concealment time of the transport time when the throughput of the semiconductor manufacturing apparatus is the same.

FIG. 12 is a diagram schematically showing the concealment time of the transport time when the throughput of the semiconductor manufacturing apparatus is different.

FIG. 13 is a diagram schematically showing the elimination of the load port waiting when the processing time varies depending on the recipe of the semiconductor manufacturing apparatus.

FIG. 14 is a diagram schematically showing the elimination of the load port waiting when the processing time becomes long due to a failure of the semiconductor manufacturing apparatus.

Explanation of symbols

[0016] 1: Semiconductor manufacturing system

2: Bay

3: Pay-to-pay transport device

4: Bay buffer

21: Semiconductor manufacturing equipment

22: In-pay transport device

BEST MODE FOR CARRYING OUT THE INVENTION

The process of manufacturing a semiconductor at a semiconductor manufacturing facility is roughly divided into a wiring process and a transistor generation process. The semiconductor manufacturing system 1 of the present invention is preferably used in the wiring process. An example of the semiconductor manufacturing system 1 in this wiring process is shown in FIG.

[0018] The semiconductor manufacturing system 1 has a plurality of pays 2 and an inter-pay transport device 3 for transporting between the pay bays. In addition, the bay 2 includes at least one semiconductor manufacturing apparatus 21 that performs processing of each process in the wiring process of semiconductor manufacturing, and an intra-pay transfer apparatus that transfers between the semiconductor manufacturing apparatuses 21 in the bay 2. And 22. The semiconductor manufacturing system 1 has a computer system called a flow shop controller that controls the transfer between the bay 2 and the bay, and the flow shop controller has a scheduler that schedules the transfer between the bay 2 and the bay. It has been. Each bay 2 has its bay 2 The bay controller is equipped with a computer system called a bay controller that controls the semiconductor manufacturing device 21 and the bay transport device 22 in the bay. The bay controller includes the semiconductor manufacturing device 21 and the bay transport device 22 in the bay 2. There is a schedule ruler for scheduling.

[0019] The scheduler of the flow shop controller and the scheduler of the bay controller are transported between the bays, mounted on the semiconductor manufacturing apparatus 21 in the bay 2, and taken out in the bay 2 based on a predetermined schedule. To realize. By using such a scheduler, it is possible to conceal the transfer time between the semiconductor manufacturing apparatuses 21 and the bays, that is, to reduce the standby time. Scheduling will be described later. Once set, scheduling is rescheduled at a predetermined timing. In the case of the scheduler of the flow shop controller, rescheduling is performed at the timing when the inter-bay transfer device 3 accesses the entrance of the flow shop. In the case of the scheduler controller of the bay controller, rescheduling is performed at the timing when the in-bay transport device 22 accesses the entrance of the bay 2.

[0020] The semiconductor manufacturing apparatus 21 in the bay 2 is an apparatus controller that controls the apparatus, the intra-bay transfer apparatus 22 is an intra-pay transfer controller that controls the apparatus, and the inter-pay transfer apparatus 3 is an A computer system called an inter-bay transfer controller that controls the devices is provided to control each device. The device controller and the transport controller in the bay realize device control based on instructions from the bay controller. The inter-bay transfer controller realizes device control based on instructions from the flow shop controller. Figure 4 shows the control hierarchy of the flow shop controller, bay controller, inter-bay transfer controller, equipment controller, and intra-pay transfer controller.

[0021] Predetermined data communication is possible between the flow shop controller and the inter-bay transfer controller, and the flow shop controller force is the transfer command to the inter-bay transfer controller, the inter-bay transfer controller force is The transfer response, the position information of the transfer robot of the inter-bay transfer device 3 from the inter-bay transfer controller to the flow shop controller are reported.

[0022] Predetermined data communication is possible between the bay controller and the intrabay transport controller. Therefore, the transfer command from the bay controller to the transfer controller in the bay, the transfer response to the transfer controller in the bay, the transfer response to the bay controller, the transfer robot in the bay 22 from the transfer controller in the bay to the bay controller Location information reports are performed.

[0023] In addition, information on the processing status, fault information, recovery information, information on the remaining processing time, and the like are communicated between the bay controller and the semiconductor manufacturing apparatus 21, and the flow shop controller and each bay controller. ing.

In the semiconductor manufacturing system 1 of FIG. 1, an inter-bay buffer 14 is provided for transport between the bays. The inter-bay buffer 4 temporarily arrives after the processing in the bay 2 is completed until the inter-bay transport device 3 arrives to transport the carrier to the other bay 2 and starts transporting the carrier. It is a device for making it wait.

As described above, each bay 2 includes the semiconductor manufacturing apparatus 21 and the intra-bay transfer apparatus 22, but various semiconductor manufacturing apparatuses 21 can be used for the semiconductor manufacturing apparatus 21. For example, lithography equipment (“litho” in FIG. 1), etching equipment (“etch” in FIG. 1), CVD (chemical vapor deposition) equipment (“CVD” in FIG. 1), inspection equipment (“inspection” in FIG. 1) ), Cleaning device (“Clean” in FIG. 1), annealing device (“Annel” in FIG. 1), PVD (Physical Vapor Deposition) device (“PVD” in FIG. 1), and measuring device (“Meching” in FIG. 1). )), A CMP (Chemical Mechanical Polising) device (“CMP” in FIG. 1), etc., but other appropriate semiconductor manufacturing devices 21 can be used as the semiconductor manufacturing device 21.

Each semiconductor manufacturing apparatus 21 is provided with at least one load port for carrying out carrier loading / unloading Z with the in-pay transport apparatus 22. In addition, the intra-bay transfer device 22 has a mechanism that can continuously carry out the carrier loading Z removal with the inter-bay buffer 4 and the load port of the semiconductor manufacturing device 21. For example, there are two arms in the transfer device 22 in the bay, the carrier that has been processed by one arm is taken out (received) from the semiconductor manufacturing device 21, and the carrier that has been transferred by the other arm is mounted (delivered) There is a mechanism. Or, if there is only one arm, the conveyor device 22 in the bay is equipped with two stages, and after placing the carrier taken out from the semiconductor manufacturing device 21 after the processing is finished on one vacant stage, There is also a mechanism for mounting the carrier on the semiconductor manufacturing apparatus 21 from the stage on which the carrier to be mounted is placed. [0027] Similarly to the intra-bay transfer device 22, the inter-bay transfer device 3 includes a mechanism for continuously carrying out the carrier loading Z.

[0028] In the semiconductor manufacturing system 1 in FIG. 1, the inter-bay transfer device 3 for transferring between the bays is shown using a transfer robot. As shown in FIG. 3 may be a transfer device on a belt conveyor. In this case, since the belt conveyor itself performs the same function as the inter-bay buffer 4, the inter-bay buffer 4 becomes unnecessary. Also, as shown in Fig. 3, the inter-bay transport places the processed carrier in the inter-bay buffer 4 and the intra-bay transport device 22 is equipped with a carrier that performs the next processing from the inter-bay buffer 4. By doing so, it can also be configured to realize the inter-bay conveyance.

In this specification, for convenience of explanation, the case of the semiconductor manufacturing system 1 in FIG. 1 is used for explanation, but the same processing is performed in FIGS. 2 and 3 or other semiconductor manufacturing systems 1. Can be realized.

[0030] Next, the number of each semiconductor manufacturing device 21 installed in the semiconductor manufacturing system 1 and one intra-pay transport device 22 are required in the semiconductor manufacturing system 1, which is required when scheduling is performed by the scheduler of the flow shop controller and the scheduler of the bay controller. A processing flow for determining the number of devices (referred to as “the number of steps per exit”) and device layout will be described. This can be done on any computer system, such as a flow shop controller or bay controller.

[0031] It should be noted that the semiconductor manufacturing apparatus 21 of the wiring process executed in the semiconductor manufacturing system 1 of the present specification includes a lithography apparatus, a CVD apparatus, a PVD apparatus, an annealing apparatus, a cleaning apparatus, an etching apparatus, a CMP apparatus, a plating apparatus, and an inspection apparatus. The case of (Inspection 1 to Inspection 4) will be explained (Fig. 5). Also assume that the processing flow of the wiring process is in the order shown in FIG. In FIG. 5 and FIG. 6, the cut-out after each semiconductor manufacturing apparatus 21 means that the same processing is performed for the same processing. For example, lithography (1) and lithography (2) This means the first processing step and the second processing step in the lithosphere device.

First, processing for determining the number of installed semiconductor manufacturing apparatuses 21 will be described.

[0033] Among the semiconductor manufacturing apparatuses 21 in the semiconductor manufacturing system 1, the lithographic apparatus power used in the lithographic process S is the most expensive and has other throughputs. Higher than 21. Therefore, it is necessary to set the lithographic apparatus to have the highest operating rate based on investment efficiency. Here, in the general wiring process, as shown in FIG. 6, there are two lithographic processes, so two lithography apparatuses are required.

Next, the apparatus operating rate in each semiconductor manufacturing apparatus 21 is set. Figure 7 shows an example of this equipment availability. It is preferable to arbitrarily set this equipment operating rate based on past experience.

Next, in each semiconductor manufacturing apparatus 21, a processing number ratio is set that indicates how many of the mounted carriers are actually processed. This is because, in a general processing process in the wiring process, not all carriers are inspected in a force inspection process that processes all carriers, so the processing number ratio is set. Figure 8 shows how this is set. Fig. 8 shows the case where the ratio of the number of processed sheets per 25 sheets is set. This is because one carrier is often composed of 25 sheets.

[0036] When the assumed operation rate and the processing number ratio per semiconductor manufacturing apparatus 21 are set in this way, the apparent throughput per semiconductor manufacturing apparatus 21 is calculated by using the following formula 1.

(Number 1)

Apparent throughput = Throughput X (Estimated operating rate ÷ 100) X (1 ÷ Processing quantity ratio

)

FIG. 9 shows a state in which the apparent throughput per semiconductor manufacturing apparatus 21 is set.

When the apparent throughput of each semiconductor manufacturing apparatus 21 is calculated as described above, the necessary number of installed semiconductor manufacturing apparatuses 21 can be calculated as the number of installations satisfying Equation 2.

(Equation 2)

Apparent throughput X Installed number ≥ Apparent throughput of lithography apparatus [0039] FIG. 10 shows the required number of installed semiconductor manufacturing apparatuses 21 used for each processing step. By performing the above processing, the required number of installed semiconductor manufacturing devices 21 can be calculated. Next, a process for determining the number of flow steps will be described.

[0041] First, let t be the maximum value of the transfer time between devices by the transfer device 22 in the bay (t includes the time for taking out the carrier loaded Z with the semiconductor manufacturing device 21). If the throughput of each semiconductor manufacturing apparatus 21 is P (Wph), the processing time per one is 3600 ZP (seconds). In the process of determining the required number of installed semiconductor manufacturing apparatuses 21 described above, the models other than the lithography apparatus are set to have a larger throughput than the lithography apparatus (from Expression 2). 21 is a lithography apparatus.

[0042] In order to conceal the transfer time, the number of flow steps that satisfies Equation 3 is determined.

(Equation 3)

(t X number of flow steps to be transported) ≤ processing time per sheet

[0043] For example, when the transfer time between apparatuses is 10 seconds and each processing step is performed in the order of a CVD apparatus, a lithography apparatus, an annealing apparatus, a CMP apparatus, a cleaning apparatus, an etching apparatus, and an inspection apparatus (inspection 1), The throughput is 60 Wph based on the throughput values shown in FIG. In other words, the processing time per sheet is 60 seconds. Then, it can be calculated from Equation 3 that the number of flow steps is 6. That is, in each processing step, six semiconductor manufacturing apparatuses 21 can be constructed to be transported by one intra-bay transport apparatus 22. This is schematically shown in Fig. 11.

[0044] Once the number of flow steps is determined, the number of semiconductor manufacturing apparatuses 21 in charge of transport is inevitably determined by one in-bay transport apparatus 22, and therefore, how many semiconductor manufacturing apparatuses are in each bay 2. 21 can be installed, ie the layout is determined.

[0045] When the number of flow steps is determined in this way, a method for concealing the transport time is set. First, the in-bay transfer device 22 sequentially removes the carrier from each semiconductor manufacturing device 21 on the basis of a preset schedule. t Shift the time. As a result, if there is a carrier that is processed continuously, the subsequent carrier can be delivered at the timing of completion of the processing of the preceding carrier, and the apparent carrier time is the first carrier for each semiconductor manufacturing device. Except for the time to pass to 21 and the transport time to return the last carrier, it will be almost concealed. [0046] Information that is the basis of scheduling is set as described above. Based on this set information, scheduling is set by the scheduler of the flow shop controller and the scheduler of the bay controller so that the transport time is concealed. Then, based on the scheduler of the flow controller, instructions related to the control processing in each bay 2 and instructions related to the control processing of the inter-bay transport device 3 are sent to the flow shop controller bay controller and inter-bay transport. The bay controller controls the bay 2 based on the instruction, and the inter-pay transport controller controls the inter-pay transport device 3. In addition, the bay controller sends instructions regarding control processing in the semiconductor manufacturing apparatus 21 in the bay 2 and instructions regarding control processing in the intra-pay transport apparatus 22 based on the scheduler of the bay controller. Based on the instruction, the apparatus controller controls the semiconductor manufacturing apparatus 21 and the intra-pay transport controller controls the intra-pay transport apparatus 22. Note that the scheduling in the bay controller and the flow shop controller only powers the same algorithm at different levels, so in the case of processing in the inter-bay transport device 3, the intra-bay transport device described above. The processing in 22 can be similarly set by replacing the intra-bay transport device 22 with the inter-bay transport device 3 and the semiconductor manufacturing device 21 with the bay 2.

[0047] By operating the semiconductor manufacturing system 1 using the scheduler set as described above, the semiconductor manufacturing system 1 with a shorter TAT than the conventional event-type semiconductor manufacturing system 1 is realized. I can do it.

In the above-described method for determining the number of flow steps, the force described for the case where the throughput of each semiconductor manufacturing apparatus 21 is the same may differ depending on the semiconductor manufacturing apparatus 21. In this case, the carrier that has been processed in the semiconductor manufacturing apparatus 21 stays in the load port of the semiconductor manufacturing apparatus 21. The process for eliminating such load port waiting is described below. This waiting for the load port can be eliminated by carrying out appropriate scheduling in the flow shop controller and appropriate scheduling in the bay controller for transfer in the inter-bay transfer device 3 and in-bay transfer device 22. A diagram schematically showing this case is shown in FIG.

[0049] In the case of FIG. 12, only the CMP apparatus has a throughput of 30 Wph, and the other semiconductors. The body manufacturing apparatus 21 is 60 Wph. In this case, it is necessary to first flatten the processing time. The flattening of the processing time can be determined by the same method as the necessary algebra determination processing for each semiconductor manufacturing apparatus 21 as described above. In the example of FIG. 12, only the throughput of the CMP apparatus is affected by the other apparatus. Therefore, if two CMP devices are installed, the processing time can be flattened. Similarly, when the throughput is 1Z3, three semiconductor manufacturing apparatuses 21 may be installed, and when the throughput is 1Z4, four semiconductor manufacturing apparatuses 21 may be installed.

[0050] Next, a load port wait cancellation process by scheduling will be described. First, for the semiconductor manufacturing apparatus 21 provided with a plurality of units, the intra-bay transfer apparatus 22 sequentially transfers the carriers. In the case of FIG. 12, since two CMP apparatuses are installed, the in-bay transport apparatus 22 transports the carrier alternately to the two transport apparatuses. When three units are installed, the waiting time on the load port in the semiconductor manufacturing equipment 21 after processing is eliminated by alternately transferring to the three units and transferring to four units when four units are installed. I can do it.

[0051] Further, in the above-mentioned scheduling, rescheduling is performed at a predetermined timing. In the power rescheduling, the carrier force that has been processed in the semiconductor manufacturing apparatus 21 even when the processing time according to the recipe is different. Semiconductor manufacturing apparatus 21 May stay at the load port. The rescheduling in that case will be described.

[0052] For example, when the recipe processing time in the lithography apparatus is increased from 60 seconds to 80 seconds, if the wafer is continuously conveyed as it is, the waiting time between the semiconductor manufacturing apparatuses 21 may vary and may stay in the port port. One solution is as follows. If the processing process requires that all semiconductor manufacturing equipment 21 to be transported not stay on the load port of the semiconductor manufacturing equipment 21, the preceding carrier is all semiconductor manufacturing equipment in the bay 2. Force required to start carrier processing, which will be described later, after the processing of 21 is completed.In a normal processing process, such a request is required for all processes, but it is required for a few processes. Is assumed. In this case, as described above, when waiting for the preceding carrier to finish the processing of all the semiconductor manufacturing apparatuses 21, the total throughput becomes very bad.

[0053] Therefore, also in the above case, it is required to perform scheduling by a method different from the above. The A process for eliminating such load port waiting will be described below. The process in this case is schematically shown in FIG.

[0054] In the case described above, after the preceding carrier is mounted on the semiconductor manufacturing apparatus 21 in the process, scheduling is performed to adjust the processing start time of the semiconductor manufacturing apparatus 21. The waiting state of is canceled. For example, in the case shown in FIG. 13, the processing time of the lithographic apparatus is 20 seconds longer in the succeeding carrier 3 than in the preceding carrier 2, so that the annealing apparatus force has a constant time between CMP apparatuses (ie, annealing). (This eliminates the waiting time for processing on the load port after the end of processing on the device).

In this case, when the subsequent carrier having a long processing time is mounted on the lithography apparatus and the preceding carrier having a short processing time mounted on the annealing apparatus is mounted on the annealing apparatus, the processing start is started. Schedule a delay of 20 seconds. This delays carrier reception by the lithography apparatus in the next transport cycle by 20 seconds, but the annealing apparatus can take out the carrier at the end of processing, and as a result, wait for the load port is eliminated. .

[0056] Further, in the rescheduling, a processing process for eliminating the load port waiting when the processing time becomes long due to a failure occurring in each semiconductor manufacturing apparatus 21 will be described below. FIG. 14 schematically shows this.

In FIG. 14, each semiconductor manufacturing apparatus 21 reports information on the remaining processing time of each process to the bay controller, and using this time information, the transport scheduling of the intra-pay transport apparatus 22 is performed. A treatment method will be described in which the semiconductor manufacturing apparatus 21 does not stay on the load port even when a failure occurs.

[0058] As described above, there is a predetermined standard between the bay controller and the semiconductor manufacturing apparatus 21.

(For example, GEM300 defined in SEMI Standard) is used for information communication, and each semiconductor manufacturing equipment 21 reports information on the remaining processing time of each process to the bay controller. To be configured.

[0059] The bay controller monitors the remaining processing time in each semiconductor manufacturing apparatus 21 and should not stay on the load port of the semiconductor manufacturing apparatus 21. Judgment is made as to whether or not the delivery is in time, and if it is judged that it is not in time, processing for changing the scheduling is performed. In the changed scheduling at this time, the retention on the load port is eliminated by performing a process of giving priority to the transfer in the semiconductor manufacturing apparatus 21 that should not stay.

However, if the bay controller determines that the bay controller is not in time, if the in-bay transport apparatus 22 already has a carrier to be transported to another semiconductor manufacturing apparatus 21, priority transport cannot be performed. Therefore, if it is determined that the intra-bay transport device 22 is not in time before the access timing to the inter-bay noffer 4, it is set so that no carrier is taken from the inter-bay noffer 4. However, if it has already passed through the entrance of the bay 2, the carrier 22 in the bay needs to place this carrier in the inter-bay buffer 4 in this case. Accordingly, the determination timing is a time including this time. In the case of Figure 14, it shows the case where the time between the annealing apparatus and the CMP apparatus is constant even if a failure occurs in the lithography apparatus!

By configuring the semiconductor manufacturing system 1 as described above, the semiconductor manufacturing system 1 in the flow shop method capable of processing with a shorter TAT than the conventional event type semiconductor manufacturing system 1 can be realized.

Industrial applicability

[0062] In the semiconductor manufacturing system 1 based on the flow shop method of the present invention, the semiconductor manufacturing system 1 in which a shorter TAT is realized can be realized by using a conventional scheduling method that does not use the event type. . Schedule again!

, Useless WiP (Work in Progress) does not occur.

[0063] Furthermore, the flow shop controller and the bay controller can perform real-time processing by performing rescheduling at each timing. And since it is real-time processing, interrupt processing can be realized in an efficient state. That is, the shortest HotLot can be realized.

Claims

The scope of the claims

[1] A semiconductor manufacturing system using a flow shop method,

The semiconductor manufacturing system includes:

A plurality of pays comprising a plurality of semiconductor manufacturing apparatuses and an in-bay transfer apparatus for transferring carriers between the semiconductor manufacturing apparatuses;

A flow shop controller having a scheduler that executes at least scheduling of the transfer between the bays. With

The bay includes a bay controller having a scheduler that executes at least scheduling of the semiconductor manufacturing apparatus and the intra-pay transport apparatus in the bay, and the flow shop controller is configured to perform the scheduling based on the scheduling in the scheduler. Sends a control instruction to the inter-pay device.

The bay controller sends a control instruction to the semiconductor manufacturing apparatus and the intra-bay transport apparatus based on scheduling in the scheduler,

The scheduling is

Among the semiconductor manufacturing apparatuses, the number of installations and the number of flow steps for each semiconductor manufacturing apparatus are calculated based on the operation rate of the lithography apparatus, and are set based on the calculated number of installations and the number of flow steps. Have been

A semiconductor manufacturing system characterized by that.

[2] The flow shop controller and the bay controller are

Receiving at least one of failure information, recovery information, and remaining processing time information from at least one of the semiconductor manufacturing apparatus, the intra-bay transfer apparatus, the bay, and the inter-bay transfer apparatus;

The flow shop controller performs rescheduling at the timing of accessing the entrance of the flow shop,

The bay controller reschedules at the timing of accessing the bay entrance.

The semiconductor manufacturing system according to claim 1.